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-rw-r--r--c/src/lib/libbsp/arm/lpc24xx/clock/clock-config.c6
-rw-r--r--c/src/lib/libbsp/arm/lpc24xx/console/console-config.c2
-rw-r--r--c/src/lib/libbsp/arm/lpc24xx/include/bsp.h2
-rw-r--r--c/src/lib/libbsp/arm/lpc24xx/include/lpc24xx.h476
-rw-r--r--c/src/lib/libbsp/arm/lpc24xx/misc/dma.c6
-rw-r--r--c/src/lib/libbsp/arm/lpc24xx/misc/io.c2
-rw-r--r--c/src/lib/libbsp/arm/lpc24xx/network/network.c14
-rw-r--r--c/src/lib/libbsp/arm/lpc24xx/startup/bspstarthooks.c56
8 files changed, 282 insertions, 282 deletions
diff --git a/c/src/lib/libbsp/arm/lpc24xx/clock/clock-config.c b/c/src/lib/libbsp/arm/lpc24xx/clock/clock-config.c
index 83f0e03ed2..35b7eabba2 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/clock/clock-config.c
+++ b/c/src/lib/libbsp/arm/lpc24xx/clock/clock-config.c
@@ -107,16 +107,16 @@ static uint32_t lpc24xx_clock_nanoseconds_since_last_tick( void)
uint64_t clock = LPC24XX_CCLK;
uint32_t clicks = T0TC;
uint64_t ns = ((uint64_t) clicks * 1000000000) / clock;
-
+
return (uint32_t) ns;
}
-
+
#define Clock_driver_support_initialize_hardware() lpc24xx_clock_initialize()
#define Clock_driver_support_install_isr( isr, old_isr) lpc24xx_clock_handler_install()
#define Clock_driver_support_shutdown_hardware() lpc24xx_clock_cleanup()
-
+
#define Clock_driver_nanoseconds_since_last_tick lpc24xx_clock_nanoseconds_since_last_tick
/* Include shared source clock driver code */
diff --git a/c/src/lib/libbsp/arm/lpc24xx/console/console-config.c b/c/src/lib/libbsp/arm/lpc24xx/console/console-config.c
index d639ef9818..fd0c26484f 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/console/console-config.c
+++ b/c/src/lib/libbsp/arm/lpc24xx/console/console-config.c
@@ -36,7 +36,7 @@ static void lpc24xx_uart_set_register( uint32_t addr, uint8_t i, uint8_t val)
{
volatile uint32_t *reg = (volatile uint32_t *) addr;
- reg [i] = val;
+ reg [i] = val;
}
rtems_device_minor_number Console_Port_Minor = 0;
diff --git a/c/src/lib/libbsp/arm/lpc24xx/include/bsp.h b/c/src/lib/libbsp/arm/lpc24xx/include/bsp.h
index e1f06b2ee3..75a6731507 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/include/bsp.h
+++ b/c/src/lib/libbsp/arm/lpc24xx/include/bsp.h
@@ -77,7 +77,7 @@ int lpc24xx_eth_attach_detach(
*
* @code
* #include <bsp.h>
- *
+ *
* #define CONFIGURE_INIT
*
* #define CONFIGURE_IDLE_TASK_BODY lpc24xx_idle
diff --git a/c/src/lib/libbsp/arm/lpc24xx/include/lpc24xx.h b/c/src/lib/libbsp/arm/lpc24xx/include/lpc24xx.h
index 98a6156cbd..b4da9f5096 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/include/lpc24xx.h
+++ b/c/src/lib/libbsp/arm/lpc24xx/include/lpc24xx.h
@@ -157,13 +157,13 @@
#define IOCLR1 (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x1C))
/* GPIO Interrupt Registers */
-#define IO0_INT_EN_R (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x90))
+#define IO0_INT_EN_R (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x90))
#define IO0_INT_EN_F (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x94))
#define IO0_INT_STAT_R (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x84))
#define IO0_INT_STAT_F (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x88))
#define IO0_INT_CLR (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x8C))
-#define IO2_INT_EN_R (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0xB0))
+#define IO2_INT_EN_R (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0xB0))
#define IO2_INT_EN_F (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0xB4))
#define IO2_INT_STAT_R (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0xA4))
#define IO2_INT_STAT_F (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0xA8))
@@ -172,224 +172,224 @@
#define IO_INT_STAT (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x80))
#define PARTCFG_BASE_ADDR 0x3FFF8000
-#define PARTCFG (*(volatile uint32_t *) (PARTCFG_BASE_ADDR + 0x00))
+#define PARTCFG (*(volatile uint32_t *) (PARTCFG_BASE_ADDR + 0x00))
/* Fast I/O setup */
#define FIO_BASE_ADDR 0x3FFFC000
-#define FIO0DIR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x00))
+#define FIO0DIR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x00))
#define FIO0MASK (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x10))
#define FIO0PIN (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x14))
#define FIO0SET (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x18))
#define FIO0CLR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x1C))
-#define FIO1DIR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x20))
+#define FIO1DIR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x20))
#define FIO1MASK (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x30))
#define FIO1PIN (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x34))
#define FIO1SET (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x38))
#define FIO1CLR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x3C))
-#define FIO2DIR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x40))
+#define FIO2DIR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x40))
#define FIO2MASK (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x50))
#define FIO2PIN (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x54))
#define FIO2SET (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x58))
#define FIO2CLR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x5C))
-#define FIO3DIR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x60))
+#define FIO3DIR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x60))
#define FIO3MASK (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x70))
#define FIO3PIN (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x74))
#define FIO3SET (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x78))
#define FIO3CLR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x7C))
-#define FIO4DIR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x80))
+#define FIO4DIR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x80))
#define FIO4MASK (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x90))
#define FIO4PIN (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x94))
#define FIO4SET (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x98))
#define FIO4CLR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x9C))
/* FIOs can be accessed through WORD, HALF-WORD or BYTE. */
-#define FIO0DIR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x01))
-#define FIO1DIR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x21))
-#define FIO2DIR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x41))
-#define FIO3DIR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x61))
-#define FIO4DIR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x81))
-
-#define FIO0DIR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x02))
-#define FIO1DIR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x22))
-#define FIO2DIR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x42))
-#define FIO3DIR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x62))
-#define FIO4DIR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x82))
-
-#define FIO0DIR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x03))
-#define FIO1DIR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x23))
-#define FIO2DIR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x43))
-#define FIO3DIR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x63))
-#define FIO4DIR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x83))
-
-#define FIO0DIR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x04))
-#define FIO1DIR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x24))
-#define FIO2DIR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x44))
-#define FIO3DIR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x64))
-#define FIO4DIR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x84))
-
-#define FIO0DIRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x00))
-#define FIO1DIRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x20))
-#define FIO2DIRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x40))
-#define FIO3DIRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x60))
-#define FIO4DIRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x80))
-
-#define FIO0DIRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x02))
-#define FIO1DIRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x22))
-#define FIO2DIRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x42))
-#define FIO3DIRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x62))
-#define FIO4DIRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x82))
-
-#define FIO0MASK0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x10))
-#define FIO1MASK0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x30))
-#define FIO2MASK0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x50))
-#define FIO3MASK0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x70))
-#define FIO4MASK0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x90))
-
-#define FIO0MASK1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x11))
-#define FIO1MASK1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x21))
-#define FIO2MASK1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x51))
-#define FIO3MASK1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x71))
-#define FIO4MASK1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x91))
-
-#define FIO0MASK2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x12))
-#define FIO1MASK2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x32))
-#define FIO2MASK2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x52))
-#define FIO3MASK2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x72))
-#define FIO4MASK2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x92))
-
-#define FIO0MASK3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x13))
-#define FIO1MASK3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x33))
-#define FIO2MASK3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x53))
-#define FIO3MASK3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x73))
-#define FIO4MASK3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x93))
-
-#define FIO0MASKL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x10))
-#define FIO1MASKL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x30))
-#define FIO2MASKL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x50))
-#define FIO3MASKL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x70))
-#define FIO4MASKL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x90))
-
-#define FIO0MASKU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x12))
-#define FIO1MASKU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x32))
-#define FIO2MASKU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x52))
-#define FIO3MASKU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x72))
-#define FIO4MASKU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x92))
-
-#define FIO0PIN0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x14))
-#define FIO1PIN0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x34))
-#define FIO2PIN0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x54))
-#define FIO3PIN0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x74))
-#define FIO4PIN0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x94))
-
-#define FIO0PIN1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x15))
-#define FIO1PIN1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x25))
-#define FIO2PIN1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x55))
-#define FIO3PIN1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x75))
-#define FIO4PIN1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x95))
-
-#define FIO0PIN2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x16))
-#define FIO1PIN2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x36))
-#define FIO2PIN2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x56))
-#define FIO3PIN2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x76))
-#define FIO4PIN2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x96))
-
-#define FIO0PIN3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x17))
-#define FIO1PIN3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x37))
-#define FIO2PIN3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x57))
-#define FIO3PIN3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x77))
-#define FIO4PIN3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x97))
-
-#define FIO0PINL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x14))
-#define FIO1PINL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x34))
-#define FIO2PINL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x54))
-#define FIO3PINL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x74))
-#define FIO4PINL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x94))
-
-#define FIO0PINU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x16))
-#define FIO1PINU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x36))
-#define FIO2PINU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x56))
-#define FIO3PINU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x76))
-#define FIO4PINU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x96))
-
-#define FIO0SET0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x18))
-#define FIO1SET0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x38))
-#define FIO2SET0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x58))
-#define FIO3SET0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x78))
-#define FIO4SET0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x98))
-
-#define FIO0SET1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x19))
-#define FIO1SET1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x29))
-#define FIO2SET1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x59))
-#define FIO3SET1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x79))
-#define FIO4SET1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x99))
-
-#define FIO0SET2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1A))
-#define FIO1SET2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3A))
-#define FIO2SET2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5A))
-#define FIO3SET2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7A))
-#define FIO4SET2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9A))
-
-#define FIO0SET3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1B))
-#define FIO1SET3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3B))
-#define FIO2SET3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5B))
-#define FIO3SET3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7B))
-#define FIO4SET3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9B))
-
-#define FIO0SETL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x18))
-#define FIO1SETL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x38))
-#define FIO2SETL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x58))
-#define FIO3SETL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x78))
-#define FIO4SETL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x98))
-
-#define FIO0SETU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x1A))
-#define FIO1SETU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x3A))
-#define FIO2SETU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x5A))
-#define FIO3SETU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x7A))
-#define FIO4SETU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x9A))
-
-#define FIO0CLR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1C))
-#define FIO1CLR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3C))
-#define FIO2CLR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5C))
-#define FIO3CLR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7C))
-#define FIO4CLR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9C))
-
-#define FIO0CLR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1D))
-#define FIO1CLR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x2D))
-#define FIO2CLR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5D))
-#define FIO3CLR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7D))
-#define FIO4CLR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9D))
-
-#define FIO0CLR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1E))
-#define FIO1CLR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3E))
-#define FIO2CLR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5E))
-#define FIO3CLR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7E))
-#define FIO4CLR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9E))
-
-#define FIO0CLR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1F))
-#define FIO1CLR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3F))
-#define FIO2CLR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5F))
-#define FIO3CLR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7F))
-#define FIO4CLR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9F))
-
-#define FIO0CLRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x1C))
-#define FIO1CLRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x3C))
-#define FIO2CLRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x5C))
-#define FIO3CLRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x7C))
-#define FIO4CLRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x9C))
-
-#define FIO0CLRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x1E))
-#define FIO1CLRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x3E))
-#define FIO2CLRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x5E))
-#define FIO3CLRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x7E))
-#define FIO4CLRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x9E))
+#define FIO0DIR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x01))
+#define FIO1DIR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x21))
+#define FIO2DIR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x41))
+#define FIO3DIR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x61))
+#define FIO4DIR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x81))
+
+#define FIO0DIR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x02))
+#define FIO1DIR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x22))
+#define FIO2DIR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x42))
+#define FIO3DIR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x62))
+#define FIO4DIR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x82))
+
+#define FIO0DIR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x03))
+#define FIO1DIR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x23))
+#define FIO2DIR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x43))
+#define FIO3DIR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x63))
+#define FIO4DIR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x83))
+
+#define FIO0DIR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x04))
+#define FIO1DIR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x24))
+#define FIO2DIR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x44))
+#define FIO3DIR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x64))
+#define FIO4DIR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x84))
+
+#define FIO0DIRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x00))
+#define FIO1DIRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x20))
+#define FIO2DIRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x40))
+#define FIO3DIRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x60))
+#define FIO4DIRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x80))
+
+#define FIO0DIRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x02))
+#define FIO1DIRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x22))
+#define FIO2DIRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x42))
+#define FIO3DIRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x62))
+#define FIO4DIRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x82))
+
+#define FIO0MASK0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x10))
+#define FIO1MASK0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x30))
+#define FIO2MASK0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x50))
+#define FIO3MASK0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x70))
+#define FIO4MASK0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x90))
+
+#define FIO0MASK1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x11))
+#define FIO1MASK1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x21))
+#define FIO2MASK1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x51))
+#define FIO3MASK1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x71))
+#define FIO4MASK1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x91))
+
+#define FIO0MASK2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x12))
+#define FIO1MASK2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x32))
+#define FIO2MASK2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x52))
+#define FIO3MASK2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x72))
+#define FIO4MASK2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x92))
+
+#define FIO0MASK3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x13))
+#define FIO1MASK3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x33))
+#define FIO2MASK3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x53))
+#define FIO3MASK3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x73))
+#define FIO4MASK3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x93))
+
+#define FIO0MASKL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x10))
+#define FIO1MASKL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x30))
+#define FIO2MASKL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x50))
+#define FIO3MASKL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x70))
+#define FIO4MASKL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x90))
+
+#define FIO0MASKU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x12))
+#define FIO1MASKU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x32))
+#define FIO2MASKU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x52))
+#define FIO3MASKU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x72))
+#define FIO4MASKU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x92))
+
+#define FIO0PIN0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x14))
+#define FIO1PIN0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x34))
+#define FIO2PIN0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x54))
+#define FIO3PIN0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x74))
+#define FIO4PIN0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x94))
+
+#define FIO0PIN1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x15))
+#define FIO1PIN1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x25))
+#define FIO2PIN1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x55))
+#define FIO3PIN1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x75))
+#define FIO4PIN1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x95))
+
+#define FIO0PIN2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x16))
+#define FIO1PIN2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x36))
+#define FIO2PIN2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x56))
+#define FIO3PIN2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x76))
+#define FIO4PIN2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x96))
+
+#define FIO0PIN3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x17))
+#define FIO1PIN3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x37))
+#define FIO2PIN3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x57))
+#define FIO3PIN3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x77))
+#define FIO4PIN3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x97))
+
+#define FIO0PINL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x14))
+#define FIO1PINL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x34))
+#define FIO2PINL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x54))
+#define FIO3PINL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x74))
+#define FIO4PINL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x94))
+
+#define FIO0PINU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x16))
+#define FIO1PINU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x36))
+#define FIO2PINU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x56))
+#define FIO3PINU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x76))
+#define FIO4PINU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x96))
+
+#define FIO0SET0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x18))
+#define FIO1SET0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x38))
+#define FIO2SET0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x58))
+#define FIO3SET0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x78))
+#define FIO4SET0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x98))
+
+#define FIO0SET1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x19))
+#define FIO1SET1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x29))
+#define FIO2SET1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x59))
+#define FIO3SET1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x79))
+#define FIO4SET1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x99))
+
+#define FIO0SET2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1A))
+#define FIO1SET2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3A))
+#define FIO2SET2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5A))
+#define FIO3SET2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7A))
+#define FIO4SET2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9A))
+
+#define FIO0SET3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1B))
+#define FIO1SET3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3B))
+#define FIO2SET3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5B))
+#define FIO3SET3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7B))
+#define FIO4SET3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9B))
+
+#define FIO0SETL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x18))
+#define FIO1SETL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x38))
+#define FIO2SETL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x58))
+#define FIO3SETL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x78))
+#define FIO4SETL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x98))
+
+#define FIO0SETU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x1A))
+#define FIO1SETU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x3A))
+#define FIO2SETU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x5A))
+#define FIO3SETU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x7A))
+#define FIO4SETU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x9A))
+
+#define FIO0CLR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1C))
+#define FIO1CLR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3C))
+#define FIO2CLR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5C))
+#define FIO3CLR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7C))
+#define FIO4CLR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9C))
+
+#define FIO0CLR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1D))
+#define FIO1CLR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x2D))
+#define FIO2CLR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5D))
+#define FIO3CLR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7D))
+#define FIO4CLR1 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9D))
+
+#define FIO0CLR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1E))
+#define FIO1CLR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3E))
+#define FIO2CLR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5E))
+#define FIO3CLR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7E))
+#define FIO4CLR2 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9E))
+
+#define FIO0CLR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x1F))
+#define FIO1CLR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x3F))
+#define FIO2CLR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x5F))
+#define FIO3CLR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x7F))
+#define FIO4CLR3 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x9F))
+
+#define FIO0CLRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x1C))
+#define FIO1CLRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x3C))
+#define FIO2CLRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x5C))
+#define FIO3CLRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x7C))
+#define FIO4CLRL (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x9C))
+
+#define FIO0CLRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x1E))
+#define FIO1CLRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x3E))
+#define FIO2CLRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x5E))
+#define FIO3CLRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x7E))
+#define FIO4CLRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x9E))
/* System Control Block(SCB) modules include Memory Accelerator Module,
-Phase Locked Loop, VPB divider, Power Control, External Interrupt,
+Phase Locked Loop, VPB divider, Power Control, External Interrupt,
Reset, and Code Security/Debugging */
#define SCB_BASE_ADDR 0xE01FC000
@@ -415,7 +415,7 @@ Reset, and Code Security/Debugging */
#define CLKSRCSEL (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x10C))
#define PCLKSEL0 (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x1A8))
#define PCLKSEL1 (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x1AC))
-
+
/* External Interrupts */
#define EXTINT (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x140))
#define INTWAKE (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x144))
@@ -433,7 +433,7 @@ Reset, and Code Security/Debugging */
#define AHBCFG2 (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x18C))
/* System Controls and Status */
-#define SCS (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x1A0))
+#define SCS (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x1A0))
/* External Memory Controller (EMC) */
@@ -506,7 +506,7 @@ Reset, and Code Security/Debugging */
#define EMC_STA_EXT_WAIT (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x880))
-
+
/* Timer 0 */
#define TMR0_BASE_ADDR 0xE0004000
#define T0IR (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x00))
@@ -835,72 +835,72 @@ Reset, and Code Security/Debugging */
/* CAN CONTROLLERS AND ACCEPTANCE FILTER */
#define CAN_ACCEPT_BASE_ADDR 0xE003C000
-#define CAN_AFMR (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x00))
-#define CAN_SFF_SA (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x04))
+#define CAN_AFMR (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x00))
+#define CAN_SFF_SA (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x04))
#define CAN_SFF_GRP_SA (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x08))
#define CAN_EFF_SA (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x0C))
-#define CAN_EFF_GRP_SA (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x10))
+#define CAN_EFF_GRP_SA (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x10))
#define CAN_EOT (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x14))
-#define CAN_LUT_ERR_ADR (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x18))
+#define CAN_LUT_ERR_ADR (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x18))
#define CAN_LUT_ERR (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x1C))
-#define CAN_CENTRAL_BASE_ADDR 0xE0040000
-#define CAN_TX_SR (*(volatile uint32_t *) (CAN_CENTRAL_BASE_ADDR + 0x00))
-#define CAN_RX_SR (*(volatile uint32_t *) (CAN_CENTRAL_BASE_ADDR + 0x04))
+#define CAN_CENTRAL_BASE_ADDR 0xE0040000
+#define CAN_TX_SR (*(volatile uint32_t *) (CAN_CENTRAL_BASE_ADDR + 0x00))
+#define CAN_RX_SR (*(volatile uint32_t *) (CAN_CENTRAL_BASE_ADDR + 0x04))
#define CAN_MSR (*(volatile uint32_t *) (CAN_CENTRAL_BASE_ADDR + 0x08))
#define CAN1_BASE_ADDR 0xE0044000
-#define CAN1MOD (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x00))
-#define CAN1CMR (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x04))
-#define CAN1GSR (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x08))
-#define CAN1ICR (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x0C))
+#define CAN1MOD (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x00))
+#define CAN1CMR (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x04))
+#define CAN1GSR (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x08))
+#define CAN1ICR (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x0C))
#define CAN1IER (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x10))
-#define CAN1BTR (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x14))
-#define CAN1EWL (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x18))
-#define CAN1SR (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x1C))
-#define CAN1RFS (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x20))
+#define CAN1BTR (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x14))
+#define CAN1EWL (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x18))
+#define CAN1SR (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x1C))
+#define CAN1RFS (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x20))
#define CAN1RID (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x24))
-#define CAN1RDA (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x28))
+#define CAN1RDA (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x28))
#define CAN1RDB (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x2C))
-
-#define CAN1TFI1 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x30))
-#define CAN1TID1 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x34))
+
+#define CAN1TFI1 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x30))
+#define CAN1TID1 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x34))
#define CAN1TDA1 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x38))
-#define CAN1TDB1 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x3C))
-#define CAN1TFI2 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x40))
-#define CAN1TID2 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x44))
-#define CAN1TDA2 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x48))
+#define CAN1TDB1 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x3C))
+#define CAN1TFI2 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x40))
+#define CAN1TID2 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x44))
+#define CAN1TDA2 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x48))
#define CAN1TDB2 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x4C))
-#define CAN1TFI3 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x50))
-#define CAN1TID3 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x54))
-#define CAN1TDA3 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x58))
+#define CAN1TFI3 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x50))
+#define CAN1TID3 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x54))
+#define CAN1TDA3 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x58))
#define CAN1TDB3 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x5C))
#define CAN2_BASE_ADDR 0xE0048000
-#define CAN2MOD (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x00))
-#define CAN2CMR (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x04))
-#define CAN2GSR (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x08))
-#define CAN2ICR (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x0C))
+#define CAN2MOD (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x00))
+#define CAN2CMR (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x04))
+#define CAN2GSR (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x08))
+#define CAN2ICR (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x0C))
#define CAN2IER (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x10))
-#define CAN2BTR (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x14))
-#define CAN2EWL (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x18))
-#define CAN2SR (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x1C))
-#define CAN2RFS (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x20))
+#define CAN2BTR (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x14))
+#define CAN2EWL (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x18))
+#define CAN2SR (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x1C))
+#define CAN2RFS (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x20))
#define CAN2RID (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x24))
-#define CAN2RDA (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x28))
+#define CAN2RDA (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x28))
#define CAN2RDB (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x2C))
-
-#define CAN2TFI1 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x30))
-#define CAN2TID1 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x34))
+
+#define CAN2TFI1 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x30))
+#define CAN2TID1 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x34))
#define CAN2TDA1 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x38))
-#define CAN2TDB1 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x3C))
-#define CAN2TFI2 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x40))
-#define CAN2TID2 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x44))
-#define CAN2TDA2 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x48))
+#define CAN2TDB1 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x3C))
+#define CAN2TFI2 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x40))
+#define CAN2TID2 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x44))
+#define CAN2TDA2 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x48))
#define CAN2TDB2 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x4C))
-#define CAN2TFI3 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x50))
-#define CAN2TID3 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x54))
-#define CAN2TDA3 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x58))
+#define CAN2TFI3 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x50))
+#define CAN2TID3 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x54))
+#define CAN2TDA3 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x58))
#define CAN2TDB3 (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x5C))
@@ -1136,9 +1136,9 @@ Reset, and Code Security/Debugging */
#define MAC_POWERDOWN (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFF4)) /* Power-down reg */
#define MAC_MODULEID (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */
-/* LCD Controller */
+/* LCD Controller */
-#define LCD_BASE_ADDR 0xFFE10000
+#define LCD_BASE_ADDR 0xFFE10000
#define LCD_CFG (*(volatile uint32_t *) 0xE01FC1B8)
#define LCD_TIMH (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x000))
#define LCD_TIMV (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x004))
diff --git a/c/src/lib/libbsp/arm/lpc24xx/misc/dma.c b/c/src/lib/libbsp/arm/lpc24xx/misc/dma.c
index c42768f4fc..1f3f896d43 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/misc/dma.c
+++ b/c/src/lib/libbsp/arm/lpc24xx/misc/dma.c
@@ -82,17 +82,17 @@ void lpc24xx_dma_channel_disable(unsigned channel, bool force)
if (channel < GPDMA_CH_NUMBER) {
volatile lpc24xx_dma_channel *ch = GPDMA_CH_BASE_ADDR(channel);
uint32_t cfg = ch->cfg;
-
+
if (!force) {
/* Halt */
ch->cfg = SET_FLAG(cfg, GPDMA_CH_CFG_HALT);
-
+
/* Wait for inactive */
do {
cfg = ch->cfg;
} while (IS_FLAG_SET(cfg, GPDMA_CH_CFG_ACTIVE));
}
-
+
/* Disable */
ch->cfg = CLEAR_FLAG(cfg, GPDMA_CH_CFG_EN);
}
diff --git a/c/src/lib/libbsp/arm/lpc24xx/misc/io.c b/c/src/lib/libbsp/arm/lpc24xx/misc/io.c
index 2ca27fc509..6526bf8b7c 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/misc/io.c
+++ b/c/src/lib/libbsp/arm/lpc24xx/misc/io.c
@@ -223,7 +223,7 @@ rtems_status_code lpc24xx_gpio_config(
/* Resistor */
LPC24XX_PINMODE [select] =
(LPC24XX_PINMODE [select] & ~(LPC24XX_IO_SELECT_MASK << shift))
- | ((resistor & LPC24XX_IO_SELECT_MASK) << shift);
+ | ((resistor & LPC24XX_IO_SELECT_MASK) << shift);
rtems_interrupt_flash(level);
diff --git a/c/src/lib/libbsp/arm/lpc24xx/network/network.c b/c/src/lib/libbsp/arm/lpc24xx/network/network.c
index 2bb9b58831..43a73a1240 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/network/network.c
+++ b/c/src/lib/libbsp/arm/lpc24xx/network/network.c
@@ -398,7 +398,7 @@ static void lpc24xx_eth_receive_task(void *arg)
volatile lpc24xx_eth_transfer_descriptor *const desc =
(volatile lpc24xx_eth_transfer_descriptor *)
LPC24XX_ETH_RECEIVE_DESC_START;
- volatile lpc24xx_eth_receive_info *const info =
+ volatile lpc24xx_eth_receive_info *const info =
(volatile lpc24xx_eth_receive_info *)
LPC24XX_ETH_RECEIVE_INFO_START;
struct mbuf **const mbuf_table =
@@ -416,7 +416,7 @@ static void lpc24xx_eth_receive_task(void *arg)
/* Wait for events */
sc = rtems_bsdnet_event_receive(
- LPC24XX_ETH_EVENT_INITIALIZE | LPC24XX_ETH_EVENT_INTERRUPT,
+ LPC24XX_ETH_EVENT_INITIALIZE | LPC24XX_ETH_EVENT_INTERRUPT,
RTEMS_EVENT_ANY | RTEMS_WAIT,
RTEMS_NO_TIMEOUT,
&events
@@ -695,7 +695,7 @@ static void lpc24xx_eth_transmit_task(void *arg)
/* Wait for events */
sc = rtems_bsdnet_event_receive(
LPC24XX_ETH_EVENT_INITIALIZE
- | LPC24XX_ETH_EVENT_START
+ | LPC24XX_ETH_EVENT_START
| LPC24XX_ETH_EVENT_INTERRUPT,
RTEMS_EVENT_ANY | RTEMS_WAIT,
RTEMS_NO_TIMEOUT,
@@ -950,8 +950,8 @@ static void lpc24xx_eth_interface_init(void *arg)
/* Start receive task */
if (e->receive_task == RTEMS_ID_NONE) {
e->receive_task = rtems_bsdnet_newproc(
- "ntrx",
- 4096,
+ "ntrx",
+ 4096,
lpc24xx_eth_receive_task,
e
);
@@ -962,8 +962,8 @@ static void lpc24xx_eth_interface_init(void *arg)
/* Start transmit task */
if (e->transmit_task == RTEMS_ID_NONE) {
e->transmit_task = rtems_bsdnet_newproc(
- "nttx",
- 4096,
+ "nttx",
+ 4096,
lpc24xx_eth_transmit_task,
e
);
diff --git a/c/src/lib/libbsp/arm/lpc24xx/startup/bspstarthooks.c b/c/src/lib/libbsp/arm/lpc24xx/startup/bspstarthooks.c
index c86cd02171..1c899a00ad 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/startup/bspstarthooks.c
+++ b/c/src/lib/libbsp/arm/lpc24xx/startup/bspstarthooks.c
@@ -145,89 +145,89 @@ static void __attribute__((section(".bsp_start"))) lpc24xx_init_emc_1(void)
*/
/* Global dynamic settings */
-
+
/* FIXME */
EMC_DYN_APR = 2;
-
+
/* Data-in to active command period tWR + tRP */
EMC_DYN_DAL = 4;
-
+
/* Load mode register to active or refresh command period 2 tCK */
EMC_DYN_MRD = 1;
-
+
/* Active to precharge command period 44 ns */
EMC_DYN_RAS = 3;
-
+
/* Active to active command period 66 ns */
EMC_DYN_RC = 4;
-
+
/* Use command delayed strategy */
EMC_DYN_RD_CFG = 1;
-
+
/* Auto refresh period 66 ns */
EMC_DYN_RFC = 4;
-
+
/* Precharge command period 20 ns */
EMC_DYN_RP = 1;
-
+
/* Active bank a to active bank b command period 15 ns */
EMC_DYN_RRD = 1;
-
+
/* FIXME */
EMC_DYN_SREX = 5;
-
+
/* Write recovery time 15 ns */
EMC_DYN_WR = 1;
-
+
/* Exit self refresh to active command period 75 ns */
EMC_DYN_XSR = 5;
-
+
/* Dynamic Memory 0: Micron M T48LC 4M16 A2 P 75 IT */
-
+
/*
* Use SDRAM, 0 0 001 01 address mapping, disabled buffer, unprotected writes
*/
EMC_DYN_CFG0 = 0x0280;
-
+
/* CAS and RAS latency */
EMC_DYN_RASCAS0 = 0x0202;
-
+
/* Wait 50 micro seconds */
lpc24xx_cpu_delay(3600);
-
+
/* Send command: NOP */
EMC_DYN_CTRL = EMC_DYN_CTRL_CE | EMC_DYN_CTRL_CS | EMC_DYN_CTRL_CMD_NOP;
-
+
/* Wait 50 micro seconds */
lpc24xx_cpu_delay(3600);
-
+
/* Send command: PRECHARGE ALL */
EMC_DYN_CTRL = EMC_DYN_CTRL_CE | EMC_DYN_CTRL_CS | EMC_DYN_CTRL_CMD_PALL;
-
+
/* Shortest possible refresh period */
EMC_DYN_RFSH = 0x01;
-
+
/* Wait at least 128 AHB clock cycles */
lpc24xx_cpu_delay(128);
-
+
/* Wait 1 micro second */
lpc24xx_cpu_delay(72);
-
+
/* Set refresh period */
EMC_DYN_RFSH = 0x46;
-
+
/* Send command: MODE */
EMC_DYN_CTRL = EMC_DYN_CTRL_CE | EMC_DYN_CTRL_CS | EMC_DYN_CTRL_CMD_MODE;
-
+
/* Set mode register in SDRAM */
*((volatile uint32_t *) (0xa0000000 | (0x23 << (1 + 2 + 8))));
-
+
/* Send command: NORMAL */
EMC_DYN_CTRL = 0;
-
+
/* Enable buffer */
EMC_DYN_CFG0 |= 0x00080000;
-
+
/* Test RAM */
lpc24xx_ram_test_32();
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-03 02:20:57 +0000