1 files changed, 28 insertions, 34 deletions
diff --git a/c/src/lib/libbsp/arm/beagle/startup/bspreset.c b/c/src/lib/libbsp/arm/beagle/startup/bspreset.c
index d937a18abd..5865b7badf 100644
--- a/c/src/lib/libbsp/arm/beagle/startup/bspreset.c
+++ b/c/src/lib/libbsp/arm/beagle/startup/bspreset.c
@@ -1,48 +1,42 @@
-/**
- * @file
- *
- * @ingroup beagle
- *
- * @brief Reset code.
- */
-
 /*
- * Copyright (c) 2012 Claas Ziemke. All rights reserved.
- *
- *  Claas Ziemke
- *  Kernerstrasse 11
- *  70182 Stuttgart
- *  Germany
- *  <claas.ziemke@gmx.net>
+ * Copyright (c) 2014 Ben Gras <beng@shrike-systems.com>. All rights reserved.
  *
  * The license and distribution terms for this file may be
  * found in the file LICENSE in this distribution or at
- * http://www.rtems.com/license/LICENSE.
+ * http://www.rtems.org/license/LICENSE.
  */
 
-#include <stdbool.h>
-
-#include <bspopts.h>
+#include <bsp.h>
 #include <bsp/bootcard.h>
-#include <bsp/beagle.h>
 
-static void watchdog_reset(void)
-{
-  #ifdef BEAGLE_ENABLE_WATCHDOG_RESET
-    //BEAGLE_TIMCLK_CTRL |= TIMCLK_CTRL_WDT;
-    //beagle.wdt.mctrl |= WDTTIM_MCTRL_M_RES1 | WDTTIM_MCTRL_M_RES2;
-    //beagle.wdt.emr = WDTTIM_EMR_MATCH_CTRL_SET(beagle.wdt.emr, 0x2);
-    //beagle.wdt.ctrl |= WDTTIM_CTRL_COUNT_ENAB;
-    //beagle.wdt.match0 = 1;
-    //beagle.wdt.counter = 0;
-  #endif
-}
+#define AM335X_CM_BASE 0x44E00000
+#define AM335X_CM_SIZE 0x1000
+
+#define AM335X_PRM_DEVICE_OFFSET 0xf00
+#define AM335X_PRM_RSTCTRL_REG 0x00
+#define AM335X_RST_GLOBAL_WARM_SW_BIT 0
 
-void bsp_reset( void)
+#define DM37XX_CM_BASE 0x48307000
+#define DM37XX_CM_SIZE 0x1000
+#define DM37XX_PRM_RSTCTRL_REG 0x250
+#define DM37XX_RST_DPLL3_BIT 2
+
+void bsp_reset(void)
 {
-  watchdog_reset();
+#if IS_DM3730
+  static uint32_t reset_base = DM37XX_CM_BASE;
+  while (true) {
+    mmio_set((reset_base + DM37XX_PRM_RSTCTRL_REG),
+             (1 << DM37XX_RST_DPLL3_BIT));
+  }
+#endif
 
+#if IS_AM335X
+  static uint32_t reset_base = AM335X_CM_BASE;
   while (true) {
-    /* Do nothing */
+    mmio_set((reset_base + AM335X_PRM_DEVICE_OFFSET +
+              AM335X_PRM_RSTCTRL_REG),
+             (1 << AM335X_RST_GLOBAL_WARM_SW_BIT));
   }
+#endif
 }