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-rw-r--r--c/src/exec/libcsupport/include/motorola/mc68230.h71
-rw-r--r--c/src/exec/libcsupport/include/motorola/mc68681.h87
-rw-r--r--c/src/exec/libcsupport/include/zilog/z8036.h109
-rw-r--r--c/src/exec/libcsupport/include/zilog/z8530.h99
-rw-r--r--c/src/exec/libcsupport/include/zilog/z8536.h112
5 files changed, 478 insertions, 0 deletions
diff --git a/c/src/exec/libcsupport/include/motorola/mc68230.h b/c/src/exec/libcsupport/include/motorola/mc68230.h
new file mode 100644
index 0000000000..cafcd318be
--- /dev/null
+++ b/c/src/exec/libcsupport/include/motorola/mc68230.h
@@ -0,0 +1,71 @@
+/*
+ * mc68230.h -- Low level support code for the Motorola 68230 Parallel
+ * Interface/Timer (PIT)
+ *
+ * Modified by Doug McBride, Colorado Space Grant College
+ *
+ * Format taken partly from RTEMS code and mostly from Motorola IDP user's
+ * manual. RTEMS copyright information below.
+ *
+ * COPYRIGHT (c) 1989-1997.
+ * On-Line Applications Research Corporation (OAR).
+ * Copyright assigned to U.S. Government, 1994.
+ *
+ * The license and distribution terms for this file may in
+ * the file LICENSE in this distribution or at
+ * http://www.OARcorp.com/rtems/license.html.
+ *
+ * $Id$
+ */
+
+#ifndef __MC68230_H__
+#define __MC68230_H__
+
+/* Some Motorola IDP User manual defines: */
+#define PIT_ADDR 0x00c01003 /* base address of the PIT */
+#define REGOFF 0x04 /* Difference between addresses */
+#define VECT 64
+#define H1VECT 0x00
+#define H2VECT 0x01
+#define H3VECT 0x02
+#define H4VECT 0x03
+
+/*
+ * mc68230 register offsets
+ */
+#define PGCR 0x00
+#define PSRR 1*REGOFF
+#define PADDR 2*REGOFF
+#define PBDDR 3*REGOFF
+#define PCDDR 4*REGOFF
+#define PIVR 5*REGOFF
+#define PACR 6*REGOFF
+#define PBCR 7*REGOFF
+#define PADR 8*REGOFF
+#define PBDR 9*REGOFF
+#define PAAR 10*REGOFF
+#define PBAR 11*REGOFF
+#define PCDR 12*REGOFF
+#define PITSR 13*REGOFF
+#define TCR 16*REGOFF
+#define TIVR 17*REGOFF
+#define CPRH 19*REGOFF
+#define CPRM 20*REGOFF
+#define CPRL 21*REGOFF
+#define CNTRH 23*REGOFF
+#define CNTRM 24*REGOFF
+#define CNTRL 25*REGOFF
+#define TSR 26*REGOFF
+
+/* Some RTEMS style defines: */
+#ifndef VOL8
+#define VOL8( ptr ) ((volatile rtems_unsigned8 *)(ptr))
+#endif
+
+#define MC68230_WRITE( reg, data ) \
+ *(VOL8(PIT_ADDR+reg)) = (data)
+
+#define MC68230_READ( reg, data ) \
+ (data) = *(VOL8(PIT_ADDR+reg))
+
+#endif
diff --git a/c/src/exec/libcsupport/include/motorola/mc68681.h b/c/src/exec/libcsupport/include/motorola/mc68681.h
new file mode 100644
index 0000000000..99e595d03c
--- /dev/null
+++ b/c/src/exec/libcsupport/include/motorola/mc68681.h
@@ -0,0 +1,87 @@
+/*
+ * mc68681-duart.h -- Low level support code for the Motorola mc68681
+ * DUART. This one is one the mc68ec0x0 board.
+ * Written by rob@cygnus.com (Rob Savoye)
+ *
+ * $Id$
+ */
+
+#ifndef __MC68681_H__
+#define __MC68681_H__
+#define DUART_ADDR 0xb00003 /* base address of the DUART */
+
+/*
+ * mc68681 register offsets
+ */
+#define DUART_MR1A 0x00 /* Mode Register A */
+#define DUART_MR2A 0x00 /* Mode Register A */
+#define DUART_SRA 0x04 /* Status Register A */
+#define DUART_CSRA 0x04 /* Clock-Select Register A */
+#define DUART_CRA 0x08 /* Command Register A */
+#define DUART_RBA 0x0c /* Receive Buffer A */
+#define DUART_TBA 0x0c /* Transmit Buffer A */
+#define DUART_IPCR 0x10 /* Input Port Change Register */
+#define DUART_ACR 0x10 /* Auxiliary Control Register */
+#define DUART_ISR 0x14 /* Interrupt Status Register */
+#define DUART_IMR 0x14 /* Interrupt Mask Register */
+#define DUART_CUR 0x18 /* Counter Mode: current MSB */
+#define DUART_CTUR 0x18 /* Counter/Timer upper reg */
+#define DUART_CLR 0x1c /* Counter Mode: current LSB */
+#define DUART_CTLR 0x1c /* Counter/Timer lower reg */
+#define DUART_MR1B 0x20 /* Mode Register B */
+#define DUART_MR2B 0x20 /* Mode Register B */
+#define DUART_SRB 0x24 /* Status Register B */
+#define DUART_CSRB 0x24 /* Clock-Select Register B */
+#define DUART_CRB 0x28 /* Command Register B */
+#define DUART_RBB 0x2c /* Receive Buffer B */
+#define DUART_TBB 0x2c /* Transmit Buffer A */
+#define DUART_IVR 0x30 /* Interrupt Vector Register */
+#define DUART_IP 0x34 /* Input Port */
+#define DUART_OPCR 0x34 /* Output Port Configuration Reg. */
+#define DUART_STRTCC 0x38 /* Start-Counter command */
+#define DUART_OPRSET 0x38 /* Output Port Reg, SET bits */
+#define DUART_STOPCC 0x3c /* Stop-Counter command */
+#define DUART_OPRRST 0x3c /* Output Port Reg, ReSeT bits */
+
+/* this is just if you want a copy of the chip's registers */
+struct duart_regs {
+ unsigned char mr1a_reg; /* Mode Register A */
+ unsigned char mr2a_reg; /* Mode Register A */
+ unsigned char sra_reg; /* Status Register A */
+ unsigned char csra_reg; /* Clock-Select Register A */
+ unsigned char cra_reg; /* Command Register A */
+ unsigned char ipcr_reg; /* Input Port Change Register */
+ unsigned char acr_reg; /* Auxiliary Control Register */
+ unsigned char isr_reg; /* Interrupt Status Register */
+ unsigned char imr_reg; /* Interrupt Mask Register */
+ unsigned char cur_reg; /* Counter Mode: current MSB */
+ unsigned char ctur_reg; /* Counter/Timer upper reg */
+ unsigned char clr_reg; /* Counter Mode: current LSB */
+ unsigned char ctlr_reg; /* Counter/Timer lower reg */
+ unsigned char mr1b_reg; /* Mode Register B */
+ unsigned char mr2b_reg; /* Mode Register B */
+ unsigned char srb_reg; /* Status Register B */
+ unsigned char csrb_reg; /* Clock-Select Register B */
+ unsigned char crb_reg; /* Command Register B */
+ unsigned char ivr_reg; /* Interrupt Vector Register */
+ unsigned char ip_reg; /* Input Port */
+ unsigned char opcr_reg; /* Output Port Configuration Reg. */
+ unsigned char oprset_reg; /* Output Port Reg; bit SET */
+ unsigned char strtcc_reg; /* Start-Counter command */
+ unsigned char oprrst_reg; /* Output Port Reg; bit ReSeT */
+ unsigned char stopcc_reg; /* Stop-Counter command */
+ unsigned char pad;
+};
+
+/* Some RTEMS style defines: */
+#ifndef VOL8
+#define VOL8( ptr ) ((volatile rtems_unsigned8 *)(ptr))
+#endif
+
+#define MC68681_WRITE( reg, data ) \
+ *(VOL8(DUART_ADDR+reg)) = (data)
+
+#define MC68681_READ( reg, data ) \
+ (data) = *(VOL8(DUART_ADDR+reg))
+
+#endif
diff --git a/c/src/exec/libcsupport/include/zilog/z8036.h b/c/src/exec/libcsupport/include/zilog/z8036.h
new file mode 100644
index 0000000000..b2b2c073cb
--- /dev/null
+++ b/c/src/exec/libcsupport/include/zilog/z8036.h
@@ -0,0 +1,109 @@
+/* z8036.h
+ *
+ * This include file defines information related to a Zilog Z8036
+ * Counter/Timer/IO Chip. It is a memory mapped part.
+ *
+ * Input parameters: NONE
+ *
+ * Output parameters: NONE
+ *
+ * NOTE: This file shares as much as possible with the include
+ * file for the Z8536 via z8x36.h.
+ *
+ * COPYRIGHT (c) 1989-1997.
+ * On-Line Applications Research Corporation (OAR).
+ * Copyright assigned to U.S. Government, 1994.
+ *
+ * The license and distribution terms for this file may in
+ * the file LICENSE in this distribution or at
+ * http://www.OARcorp.com/rtems/license.html.
+ *
+ * $Id$
+ */
+
+#ifndef __Z8036_h
+#define __Z8036_h
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* macros */
+
+#define Z8036( ptr ) ((volatile struct z8036_map *)(ptr))
+
+#define Z8x36_STATE0 ( z8036 ) \
+ { /*char *garbage = *(Z8036(z8036))->???; */ }
+
+
+#define Z8x36_WRITE( z8036, reg, data ) \
+ (Z8036(z8036))->reg = (data)
+
+
+#define Z8x36_READ( z8036, reg, data ) \
+ (Z8036(z8036))->reg = (data)
+
+/* structures */
+
+struct z8036_map {
+/* MAIN CONTROL REGISTERS (0x00-0x07) */
+ rtems_unsigned8 MASTER_INTR; /* Master Interrupt Ctl Reg */
+ rtems_unsigned8 MASTER_CFG; /* Master Configuration Ctl Reg */
+ rtems_unsigned8 PORTA_VECTOR; /* Port A - Interrupt Vector */
+ rtems_unsigned8 PORTB_VECTOR; /* Port B - Interrupt Vector */
+ rtems_unsigned8 CNT_TMR_VECTOR; /* Counter/Timer Interrupt Vector */
+ rtems_unsigned8 PORTC_DATA_POLARITY; /* Port C - Data Path Polarity */
+ rtems_unsigned8 PORTC_DIRECTION; /* Port C - Data Direction */
+ rtems_unsigned8 PORTC_SPECIAL_IO_CTL; /* Port C - Special IO Control */
+/* MOST OFTEN ACCESSED REGISTERS (0x08 - 0x0f) */
+ rtems_unsigned8 PORTA_CMD_STATUS; /* Port A - Command Status Reg */
+ rtems_unsigned8 PORTB_CMD_STATUS; /* Port B - Command Status Reg */
+ rtems_unsigned8 CT1_CMD_STATUS; /* Ctr/Timer 1 - Command Status Reg */
+ rtems_unsigned8 CT2_CMD_STATUS; /* Ctr/Timer 2 - Command Status Reg */
+ rtems_unsigned8 CT3_CMD_STATUS; /* Ctr/Timer 3 - Command Status Reg */
+ rtems_unsigned8 PORTA_DATA; /* Port A - Data */
+ rtems_unsigned8 PORTB_DATA; /* Port B - Data */
+ rtems_unsigned8 PORTC_DATA; /* Port C - Data */
+/* COUNTER/TIMER RELATED REGISTERS (0x10-0x1f) */
+ rtems_unsigned8 CT1_CUR_CNT_MSB; /* Ctr/Timer 1 - Current Count (MSB) */
+ rtems_unsigned8 CT1_CUR_CNT_LSB; /* Ctr/Timer 1 - Current Count (LSB) */
+ rtems_unsigned8 CT2_CUR_CNT_MSB; /* Ctr/Timer 2 - Current Count (MSB) */
+ rtems_unsigned8 CT2_CUR_CNT_LSB; /* Ctr/Timer 2 - Current Count (LSB) */
+ rtems_unsigned8 CT3_CUR_CNT_MSB; /* Ctr/Timer 3 - Current Count (MSB) */
+ rtems_unsigned8 CT3_CUR_CNT_LSB; /* Ctr/Timer 3 - Current Count (LSB) */
+ rtems_unsigned8 CT1_TIME_CONST_MSB; /* Ctr/Timer 1 - Time Constant (MSB) */
+ rtems_unsigned8 CT1_TIME_CONST_LSB; /* Ctr/Timer 1 - Time Constant (LSB) */
+ rtems_unsigned8 CT2_TIME_CONST_MSB; /* Ctr/Timer 2 - Time Constant (MSB) */
+ rtems_unsigned8 CT2_TIME_CONST_LSB; /* Ctr/Timer 2 - Time Constant (LSB) */
+ rtems_unsigned8 CT3_TIME_CONST_MSB; /* Ctr/Timer 3 - Time Constant (MSB) */
+ rtems_unsigned8 CT3_TIME_CONST_LSB; /* Ctr/Timer 3 - Time Constant (LSB) */
+ rtems_unsigned8 CT1_MODE_SPEC; /* Ctr/Timer 1 - Mode Specification */
+ rtems_unsigned8 CT2_MODE_SPEC; /* Ctr/Timer 2 - Mode Specification */
+ rtems_unsigned8 CT3_MODE_SPEC; /* Ctr/Timer 3 - Mode Specification */
+ rtems_unsigned8 CURRENT_VECTOR; /* Current Vector */
+/* PORT A SPECIFICATION REGISTERS (0x20 -0x27) */
+ rtems_unsigned8 PORTA_MODE; /* Port A - Mode Specification */
+ rtems_unsigned8 PORTA_HANDSHAKE; /* Port A - Handshake Specification */
+ rtems_unsigned8 PORTA_DATA_POLARITY; /* Port A - Data Path Polarity */
+ rtems_unsigned8 PORTA_DIRECTION; /* Port A - Data Direction */
+ rtems_unsigned8 PORTA_SPECIAL_IO_CTL; /* Port A - Special IO Control */
+ rtems_unsigned8 PORTA_PATT_POLARITY; /* Port A - Pattern Polarity */
+ rtems_unsigned8 PORTA_PATT_TRANS; /* Port A - Pattern Transition */
+ rtems_unsigned8 PORTA_PATT_MASK; /* Port A - Pattern Mask */
+/* PORT B SPECIFICATION REGISTERS (0x28-0x2f) */
+ rtems_unsigned8 PORTB_MODE; /* Port B - Mode Specification */
+ rtems_unsigned8 PORTB_HANDSHAKE; /* Port B - Handshake Specification */
+ rtems_unsigned8 PORTB_DATA_POLARITY; /* Port B - Data Path Polarity */
+ rtems_unsigned8 PORTB_DIRECTION; /* Port B - Data Direction */
+ rtems_unsigned8 PORTB_SPECIAL_IO_CTL; /* Port B - Special IO Control */
+ rtems_unsigned8 PORTB_PATT_POLARITY; /* Port B - Pattern Polarity */
+ rtems_unsigned8 PORTB_PATT_TRANS; /* Port B - Pattern Transition */
+ rtems_unsigned8 PORTB_PATT_MASK; /* Port B - Pattern Mask */
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/c/src/exec/libcsupport/include/zilog/z8530.h b/c/src/exec/libcsupport/include/zilog/z8530.h
new file mode 100644
index 0000000000..cd6399844f
--- /dev/null
+++ b/c/src/exec/libcsupport/include/zilog/z8530.h
@@ -0,0 +1,99 @@
+/* z8530.h
+ *
+ * This include file defines information related to a Zilog Z8530
+ * SCC Chip. It is a IO mapped part.
+ *
+ * Input parameters: NONE
+ *
+ * Output parameters: NONE
+ *
+ * COPYRIGHT (c) 1989-1997.
+ * On-Line Applications Research Corporation (OAR).
+ * Copyright assigned to U.S. Government, 1994.
+ *
+ * The license and distribution terms for this file may in
+ * the file LICENSE in this distribution or at
+ * http://www.OARcorp.com/rtems/license.html.
+ *
+ * $Id$
+ */
+
+#ifndef __Z8530_h
+#define __Z8530_h
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* macros */
+
+#define VOL8( ptr ) ((volatile rtems_unsigned8 *)(ptr))
+
+#define Z8x30_STATE0 ( z8530 ) \
+ { char *garbage; \
+ (garbage) = *(VOL8(z8530)) \
+ }
+
+#define Z8x30_WRITE_CONTROL( z8530, reg, data ) \
+ *(VOL8(z8530)) = (reg); \
+ *(VOL8(z8530)) = (data)
+
+#define Z8x30_READ_CONTROL( z8530, reg, data ) \
+ *(VOL8(z8530)) = (reg); \
+ (data) = *(VOL8(z8530))
+
+#define Z8x30_WRITE_DATA( z8530, data ) \
+ *(VOL8(z8530)) = (data);
+
+#define Z8x30_READ_DATA( z8530, data ) \
+ (data) = *(VOL8(z8530));
+
+
+/* RR_0 Bit Definitions */
+
+#define RR_0_TX_BUFFER_EMPTY 0x04
+#define RR_0_RX_DATA_AVAILABLE 0x01
+
+/* read registers */
+
+#define RR_0 0x00
+#define RR_1 0x01
+#define RR_2 0x02
+#define RR_3 0x03
+#define RR_4 0x04
+#define RR_5 0x05
+#define RR_6 0x06
+#define RR_7 0x07
+#define RR_8 0x08
+#define RR_9 0x09
+#define RR_10 0x0A
+#define RR_11 0x0B
+#define RR_12 0x0C
+#define RR_13 0x0D
+#define RR_14 0x0E
+#define RR_15 0x0F
+
+/* write registers */
+
+#define WR_0 0x00
+#define WR_1 0x01
+#define WR_2 0x02
+#define WR_3 0x03
+#define WR_4 0x04
+#define WR_5 0x05
+#define WR_6 0x06
+#define WR_7 0x07
+#define WR_8 0x08
+#define WR_9 0x09
+#define WR_10 0x0A
+#define WR_11 0x0B
+#define WR_12 0x0C
+#define WR_13 0x0D
+#define WR_14 0x0E
+#define WR_15 0x0F
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/c/src/exec/libcsupport/include/zilog/z8536.h b/c/src/exec/libcsupport/include/zilog/z8536.h
new file mode 100644
index 0000000000..8d72f2c8af
--- /dev/null
+++ b/c/src/exec/libcsupport/include/zilog/z8536.h
@@ -0,0 +1,112 @@
+/* z8536.h
+ *
+ * This include file defines information related to a Zilog Z8536
+ * Counter/Timer/IO Chip. It is a IO mapped part.
+ *
+ * Input parameters: NONE
+ *
+ * Output parameters: NONE
+ *
+ * NOTE: This file shares as much as possible with the include
+ * file for the Z8036 via z8x36.h.
+ *
+ * COPYRIGHT (c) 1989-1997.
+ * On-Line Applications Research Corporation (OAR).
+ * Copyright assigned to U.S. Government, 1994.
+ *
+ * The license and distribution terms for this file may in
+ * the file LICENSE in this distribution or at
+ * http://www.OARcorp.com/rtems/license.html.
+ *
+ * $Id$
+ */
+
+#ifndef __Z8536_h
+#define __Z8536_h
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* macros */
+
+#define VOL8( ptr ) ((volatile rtems_unsigned8 *)(ptr))
+
+#define Z8x36_STATE0 ( z8536 ) \
+ { char *garbage; \
+ (garbage) = *(VOL8(z8536+0xC)) \
+ }
+
+#define Z8x36_WRITE( z8536, reg, data ) \
+ *(VOL8(z8536+0xC)) = (reg); \
+ *(VOL8(z8536+0xC)) = (data)
+
+#define Z8x36_READ( z8536, reg, data ) \
+ *(VOL8(z8536+0xC)) = (reg); \
+ (data) = *(VOL8(z8536+0xC))
+
+/* structures */
+
+/* MAIN CONTROL REGISTERS (0x00-0x07) */
+#define MASTER_INTR 0x00 /* Master Interrupt Ctl Reg */
+#define MASTER_CFG 0x01 /* Master Configuration Ctl Reg */
+#define PORTA_VECTOR 0x02 /* Port A - Interrupt Vector */
+#define PORTB_VECTOR 0x03 /* Port B - Interrupt Vector */
+#define CNT_TMR_VECTOR 0x04 /* Counter/Timer Interrupt Vector */
+#define PORTC_DATA_POLARITY 0x05 /* Port C - Data Path Polarity */
+#define PORTC_DIRECTION 0x06 /* Port C - Data Direction */
+#define PORTC_SPECIAL_IO_CTL 0x07 /* Port C - Special IO Control */
+
+/* MOST OFTEN ACCESSED REGISTERS (0x08 - 0x0f) */
+#define PORTA_CMD_STATUS 0x08 /* Port A - Command Status Reg */
+#define PORTB_CMD_STATUS 0x09 /* Port B - Command Status Reg */
+#define CT1_CMD_STATUS 0x0a /* Ctr/Timer 1 - Command Status Reg */
+#define CT2_CMD_STATUS 0x0b /* Ctr/Timer 2 - Command Status Reg */
+#define CT3_CMD_STATUS 0x0c /* Ctr/Timer 3 - Command Status Reg */
+#define PORTA_DATA 0x0d /* Port A - Data */
+#define PORTB_DATA 0x0e /* Port B - Data */
+#define PORTC_DATA 0x0f /* Port C - Data */
+
+/* COUNTER/TIMER RELATED REGISTERS (0x10-0x1f) */
+#define CT1_CUR_CNT_MSB 0x10 /* Ctr/Timer 1 - Current Count (MSB) */
+#define CT1_CUR_CNT_LSB 0x11 /* Ctr/Timer 1 - Current Count (LSB) */
+#define CT2_CUR_CNT_MSB 0x12 /* Ctr/Timer 2 - Current Count (MSB) */
+#define CT2_CUR_CNT_LSB 0x13 /* Ctr/Timer 2 - Current Count (LSB) */
+#define CT3_CUR_CNT_MSB 0x14 /* Ctr/Timer 3 - Current Count (MSB) */
+#define CT3_CUR_CNT_LSB 0x15 /* Ctr/Timer 3 - Current Count (LSB) */
+#define CT1_TIME_CONST_MSB 0x16 /* Ctr/Timer 1 - Time Constant (MSB) */
+#define CT1_TIME_CONST_LSB 0x17 /* Ctr/Timer 1 - Time Constant (LSB) */
+#define CT2_TIME_CONST_MSB 0x18 /* Ctr/Timer 2 - Time Constant (MSB) */
+#define CT2_TIME_CONST_LSB 0x19 /* Ctr/Timer 2 - Time Constant (LSB) */
+#define CT3_TIME_CONST_MSB 0x1a /* Ctr/Timer 3 - Time Constant (MSB) */
+#define CT3_TIME_CONST_LSB 0x1b /* Ctr/Timer 3 - Time Constant (LSB) */
+#define CT1_MODE_SPEC 0x1c /* Ctr/Timer 1 - Mode Specification */
+#define CT2_MODE_SPEC 0x1d /* Ctr/Timer 2 - Mode Specification */
+#define CT3_MODE_SPEC 0x1e /* Ctr/Timer 3 - Mode Specification */
+#define CURRENT_VECTOR 0x1f /* Current Vector */
+
+/* PORT A SPECIFICATION REGISTERS (0x20 -0x27) */
+#define PORTA_MODE 0x20 /* Port A - Mode Specification */
+#define PORTA_HANDSHAKE 0x21 /* Port A - Handshake Specification */
+#define PORTA_DATA_POLARITY 0x22 /* Port A - Data Path Polarity */
+#define PORTA_DIRECTION 0x23 /* Port A - Data Direction */
+#define PORTA_SPECIAL_IO_CTL 0x24 /* Port A - Special IO Control */
+#define PORTA_PATT_POLARITY 0x25 /* Port A - Pattern Polarity */
+#define PORTA_PATT_TRANS 0x26 /* Port A - Pattern Transition */
+#define PORTA_PATT_MASK 0x27 /* Port A - Pattern Mask */
+
+/* PORT B SPECIFICATION REGISTERS (0x28-0x2f) */
+#define PORTB_MODE 0x28 /* Port B - Mode Specification */
+#define PORTB_HANDSHAKE 0x29 /* Port B - Handshake Specification */
+#define PORTB_DATA_POLARITY 0x2a /* Port B - Data Path Polarity */
+#define PORTB_DIRECTION 0x2b /* Port B - Data Direction */
+#define PORTB_SPECIAL_IO_CTL 0x2c /* Port B - Special IO Control */
+#define PORTB_PATT_POLARITY 0x2d /* Port B - Pattern Polarity */
+#define PORTB_PATT_TRANS 0x2e /* Port B - Pattern Transition */
+#define PORTB_PATT_MASK 0x2f /* Port B - Pattern Mask */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif