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-rw-r--r--c/src/exec/score/cpu/hppa1.1/cpu.c21
-rw-r--r--c/src/exec/score/cpu/hppa1.1/cpu.h9
-rw-r--r--c/src/exec/score/cpu/hppa1.1/cpu_asm.s12
-rw-r--r--c/src/exec/score/cpu/hppa1.1/hppa.h40
-rw-r--r--c/src/exec/score/cpu/m68k/cpu_asm.s34
-rw-r--r--c/src/exec/score/cpu/unix/cpu.c2
6 files changed, 86 insertions, 32 deletions
diff --git a/c/src/exec/score/cpu/hppa1.1/cpu.c b/c/src/exec/score/cpu/hppa1.1/cpu.c
index f132033595..09c5d3d54b 100644
--- a/c/src/exec/score/cpu/hppa1.1/cpu.c
+++ b/c/src/exec/score/cpu/hppa1.1/cpu.c
@@ -14,12 +14,13 @@
* Division Incorporated makes no representations about the
* suitability of this software for any purpose.
*
- * $Id$
+ * cpu.c,v 1.7 1995/09/19 14:49:35 joel Exp
*/
#include <rtems/system.h>
-#include <rtems/score/isr.h>
-#include <rtems/score/wkspace.h>
+#include <rtems/fatal.h>
+#include <rtems/core/isr.h>
+#include <rtems/core/wkspace.h>
void hppa_external_interrupt_initialize(void);
void hppa_external_interrupt_enable(unsigned32);
@@ -105,6 +106,20 @@ void _CPU_Initialize(
/*PAGE
*
+ * _CPU_ISR_Get_level
+ */
+
+unsigned32 _CPU_ISR_Get_level(void)
+{
+ int level;
+ HPPA_ASM_SSM(0, level); /* change no bits; just get copy */
+ if (level & HPPA_PSW_I)
+ return 1;
+ return 0;
+}
+
+/*PAGE
+ *
* _CPU_ISR_install_raw_handler
*/
diff --git a/c/src/exec/score/cpu/hppa1.1/cpu.h b/c/src/exec/score/cpu/hppa1.1/cpu.h
index af3573d9a8..caeee7c8ff 100644
--- a/c/src/exec/score/cpu/hppa1.1/cpu.h
+++ b/c/src/exec/score/cpu/hppa1.1/cpu.h
@@ -20,7 +20,7 @@
* Note:
* This file is included by both C and assembler code ( -DASM )
*
- * $Id$
+ * cpu.h,v 1.5 1995/09/11 19:24:10 joel Exp
*/
#ifndef __CPU_h
@@ -30,9 +30,9 @@
extern "C" {
#endif
-#include <rtems/score/hppa.h> /* pick up machine definitions */
+#include <rtems/core/hppa.h> /* pick up machine definitions */
#ifndef ASM
-#include <rtems/score/hppatypes.h>
+#include <rtems/core/hppatypes.h>
#endif
/* conditional compilation parameters */
@@ -368,6 +368,9 @@ EXTERN void *_CPU_Interrupt_stack_high;
else HPPA_ASM_SSM(HPPA_PSW_I, ignore); \
}
+/* return current level */
+unsigned32 _CPU_ISR_Get_level( void );
+
/* end of ISR handler macros */
/*
diff --git a/c/src/exec/score/cpu/hppa1.1/cpu_asm.s b/c/src/exec/score/cpu/hppa1.1/cpu_asm.s
index afca4b773f..ea7c879183 100644
--- a/c/src/exec/score/cpu/hppa1.1/cpu_asm.s
+++ b/c/src/exec/score/cpu/hppa1.1/cpu_asm.s
@@ -1,4 +1,4 @@
-# @(#)cpu_asm.S 1.6 - 95/05/16
+# @(#)cpu_asm.S 1.7 - 95/09/21
#
#
# TODO:
@@ -24,14 +24,14 @@
# Division Incorporated makes no representations about the
# suitability of this software for any purpose.
#
-# $Id$
+# cpu_asm.S,v 1.5 1995/09/19 14:49:36 joel Exp
#
-#include <rtems/score/hppa.h>
-#include <rtems/score/cpu_asm.h>
-#include <rtems/score/cpu.h>
+#include <rtems/core/hppa.h>
+#include <rtems/core/cpu_asm.h>
+#include <rtems/core/cpu.h>
-#include <rtems/score/offsets.h>
+#include <rtems/core/offsets.h>
.SPACE $PRIVATE$
.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31
diff --git a/c/src/exec/score/cpu/hppa1.1/hppa.h b/c/src/exec/score/cpu/hppa1.1/hppa.h
index 74691eb1a7..1d9839995a 100644
--- a/c/src/exec/score/cpu/hppa1.1/hppa.h
+++ b/c/src/exec/score/cpu/hppa1.1/hppa.h
@@ -1,5 +1,5 @@
/*
- * @(#)hppa.h 1.9 - 95/06/28
+ * @(#)hppa.h 1.13 - 95/09/21
*
*
* Description:
@@ -24,7 +24,7 @@
* Note:
* This file is included by both C and assembler code ( -DASM )
*
- * $Id$
+ * hppa.h,v 1.4 1995/09/19 14:49:37 joel Exp
*/
#ifndef _INCLUDE_HPPA_H
@@ -64,23 +64,23 @@ extern "C" {
* present in a particular member of the family.
*/
-#if !defined(CPU_MODEL_NAME)
+#if !defined(RTEMS_MODEL_NAME)
#if defined(hppa7100)
-#define CPU_MODEL_NAME "hppa 7100"
+#define RTEMS_MODEL_NAME "hppa 7100"
#elif defined(hppa7200)
-#define CPU_MODEL_NAME "hppa 7200"
+#define RTEMS_MODEL_NAME "hppa 7200"
#else
-#error "Unsupported CPU Model"
+#define RTEMS_MODEL_NAME Unsupported CPU Model /* cause an error on usage */
#endif
-#endif /* !defined(CPU_MODEL_NAME) */
+#endif /* !defined(RTEMS_MODEL_NAME) */
/*
* Define the name of the CPU family.
@@ -223,6 +223,32 @@ extern "C" {
/*
+ * TLB characteristics
+ *
+ * Flags and Access Control layout for using TLB protection insertion
+ *
+ * 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
+ * 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |?|?|T|D|B|type |PL1|Pl2|U| access id |?|
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ *
+ */
+
+/*
+ * Access rights (type + PL1 + PL2)
+ */
+#define HPPA_PROT_R 0x00c00000 /* Read Only, no Write, no Execute */
+#define HPPA_PROT_RW 0x01c00000 /* Read & Write Only, no Execute */
+#define HPPA_PROT_RX 0x02c00000 /* Read & Execute Only, no Write */
+#define HPPA_PROT_RWX 0x03c00000 /* Read, Write, Execute */
+#define HPPA_PROT_X0 0x04c00000 /* Execute Only, Promote to Level 0 */
+#define HPPA_PROT_X1 0x05c00000 /* Execute Only, Promote to Level 1 */
+#define HPPA_PROT_X2 0x06c00000 /* Execute Only, Promote to Level 2 */
+#define HPPA_PROT_X3 0x07c00000 /* Execute Only, Promote to Level 3 */
+
+
+/*
* Inline macros for misc. interesting opcodes
*/
diff --git a/c/src/exec/score/cpu/m68k/cpu_asm.s b/c/src/exec/score/cpu/m68k/cpu_asm.s
index 2f0758f33d..fb8ba678b2 100644
--- a/c/src/exec/score/cpu/m68k/cpu_asm.s
+++ b/c/src/exec/score/cpu/m68k/cpu_asm.s
@@ -59,15 +59,15 @@ restore: movml a0@,d1-d7/a2-a7 | restore context
.global SYM (_CPU_Context_save_fp)
SYM (_CPU_Context_save_fp):
#if ( M68K_HAS_FPU == 1 )
- moval a7@(FPCONTEXT_ARG),a1 | a1 = &ptr to context area
- moval a1@,a0 | a0 = Save context area
+ moval a7@(FPCONTEXT_ARG),a1 | a1 = &ptr to context area
+ moval a1@,a0 | a0 = Save context area
fsave a0@- | save 68881/68882 state frame
tstb a0@ | check for a null frame
- beq nosv | Yes, skip save of user model
- fmovem fp0-fp7,a0@- | save data registers (fp0-fp7)
- fmovem fpc/fps/fpi,a0@- | and save control registers
+ beq nosv | Yes, skip save of user model
+ fmovem fp0-fp7,a0@- | save data registers (fp0-fp7)
+ fmovem fpc/fps/fpi,a0@- | and save control registers
movl #-1,a0@- | place not-null flag on stack
-nosv: movl a0,a1@ | save pointer to saved context
+nosv: movl a0,a1@ | save pointer to saved context
#endif
rts
@@ -75,15 +75,15 @@ nosv: movl a0,a1@ | save pointer to saved context
.global SYM (_CPU_Context_restore_fp)
SYM (_CPU_Context_restore_fp):
#if ( M68K_HAS_FPU == 1 )
- moval a7@(FPCONTEXT_ARG),a1 | a1 = &ptr to context area
- moval a1@,a0 | a0 = address of saved context
+ moval a7@(FPCONTEXT_ARG),a1 | a1 = &ptr to context area
+ moval a1@,a0 | a0 = address of saved context
tstb a0@ | Null context frame?
- beq norst | Yes, skip fp restore
+ beq norst | Yes, skip fp restore
addql #4,a0 | throwaway non-null flag
- fmovem a0@+,fpc/fps/fpi | restore control registers
- fmovem a0@+,fp0-fp7 | restore data regs (fp0-fp7)
+ fmovem a0@+,fpc/fps/fpi | restore control registers
+ fmovem a0@+,fp0-fp7 | restore data regs (fp0-fp7)
norst: frestore a0@+ | restore the fp state frame
- movl a0,a1@ | save pointer to saved context
+ movl a0,a1@ | save pointer to saved context
#endif
rts
@@ -112,6 +112,9 @@ norst: frestore a0@+ | restore the fp state frame
* higher priority interrupt in the new context if
* permitted by the new interrupt level mask, and (2) when
* the original context regains the cpu.
+ *
+ * XXX: Code for switching to a software maintained interrupt stack is
+ * not in place.
*/
#if ( M68K_HAS_VBR == 1)
@@ -134,6 +137,13 @@ SYM (_ISR_Handler):
addql #1,SYM (_Thread_Dispatch_disable_level) | disable multitasking
moveml d0-d1/a0-a1,a7@- | save d0-d1,a0-a1
+/*
+ * NOTE FOR CPUs WITHOUT HARDWARE INTERRUPT STACK:
+ *
+ * After the interrupted codes registers have been saved, it is save
+ * to switch to the software maintained interrupt stack.
+ */
+
#if ( M68K_HAS_VBR == 0)
movel a7@(SAVED+JSR_OFFSET),d0 | assume the exception table at 0x0000
addql #6,d0 | points to a jump table (jsr) in RAM
diff --git a/c/src/exec/score/cpu/unix/cpu.c b/c/src/exec/score/cpu/unix/cpu.c
index 54d4104ac7..a7b2140742 100644
--- a/c/src/exec/score/cpu/unix/cpu.c
+++ b/c/src/exec/score/cpu/unix/cpu.c
@@ -173,7 +173,7 @@ void _CPU_Signal_initialize( void )
void _CPU_Context_From_CPU_Init()
{
-#if defined(hppa1_1) && defined(RTEMS_UNIXLIB)
+#if defined(hppa1_1) && defined(RTEMS_UNIXLIB_SETJMP)
/*
* HACK - set the _SYSTEM_ID to 0x20c so that setjmp/longjmp
* will handle the full 32 floating point registers.
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-01 22:25:21 +0000