diff options
Diffstat (limited to '')
| -rw-r--r-- | c/src/exec/score/cpu/sh/rtems/score/Makefile.am | 6 | ||||
| -rw-r--r-- | c/src/exec/score/cpu/sh/rtems/score/iosh7032.h | 223 | ||||
| -rw-r--r-- | c/src/exec/score/cpu/sh/rtems/score/iosh7045.h | 321 | ||||
| -rw-r--r-- | c/src/exec/score/cpu/sh/rtems/score/ispsh7032.h | 165 | ||||
| -rw-r--r-- | c/src/exec/score/cpu/sh/rtems/score/ispsh7045.h | 211 | ||||
| -rw-r--r-- | c/src/exec/score/cpu/sh/rtems/score/sh.h | 19 |
6 files changed, 12 insertions, 933 deletions
diff --git a/c/src/exec/score/cpu/sh/rtems/score/Makefile.am b/c/src/exec/score/cpu/sh/rtems/score/Makefile.am index f650704221..a9b4cae02a 100644 --- a/c/src/exec/score/cpu/sh/rtems/score/Makefile.am +++ b/c/src/exec/score/cpu/sh/rtems/score/Makefile.am @@ -4,10 +4,8 @@ AUTOMAKE_OPTIONS = foreign 1.4 -H_FILES = cpu.h shtypes.h sh.h sh_io.h isp$(RTEMS_CPU_MODEL).h \ - io$(RTEMS_CPU_MODEL).h -noinst_HEADERS = cpu.h shtypes.h sh.h sh_io.h iosh7032.h ispsh7032.h \ - iosh7045.h ispsh7045.h +H_FILES = cpu.h shtypes.h sh.h sh_io.h +noinst_HEADERS = cpu.h shtypes.h sh.h sh_io.h # # (OPTIONAL) Add local stuff here using += diff --git a/c/src/exec/score/cpu/sh/rtems/score/iosh7032.h b/c/src/exec/score/cpu/sh/rtems/score/iosh7032.h deleted file mode 100644 index e98185414b..0000000000 --- a/c/src/exec/score/cpu/sh/rtems/score/iosh7032.h +++ /dev/null @@ -1,223 +0,0 @@ -/* - * This include file contains information pertaining to the Hitachi SH - * processor. - * - * NOTE: NOT ALL VALUES HAVE BEEN CHECKED !! - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which - * contained no copyright notice. - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __IOSH7030_H -#define __IOSH7030_H - -/* - * After each line is explained whether the access is char short or long. - * The functions read/writeb, w, l, 8, 16, 32 can be found - * in exec/score/cpu/sh/sh_io.h - * - * 8 bit == char ( readb, writeb, read8, write8) - * 16 bit == short ( readw, writew, read16, write16 ) - * 32 bit == long ( readl, writel, read32, write32 ) - */ - -#define SCI0_SMR 0x05fffec0 /* char */ -#define SCI0_BRR 0x05fffec1 /* char */ -#define SCI0_SCR 0x05fffec2 /* char */ -#define SCI0_TDR 0x05fffec3 /* char */ -#define SCI0_SSR 0x05fffec4 /* char */ -#define SCI0_RDR 0x05fffec5 /* char */ - -#define SCI1_SMR 0x05fffec8 /* char */ -#define SCI1_BRR 0x05fffec9 /* char */ -#define SCI1_SCR 0x05fffeca /* char */ -#define SCI1_TDR 0x05fffecb /* char */ -#define SCI1_SSR 0x05fffecc /* char */ -#define SCI1_RDR 0x05fffecd /* char */ - - -#define ADDRAH 0x05fffee0 /* char */ -#define ADDRAL 0x05fffee1 /* char */ -#define ADDRBH 0x05fffee2 /* char */ -#define ADDRBL 0x05fffee3 /* char */ -#define ADDRCH 0x05fffee4 /* char */ -#define ADDRCL 0x05fffee5 /* char */ -#define ADDRDH 0x05fffee6 /* char */ -#define ADDRDL 0x05fffee7 /* char */ -#define AD_DRA 0x05fffee0 /* short */ -#define AD_DRB 0x05fffee2 /* short */ -#define AD_DRC 0x05fffee4 /* short */ -#define AD_DRD 0x05fffee6 /* short */ -#define ADCSR 0x05fffee8 /* char */ -#define ADCR 0x05fffee9 /* char */ - -/*ITU SHARED*/ -#define ITU_TSTR 0x05ffff00 /* char */ -#define ITU_TSNC 0x05ffff01 /* char */ -#define ITU_TMDR 0x05ffff02 /* char */ -#define ITU_TFCR 0x05ffff03 /* char */ - -/*ITU CHANNEL 0*/ -#define ITU_TCR0 0x05ffff04 /* char */ -#define ITU_TIOR0 0x05ffff05 /* char */ -#define ITU_TIER0 0x05ffff06 /* char */ -#define ITU_TSR0 0x05ffff07 /* char */ -#define ITU_TCNT0 0x05ffff08 /* short */ -#define ITU_GRA0 0x05ffff0a /* short */ -#define ITU_GRB0 0x05ffff0c /* short */ - - /*ITU CHANNEL 1*/ -#define ITU_TCR1 0x05ffff0E /* char */ -#define ITU_TIOR1 0x05ffff0F /* char */ -#define ITU_TIER1 0x05ffff10 /* char */ -#define ITU_TSR1 0x05ffff11 /* char */ -#define ITU_TCNT1 0x05ffff12 /* short */ -#define ITU_GRA1 0x05ffff14 /* short */ -#define ITU_GRB1 0x05ffff16 /* short */ - - - /*ITU CHANNEL 2*/ -#define ITU_TCR2 0x05ffff18 /* char */ -#define ITU_TIOR2 0x05ffff19 /* char */ -#define ITU_TIER2 0x05ffff1A /* char */ -#define ITU_TSR2 0x05ffff1B /* char */ -#define ITU_TCNT2 0x05ffff1C /* short */ -#define ITU_GRA2 0x05ffff1E /* short */ -#define ITU_GRB2 0x05ffff20 /* short */ - - /*ITU CHANNEL 3*/ -#define ITU_TCR3 0x05ffff22 /* char */ -#define ITU_TIOR3 0x05ffff23 /* char */ -#define ITU_TIER3 0x05ffff24 /* char */ -#define ITU_TSR3 0x05ffff25 /* char */ -#define ITU_TCNT3 0x05ffff26 /* short */ -#define ITU_GRA3 0x05ffff28 /* short */ -#define ITU_GRB3 0x05ffff2A /* short */ -#define ITU_BRA3 0x05ffff2C /* short */ -#define ITU_BRB3 0x05ffff2E /* short */ - - /*ITU CHANNELS 0-4 SHARED*/ -#define ITU_TOCR 0x05ffff31 /* char */ - - /*ITU CHANNEL 4*/ -#define ITU_TCR4 0x05ffff32 /* char */ -#define ITU_TIOR4 0x05ffff33 /* char */ -#define ITU_TIER4 0x05ffff34 /* char */ -#define ITU_TSR4 0x05ffff35 /* char */ -#define ITU_TCNT4 0x05ffff36 /* short */ -#define ITU_GRA4 0x05ffff38 /* short */ -#define ITU_GRB4 0x05ffff3A /* short */ -#define ITU_BRA4 0x05ffff3C /* short */ -#define ITU_BRB4 0x05ffff3E /* short */ - - /*DMAC CHANNELS 0-3 SHARED*/ -#define DMAOR 0x05ffff48 /* short */ - - /*DMAC CHANNEL 0*/ -#define DMA_SAR0 0x05ffff40 /* long */ -#define DMA_DAR0 0x05ffff44 /* long */ -#define DMA_TCR0 0x05ffff4a /* short */ -#define DMA_CHCR0 0x05ffff4e /* short */ - - /*DMAC CHANNEL 1*/ -#define DMA_SAR1 0x05ffff50 /* long */ -#define DMA_DAR1 0x05ffff54 /* long */ -#define DMA_TCR1 0x05fffF5a /* short */ -#define DMA_CHCR1 0x05ffff5e /* short */ - - /*DMAC CHANNEL 3*/ -#define DMA_SAR3 0x05ffff60 /* long */ -#define DMA_DAR3 0x05ffff64 /* long */ -#define DMA_TCR3 0x05fffF6a /* short */ -#define DMA_CHCR3 0x05ffff6e /* short */ - -/*DMAC CHANNEL 4*/ -#define DMA_SAR4 0x05ffff70 /* long */ -#define DMA_DAR4 0x05ffff74 /* long */ -#define DMA_TCR4 0x05fffF7a /* short */ -#define DMA_CHCR4 0x05ffff7e /* short */ - -/*INTC*/ -#define INTC_IPRA 0x05ffff84 /* short */ -#define INTC_IPRB 0x05ffff86 /* short */ -#define INTC_IPRC 0x05ffff88 /* short */ -#define INTC_IPRD 0x05ffff8A /* short */ -#define INTC_IPRE 0x05ffff8C /* short */ -#define INTC_ICR 0x05ffff8E /* short */ - -/*UBC*/ -#define UBC_BARH 0x05ffff90 /* short */ -#define UBC_BARL 0x05ffff92 /* short */ -#define UBC_BAMRH 0x05ffff94 /* short */ -#define UBC_BAMRL 0x05ffff96 /* short */ -#define UBC_BBR 0x05ffff98 /* short */ - -/*BSC*/ -#define BSC_BCR 0x05ffffA0 /* short */ -#define BSC_WCR1 0x05ffffA2 /* short */ -#define BSC_WCR2 0x05ffffA4 /* short */ -#define BSC_WCR3 0x05ffffA6 /* short */ -#define BSC_DCR 0x05ffffA8 /* short */ -#define BSC_PCR 0x05ffffAA /* short */ -#define BSC_RCR 0x05ffffAC /* short */ -#define BSC_RTCSR 0x05ffffAE /* short */ -#define BSC_RTCNT 0x05ffffB0 /* short */ -#define BSC_RTCOR 0x05ffffB2 /* short */ - -/*WDT*/ -#define WDT_TCSR 0x05ffffB8 /* char */ -#define WDT_TCNT 0x05ffffB9 /* char */ -#define WDT_RSTCSR 0x05ffffBB /* char */ - -/*POWER DOWN STATE*/ -#define PDT_SBYCR 0x05ffffBC /* char */ - -/*PORT A*/ -#define PADR 0x05ffffC0 /* short */ - -/*PORT B*/ -#define PBDR 0x05ffffC2 /* short */ - - /*PORT C*/ -#define PCDR 0x05ffffD0 /* short */ - -/*PFC*/ -#define PFC_PAIOR 0x05ffffC4 /* short */ -#define PFC_PBIOR 0x05ffffC6 /* short */ -#define PFC_PACR1 0x05ffffC8 /* short */ -#define PFC_PACR2 0x05ffffCA /* short */ -#define PFC_PBCR1 0x05ffffCC /* short */ -#define PFC_PBCR2 0x05ffffCE /* short */ -#define PFC_CASCR 0x05ffffEE /* short */ - -/*TPC*/ -#define TPC_TPMR 0x05ffffF0 /* short */ -#define TPC_TPCR 0x05ffffF1 /* short */ -#define TPC_NDERH 0x05ffffF2 /* short */ -#define TPC_NDERL 0x05ffffF3 /* short */ -#define TPC_NDRB 0x05ffffF4 /* char */ -#define TPC_NDRA 0x05ffffF5 /* char */ -#define TPC_NDRB1 0x05ffffF6 /* char */ -#define TPC_NDRA1 0x05ffffF7 /* char */ - -#endif diff --git a/c/src/exec/score/cpu/sh/rtems/score/iosh7045.h b/c/src/exec/score/cpu/sh/rtems/score/iosh7045.h deleted file mode 100644 index 62918dd958..0000000000 --- a/c/src/exec/score/cpu/sh/rtems/score/iosh7045.h +++ /dev/null @@ -1,321 +0,0 @@ -/* - * This include file contains information pertaining to the Hitachi SH - * processor. - * - * NOTE: NOT ALL VALUES HAVE BEEN CHECKED !! - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which - * contained no copyright notice. - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * Modified to reflect on-chip registers for sh7045 processor, based on - * "Register.h" distributed with Hitachi's EVB7045F tutorials, and which - * contained no copyright notice: - * John M. Mills (jmills@tga.com) - * TGA Technologies, Inc. - * 100 Pinnacle Way, Suite 140 - * Norcross, GA 30071 U.S.A. - * August, 1999 - * - * This modified file may be copied and distributed in accordance - * the above-referenced license. It is provided for critique and - * developmental purposes without any warranty nor representation - * by the authors or by TGA Technologies. - * - * $Id$ - */ - -#ifndef __IOSH7045_H -#define __IOSH7045_H - -/* - * After each line is explained whether the access is char short or long. - * The functions read/writeb, w, l, 8, 16, 32 can be found - * in exec/score/cpu/sh/sh_io.h - * - * 8 bit == char ( readb, writeb, read8, write8) - * 16 bit == short ( readw, writew, read16, write16 ) - * 32 bit == long ( readl, writel, read32, write32 ) - * JMM: Addresses noted "[char, ]short,word" are per Hitachi _SuperH_RISC_ - * ENGINE_..Hardware_Manual; alignment access-restrictions may apply - */ - -#define REG_BASE 0xFFFF8000 - -/* SCI0 Registers */ -#define SCI_SMR0 (REG_BASE + 0x01a0) /*char: Serial mode ch 0 */ -#define SCI_BRR0 (REG_BASE + 0x01a1) /*char: Bit rate ch 0 */ -#define SCI_SCR0 (REG_BASE + 0x01a2) /*char: Serial control ch 0 */ -#define SCI_TDR0 (REG_BASE + 0x01a3) /*char: Transmit data ch 0 */ -#define SCI_SSR0 (REG_BASE + 0x01a4) /*char: Serial status ch 0 */ -#define SCI_RDR0 (REG_BASE + 0x01a5) /*char: Receive data ch 0 */ - -/* SCI1 Registers */ -#define SCI_SMR1 (REG_BASE + 0x01b0) /* char: Serial mode ch 1 */ -#define SCI_BRR1 (REG_BASE + 0x01b1) /* char: Bit rate ch 1 */ -#define SCI_SCR1 (REG_BASE + 0x01b2) /* char: Serial control ch 1 */ -#define SCI_TDR1 (REG_BASE + 0x01b3) /* char: Transmit data ch 1 */ -#define SCI_SSR1 (REG_BASE + 0x01b4) /* char: Serial status ch 1 */ -#define SCI_RDR1 (REG_BASE + 0x01b5) /* char: Receive data ch 1 */ - -/* ADI */ -/* High Speed A/D (Excluding A-Mask Part)*/ -#define ADDRA (REG_BASE + 0x03F0) /* short */ -#define ADDRB (REG_BASE + 0x03F2) /* short */ -#define ADDRC (REG_BASE + 0x03F4) /* short */ -#define ADDRD (REG_BASE + 0x03F6) /* short */ -#define ADDRE (REG_BASE + 0x03F8) /* short */ -#define ADDRF (REG_BASE + 0x03FA) /* short */ -#define ADDRG (REG_BASE + 0x03FC) /* short */ -#define ADDRH (REG_BASE + 0x03FE) /* short */ -#define ADCSR (REG_BASE + 0x03E0) /* char */ -#define ADCR (REG_BASE + 0x03E1) /* char */ - -/* Mid-Speed A/D (A-Mask part)*/ -#define ADDRA0 (REG_BASE + 0x0400) /* char, short */ -#define ADDRA0H (REG_BASE + 0x0400) /* char, short */ -#define ADDRA0L (REG_BASE + 0x0401) /* char */ -#define ADDRB0 (REG_BASE + 0x0402) /* char, short */ -#define ADDRB0H (REG_BASE + 0x0402) /* char, short */ -#define ADDRB0L (REG_BASE + 0x0403) /* char */ -#define ADDRC0 (REG_BASE + 0x0404) /* char, short */ -#define ADDRC0H (REG_BASE + 0x0404) /* char, short */ -#define ADDRC0L (REG_BASE + 0x0405) /* char */ -#define ADDRD0 (REG_BASE + 0x0406) /* char, short */ -#define ADDRD0H (REG_BASE + 0x0406) /* char, short */ -#define ADDRD0L (REG_BASE + 0x0407) /* char */ -#define ADCSR0 (REG_BASE + 0x0410) /* char */ -#define ADCR0 (REG_BASE + 0x0412) /* char */ -#define ADDRA1 (REG_BASE + 0x0408) /* char, short */ -#define ADDRA1H (REG_BASE + 0x0408) /* char, short */ -#define ADDRA1L (REG_BASE + 0x0409) /* char */ -#define ADDRB1 (REG_BASE + 0x040A) /* char, short */ -#define ADDRB1H (REG_BASE + 0x040A) /* char, short */ -#define ADDRB1L (REG_BASE + 0x040B) /* char */ -#define ADDRC1 (REG_BASE + 0x040C) /* char, short */ -#define ADDRC1H (REG_BASE + 0x040C) /* char, short */ -#define ADDRC1L (REG_BASE + 0x040D) /* char */ -#define ADDRD1 (REG_BASE + 0x040E) /* char, short */ -#define ADDRD1H (REG_BASE + 0x040E) /* char, short */ -#define ADDRD1L (REG_BASE + 0x040F) /* char */ -#define ADCSR1 (REG_BASE + 0x0411) /* char */ -#define ADCR1 (REG_BASE + 0x0413) /* char */ - -/*MTU SHARED*/ -#define MTU_TSTR (REG_BASE + 0x0240) /* char, short, word */ -#define MTU_TSYR (REG_BASE + 0x0241) /* char, short, word */ -#define MTU_ICSR (REG_BASE + 0x03C0) /* input lev. CSR */ -#define MTU_OCSR (REG_BASE + 0x03C0) /* output lev. CSR */ - -/*MTU CHANNEL 0*/ -#define MTU_TCR0 (REG_BASE + 0x0260) /* char, short, word */ -#define MTU_TMDR0 (REG_BASE + 0x0261) /* char, short, word */ -#define MTU_TIORH0 (REG_BASE + 0x0262) /* char, short, word */ -#define MTU_TIORL0 (REG_BASE + 0x0263) /* char, short, word */ -#define MTU_TIER0 (REG_BASE + 0x0264) /* char, short, word */ -#define MTU_TSR0 (REG_BASE + 0x0265) /* char, short, word */ -#define MTU_TCNT0 (REG_BASE + 0x0266) /* short, word */ -#define MTU_GR0A (REG_BASE + 0x0268) /* short, word */ -#define MTU_GR0B (REG_BASE + 0x026A) /* short, word */ -#define MTU_GR0C (REG_BASE + 0x026C) /* short, word */ -#define MTU_GR0D (REG_BASE + 0x026E) /* short, word */ - -/*MTU CHANNEL 1*/ -#define MTU_TCR1 (REG_BASE + 0x0280) /* char, short, word */ -#define MTU_TMDR1 (REG_BASE + 0x0281) /* char, short, word */ -#define MTU_TIOR1 (REG_BASE + 0x0282) /* char, short, word */ -#define MTU_TIER1 (REG_BASE + 0x0284) /* char, short, word */ -#define MTU_TSR1 (REG_BASE + 0x0285) /* char, short, word */ -#define MTU_TCNT1 (REG_BASE + 0x0286) /* short, word */ -#define MTU_GR1A (REG_BASE + 0x0288) /* short, word */ -#define MTU_GR1B (REG_BASE + 0x028A) /* short, word */ - -/*MTU CHANNEL 2*/ -#define MTU_TCR2 (REG_BASE + 0x02A0) /* char, short, word */ -#define MTU_TMDR2 (REG_BASE + 0x02A1) /* char, short, word */ -#define MTU_TIOR2 (REG_BASE + 0x02A2) /* char, short, word */ -#define MTU_TIER2 (REG_BASE + 0x02A4) /* char, short, word */ -#define MTU_TSR2 (REG_BASE + 0x02A5) /* char, short, word */ -#define MTU_TCNT2 (REG_BASE + 0x02A6) /* short, word */ -#define MTU_GR2A (REG_BASE + 0x02A8) /* short, word */ -#define MTU_GR2B (REG_BASE + 0x02AA) /* short, word */ - -/*MTU CHANNELS 3-4 SHARED*/ -#define MTU_TOER (REG_BASE + 0x020A) /* char, short, word */ -#define MTU_TOCR (REG_BASE + 0x020B) /* char, short, word */ -#define MTU_TGCR (REG_BASE + 0x020D) /* char, short, word */ -#define MTU_TCDR (REG_BASE + 0x0214) /* short, word */ -#define MTU_TDDR (REG_BASE + 0x0216) /* short, word */ -#define MTU_TCNTS (REG_BASE + 0x0220) /* short, word */ -#define MTU_TCBR (REG_BASE + 0x0222) /* short, word */ - -/*MTU CHANNEL 3*/ -#define MTU_TCR3 (REG_BASE + 0x0200) /* char, short, word */ -#define MTU_TMDR3 (REG_BASE + 0x0202) /* char, short, word */ -#define MTU_TIORH3 (REG_BASE + 0x0204) /* char, short, word */ -#define MTU_TIORL3 (REG_BASE + 0x0205) /* char, short, word */ -#define MTU_TIER3 (REG_BASE + 0x0208) /* char, short, word */ -#define MTU_TSR3 (REG_BASE + 0x022C) /* char, short, word */ -#define MTU_TCNT3 (REG_BASE + 0x0210) /* short, word */ -#define MTU_GR3A (REG_BASE + 0x0218) /* short, word */ -#define MTU_GR3B (REG_BASE + 0x021A) /* short, word */ -#define MTU_GR3C (REG_BASE + 0x0224) /* short, word */ -#define MTU_GR3D (REG_BASE + 0x0226) /* short, word */ - -/*MTU CHANNEL 4*/ -#define MTU_TCR4 (REG_BASE + 0x0201) /* char, short, word */ -#define MTU_TMDR4 (REG_BASE + 0x0203) /* char, short, word */ -#define MTU_TIOR4 (REG_BASE + 0x0206) /* char, short, word */ -#define MTU_TIORH4 (REG_BASE + 0x0206) /* char, short, word */ -#define MTU_TIORL4 (REG_BASE + 0x0207) /* char, short, word */ -#define MTU_TIER4 (REG_BASE + 0x0209) /* char, short, word */ -#define MTU_TSR4 (REG_BASE + 0x022D) /* char, short, word */ -#define MTU_TCNT4 (REG_BASE + 0x0212) /* short, word */ -#define MTU_GR4A (REG_BASE + 0x021C) /* short, word */ -#define MTU_GR4B (REG_BASE + 0x021E) /* short, word */ -#define MTU_GR4C (REG_BASE + 0x0228) /* short, word */ -#define MTU_GR4D (REG_BASE + 0x022A) /* short, word */ - -/*DMAC CHANNELS 0-3 SHARED*/ -#define DMAOR (REG_BASE + 0x06B0) /* short */ - -/*DMAC CHANNEL 0*/ -#define DMA_SAR0 (REG_BASE + 0x06C0) /* short, word */ -#define DMA_DAR0 (REG_BASE + 0x06C4) /* short, word */ -#define DMA_DMATCR0 (REG_BASE + 0x06C8) /* short, word */ -#define DMA_CHCR0 (REG_BASE + 0x06CC) /* short, word */ - -/*DMAC CHANNEL 1*/ -#define DMA_SAR1 (REG_BASE + 0x06D0) /* short, word */ -#define DMA_DAR1 (REG_BASE + 0x06D4) /* short, word */ -#define DMA_DMATCR1 (REG_BASE + 0x06D8) /* short, wordt */ -#define DMA_CHCR1 (REG_BASE + 0x06DC) /* short, word */ - -/*DMAC CHANNEL 3*/ -#define DMA_SAR3 (REG_BASE + 0x06E0) /* short, word */ -#define DMA_DAR3 (REG_BASE + 0x06E4) /* short, word */ -#define DMA_DMATCR3 (REG_BASE + 0x06E8) /* short, word */ -#define DMA_CHCR3 (REG_BASE + 0x06EC) /* short, word */ - -/*DMAC CHANNEL 4*/ -#define DMA_SAR4 (REG_BASE + 0x06F0) /* short, word */ -#define DMA_DAR4 (REG_BASE + 0x06F4) /* short, word */ -#define DMA_DMATCR4 (REG_BASE + 0x06F8) /* short, word */ -#define DMA_CHCR4 (REG_BASE + 0x06FC) /* short, word */ - -/*Data Transfer Controller*/ -#define DTC_DTEA (REG_BASE + 0x0700) /* char, short, word */ -#define DTC_DTEB (REG_BASE + 0x0701) /* char, short(?), word(?) */ -#define DTC_DTEC (REG_BASE + 0x0702) /* char, short(?), word(?) */ -#define DTC_DTED (REG_BASE + 0x0703) /* char, short(?), word(?) */ -#define DTC_DTEE (REG_BASE + 0x0704) /* char, short(?), word(?) */ -#define DTC_DTCSR (REG_BASE + 0x0706) /* char, short, word */ -#define DTC_DTBR (REG_BASE + 0x0708) /* short, word */ - -/*Cache Memory*/ -#define CAC_CCR (REG_BASE + 0x0740) /* char, short, word */ - -/*INTC*/ -#define INTC_IPRA (REG_BASE + 0x0348) /* char, short, word */ -#define INTC_IPRB (REG_BASE + 0x034A) /* char, short, word */ -#define INTC_IPRC (REG_BASE + 0x034C) /* char, short, word */ -#define INTC_IPRD (REG_BASE + 0x034E) /* char, short, word */ -#define INTC_IPRE (REG_BASE + 0x0350) /* char, short, word */ -#define INTC_IPRF (REG_BASE + 0x0352) /* char, short, word */ -#define INTC_IPRG (REG_BASE + 0x0354) /* char, short, word */ -#define INTC_IPRH (REG_BASE + 0x0356) /* char, short, word */ -#define INTC_ICR (REG_BASE + 0x0358) /* char, short, word */ -#define INTC_ISR (REG_BASE + 0x035A) /* char, short, word */ - -/*Flash (F-ZTAT)*/ -#define FL_FLMCR1 (REG_BASE + 0x0580) /* Fl.Mem.Contr.Reg 1: char */ -#define FL_FLMCR2 (REG_BASE + 0x0581) /* Fl.Mem.Contr.Reg 2: char */ -#define FL_EBR1 (REG_BASE + 0x0582) /* Fl.Mem.Erase Blk.1: char */ -#define FL_EBR2 (REG_BASE + 0x0584) /* Fl.Mem.Erase Blk.2: char */ -#define FL_RAMER (REG_BASE + 0x0628) /* Ram Emul.Reg.- char,short,word */ - -/*UBC*/ -#define UBC_BARH (REG_BASE + 0x0600) /* char, short, word */ -#define UBC_BARL (REG_BASE + 0x0602) /* char, short, word */ -#define UBC_BAMRH (REG_BASE + 0x0604) /* char, short, word */ -#define UBC_BAMRL (REG_BASE + 0x0606) /* char, short, word */ -#define UBC_BBR (REG_BASE + 0x0608) /* char, short, word */ -/*BSC*/ -#define BSC_BCR1 (REG_BASE + 0x0620) /* short */ -#define BSC_BCR2 (REG_BASE + 0x0622) /* short */ -#define BSC_WCR1 (REG_BASE + 0x0624) /* short */ -#define BSC_WCR2 (REG_BASE + 0x0626) /* short */ -#define BSC_DCR (REG_BASE + 0x062A) /* short */ -#define BSC_RTCSR (REG_BASE + 0x062C) /* short */ -#define BSC_RTCNT (REG_BASE + 0x062E) /* short */ -#define BSC_RTCOR (REG_BASE + 0x0630) /* short */ - -/*WDT*/ -#define WDT_R_TCSR (REG_BASE + 0x0610) /* rd: char */ -#define WDT_R_TCNT (REG_BASE + 0x0611) /* rd: char */ -#define WDT_R_RSTCSR (REG_BASE + 0x0613) /* rd: char */ -#define WDT_W_TCSR (REG_BASE + 0x0610) /* wrt: short */ -#define WDT_W_TCNT (REG_BASE + 0x0610) /* wrt: short */ -#define WDT_W_RSTCSR (REG_BASE + 0x0612) /* wrt: short */ - -/*POWER DOWN STATE*/ -#define PDT_SBYCR (REG_BASE + 0x0614) /* char */ - -/* Port I/O Control Registers */ -#define IO_PADRH (REG_BASE + 0x0380) /* Port A Data Register */ -#define IO_PADRL (REG_BASE + 0x0382) /* Port A Data Register */ -#define IO_PBDR (REG_BASE + 0x0390) /* Port B Data Register */ -#define IO_PCDR (REG_BASE + 0x0392) /* Port C Data Register */ -#define IO_PDDRH (REG_BASE + 0x03A0) /* Port D Data Register */ -#define IO_PDDRL (REG_BASE + 0x03A2) /* Port D Data Register */ -#define IO_PEDR (REG_BASE + 0x03B0) /* Port E Data Register */ -#define IO_PFDR (REG_BASE + 0x03B2) /* Port F Data Register */ - -/*Pin Function Control Register*/ -#define PFC_PAIORH (REG_BASE + 0x0384) /* Port A I/O Reg. H */ -#define PFC_PAIORL (REG_BASE + 0x0386) /* Port A I/O Reg. L */ -#define PFC_PACRH (REG_BASE + 0x0388) /* Port A Ctr. Reg. H */ -#define PFC_PACRL1 (REG_BASE + 0x038C) /* Port A Ctr. Reg. L1 */ -#define PFC_PACRL2 (REG_BASE + 0x038E) /* Port A Ctr. Reg. L2 */ -#define PFC_PBIOR (REG_BASE + 0x0394) /* Port B I/O Register */ -#define PFC_PBCR1 (REG_BASE + 0x0398) /* Port B Ctr. Reg. R1 */ -#define PFC_PBCR2 (REG_BASE + 0x039A) /* Port B Ctr. Reg. R2 */ -#define PFC_PCIOR (REG_BASE + 0x0396) /* Port C I/O Register */ -#define PFC_PCCR (REG_BASE + 0x039C) /* Port C Ctr. Reg. */ -#define PFC_PDIORH (REG_BASE + 0x03A4) /* Port D I/O Reg. H */ -#define PFC_PDIORL (REG_BASE + 0x03A6) /* Port D I/O Reg. L */ -#define PFC_PDCRH1 (REG_BASE + 0x03A8) /* Port D Ctr. Reg. H1 */ -#define PFC_PDCRH2 (REG_BASE + 0x03AA) /* Port D Ctr. Reg. H2 */ -#define PFC_PDCRL (REG_BASE + 0x03AC) /* Port D Ctr. Reg. L */ -#define PFC_PEIOR (REG_BASE + 0x03B4) /* Port E I/O Register */ -#define PFC_PECR1 (REG_BASE + 0x03B8) /* Port E Ctr. Reg. 1 */ -#define PFC_PECR2 (REG_BASE + 0x03BA) /* Port E Ctr. Reg. 2 */ -#define PFC_IFCR (REG_BASE + 0x03C8) /* short */ - -/*Compare/Match Timer*/ -#define CMT_CMSTR (REG_BASE + 0x3D0) /* Start Reg. char, short, word */ -#define CMT_CMCSR0 (REG_BASE + 0x3D2) /* C0 SCR short, word */ -#define CMT_CMCNT0 (REG_BASE + 0x3D4) /* C0 Counter char, short, word */ -#define CMT_CMCOR0 (REG_BASE + 0x3D6) /* C0 Const.Reg. char, short, word */ -#define CMT_CMCSR1 (REG_BASE + 0x3D8) /* C1 SCR short, word */ -#define CMT_CMCNT1 (REG_BASE + 0x3DA) /* C1 Counter char, short, word */ -#define CMT_CMCOR1 (REG_BASE + 0x3DC) /* C1 Const.Reg. char, short, word */ - -#endif diff --git a/c/src/exec/score/cpu/sh/rtems/score/ispsh7032.h b/c/src/exec/score/cpu/sh/rtems/score/ispsh7032.h deleted file mode 100644 index 3f9baf1ad2..0000000000 --- a/c/src/exec/score/cpu/sh/rtems/score/ispsh7032.h +++ /dev/null @@ -1,165 +0,0 @@ -/* - * This include file contains information pertaining to the Hitachi SH - * processor. - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -#ifndef __CPU_ISPS_H -#define __CPU_ISPS_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/shtypes.h> - -extern void __ISR_Handler( unsigned32 vector ); - - -/* - * interrupt vector table offsets - */ -#define NMI_ISP_V 11 -#define USB_ISP_V 12 -#define IRQ0_ISP_V 64 -#define IRQ1_ISP_V 65 -#define IRQ2_ISP_V 66 -#define IRQ3_ISP_V 67 -#define IRQ4_ISP_V 68 -#define IRQ5_ISP_V 69 -#define IRQ6_ISP_V 70 -#define IRQ7_ISP_V 71 -#define DMA0_ISP_V 72 -#define DMA1_ISP_V 74 -#define DMA2_ISP_V 76 -#define DMA3_ISP_V 78 - -#define IMIA0_ISP_V 80 -#define IMIB0_ISP_V 81 -#define OVI0_ISP_V 82 - -#define IMIA1_ISP_V 84 -#define IMIB1_ISP_V 85 -#define OVI1_ISP_V 86 - -#define IMIA2_ISP_V 88 -#define IMIB2_ISP_V 89 -#define OVI2_ISP_V 90 - -#define IMIA3_ISP_V 92 -#define IMIB3_ISP_V 93 -#define OVI3_ISP_V 94 - -#define IMIA4_ISP_V 96 -#define IMIB4_ISP_V 97 -#define OVI4_ISP_V 98 - -#define ERI0_ISP_V 100 -#define RXI0_ISP_V 101 -#define TXI0_ISP_V 102 -#define TEI0_ISP_V 103 - -#define ERI1_ISP_V 104 -#define RXI1_ISP_V 105 -#define TXI1_ISP_V 106 -#define TEI1_ISP_V 107 - -#define PRT_ISP_V 108 -#define ADU_ISP_V 109 -#define WDT_ISP_V 112 -#define DREF_ISP_V 113 - - -/* dummy ISP */ -extern void _dummy_isp( void ); - -/* Non Maskable Interrupt */ -extern void _nmi_isp( void ); - -/* User Break Controller */ -extern void _usb_isp( void ); - -/* External interrupts 0-7 */ -extern void _irq0_isp( void ); -extern void _irq1_isp( void ); -extern void _irq2_isp( void ); -extern void _irq3_isp( void ); -extern void _irq4_isp( void ); -extern void _irq5_isp( void ); -extern void _irq6_isp( void ); -extern void _irq7_isp( void ); - -/* DMA - Controller */ -extern void _dma0_isp( void ); -extern void _dma1_isp( void ); -extern void _dma2_isp( void ); -extern void _dma3_isp( void ); - -/* Interrupt Timer Unit */ -/* Timer 0 */ -extern void _imia0_isp( void ); -extern void _imib0_isp( void ); -extern void _ovi0_isp( void ); -/* Timer 1 */ -extern void _imia1_isp( void ); -extern void _imib1_isp( void ); -extern void _ovi1_isp( void ); -/* Timer 2 */ -extern void _imia2_isp( void ); -extern void _imib2_isp( void ); -extern void _ovi2_isp( void ); -/* Timer 3 */ -extern void _imia3_isp( void ); -extern void _imib3_isp( void ); -extern void _ovi3_isp( void ); -/* Timer 4 */ -extern void _imia4_isp( void ); -extern void _imib4_isp( void ); -extern void _ovi4_isp( void ); - -/* seriell interfaces */ -extern void _eri0_isp( void ); -extern void _rxi0_isp( void ); -extern void _txi0_isp( void ); -extern void _tei0_isp( void ); -extern void _eri1_isp( void ); -extern void _rxi1_isp( void ); -extern void _txi1_isp( void ); -extern void _tei1_isp( void ); - -/* Parity Control Unit of the Bus State Controllers */ -extern void _prt_isp( void ); - -/* ADC */ -extern void _adu_isp( void ); - -/* Watchdog Timer */ -extern void _wdt_isp( void ); - -/* DRAM refresh control unit of bus state controller */ -extern void _dref_isp( void ); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/exec/score/cpu/sh/rtems/score/ispsh7045.h b/c/src/exec/score/cpu/sh/rtems/score/ispsh7045.h deleted file mode 100644 index e711bb1a21..0000000000 --- a/c/src/exec/score/cpu/sh/rtems/score/ispsh7045.h +++ /dev/null @@ -1,211 +0,0 @@ -/* - * This include file contains information pertaining to the Hitachi SH - * processor. - * - * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and - * Bernd Becker (becker@faw.uni-ulm.de) - * - * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * - * COPYRIGHT (c) 1998. - * On-Line Applications Research Corporation (OAR). - * Copyright assigned to U.S. Government, 1994. - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * Modified to reflect isp entries for sh7045 processor: - * John M. Mills (jmills@tga.com) - * TGA Technologies, Inc. - * 100 Pinnacle Way, Suite 140 - * Norcross, GA 30071 U.S.A. - * - * - * This modified file may be copied and distributed in accordance - * the above-referenced license. It is provided for critique and - * developmental purposes without any warranty nor representation - * by the authors or by TGA Technologies. - * - * $Id$ - */ - -#ifndef __CPU_ISPS_H -#define __CPU_ISPS_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/shtypes.h> - -extern void __ISR_Handler( unsigned32 vector ); - - -/* - * interrupt vector table offsets - */ -#define NMI_ISP_V 11 -#define USB_ISP_V 12 -#define IRQ0_ISP_V 64 -#define IRQ1_ISP_V 65 -#define IRQ2_ISP_V 66 -#define IRQ3_ISP_V 67 -#define IRQ4_ISP_V 68 -#define IRQ5_ISP_V 69 -#define IRQ6_ISP_V 70 -#define IRQ7_ISP_V 71 -#define DMA0_ISP_V 72 -#define DMA1_ISP_V 76 -#define DMA2_ISP_V 80 -#define DMA3_ISP_V 84 - -#define MTUA0_ISP_V 88 -#define MTUB0_ISP_V 89 -#define MTUC0_ISP_V 90 -#define MTUD0_ISP_V 91 -#define MTUV0_ISP_V 92 - -#define MTUA1_ISP_V 96 -#define MTUB1_ISP_V 97 -#define MTUV1_ISP_V 100 -#define MTUU1_ISP_V 101 - -#define MTUA2_ISP_V 104 -#define MTUB2_ISP_V 105 -#define MTUV2_ISP_V 108 -#define MTUU2_ISP_V 109 - -#define MTUA3_ISP_V 112 -#define MTUB3_ISP_V 113 -#define MTUC3_ISP_V 114 -#define MTUD3_ISP_V 115 -#define MTUV3_ISP_V 116 - -#define MTUA4_ISP_V 120 -#define MTUB4_ISP_V 121 -#define MTUC4_ISP_V 122 -#define MTUD4_ISP_V 123 -#define MTUV4_ISP_V 124 - -#define ERI0_ISP_V 128 -#define RXI0_ISP_V 129 -#define TXI0_ISP_V 130 -#define TEI0_ISP_V 131 - -#define ERI1_ISP_V 132 -#define RXI1_ISP_V 133 -#define TXI1_ISP_V 134 -#define TEI1_ISP_V 135 - -#define ADI0_ISP_V 136 -#define ADI1_ISP_V 137 -#define DTC_ISP_V 140 /* Data Transfer Controller */ -#define CMT0_ISP_V 144 /* Compare Match Timer */ -#define CMT1_ISP_V 148 -#define WDT_ISP_V 152 /* Wtachdog Timer */ -#define CMI_ISP_V 153 /* BSC RAS interrupt */ -#define OEI_ISP_V 156 /* I/O Port */ -#define DREF_ISP_V CMI_ISP_V /* DRAM Refresh from BSC */ -#if 0 -#define PRT_ISP_V /* parity error - no equivalent */ -#endif - -/* dummy ISP */ -extern void _dummy_isp( void ); - -/* Non Maskable Interrupt */ -extern void _nmi_isp( void ); - -/* User Break Controller */ -extern void _usb_isp( void ); - -/* External interrupts 0-7 */ -extern void _irq0_isp( void ); -extern void _irq1_isp( void ); -extern void _irq2_isp( void ); -extern void _irq3_isp( void ); -extern void _irq4_isp( void ); -extern void _irq5_isp( void ); -extern void _irq6_isp( void ); -extern void _irq7_isp( void ); - -/* DMA - Controller */ -extern void _dma0_isp( void ); -extern void _dma1_isp( void ); -extern void _dma2_isp( void ); -extern void _dma3_isp( void ); - -/* Interrupt Timer Unit */ -/* Timer 0 */ -extern void _mtua0_isp( void ); -extern void _mtub0_isp( void ); -extern void _mtuc0_isp( void ); -extern void _mtud0_isp( void ); -extern void _mtuv0_isp( void ); -/* Timer 1 */ -extern void _mtua1_isp( void ); -extern void _mtub1_isp( void ); -extern void _mtuv1_isp( void ); -extern void _mtuu1_isp( void ); -/* Timer 2 */ -extern void _mtua2_isp( void ); -extern void _mtub2_isp( void ); -extern void _mtuv2_isp( void ); -extern void _mtuu2_isp( void ); -/* Timer 3 */ -extern void _mtua3_isp( void ); -extern void _mtub3_isp( void ); -extern void _mtuc3_isp( void ); -extern void _mtud3_isp( void ); -extern void _mtuv3_isp( void ); -/* Timer 4 */ -extern void _mtua4_isp( void ); -extern void _mtub4_isp( void ); -extern void _mtuc4_isp( void ); -extern void _mtud4_isp( void ); -extern void _mtuv4_isp( void ); - -/* serial interfaces */ -extern void _eri0_isp( void ); -extern void _rxi0_isp( void ); -extern void _txi0_isp( void ); -extern void _tei0_isp( void ); -extern void _eri1_isp( void ); -extern void _rxi1_isp( void ); -extern void _txi1_isp( void ); -extern void _tei1_isp( void ); - -/* ADC */ -extern void _adi0_isp( void ); -extern void _adi1_isp( void ); - -/* Data Transfer Controller */ -extern void _dtci_isp( void ); - -/* Compare Match Timer */ -extern void _cmt0_isp( void ); -extern void _cmt1_isp( void ); - -/* Watchdog Timer */ -extern void _wdt_isp( void ); - -/* DRAM refresh control unit of bus state controller */ -extern void _bsc_isp( void ); - -/* I/O Port */ -extern void _oei_isp( void ); - -/* Parity Control Unit of the Bus State Controllers */ -/* extern void _prt_isp( void ); */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/exec/score/cpu/sh/rtems/score/sh.h b/c/src/exec/score/cpu/sh/rtems/score/sh.h index 26c633c190..2834ea6c64 100644 --- a/c/src/exec/score/cpu/sh/rtems/score/sh.h +++ b/c/src/exec/score/cpu/sh/rtems/score/sh.h @@ -40,6 +40,7 @@ extern "C" { */ #if defined(rtems_multilib) + /* * Figure out all CPU Model Feature Flags based upon compiler * predefines. @@ -49,19 +50,19 @@ extern "C" { #define SH_HAS_FPU 0 #define SH_HAS_SEPARATE_STACKS 1 -#elif defined(sh7032) -#define CPU_MODEL_NAME "SH7032" -#define SH_HAS_FPU 0 - -#elif defined (sh7045) -#define CPU_MODEL_NAME "SH7045" -#define SH_HAS_FPU 0 +#else +#if defined(__sh1__) || defined(__sh2__) || defined(__sh3__) +#define SH_HAS_FPU 0 #else -#error "Unsupported CPU Model" - +#define SH_HAS_FPU 1 #endif +/* this should not be here */ +#define CPU_MODEL_NAME "SH-Multilib" + +#endif /* multilib */ + /* * If the following macro is set to 0 there will be no software irq stack */ |