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-rw-r--r--c/src/exec/score/cpu/sh/rtems/score/Makefile.in3
-rw-r--r--c/src/exec/score/cpu/sh/rtems/score/cpu.h9
-rw-r--r--c/src/exec/score/cpu/sh/rtems/score/cpu_isps.h165
-rw-r--r--c/src/exec/score/cpu/sh/rtems/score/iosh7030.h223
-rw-r--r--c/src/exec/score/cpu/sh/rtems/score/sh.h9
5 files changed, 17 insertions, 392 deletions
diff --git a/c/src/exec/score/cpu/sh/rtems/score/Makefile.in b/c/src/exec/score/cpu/sh/rtems/score/Makefile.in
index bd536daf80..72b3471072 100644
--- a/c/src/exec/score/cpu/sh/rtems/score/Makefile.in
+++ b/c/src/exec/score/cpu/sh/rtems/score/Makefile.in
@@ -18,7 +18,8 @@ C_PIECES =
C_FILES = $(C_PIECES:%=%.c)
C_O_FILES = $(C_PIECES:%=${ARCH}/%.o)
-H_PIECES = cpu.h shtypes.h sh.h sh_io.h cpu_isps.h iosh7030.h
+H_PIECES = cpu.h shtypes.h sh.h sh_io.h isp$(RTEMS_CPU_MODEL).h \
+ io$(RTEMS_CPU_MODEL).h
H_FILES = $(H_PIECES:%=$(srcdir)/%)
# Assembly source names, if any, go here -- minus the .S
diff --git a/c/src/exec/score/cpu/sh/rtems/score/cpu.h b/c/src/exec/score/cpu/sh/rtems/score/cpu.h
index 8a18848f09..dedd11c055 100644
--- a/c/src/exec/score/cpu/sh/rtems/score/cpu.h
+++ b/c/src/exec/score/cpu/sh/rtems/score/cpu.h
@@ -377,6 +377,7 @@ typedef struct {
void * (*stack_allocate_hook)( unsigned32 );
void (*stack_free_hook)( void* );
/* end of fields required on all CPUs */
+ unsigned32 clicks_per_second ; /* cpu frequency in Hz */
} rtems_cpu_table;
/*
@@ -388,8 +389,9 @@ typedef struct {
* Macros to access SH specific additions to the CPU Table
*/
-/* There are no CPU specific additions to the CPU Table for this port. */
-
+#define rtems_cpu_configuration_get_clicks_per_second() \
+ (_CPU_Table.clicks_per_second)
+
/*
* This variable is optional. It is used on CPUs on which it is difficult
* to generate an "uninitialized" FP context. It is filled in by
@@ -434,6 +436,7 @@ SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)();
*/
/* XXX: if needed, put more variables here */
+SCORE_EXTERN void CPU_delay( unsigned32 microseconds );
/*
* The size of the floating point context area. On some CPUs this
@@ -637,7 +640,7 @@ SCORE_EXTERN void _CPU_Context_Initialize(
*
* Other models include (1) not doing anything, and (2) putting
* a "null FP status word" in the correct place in the FP context.
- * SH has no FPU !!!!!!!!!!!!
+ * SH1, SH2, SH3 have no FPU, but the SH3e and SH4 have.
*/
#define _CPU_Context_Initialize_fp( _destination ) \
diff --git a/c/src/exec/score/cpu/sh/rtems/score/cpu_isps.h b/c/src/exec/score/cpu/sh/rtems/score/cpu_isps.h
deleted file mode 100644
index 3f9baf1ad2..0000000000
--- a/c/src/exec/score/cpu/sh/rtems/score/cpu_isps.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * This include file contains information pertaining to the Hitachi SH
- * processor.
- *
- * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
- * Bernd Becker (becker@faw.uni-ulm.de)
- *
- * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- *
- *
- * COPYRIGHT (c) 1998.
- * On-Line Applications Research Corporation (OAR).
- * Copyright assigned to U.S. Government, 1994.
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.OARcorp.com/rtems/license.html.
- *
- * $Id$
- */
-
-#ifndef __CPU_ISPS_H
-#define __CPU_ISPS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rtems/score/shtypes.h>
-
-extern void __ISR_Handler( unsigned32 vector );
-
-
-/*
- * interrupt vector table offsets
- */
-#define NMI_ISP_V 11
-#define USB_ISP_V 12
-#define IRQ0_ISP_V 64
-#define IRQ1_ISP_V 65
-#define IRQ2_ISP_V 66
-#define IRQ3_ISP_V 67
-#define IRQ4_ISP_V 68
-#define IRQ5_ISP_V 69
-#define IRQ6_ISP_V 70
-#define IRQ7_ISP_V 71
-#define DMA0_ISP_V 72
-#define DMA1_ISP_V 74
-#define DMA2_ISP_V 76
-#define DMA3_ISP_V 78
-
-#define IMIA0_ISP_V 80
-#define IMIB0_ISP_V 81
-#define OVI0_ISP_V 82
-
-#define IMIA1_ISP_V 84
-#define IMIB1_ISP_V 85
-#define OVI1_ISP_V 86
-
-#define IMIA2_ISP_V 88
-#define IMIB2_ISP_V 89
-#define OVI2_ISP_V 90
-
-#define IMIA3_ISP_V 92
-#define IMIB3_ISP_V 93
-#define OVI3_ISP_V 94
-
-#define IMIA4_ISP_V 96
-#define IMIB4_ISP_V 97
-#define OVI4_ISP_V 98
-
-#define ERI0_ISP_V 100
-#define RXI0_ISP_V 101
-#define TXI0_ISP_V 102
-#define TEI0_ISP_V 103
-
-#define ERI1_ISP_V 104
-#define RXI1_ISP_V 105
-#define TXI1_ISP_V 106
-#define TEI1_ISP_V 107
-
-#define PRT_ISP_V 108
-#define ADU_ISP_V 109
-#define WDT_ISP_V 112
-#define DREF_ISP_V 113
-
-
-/* dummy ISP */
-extern void _dummy_isp( void );
-
-/* Non Maskable Interrupt */
-extern void _nmi_isp( void );
-
-/* User Break Controller */
-extern void _usb_isp( void );
-
-/* External interrupts 0-7 */
-extern void _irq0_isp( void );
-extern void _irq1_isp( void );
-extern void _irq2_isp( void );
-extern void _irq3_isp( void );
-extern void _irq4_isp( void );
-extern void _irq5_isp( void );
-extern void _irq6_isp( void );
-extern void _irq7_isp( void );
-
-/* DMA - Controller */
-extern void _dma0_isp( void );
-extern void _dma1_isp( void );
-extern void _dma2_isp( void );
-extern void _dma3_isp( void );
-
-/* Interrupt Timer Unit */
-/* Timer 0 */
-extern void _imia0_isp( void );
-extern void _imib0_isp( void );
-extern void _ovi0_isp( void );
-/* Timer 1 */
-extern void _imia1_isp( void );
-extern void _imib1_isp( void );
-extern void _ovi1_isp( void );
-/* Timer 2 */
-extern void _imia2_isp( void );
-extern void _imib2_isp( void );
-extern void _ovi2_isp( void );
-/* Timer 3 */
-extern void _imia3_isp( void );
-extern void _imib3_isp( void );
-extern void _ovi3_isp( void );
-/* Timer 4 */
-extern void _imia4_isp( void );
-extern void _imib4_isp( void );
-extern void _ovi4_isp( void );
-
-/* seriell interfaces */
-extern void _eri0_isp( void );
-extern void _rxi0_isp( void );
-extern void _txi0_isp( void );
-extern void _tei0_isp( void );
-extern void _eri1_isp( void );
-extern void _rxi1_isp( void );
-extern void _txi1_isp( void );
-extern void _tei1_isp( void );
-
-/* Parity Control Unit of the Bus State Controllers */
-extern void _prt_isp( void );
-
-/* ADC */
-extern void _adu_isp( void );
-
-/* Watchdog Timer */
-extern void _wdt_isp( void );
-
-/* DRAM refresh control unit of bus state controller */
-extern void _dref_isp( void );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/c/src/exec/score/cpu/sh/rtems/score/iosh7030.h b/c/src/exec/score/cpu/sh/rtems/score/iosh7030.h
deleted file mode 100644
index 48463aed47..0000000000
--- a/c/src/exec/score/cpu/sh/rtems/score/iosh7030.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * This include file contains information pertaining to the Hitachi SH
- * processor.
- *
- * NOTE: NOT ALL VALUES HAVE BEEN CHECKED !!
- *
- * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
- * Bernd Becker (becker@faw.uni-ulm.de)
- *
- * Based on "iosh7030.h" distributed with Hitachi's EVB's tutorials, which
- * contained no copyright notice.
- *
- * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- *
- *
- * COPYRIGHT (c) 1998.
- * On-Line Applications Research Corporation (OAR).
- * Copyright assigned to U.S. Government, 1994.
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.OARcorp.com/rtems/license.html.
- *
- * $Id$
- */
-
-#ifndef __IOSH7030_H
-#define __IOSH7030_H
-
-/*
- * After each line is explained whether the access is char short or long.
- * The functions read/writeb, w, l, 8, 16, 32 can be found
- * in exec/score/cpu/sh/sh_io.h
- *
- * 8 bit == char ( readb, writeb, read8, write8)
- * 16 bit == short ( readw, writew, read16, write16 )
- * 32 bit == long ( readl, writel, read32, write32 )
- */
-
-#define SCI0_SMR 0x05fffec0 /* char */
-#define SCI0_BRR 0x05fffec1 /* char */
-#define SCI0_SCR 0x05fffec2 /* char */
-#define SCI0_TDR 0x05fffec3 /* char */
-#define SCI0_SSR 0x05fffec4 /* char */
-#define SCI0_RDR 0x05fffec5 /* char */
-
-#define SCI1_SMR 0x05fffec8 /* char */
-#define SCI1_BRR 0x05fffec9 /* char */
-#define SCI1_SCR 0x05fffeca /* char */
-#define SCI1_TDR 0x05fffecb /* char */
-#define SCI1_SSR 0x05fffecc /* char */
-#define SCI1_RDR 0x05fffecd /* char */
-
-
-#define ADDRAH 0x05fffee0 /* char */
-#define ADDRAL 0x05fffee1 /* char */
-#define ADDRBH 0x05fffee2 /* char */
-#define ADDRBL 0x05fffee3 /* char */
-#define ADDRCH 0x05fffee4 /* char */
-#define ADDRCL 0x05fffee5 /* char */
-#define ADDRDH 0x05fffee6 /* char */
-#define ADDRDL 0x05fffee7 /* char */
-#define AD_DRA 0x05fffee0 /* short */
-#define AD_DRB 0x05fffee2 /* short */
-#define AD_DRC 0x05fffee4 /* short */
-#define AD_DRD 0x05fffee6 /* short */
-#define ADCSR 0x05fffee8 /* char */
-#define ADCR 0x05fffee9 /* char */
-
-/*ITU SHARED*/
-#define ITU_TSTR 0x05ffff00 /* char */
-#define ITU_TSNC 0x05ffff01 /* char */
-#define ITU_TMDR 0x05ffff02 /* char */
-#define ITU_TFCR 0x05ffff03 /* char */
-
-/*ITU CHANNEL 0*/
-#define ITU_TCR0 0x05ffff04 /* char */
-#define ITU_TIOR0 0x05ffff05 /* char */
-#define ITU_TIER0 0x05ffff06 /* char */
-#define ITU_TSR0 0x05ffff07 /* char */
-#define ITU_TCNT0 0x05ffff08 /* short */
-#define ITU_GRA0 0x05ffff0a /* short */
-#define ITU_GRB0 0x05ffff0c /* short */
-
- /*ITU CHANNEL 1*/
-#define ITU_TCR1 0x05ffff0E /* char */
-#define ITU_TIOR1 0x05ffff0F /* char */
-#define ITU_TIER1 0x05ffff10 /* char */
-#define ITU_TSR1 0x05ffff11 /* char */
-#define ITU_TCNT1 0x05ffff12 /* short */
-#define ITU_GRA1 0x05ffff14 /* short */
-#define ITU_GRB1 0x05ffff16 /* short */
-
-
- /*ITU CHANNEL 2*/
-#define ITU_TCR2 0x05ffff18 /* char */
-#define ITU_TIOR2 0x05ffff19 /* char */
-#define ITU_TIER2 0x05ffff1A /* char */
-#define ITU_TSR2 0x05ffff1B /* char */
-#define ITU_TCNT2 0x05ffff1C /* short */
-#define ITU_GRA2 0x05ffff1E /* short */
-#define ITU_GRB2 0x05ffff20 /* short */
-
- /*ITU CHANNEL 3*/
-#define ITU_TCR3 0x05ffff22 /* char */
-#define ITU_TIOR3 0x05ffff23 /* char */
-#define ITU_TIER3 0x05ffff24 /* char */
-#define ITU_TSR3 0x05ffff25 /* char */
-#define ITU_TCNT3 0x05ffff26 /* short */
-#define ITU_GRA3 0x05ffff28 /* short */
-#define ITU_GRB3 0x05ffff2A /* short */
-#define ITU_BRA3 0x05ffff2C /* short */
-#define ITU_BRB3 0x05ffff2E /* short */
-
- /*ITU CHANNELS 0-4 SHARED*/
-#define ITU_TOCR 0x05ffff31 /* char */
-
- /*ITU CHANNEL 4*/
-#define ITU_TCR4 0x05ffff32 /* char */
-#define ITU_TIOR4 0x05ffff33 /* char */
-#define ITU_TIER4 0x05ffff34 /* char */
-#define ITU_TSR4 0x05ffff35 /* char */
-#define ITU_TCNT4 0x05ffff36 /* short */
-#define ITU_GRA4 0x05ffff38 /* short */
-#define ITU_GRB4 0x05ffff3A /* short */
-#define ITU_BRA4 0x05ffff3C /* short */
-#define ITU_BRB4 0x05ffff3E /* short */
-
- /*DMAC CHANNELS 0-3 SHARED*/
-#define DMAOR 0x05ffff48 /* short */
-
- /*DMAC CHANNEL 0*/
-#define DMA_SAR0 0x05ffff40 /* long */
-#define DMA_DAR0 0x05ffff44 /* long */
-#define DMA_TCR0 0x05ffff4a /* short */
-#define DMA_CHCR0 0x05ffff4e /* short */
-
- /*DMAC CHANNEL 1*/
-#define DMA_SAR1 0x05ffff50 /* long */
-#define DMA_DAR1 0x05ffff54 /* long */
-#define DMA_TCR1 0x05fffF5a /* short */
-#define DMA_CHCR1 0x05ffff5e /* short */
-
- /*DMAC CHANNEL 3*/
-#define DMA_SAR3 0x05ffff60 /* long */
-#define DMA_DAR3 0x05ffff64 /* long */
-#define DMA_TCR3 0x05fffF6a /* short */
-#define DMA_CHCR3 0x05ffff6e /* short */
-
-/*DMAC CHANNEL 4*/
-#define DMA_SAR4 0x05ffff70 /* long */
-#define DMA_DAR4 0x05ffff74 /* long */
-#define DMA_TCR4 0x05fffF7a /* short */
-#define DMA_CHCR4 0x05ffff7e /* short */
-
-/*INTC*/
-#define INTC_IPRA 0x05ffff84 /* short */
-#define INTC_IPRB 0x05ffff86 /* short */
-#define INTC_IPRC 0x05ffff88 /* short */
-#define INTC_IPRD 0x05ffff8A /* short */
-#define INTC_IPRE 0x05ffff8C /* short */
-#define INTC_ICR 0x05ffff8E /* short */
-
-/*UBC*/
-#define UBC_BARH 0x05ffff90 /* short */
-#define UBC_BARL 0x05ffff92 /* short */
-#define UBC_BAMRH 0x05ffff94 /* short */
-#define UBC_BAMRL 0x05ffff96 /* short */
-#define UBC_BBR 0x05ffff98 /* short */
-
-/*BSC*/
-#define BSC_BCR 0x05ffffA0 /* short */
-#define BSC_WCR1 0x05ffffA2 /* short */
-#define BSC_WCR2 0x05ffffA4 /* short */
-#define BSC_WCR3 0x05ffffA6 /* short */
-#define BSC_DCR 0x05ffffA8 /* short */
-#define BSC_PCR 0x05ffffAA /* short */
-#define BSC_RCR 0x05ffffAC /* short */
-#define BSC_RTCSR 0x05ffffAE /* short */
-#define BSC_RTCNT 0x05ffffB0 /* short */
-#define BSC_RTCOR 0x05ffffB2 /* short */
-
-/*WDT*/
-#define WDT_TCSR 0x05ffffB8 /* char */
-#define WDT_TCNT 0x05ffffB9 /* char */
-#define WDT_RSTCSR 0x05ffffBB /* char */
-
-/*POWER DOWN STATE*/
-#define PDT_SBYCR 0x05ffffBC /* char */
-
-/*PORT A*/
-#define PADR 0x05ffffC0 /* short */
-
-/*PORT B*/
-#define PBDR 0x05ffffC2 /* short */
-
- /*PORT C*/
-#define PCDR 0x05ffffD0 /* short */
-
-/*PFC*/
-#define PFC_PAIOR 0x05ffffC4 /* short */
-#define PFC_PBIOR 0x05ffffC6 /* short */
-#define PFC_PACR1 0x05ffffC8 /* short */
-#define PFC_PACR2 0x05ffffCA /* short */
-#define PFC_PBCR1 0x05ffffCC /* short */
-#define PFC_PBCR2 0x05ffffCE /* short */
-#define PFC_CASCR 0x05ffffEE /* short */
-
-/*TPC*/
-#define TPC_TPMR 0x05ffffF0 /* short */
-#define TPC_TPCR 0x05ffffF1 /* short */
-#define TPC_NDERH 0x05ffffF2 /* short */
-#define TPC_NDERL 0x05ffffF3 /* short */
-#define TPC_NDRB 0x05ffffF4 /* char */
-#define TPC_NDRA 0x05ffff5F /* char */
-#define TPC_NDRB1 0x05ffffF6 /* char */
-#define TPC_NDRA1 0x05ffffF7 /* char */
-
-#endif
diff --git a/c/src/exec/score/cpu/sh/rtems/score/sh.h b/c/src/exec/score/cpu/sh/rtems/score/sh.h
index 96e10bfb1b..45228c5fe0 100644
--- a/c/src/exec/score/cpu/sh/rtems/score/sh.h
+++ b/c/src/exec/score/cpu/sh/rtems/score/sh.h
@@ -42,7 +42,16 @@ extern "C" {
#if defined(sh7032)
#define CPU_MODEL_NAME "SH 7032"
+#define SH_HAS_FPU 0
+
+/*
+ * If the following macro is set to 0 there will be no software irq stack
+ */
+#define SH_HAS_SEPARATE_STACKS 1
+
+#elif defined (sh7045)
+#define CPU_MODEL_NAME "SH 7045"
#define SH_HAS_FPU 0
/*