diff options
Diffstat (limited to '')
| -rw-r--r-- | c/src/exec/score/cpu/powerpc/mpc750/cpu.h (renamed from c/src/exec/score/cpu/powerpc/rtems/score/cpu.h) | 275 |
1 files changed, 38 insertions, 237 deletions
diff --git a/c/src/exec/score/cpu/powerpc/rtems/score/cpu.h b/c/src/exec/score/cpu/powerpc/mpc750/cpu.h index 0bb28110d4..e3ea78eb82 100644 --- a/c/src/exec/score/cpu/powerpc/rtems/score/cpu.h +++ b/c/src/exec/score/cpu/powerpc/mpc750/cpu.h @@ -24,7 +24,7 @@ * On-Line Applications Research Corporation (OAR). * Copyright assigned to U.S. Government, 1994. * - * The license and distribution terms for this file may in + * The license and distribution terms for this file may be found in * the file LICENSE in this distribution or at * http://www.OARcorp.com/rtems/license.html. * @@ -39,9 +39,9 @@ extern "C" { #endif #include <rtems/score/ppc.h> /* pick up machine definitions */ +#include <libcpu/cpu.h> + #ifndef ASM -struct CPU_Interrupt_frame; - #include <rtems/score/ppctypes.h> #endif @@ -110,7 +110,7 @@ struct CPU_Interrupt_frame; * procedure on that CPU. */ -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE +#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE /* * Does this CPU have hardware support for a dedicated interrupt stack? @@ -127,12 +127,7 @@ struct CPU_Interrupt_frame; * procedure on that CPU. */ -/* - * ACB: This is a lie, but it gets us a handle on a call to set up - * a variable derived from the top of the interrupt stack. - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE +#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE /* * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? @@ -144,7 +139,7 @@ struct CPU_Interrupt_frame; * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. */ -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE +#define CPU_ALLOCATE_INTERRUPT_STACK FALSE /* * Does the RTEMS invoke the user's ISR with the vector number and @@ -152,7 +147,7 @@ struct CPU_Interrupt_frame; * number (0)? */ -#define CPU_ISR_PASSES_FRAME_POINTER 1 +#define CPU_ISR_PASSES_FRAME_POINTER 0 /* * Does the CPU have hardware floating point? @@ -304,31 +299,6 @@ struct CPU_Interrupt_frame; #define CPU_BIG_ENDIAN TRUE #define CPU_LITTLE_ENDIAN FALSE -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - * - * The interrupt level is bit mapped for the PowerPC family. The - * bits are set to 0 to indicate that a particular exception source - * enabled and 1 if it is disabled. This keeps with RTEMS convention - * that interrupt level 0 means all sources are enabled. - * - * The bits are assigned to correspond to enable bits in the MSR. - */ - -#define PPC_INTERRUPT_LEVEL_ME 0x01 -#define PPC_INTERRUPT_LEVEL_EE 0x02 -#define PPC_INTERRUPT_LEVEL_CE 0x04 - -/* XXX should these be maskable? */ -#if 0 -#define PPC_INTERRUPT_LEVEL_DE 0x08 -#define PPC_INTERRUPT_LEVEL_BE 0x10 -#define PPC_INTERRUPT_LEVEL_SE 0x20 -#endif - -#define CPU_MODES_INTERRUPT_MASK 0x00000007 /* * Processor defined structures @@ -419,12 +389,8 @@ typedef struct { typedef struct CPU_Interrupt_frame { unsigned32 stacklink; /* Ensure this is a real frame (also reg1 save) */ -#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) - unsigned32 dummy[13]; /* Used by callees: PowerOpen ABI */ -#else - unsigned32 dummy[1]; /* Used by callees: SVR4/EABI */ -#endif - /* This is what is left out of the primary contexts */ + unsigned32 calleeLr; /* link register used by callees: SVR4/EABI */ + /* This is what is left out of the primary contexts */ unsigned32 gpr0; unsigned32 gpr2; /* play safe */ unsigned32 gpr3; @@ -450,8 +416,7 @@ typedef struct CPU_Interrupt_frame { unsigned32 msr; unsigned32 pad[3]; } CPU_Interrupt_frame; - - + /* * The following table contains the information required to configure * the PowerPC processor specific parameters. @@ -471,42 +436,11 @@ typedef struct { /* end of fields required on all CPUs */ unsigned32 clicks_per_usec; /* Timer clicks per microsecond */ - void (*spurious_handler)(unsigned32 vector, CPU_Interrupt_frame *); boolean exceptions_in_RAM; /* TRUE if in RAM */ -#if (defined(ppc403) || defined(mpc860) || defined(mpc821)) - unsigned32 serial_per_sec; /* Serial clocks per second */ - boolean serial_external_clock; - boolean serial_xon_xoff; - boolean serial_cts_rts; - unsigned32 serial_rate; - unsigned32 timer_average_overhead; /* Average overhead of timer in ticks */ - unsigned32 timer_least_valid; /* Least valid number from timer */ - boolean timer_internal_clock; /* TRUE, when timer runs with CPU clk */ -#endif - -#if (defined(mpc860) || defined(mpc821)) - unsigned32 clock_speed; /* Speed of CPU in Hz */ -#endif } rtems_cpu_table; /* - * The following type defines an entry in the PPC's trap table. - * - * NOTE: The instructions chosen are RTEMS dependent although one is - * obligated to use two of the four instructions to perform a - * long jump. The other instructions load one register with the - * trap type (a.k.a. vector) and another with the psr. - */ - -typedef struct { - unsigned32 stwu_r1; /* stwu %r1, -(??+IP_END)(%1)*/ - unsigned32 stw_r0; /* stw %r0, IP_0(%r1) */ - unsigned32 li_r0_IRQ; /* li %r0, _IRQ */ - unsigned32 b_Handler; /* b PROC (_ISR_Handler) */ -} CPU_Trap_table_entry; - -/* * This variable is optional. It is used on CPUs on which it is difficult * to generate an "uninitialized" FP context. It is filled in by * _CPU_Initialize and copied into the task's FP context area during @@ -532,6 +466,14 @@ SCORE_EXTERN void *_CPU_Interrupt_stack_low; SCORE_EXTERN void *_CPU_Interrupt_stack_high; /* + * This defines the number of levels and the mask used to pick those + * bits out of a thread mode. + */ + +#define CPU_MODES_INTERRUPT_LEVEL 0x00000001 /* interrupt level in mode */ +#define CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */ + +/* * With some compilation systems, it is difficult if not impossible to * call a high-level language routine from assembly language. This * is especially true of commercial Ada compilers and name mangling @@ -549,22 +491,11 @@ SCORE_EXTERN void *_CPU_Interrupt_stack_high; SCORE_EXTERN struct { - unsigned32 *Nest_level; unsigned32 *Disable_level; - void *Vector_table; void *Stack; -#if (PPC_ABI == PPC_ABI_POWEROPEN) - unsigned32 Dispatch_r2; -#else - unsigned32 Default_r2; -#if (PPC_ABI != PPC_ABI_GCC27) - unsigned32 Default_r13; -#endif -#endif volatile boolean *Switch_necessary; boolean *Signal; - unsigned32 msr_initial; } _CPU_IRQ_info CPU_STRUCTURE_ALIGNMENT; /* @@ -662,148 +593,29 @@ SCORE_EXTERN struct { #define loc_string(a,b) a " (" #b ")\n" -#define _CPU_MSR_Value( _msr_value ) \ - do { \ - _msr_value = 0; \ - asm volatile ("mfmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \ - } while (0) - -#define _CPU_MSR_SET( _msr_value ) \ -{ asm volatile ("mtmsr %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); } - -#if 0 -#define _CPU_ISR_Disable( _isr_cookie ) \ - { register unsigned int _disable_mask = PPC_MSR_DISABLE_MASK; \ - _isr_cookie = 0; \ - asm volatile ( - "mfmsr %0" : \ - "=r" ((_isr_cookie)) : \ - "0" ((_isr_cookie)) \ - ); \ - asm volatile ( - "andc %1,%0,%1" : \ - "=r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \ - "0" ((_isr_cookie)), "1" ((_disable_mask)) \ - ); \ - asm volatile ( - "mtmsr %1" : \ - "=r" ((_disable_mask)) : \ - "0" ((_disable_mask)) \ - ); \ - } -#endif - -#define _CPU_ISR_Disable( _isr_cookie ) \ - { register unsigned int _disable_mask = PPC_MSR_DISABLE_MASK; \ - _isr_cookie = 0; \ - asm volatile ( \ - "mfmsr %0; andc %1,%0,%1; mtmsr %1" : \ - "=&r" ((_isr_cookie)), "=&r" ((_disable_mask)) : \ - "0" ((_isr_cookie)), "1" ((_disable_mask)) \ - ); \ - } - - -#define _CPU_Data_Cache_Block_Flush( _address ) \ - do { register void *__address = (_address); \ - register unsigned32 _zero = 0; \ - asm volatile ( "dcbf %0,%1" : \ - "=r" (_zero), "=r" (__address) : \ - "0" (_zero), "1" (__address) \ - ); \ - } while (0) - - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _isr_cookie is not modified. - */ + +static inline unsigned32 _CPU_ISR_Get_level( void ) +{ + register unsigned int msr; + _CPU_MSR_GET(msr); + if (msr & MSR_EE) return 0; + else return 1; +} -#define _CPU_ISR_Enable( _isr_cookie ) \ - { \ - asm volatile ( "mtmsr %0" : \ - "=r" ((_isr_cookie)) : \ - "0" ((_isr_cookie))); \ +static inline void _CPU_ISR_Set_level( unsigned32 level ) +{ + register unsigned int msr; + _CPU_MSR_GET(msr); + if (!(level & CPU_MODES_INTERRUPT_MASK)) { + msr |= MSR_EE; } - -/* - * This temporarily restores the interrupt to _isr_cookie before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _isr_cookie is not - * modified. - * - * NOTE: The version being used is not very optimized but it does - * not trip a problem in gcc where the disable mask does not - * get loaded. Check this for future (post 10/97 gcc versions. - */ - -#define _CPU_ISR_Flash( _isr_cookie ) \ - { register unsigned int _disable_mask = PPC_MSR_DISABLE_MASK; \ - asm volatile ( \ - "mtmsr %0; andc %1,%0,%1; mtmsr %1" : \ - "=r" ((_isr_cookie)), "=r" ((_disable_mask)) : \ - "0" ((_isr_cookie)), "1" ((_disable_mask)) \ - ); \ + else { + msr &= ~MSR_EE; } - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - */ - -unsigned32 _CPU_ISR_Calculate_level( - unsigned32 new_level -); - -void _CPU_ISR_Set_level( - unsigned32 new_level -); + _CPU_MSR_SET(msr); +} -unsigned32 _CPU_ISR_Get_level( void ); - -void _CPU_ISR_install_raw_handler( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* end of ISR handler macros */ - -/* - * Simple spin delay in microsecond units for device drivers. - * This is very dependent on the clock speed of the target. - */ - -#define CPU_Get_timebase_low( _value ) \ - asm volatile( "mftb %0" : "=r" (_value) ) - -#define delay( _microseconds ) \ - do { \ - unsigned32 start, ticks, now; \ - CPU_Get_timebase_low( start ) ; \ - ticks = (_microseconds) * Cpu_table.clicks_per_usec; \ - do \ - CPU_Get_timebase_low( now ) ; \ - while (now - start < ticks); \ - } while (0) - -#define delay_in_bus_cycles( _cycles ) \ - do { \ - unsigned32 start, now; \ - CPU_Get_timebase_low( start ); \ - do \ - CPU_Get_timebase_low( now ); \ - while (now - start < (_cycles)); \ - } while (0) - - +#define _CPU_ISR_install_vector(irq, new, old) {BSP_panic("_CPU_ISR_install_vector called\n");} /* Context handler macros */ @@ -892,7 +704,7 @@ void _CPU_Context_Initialize( */ #define _CPU_Fatal_halt( _error ) \ - _CPU_Fatal_error(_error) + _BSP_Fatal_error(_error) /* end of Fatal Error manager macros */ @@ -999,17 +811,6 @@ void _CPU_Initialize( void (*thread_dispatch) ); -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); /* * _CPU_Install_interrupt_stack |