diff options
Diffstat (limited to 'c/src/exec/score/cpu/hppa1.1/cpu_asm.s')
| -rw-r--r-- | c/src/exec/score/cpu/hppa1.1/cpu_asm.s | 512 |
1 files changed, 296 insertions, 216 deletions
diff --git a/c/src/exec/score/cpu/hppa1.1/cpu_asm.s b/c/src/exec/score/cpu/hppa1.1/cpu_asm.s index bf0d4b0bee..a62237c76c 100644 --- a/c/src/exec/score/cpu/hppa1.1/cpu_asm.s +++ b/c/src/exec/score/cpu/hppa1.1/cpu_asm.s @@ -1,29 +1,29 @@ -# -# TODO: -# Context_switch needs to only save callee save registers -# I think this means can skip: r1, r2, r19-29, r31 -# Ref: p 3-2 of Procedure Calling Conventions Manual -# This should be #ifndef DEBUG so that debugger has -# accurate visibility into all registers -# -# This file contains the assembly code for the HPPA implementation -# of RTEMS. -# -# COPYRIGHT (c) 1994,95 by Division Incorporated -# -# To anyone who acknowledges that this file is provided "AS IS" -# without any express or implied warranty: -# permission to use, copy, modify, and distribute this file -# for any purpose is hereby granted without fee, provided that -# the above copyright notice and this notice appears in all -# copies, and that the name of Division Incorporated not be -# used in advertising or publicity pertaining to distribution -# of the software without specific, written prior permission. -# Division Incorporated makes no representations about the -# suitability of this software for any purpose. -# -# $Id$ -# +/* + * TODO: + * Context_switch needs to only save callee save registers + * I think this means can skip: r1, r2, r19-29, r31 + * Ref: p 3-2 of Procedure Calling Conventions Manual + * This should be #ifndef DEBUG so that debugger has + * accurate visibility into all registers + * + * This file contains the assembly code for the HPPA implementation + * of RTEMS. + * + * COPYRIGHT (c) 1994,95 by Division Incorporated + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of Division Incorporated not be + * used in advertising or publicity pertaining to distribution + * of the software without specific, written prior permission. + * Division Incorporated makes no representations about the + * suitability of this software for any purpose. + * + * $Id$ + */ #include <rtems/score/hppa.h> #include <rtems/score/cpu_asm.h> @@ -39,69 +39,69 @@ .SPACE $TEXT$ .SUBSPA $CODE$ -# -# Special register usage for context switch and interrupts -# Stay away from %cr28 which is used for TLB misses on 72000 -# +/* + * Special register usage for context switch and interrupts + * Stay away from %cr28 which is used for TLB misses on 72000 + */ isr_arg0 .reg %cr24 isr_r9 .reg %cr25 isr_r8 .reg %cr26 -# -# Interrupt stack frame looks like this -# -# offset item -# ----------------------------------------------------------------- -# INTEGER_CONTEXT_OFFSET Context_Control -# FP_CONTEXT_OFFSET Context_Control_fp -# -# It is padded out to a multiple of 64 -# - - -# PAGE^L -# void _Generic_ISR_Handler() -# -# This routine provides the RTEMS interrupt management. -# -# We jump here from the interrupt vector. -# The HPPA hardware has done some stuff for us: -# PSW saved in IPSW -# PSW set to 0 -# PSW[E] set to default (0) -# PSW[M] set to 1 iff this is HPMC -# -# IIA queue is frozen (since PSW[Q] is now 0) -# privilege level promoted to 0 -# IIR, ISR, IOR potentially updated if PSW[Q] was 1 at trap -# registers GR 1,8,9,16,17,24,25 copied to shadow regs -# SHR 0 1 2 3 4 5 6 -# -# Our vector stub (in the BSP) MUST have done the following: -# -# a) Saved the original %r9 into %isr_r9 (%cr25) -# b) Placed the vector number in %r9 -# c) Was allowed to also destroy $isr_r8 (%cr26), -# but the stub was NOT allowed to destroy any other registers. -# -# The typical stub sequence (in the BSP) should look like this: -# -# a) mtctl %r9,isr_r9 ; (save r9 in cr25) -# b) ldi vector,%r9 ; (load constant vector number in r9) -# c) mtctl %r8,isr_r8 ; (save r8 in cr26) -# d) ldil L%MY_BSP_first_level_interrupt_handler,%r8 -# e) ldo R%MY_BSP_first_level_interrupt_handler(%r8),%r8 -# ; (point to BSP raw handler table) -# f) ldwx,s %r9(%r8),%r8 ; (load value from raw handler table) -# g) bv 0(%r8) ; (call raw handler: _Generic_ISR_Handler) -# h) mfctl isr_r8,%r8 ; (restore r8 from cr26 in delay slot) -# -# Optionally, steps (c) thru (h) _could_ be replaced with a single -# bl,n _Generic_ISR_Handler,%r0 -# -# -# +/* + * Interrupt stack frame looks like this + * + * offset item + * ----------------------------------------------------------------- + * INTEGER_CONTEXT_OFFSET Context_Control + * FP_CONTEXT_OFFSET Context_Control_fp + * + * It is padded out to a multiple of 64 + */ + + +/*PAGE^L + * void _Generic_ISR_Handler() + * + * This routine provides the RTEMS interrupt management. + * + * We jump here from the interrupt vector. + * The HPPA hardware has done some stuff for us: + * PSW saved in IPSW + * PSW set to 0 + * PSW[E] set to default (0) + * PSW[M] set to 1 iff this is HPMC + * + * IIA queue is frozen (since PSW[Q] is now 0) + * privilege level promoted to 0 + * IIR, ISR, IOR potentially updated if PSW[Q] was 1 at trap + * registers GR 1,8,9,16,17,24,25 copied to shadow regs + * SHR 0 1 2 3 4 5 6 + * + * Our vector stub (in the BSP) MUST have done the following: + * + * a) Saved the original %r9 into %isr_r9 (%cr25) + * b) Placed the vector number in %r9 + * c) Was allowed to also destroy $isr_r8 (%cr26), + * but the stub was NOT allowed to destroy any other registers. + * + * The typical stub sequence (in the BSP) should look like this: + * + * a) mtctl %r9,isr_r9 ; (save r9 in cr25) + * b) ldi vector,%r9 ; (load constant vector number in r9) + * c) mtctl %r8,isr_r8 ; (save r8 in cr26) + * d) ldil L%MY_BSP_first_level_interrupt_handler,%r8 + * e) ldo R%MY_BSP_first_level_interrupt_handler(%r8),%r8 + * ; (point to BSP raw handler table) + * f) ldwx,s %r9(%r8),%r8 ; (load value from raw handler table) + * g) bv 0(%r8) ; (call raw handler: _Generic_ISR_Handler) + * h) mfctl isr_r8,%r8 ; (restore r8 from cr26 in delay slot) + * + * Optionally, steps (c) thru (h) _could_ be replaced with a single + * bl,n _Generic_ISR_Handler,%r0 + * + * + */ .EXPORT _Generic_ISR_Handler,ENTRY,PRIV_LEV=0 _Generic_ISR_Handler: .PROC @@ -110,7 +110,9 @@ _Generic_ISR_Handler: mtctl arg0, isr_arg0 -# save interrupt state +/* + * save interrupt state + */ mfctl ipsw, arg0 stw arg0, IPSW_OFFSET(sp) @@ -130,18 +132,19 @@ _Generic_ISR_Handler: mfctl %sar, arg0 stw arg0, SAR_OFFSET(sp) -# -# Build an interrupt frame to hold the contexts we will need. -# We have already saved the interrupt items on the stack - -# At this point the following registers are damaged wrt the interrupt -# reg current value saved value -# ------------------------------------------------ -# arg0 scratch isr_arg0 (cr24) -# r9 vector number isr_r9 (cr25) -# -# Point to beginning of integer context and -# save the integer context +/* + * Build an interrupt frame to hold the contexts we will need. + * We have already saved the interrupt items on the stack + * + * At this point the following registers are damaged wrt the interrupt + * reg current value saved value + * ------------------------------------------------ + * arg0 scratch isr_arg0 (cr24) + * r9 vector number isr_r9 (cr25) + * + * Point to beginning of integer context and + * save the integer context + */ stw %r1,R1_OFFSET(sp) stw %r2,R2_OFFSET(sp) stw %r3,R3_OFFSET(sp) @@ -150,7 +153,9 @@ _Generic_ISR_Handler: stw %r6,R6_OFFSET(sp) stw %r7,R7_OFFSET(sp) stw %r8,R8_OFFSET(sp) -# skip r9 +/* + * skip r9 + */ stw %r10,R10_OFFSET(sp) stw %r11,R11_OFFSET(sp) stw %r12,R12_OFFSET(sp) @@ -167,22 +172,25 @@ _Generic_ISR_Handler: stw %r23,R23_OFFSET(sp) stw %r24,R24_OFFSET(sp) stw %r25,R25_OFFSET(sp) -# skip arg0 +/* + * skip arg0 + */ stw %r27,R27_OFFSET(sp) stw %r28,R28_OFFSET(sp) stw %r29,R29_OFFSET(sp) stw %r30,R30_OFFSET(sp) stw %r31,R31_OFFSET(sp) -# Now most registers are available since they have been saved -# -# The following items are currently wrong in the integer context -# reg current value saved value -# ------------------------------------------------ -# arg0 scratch isr_arg0 (cr24) -# r9 vector number isr_r9 (cr25) -# -# Fix them +/* Now most registers are available since they have been saved + * + * The following items are currently wrong in the integer context + * reg current value saved value + * ------------------------------------------------ + * arg0 scratch isr_arg0 (cr24) + * r9 vector number isr_r9 (cr25) + * + * Fix them + */ mfctl isr_arg0,%r3 stw %r3,ARG0_OFFSET(sp) @@ -190,19 +198,21 @@ _Generic_ISR_Handler: mfctl isr_r9,%r3 stw %r3,R9_OFFSET(sp) -# -# At this point we are done with isr_arg0, and isr_r9 control registers -# -# Prepare to re-enter virtual mode -# We need Q in case the interrupt handler enables interrupts -# +/* + * At this point we are done with isr_arg0, and isr_r9 control registers + * + * Prepare to re-enter virtual mode + * We need Q in case the interrupt handler enables interrupts + */ ldil L%CPU_PSW_DEFAULT, arg0 ldo R%CPU_PSW_DEFAULT(arg0), arg0 mtctl arg0, ipsw -# Now jump to "rest_of_isr_handler" with the rfi -# We are assuming the space queues are all correct already +/* + * Now jump to "rest_of_isr_handler" with the rfi + * We are assuming the space queues are all correct already + */ ldil L%rest_of_isr_handler, arg0 ldo R%rest_of_isr_handler(arg0), arg0 @@ -213,32 +223,43 @@ _Generic_ISR_Handler: rfi nop -# At this point we are back in virtual mode and all our -# normal addressing is once again ok. -# -# It is now ok to take an exception or trap -# +/* + * At this point we are back in virtual mode and all our + * normal addressing is once again ok. + * + * It is now ok to take an exception or trap + */ rest_of_isr_handler: -# Point to beginning of float context and -# save the floating point context -- doing whatever patches are necessary +/* + * Point to beginning of float context and + * save the floating point context -- doing whatever patches are necessary + */ + .call ARGW0=GR bl _CPU_Save_float_context,%r2 ldo FP_CONTEXT_OFFSET(sp),arg0 -# save the ptr to interrupt frame as an argument for the interrupt handler +/* + * save the ptr to interrupt frame as an argument for the interrupt handler + */ + copy sp, arg1 -# Advance the frame to point beyond all interrupt contexts (integer & float) -# this also includes the pad to align to 64byte stack boundary +/* + * Advance the frame to point beyond all interrupt contexts (integer & float) + * this also includes the pad to align to 64byte stack boundary + */ ldo CPU_INTERRUPT_FRAME_SIZE(sp), sp -# r3 -- &_ISR_Nest_level -# r5 -- value _ISR_Nest_level -# r4 -- &_Thread_Dispatch_disable_level -# r6 -- value _Thread_Dispatch_disable_level -# r9 -- vector number +/* + * r3 -- &_ISR_Nest_level + * r5 -- value _ISR_Nest_level + * r4 -- &_Thread_Dispatch_disable_level + * r6 -- value _Thread_Dispatch_disable_level + * r9 -- vector number + */ .import _ISR_Nest_level,data ldil L%_ISR_Nest_level,%r3 @@ -250,50 +271,64 @@ rest_of_isr_handler: ldo R%_Thread_Dispatch_disable_level(%r4),%r4 ldw 0(%r4),%r6 -# increment interrupt nest level counter. If outermost interrupt -# switch the stack and squirrel away the previous sp. +/* + * increment interrupt nest level counter. If outermost interrupt + * switch the stack and squirrel away the previous sp. + */ addi 1,%r5,%r5 stw %r5, 0(%r3) -# compute and save new stack (with frame) -# just in case we are nested -- simpler this way +/* + * compute and save new stack (with frame) + * just in case we are nested -- simpler this way + */ comibf,= 1,%r5,stack_done ldo 128(sp),%r7 -# -# Switch to interrupt stack allocated by the interrupt manager (intr.c) -# +/* + * Switch to interrupt stack allocated by the interrupt manager (intr.c) + */ .import _CPU_Interrupt_stack_low,data ldil L%_CPU_Interrupt_stack_low,%r7 ldw R%_CPU_Interrupt_stack_low(%r7),%r7 ldo 128(%r7),%r7 stack_done: -# save our current stack pointer where the "old sp" is supposed to be +/* + * save our current stack pointer where the "old sp" is supposed to be + */ stw sp, -4(%r7) -# and switch stacks (or advance old stack in nested case) +/* + * and switch stacks (or advance old stack in nested case) + */ copy %r7, sp -# increment the dispatch disable level counter. +/* + * increment the dispatch disable level counter. + */ addi 1,%r6,%r6 stw %r6, 0(%r4) -# load address of user handler -# Note: No error checking is done, it is assumed that the -# vector table contains a valid address or a stub -# spurious handler. +/* + * load address of user handler + * Note: No error checking is done, it is assumed that the + * vector table contains a valid address or a stub + * spurious handler. + */ .import _ISR_Vector_table,data ldil L%_ISR_Vector_table,%r8 ldo R%_ISR_Vector_table(%r8),%r8 ldwx,s %r9(%r8),%r8 -# invoke user interrupt handler -# Interrupts are currently disabled, as per RTEMS convention -# The handler has the option of re-enabling interrupts -# NOTE: can not use 'bl' since it uses "pc-relative" addressing -# and we are using a hard coded address from a table -# So... we fudge r2 ourselves (ala dynacall) -# arg0 = vector number, arg1 = ptr to rtems_interrupt_frame +/* + * invoke user interrupt handler + * Interrupts are currently disabled, as per RTEMS convention + * The handler has the option of re-enabling interrupts + * NOTE: can not use 'bl' since it uses "pc-relative" addressing + * and we are using a hard coded address from a table + * So... we fudge r2 ourselves (ala dynacall) + * arg0 = vector number, arg1 = ptr to rtems_interrupt_frame + */ copy %r9, %r26 .call ARGW0=GR, ARGW1=GR blr %r0, rp @@ -301,20 +336,24 @@ stack_done: post_user_interrupt_handler: -# Back from user handler(s) -# Disable external interrupts (since the interrupt handler could -# have turned them on) and return to the interrupted task stack (assuming -# (_ISR_Nest_level == 0) +/* + * Back from user handler(s) + * Disable external interrupts (since the interrupt handler could + * have turned them on) and return to the interrupted task stack (assuming + * (_ISR_Nest_level == 0) + */ rsm HPPA_PSW_I + HPPA_PSW_R, %r0 ldw -4(sp), sp -# r3 -- (most of) &_ISR_Nest_level -# r5 -- value _ISR_Nest_level -# r4 -- (most of) &_Thread_Dispatch_disable_level -# r6 -- value _Thread_Dispatch_disable_level -# r7 -- (most of) &_ISR_Signals_to_thread_executing -# r8 -- value _ISR_Signals_to_thread_executing +/* + * r3 -- (most of) &_ISR_Nest_level + * r5 -- value _ISR_Nest_level + * r4 -- (most of) &_Thread_Dispatch_disable_level + * r6 -- value _Thread_Dispatch_disable_level + * r7 -- (most of) &_ISR_Signals_to_thread_executing + * r8 -- value _ISR_Signals_to_thread_executing + */ .import _ISR_Nest_level,data ldil L%_ISR_Nest_level,%r3 @@ -327,33 +366,42 @@ post_user_interrupt_handler: .import _ISR_Signals_to_thread_executing,data ldil L%_ISR_Signals_to_thread_executing,%r7 -# decrement isr nest level +/* + * decrement isr nest level + */ addi -1, %r5, %r5 stw %r5, R%_ISR_Nest_level(%r3) -# decrement dispatch disable level counter and, if not 0, go on +/* + * decrement dispatch disable level counter and, if not 0, go on + */ addi -1,%r6,%r6 comibf,= 0,%r6,isr_restore stw %r6, R%_Thread_Dispatch_disable_level(%r4) -# check whether or not a context switch is necessary +/* + * check whether or not a context switch is necessary + */ .import _Context_Switch_necessary,data ldil L%_Context_Switch_necessary,%r8 ldw R%_Context_Switch_necessary(%r8),%r8 comibf,=,n 0,%r8,ISR_dispatch -# check whether or not a context switch is necessary because an ISR -# sent signals to the interrupted task +/* + * check whether or not a context switch is necessary because an ISR + * sent signals to the interrupted task + */ ldw R%_ISR_Signals_to_thread_executing(%r7),%r8 comibt,=,n 0,%r8,isr_restore -# OK, something happened while in ISR and we need to switch to a task -# other than the one which was interrupted or the -# ISR_Signals_to_thread_executing case -# We also turn on interrupts, since the interrupted task had them -# on (obviously :-) and Thread_Dispatch is happy to leave ints on. -# +/* + * OK, something happened while in ISR and we need to switch to a task + * other than the one which was interrupted or the + * ISR_Signals_to_thread_executing case + * We also turn on interrupts, since the interrupted task had them + * on (obviously :-) and Thread_Dispatch is happy to leave ints on. + */ ISR_dispatch: stw %r0, R%_ISR_Signals_to_thread_executing(%r7) @@ -369,32 +417,41 @@ ISR_dispatch: isr_restore: -# enable interrupts during most of restore +/* + * enable interrupts during most of restore + */ ssm HPPA_PSW_I, %r0 -# Get a pointer to beginning of our stack frame +/* + * Get a pointer to beginning of our stack frame + */ ldo -CPU_INTERRUPT_FRAME_SIZE(sp), %arg1 -# restore float +/* + * restore float + */ .call ARGW0=GR bl _CPU_Restore_float_context,%r2 ldo FP_CONTEXT_OFFSET(%arg1), arg0 copy %arg1, %arg0 -# ********** FALL THRU ********** +/* + * ********** FALL THRU ********** + */ -# Jump here from bottom of Context_Switch -# Also called directly by _CPU_Context_Restart_self via _Thread_Restart_self -# restore interrupt state -# +/* + * Jump here from bottom of Context_Switch + * Also called directly by _CPU_Context_Restart_self via _Thread_Restart_self + * restore interrupt state + */ .EXPORT _CPU_Context_restore _CPU_Context_restore: -# -# restore integer state -# +/* + * restore integer state + */ ldw R1_OFFSET(arg0),%r1 ldw R2_OFFSET(arg0),%r2 ldw R3_OFFSET(arg0),%r3 @@ -419,18 +476,26 @@ _CPU_Context_restore: ldw R22_OFFSET(arg0),%r22 ldw R23_OFFSET(arg0),%r23 ldw R24_OFFSET(arg0),%r24 -# skipping r25; used as scratch register below -# skipping r26 (arg0) until we are done with it +/* + * skipping r25; used as scratch register below + * skipping r26 (arg0) until we are done with it + */ ldw R27_OFFSET(arg0),%r27 ldw R28_OFFSET(arg0),%r28 ldw R29_OFFSET(arg0),%r29 -# skipping r30 (sp) until we turn off interrupts +/* + * skipping r30 (sp) until we turn off interrupts + */ ldw R31_OFFSET(arg0),%r31 -# Turn off Q & R & I so we can write r30 and interrupt control registers +/* + * Turn off Q & R & I so we can write r30 and interrupt control registers + */ rsm HPPA_PSW_Q + HPPA_PSW_R + HPPA_PSW_I, %r0 -# now safe to restore r30 +/* + * now safe to restore r30 + */ ldw R30_OFFSET(arg0),%r30 ldw IPSW_OFFSET(arg0), %r25 @@ -445,9 +510,13 @@ _CPU_Context_restore: ldw PCOQBACK_OFFSET(arg0), %r25 mtctl %r25, pcoq -# Load r25 with interrupts off +/* + * Load r25 with interrupts off + */ ldw R25_OFFSET(arg0),%r25 -# Must load r26 (arg0) last +/* + * Must load r26 (arg0) last + */ ldw R26_OFFSET(arg0),%r26 isr_exit: @@ -455,13 +524,14 @@ isr_exit: .EXIT .PROCEND -# -# This section is used to context switch floating point registers. -# Ref: 6-35 of Architecture 1.1 -# -# NOTE: since integer multiply uses the floating point unit, -# we have to save/restore fp on every trap. We cannot -# just try to keep track of fp usage. +/* + * This section is used to context switch floating point registers. + * Ref: 6-35 of Architecture 1.1 + * + * NOTE: since integer multiply uses the floating point unit, + * we have to save/restore fp on every trap. We cannot + * just try to keep track of fp usage. + */ .align 32 .EXPORT _CPU_Save_float_context,ENTRY,PRIV_LEV=0 @@ -549,13 +619,14 @@ _CPU_Restore_float_context: .EXIT .PROCEND -# -# These 2 small routines are unused right now. -# Normally we just go thru _CPU_Save_float_context (and Restore) -# -# Here we just deref the ptr and jump up, letting _CPU_Save_float_context -# do the return for us. -# +/* + * These 2 small routines are unused right now. + * Normally we just go thru _CPU_Save_float_context (and Restore) + * + * Here we just deref the ptr and jump up, letting _CPU_Save_float_context + * do the return for us. + */ + .EXPORT _CPU_Context_save_fp,ENTRY,PRIV_LEV=0 _CPU_Context_save_fp: .PROC @@ -577,10 +648,11 @@ _CPU_Context_restore_fp: .PROCEND -# void _CPU_Context_switch( run_context, heir_context ) -# -# This routine performs a normal non-FP context switch. -# +/* + * void _CPU_Context_switch( run_context, heir_context ) + * + * This routine performs a normal non-FP context switch. + */ .align 32 .EXPORT _CPU_Context_switch,ENTRY,PRIV_LEV=0,ARGW0=GR,ARGW1=GR @@ -589,7 +661,9 @@ _CPU_Context_switch: .CALLINFO FRAME=64 .ENTRY -# Save the integer context +/* + * Save the integer context + */ stw %r1,R1_OFFSET(arg0) stw %r2,R2_OFFSET(arg0) stw %r3,R3_OFFSET(arg0) @@ -622,13 +696,17 @@ _CPU_Context_switch: stw %r30,R30_OFFSET(arg0) stw %r31,R31_OFFSET(arg0) -# fill in interrupt context section +/* + * fill in interrupt context section + */ stw %r2, PCOQFRONT_OFFSET(%arg0) ldo 4(%r2), %r2 stw %r2, PCOQBACK_OFFSET(%arg0) -# Generate a suitable IPSW by using the system default psw -# with the current low bits added in. +/* + * Generate a suitable IPSW by using the system default psw + * with the current low bits added in. + */ ldil L%CPU_PSW_DEFAULT, %r2 ldo R%CPU_PSW_DEFAULT(%r2), %r2 @@ -636,9 +714,11 @@ _CPU_Context_switch: dep %arg2, 31, 8, %r2 stw %r2, IPSW_OFFSET(%arg0) -# at this point, the running task context is completely saved -# Now jump to the bottom of the interrupt handler to load the -# heirs context +/* + * at this point, the running task context is completely saved + * Now jump to the bottom of the interrupt handler to load the + * heirs context + */ b _CPU_Context_restore copy %arg1, %arg0 |