diff options
Diffstat (limited to '')
-rw-r--r-- | c/src/exec/score/cpu/arm/.cvsignore | 14 | ||||
-rw-r--r-- | c/src/exec/score/cpu/arm/ChangeLog | 153 | ||||
-rw-r--r-- | c/src/exec/score/cpu/arm/Makefile.am | 55 | ||||
-rw-r--r-- | c/src/exec/score/cpu/arm/asm.h | 125 | ||||
-rw-r--r-- | c/src/exec/score/cpu/arm/configure.ac | 30 | ||||
-rw-r--r-- | c/src/exec/score/cpu/arm/cpu.c | 243 | ||||
-rw-r--r-- | c/src/exec/score/cpu/arm/cpu_asm.S | 216 | ||||
-rw-r--r-- | c/src/exec/score/cpu/arm/rtems/.cvsignore | 2 | ||||
-rw-r--r-- | c/src/exec/score/cpu/arm/rtems/score/.cvsignore | 2 | ||||
-rw-r--r-- | c/src/exec/score/cpu/arm/rtems/score/arm.h | 62 | ||||
-rw-r--r-- | c/src/exec/score/cpu/arm/rtems/score/cpu.h | 962 | ||||
-rw-r--r-- | c/src/exec/score/cpu/arm/rtems/score/cpu_asm.h | 41 | ||||
-rw-r--r-- | c/src/exec/score/cpu/arm/rtems/score/types.h | 55 |
13 files changed, 0 insertions, 1960 deletions
diff --git a/c/src/exec/score/cpu/arm/.cvsignore b/c/src/exec/score/cpu/arm/.cvsignore deleted file mode 100644 index d29e5050f5..0000000000 --- a/c/src/exec/score/cpu/arm/.cvsignore +++ /dev/null @@ -1,14 +0,0 @@ -Makefile -Makefile.in -aclocal.m4 -autom4te.cache -config.cache -config.guess -config.log -config.status -config.sub -configure -depcomp -install-sh -missing -mkinstalldirs diff --git a/c/src/exec/score/cpu/arm/ChangeLog b/c/src/exec/score/cpu/arm/ChangeLog deleted file mode 100644 index 8b946f1ad2..0000000000 --- a/c/src/exec/score/cpu/arm/ChangeLog +++ /dev/null @@ -1,153 +0,0 @@ -2002-07-17 Jay Monkman <jtm@smoothsmoothie.com> - - * rtems/score/cpu_asm.h: Enhanced to include register offsets. - * Makefile.am: Install rtems/score/cpu_asm.h. - * cpu.c: Significantly enhanced including the implementation of - _CPU_ISR_Get_level. - * cpu_asm.S: Improved behavior of context switch and interrupt - dispatching. - * rtems/score/arm.h: Improved the CPU model name determination. - * rtems/score/cpu.h: Improved interrupt disable/enable functions. - -2002-07-05 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/cpu.h: Filled in something that was marked XXX. - -2002-07-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: RTEMS_TOP(../../../..). - -2002-07-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems.c: Remove. - * Makefile.am: Reflect changes above. - -2002-07-01 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Remove RTEMS_PROJECT_ROOT. - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Add RTEMS_PROG_CCAS - -2002-06-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..). - Add AC_PROG_RANLIB. - -2002-06-17 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include $(top_srcdir)/../../../automake/*.am. - Use ../../../aclocal. - -2002-04-18 Jay Monkman <jtm@smoothsmoothie.com> - - * rtems/score/cpu.h (CPU_ISR_Disable and CPU_ISR_Enable): Correct them - where they correctly inform the compiler about the register they - are modifying. - -2001-04-03 Joel Sherrill <joel@OARcorp.com> - - * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h. - * rtems/score/a29ktypes.h: Removed. - * rtems/score/types.h: New file via CVS magic. - * Makefile.am, rtems/score/cpu.h: Account for name change. - -2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: - AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS). - AM_INIT_AUTOMAKE([no-define foreign 1.6]). - * Makefile.am: Remove AUTOMAKE_OPTIONS. - -2001-02-04 Joel Sherrill <joel@OARcorp.com> - - * configure.ac: Removed references to rtems/Makefile and - rtems/score/Makefile. - -2002-01-29 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/Makefile.am: Removed. - * rtems/score/Makefile.am: Removed. - * configure.ac: Reflect changes above. - * Makefile.am: Reflect changes above. - -2002-02-05 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP. - -2002-01-03 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * cpu.c: Include rtems/bspIo.h instead of bspIo.h. - -2001-12-20 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * configure.ac: Use RTEMS_ENV_RTEMSCPU. - -2001-12-19 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Add multilib support. - -2001-12-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * asm.h: include cpuopts.h instead of targopts.h - * rtems/score/arm.h: Use __arm__. - -2001-11-28 Joel Sherrill <joel@OARcorp.com>, - - This was tracked as PR91. - * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which - is used to specify if the port uses the standard macro for this (FALSE). - A TRUE setting indicates the port provides its own implementation. - -2001-10-11 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * .cvsignore: Add autom4te.cache for autoconf > 2.52. - * configure.in: Remove. - * configure.ac: New file, generated from configure.in by autoupdate. - -2001-09-23 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='. - * Makefile.am: Use 'PREINSTALL_FILES ='. - -2001-02-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am, rtems/score/Makefile.am: - Apply include_*HEADERS instead of H_FILES. - -2001-01-03 Joel Sherrill <joel@OARcorp.com> - - * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). - -2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS. - -2000-11-02 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal. - -2000-10-25 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros. - Switch to GNU canonicalization. - -2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> - - * Makefile.am: Include compile.am, formatting. - * rtems/Makefile.am: Formatting. - * rtems/score/Makefile.am: Formatting. - -2000-08-29 Joel Sherrill <joel.sherrill@OARcorp.com> - - * cpu.c: Spacing issues. - * rtems/score/cpu.h: Removed warning by setting _level. - -2000-08-29 Joel Sherrill <joel.sherrill@OARcorp.com> - - * Makefile.am: Added S_O_FILES to list of objects. - -2000-08-10 Joel Sherrill <joel@OARcorp.com> - - * ChangeLog: New file. diff --git a/c/src/exec/score/cpu/arm/Makefile.am b/c/src/exec/score/cpu/arm/Makefile.am deleted file mode 100644 index 03e6e36ebf..0000000000 --- a/c/src/exec/score/cpu/arm/Makefile.am +++ /dev/null @@ -1,55 +0,0 @@ -## -## $Id$ -## - -ACLOCAL_AMFLAGS = -I ../../../aclocal - -include $(top_srcdir)/../../../automake/multilib.am -include $(top_srcdir)/../../../automake/compile.am -include $(top_srcdir)/../../../automake/lib.am - -$(PROJECT_INCLUDE)/%.h: %.h - $(INSTALL_DATA) $< $@ - -$(PROJECT_INCLUDE): - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems: - $(mkinstalldirs) $@ - -$(PROJECT_INCLUDE)/rtems/score: - $(mkinstalldirs) $@ - -include_HEADERS = asm.h -PREINSTALL_FILES = $(PROJECT_INCLUDE) $(include_HEADERS:%=$(PROJECT_INCLUDE)/%) - -include_rtems_scoredir = $(includedir)/rtems/score -include_rtems_score_HEADERS = \ - rtems/score/cpu.h \ - rtems/score/cpu_asm.h \ - rtems/score/arm.h \ - rtems/score/types.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score \ - $(include_rtems_score_HEADERS:%.h=$(PROJECT_INCLUDE)/%.h) - -C_FILES = cpu.c -C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o) - -S_FILES = cpu_asm.S -S_O_FILES = $(S_FILES:%.S=$(ARCH)/%.o) - -REL = $(ARCH)/rtems-cpu.rel - -rtems_cpu_rel_OBJECTS = $(C_O_FILES) $(S_O_FILES) - -$(REL): $(rtems_cpu_rel_OBJECTS) - $(make-rel) - -all: $(ARCH) $(PREINSTALL_FILES) $(rtems_cpu_rel_OBJECTS) $(REL) \ - $(TMPINSTALL_FILES) - -.PRECIOUS: $(REL) - -EXTRA_DIST = cpu.c cpu_asm.S - -include $(top_srcdir)/../../../automake/local.am diff --git a/c/src/exec/score/cpu/arm/asm.h b/c/src/exec/score/cpu/arm/asm.h deleted file mode 100644 index b974287b45..0000000000 --- a/c/src/exec/score/cpu/arm/asm.h +++ /dev/null @@ -1,125 +0,0 @@ -/* asm.h - * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. - * - * - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * COPYRIGHT: - * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: - * - * COPYRIGHT (c) 2000 Canon Research Centre France SA. - * Emmanuel Raguet, mailto:raguet@crf.canon.fr - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - */ - -#ifndef __ARM_ASM_h -#define __ARM_ASM_h - -/* - * Indicate we are in an assembly file and get the basic CPU definitions. - */ - -#ifndef ASM -#define ASM -#endif -#include <rtems/score/cpuopts.h> -#include <rtems/score/arm.h> - -/* - * Recent versions of GNU cpp define variables which indicate the - * need for underscores and percents. If not using GNU cpp or - * the version does not support this, then you will obviously - * have to define these as appropriate. - */ - -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ _ -#endif - -#ifndef __REGISTER_PREFIX__ -#define __REGISTER_PREFIX__ -#endif - -/* ANSI concatenation macros. */ - -#define CONCAT1(a, b) CONCAT2(a, b) -#define CONCAT2(a, b) a ## b - -/* Use the right prefix for global labels. */ - -#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) - -/* Use the right prefix for registers. */ - -#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) - -/* - * define macros for all of the registers on this CPU - * - * EXAMPLE: #define d0 REG (d0) - */ - -#define r0 REG(r0) -#define r1 REG(r1) -#define r2 REG(r2) -#define r3 REG(r3) -#define r4 REG(r4) -#define r5 REG(r5) -#define r6 REG(r6) -#define r7 REG(r7) -#define r8 REG(r8) -#define r9 REG(r9) -#define r10 REG(r10) -#define r11 REG(r11) -#define r12 REG(r12) -#define r13 REG(r13) -#define r14 REG(r14) -#define r15 REG(r15) - -#define CPSR REG(CPSR) - -#define SPSR REG(SPSR) - -/* - * Define macros to handle section beginning and ends. - */ - - -#define BEGIN_CODE_DCL .text -#define END_CODE_DCL -#define BEGIN_DATA_DCL .data -#define END_DATA_DCL -#define BEGIN_CODE .text -#define END_CODE -#define BEGIN_DATA -#define END_DATA -#define BEGIN_BSS -#define END_BSS -#define END - -/* - * Following must be tailor for a particular flavor of the C compiler. - * They may need to put underscores in front of the symbols. - */ - -#define PUBLIC(sym) .globl SYM (sym) -#define EXTERN(sym) .globl SYM (sym) - -#endif -/* end of include file */ - - diff --git a/c/src/exec/score/cpu/arm/configure.ac b/c/src/exec/score/cpu/arm/configure.ac deleted file mode 100644 index d7094bae11..0000000000 --- a/c/src/exec/score/cpu/arm/configure.ac +++ /dev/null @@ -1,30 +0,0 @@ -## Process this file with autoconf to produce a configure script. -## -## $Id$ - -AC_PREREQ(2.52) -AC_INIT([rtems-c-src-exec-score-cpu-arm],[_RTEMS_VERSION],[rtems-bugs@OARcorp.com]) -AC_CONFIG_SRCDIR([cpu_asm.S]) -RTEMS_TOP(../../../..) -AC_CONFIG_AUX_DIR(../../../..) - -RTEMS_CANONICAL_TARGET_CPU - -AM_INIT_AUTOMAKE([no-define foreign 1.6]) -AM_MAINTAINER_MODE - -RTEMS_ENV_RTEMSCPU - -RTEMS_CHECK_CPU -RTEMS_CANONICAL_HOST - -RTEMS_PROG_CC_FOR_TARGET -RTEMS_PROG_CCAS -RTEMS_CANONICALIZE_TOOLS -AC_PROG_RANLIB - -RTEMS_CHECK_NEWLIB - -# Explicitly list all Makefiles here -AC_CONFIG_FILES([Makefile]) -AC_OUTPUT diff --git a/c/src/exec/score/cpu/arm/cpu.c b/c/src/exec/score/cpu/arm/cpu.c deleted file mode 100644 index 3ae3f5828a..0000000000 --- a/c/src/exec/score/cpu/arm/cpu.c +++ /dev/null @@ -1,243 +0,0 @@ -/* - * ARM CPU Dependent Source - * - * - * COPYRIGHT (c) 2000 Canon Research Centre France SA. - * Emmanuel Raguet, mailto:raguet@crf.canon.fr - * - * Copyright (c) 2002 Advent Networks, Inc - * Jay Monkman <jmonkman@adventnetworks.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - */ - -#include <rtems/system.h> -#include <rtems.h> -#include <rtems/bspIo.h> -#include <rtems/score/isr.h> -#include <rtems/score/wkspace.h> -#include <rtems/score/thread.h> -#include <rtems/score/cpu.h> - -/* _CPU_Initialize - * - * This routine performs processor dependent initialization. - * - * INPUT PARAMETERS: - * cpu_table - CPU table to initialize - * thread_dispatch - address of ISR disptaching routine (unused) - * - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) /* ignored on this CPU */ -) -{ - _CPU_Table = *cpu_table; -} - -/* - * - * _CPU_ISR_Get_level - returns the current interrupt level - */ - -unsigned32 _CPU_ISR_Get_level( void ) -{ - unsigned32 reg; - - asm volatile ("mrs %0, cpsr \n" \ - "and %0, %0, #0xc0 \n" \ - : "=r" (reg)); - - return reg; -} - -/* - * _CPU_ISR_install_vector - * - * This kernel routine installs the RTEMS handler for the - * specified vector. - * - * Input parameters: - * vector - interrupt vector number - * new_handler - replacement ISR for this vector number - * old_handler - pointer to store former ISR for this vector number - * - * FIXME: This vector scheme should be changed to allow FIQ to be - * handled better. I'd like to be able to put VectorTable - * elsewhere - JTM - * - * - * Output parameters: NONE - * - */ -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -) -{ - /* pointer on the redirection table in RAM */ - long *VectorTable = (long *)(MAX_EXCEPTIONS * 4); - - if (old_handler != NULL) { - old_handler = *(proc_ptr *)(VectorTable + vector); - } - - *(VectorTable + vector) = (long)new_handler ; - -} - -void _CPU_Context_Initialize( - Context_Control *the_context, - unsigned32 *stack_base, - unsigned32 size, - unsigned32 new_level, - void *entry_point, - boolean is_fp -) -{ - the_context->register_sp = ((unsigned32)(stack_base)) + (size) ; - the_context->register_pc = (entry_point); - the_context->register_cpsr = (new_level | 0x13); -} - -/*PAGE - * - * _CPU_Install_interrupt_stack - */ - -void _CPU_Install_interrupt_stack( void ) -{ -/* FIXME: do something here */ -#if 0 - extern unsigned long _fiq_stack; - extern unsigned long _fiq_stack_size; - extern unsigned long _irq_stack; - extern unsigned long _irq_stack_size; - extern unsigned long _abt_stack; - extern unsigned long _abt_stack_size; - unsigned long *ptr; - int i; - - ptr = &_fiq_stack; - for (i = 0; i < ((int)&_fiq_stack_size/4); i++) { - ptr[i] = 0x13131313; - } - - ptr = &_irq_stack; - for (i = 0; i < ((int)&_irq_stack_size/4); i++) { - ptr[i] = 0xf0f0f0f0; - } - - ptr = &_abt_stack; - for (i = 0; i < ((int)&_abt_stack_size/4); i++) { - ptr[i] = 0x55555555; - } -#endif -} - -/*PAGE - * - * _CPU_Thread_Idle_body - * - * NOTES: - * - * 1. This is the same as the regular CPU independent algorithm. - * - * 2. If you implement this using a "halt", "idle", or "shutdown" - * instruction, then don't forget to put it in an infinite loop. - * - * 3. Be warned. Some processors with onboard DMA have been known - * to stop the DMA if the CPU were put in IDLE mode. This might - * also be a problem with other on-chip peripherals. So use this - * hook with caution. - */ - -void _CPU_Thread_Idle_body( void ) -{ - - while(1); /* FIXME: finish this */ - /* insert your "halt" instruction here */ ; -} - -void _defaultExcHandler (CPU_Exception_frame *ctx) -{ - printk("\n\r"); - printk("----------------------------------------------------------\n\r"); - printk("Exception 0x%x caught at PC 0x%x by thread %d\n", - ctx->register_pc, ctx->register_lr - 4, - _Thread_Executing->Object.id); - printk("----------------------------------------------------------\n\r"); - printk("Processor execution context at time of the fault was :\n\r"); - printk("----------------------------------------------------------\n\r"); - printk(" r0 = %8x r1 = %8x r2 = %8x r3 = %8x\n\r", - ctx->register_r0, ctx->register_r1, - ctx->register_r2, ctx->register_r3); - printk(" r4 = %8x r5 = %8x r6 = %8x r7 = %8x\n\r", - ctx->register_r4, ctx->register_r5, - ctx->register_r6, ctx->register_r7); - printk(" r8 = %8x r9 = %8x r10 = %8x\n\r", - ctx->register_r8, ctx->register_r9, ctx->register_r10); - printk(" fp = %8x ip = %8x sp = %8x pc = %8x\n\r", - ctx->register_fp, ctx->register_ip, - ctx->register_sp, ctx->register_lr - 4); - printk("----------------------------------------------------------\n\r"); - - if (_ISR_Nest_level > 0) { - /* - * In this case we shall not delete the task interrupted as - * it has nothing to do with the fault. We cannot return either - * because the eip points to the faulty instruction so... - */ - printk("Exception while executing ISR!!!. System locked\n\r"); - while(1); - } - else { - printk("*********** FAULTY THREAD WILL BE DELETED **************\n\r"); - rtems_task_delete(_Thread_Executing->Object.id); - } -} - -cpuExcHandlerType _currentExcHandler = _defaultExcHandler; - -extern void _Exception_Handler_Undef_Swi(); -extern void _Exception_Handler_Abort(); -/* FIXME: put comments here */ -void rtems_exception_init_mngt() -{ - ISR_Level level; - - _CPU_ISR_Disable(level); - _CPU_ISR_install_vector(ARM_EXCEPTION_UNDEF, - _Exception_Handler_Undef_Swi, - NULL); - - _CPU_ISR_install_vector(ARM_EXCEPTION_SWI, - _Exception_Handler_Undef_Swi, - NULL); - - _CPU_ISR_install_vector(ARM_EXCEPTION_PREF_ABORT, - _Exception_Handler_Abort, - NULL); - - _CPU_ISR_install_vector(ARM_EXCEPTION_DATA_ABORT, - _Exception_Handler_Abort, - NULL); - - _CPU_ISR_install_vector(ARM_EXCEPTION_FIQ, - _Exception_Handler_Abort, - NULL); - - _CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, - _Exception_Handler_Abort, - NULL); - - _CPU_ISR_Enable(level); -} - - diff --git a/c/src/exec/score/cpu/arm/cpu_asm.S b/c/src/exec/score/cpu/arm/cpu_asm.S deleted file mode 100644 index 60c638d80a..0000000000 --- a/c/src/exec/score/cpu/arm/cpu_asm.S +++ /dev/null @@ -1,216 +0,0 @@ -/* - * $Id$ - * - * This file contains all assembly code for the ARM implementation - * of RTEMS. - * - * Copyright (c) 2002 by Advent Networks, Inc. - * Jay Monkman <jmonkman@adventnetworks.com> - * - * COPYRIGHT (c) 2000 Canon Research Centre France SA. - * Emmanuel Raguet, mailto:raguet@crf.canon.fr - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - */ - -#include <asm.h> -#include <rtems/score/cpu_asm.h> - - -/* - * void _CPU_Context_switch( run_context, heir_context ) - * void _CPU_Context_restore( run_context, heir_context ) - * - * This routine performs a normal non-FP context. - * - * R0 = run_context R1 = heir_context - * - * This function copies the current registers to where r0 points, then - * restores the ones from where r1 points. - * - * - * NOTE: The function should be able to only save/restore the registers - * that would be saved by a C function since the others have already - * been saved. - * - * It should also be able to use the stm/ldm instructions. - * - */ - - .globl _CPU_Context_switch -_CPU_Context_switch: -/* FIXME: This should use load and store multiple instructions */ -/* Start saving context */ - str r2, [r0, #REG_R2] - str r3, [r0, #REG_R3] - str r4, [r0, #REG_R4] - str r5, [r0, #REG_R5] - str r6, [r0, #REG_R6] - str r7, [r0, #REG_R7] - str r8, [r0, #REG_R8] - str r9, [r0, #REG_R9] - str r10, [r0, #REG_R10] - - str r11, [r0, #REG_R11] - str r12, [r0, #REG_R12] - - str sp, [r0, #REG_SP] - str lr, [r0, #REG_PC] /* save LR at PC's location */ - - mrs r2, cpsr - str r2, [r0, #REG_CPSR] - -/* Start restoring context */ - - ldr r2, [r1, #REG_CPSR] - msr cpsr, r2 - - ldr r2, [r1, #REG_R2] - ldr r3, [r1, #REG_R3] - ldr r4, [r1, #REG_R4] - ldr r5, [r1, #REG_R5] - ldr r6, [r1, #REG_R6] - ldr r7, [r1, #REG_R7] - ldr r8, [r1, #REG_R8] - ldr r9, [r1, #REG_R9] - ldr r10, [r1, #REG_R10] - ldr r11, [r1, #REG_R11] - ldr r12, [r1, #REG_R12] - - ldr sp, [r1, #REG_SP] - ldr lr, [r1, #REG_PC] - mov pc, lr - -/* - * void _CPU_Context_restore( new_context ) - * - * This function copies the restores the registers from where r0 points. - * It must match _CPU_Context_switch() - * - * NOTE: The function should be able to only save/restore the registers - * that would be saved by a C function since the others have already - * been saved. - * - * It should also be able to use the stm/ldm instructions. - * - */ - .globl _CPU_Context_restore -_CPU_Context_restore: -/* FIXME: This should use load and store multiple instructions */ - ldr r2, [r0, #REG_CPSR] - msr cpsr, r2 - - ldr r2, [r0, #REG_R2] - ldr r3, [r0, #REG_R3] - ldr r4, [r0, #REG_R4] - ldr r5, [r0, #REG_R5] - ldr r6, [r0, #REG_R6] - ldr r7, [r0, #REG_R7] - ldr r8, [r0, #REG_R8] - ldr r9, [r0, #REG_R9] - ldr r10, [r0, #REG_R10] - ldr r11, [r1, #REG_R11] - ldr r12, [r1, #REG_R12] - - ldr sp, [r0, #REG_SP] - ldr lr, [r0, #REG_PC] - mov pc, lr - - -/* FIXME: _Exception_Handler_Undef_Swi is untested */ - .globl _Exception_Handler_Undef_Swi -_Exception_Handler_Undef_Swi: -/* FIXME: This should use load and store multiple instructions */ - sub r13,r13,#SIZE_REGS - str r0, [r13, #REG_R0] - str r1, [r13, #REG_R1] - str r2, [r13, #REG_R2] - str r3, [r13, #REG_R3] - str r4, [r13, #REG_R4] - str r5, [r13, #REG_R5] - str r6, [r13, #REG_R6] - str r7, [r13, #REG_R7] - str r8, [r13, #REG_R8] - str r9, [r13, #REG_R9] - str r10, [r13, #REG_R10] - str r11, [r13, #REG_R11] - str r12, [r13, #REG_R12] - str sp, [r13, #REG_SP] - str lr, [r13, #REG_LR] - mrs r0, cpsr /* read the status */ - and r0, r0,#0x1f /* we keep the mode as exception number */ - str r0, [r13, #REG_PC] /* we store it in a free place */ - mov r0, r13 /* put frame address in r0 (C arg 1) */ - - ldr r1, =SWI_Handler - ldr lr, =_go_back_1 - ldr pc,[r1] /* call handler */ -_go_back_1: - ldr r0, [r13, #REG_R0] - ldr r1, [r13, #REG_R1] - ldr r2, [r13, #REG_R2] - ldr r3, [r13, #REG_R3] - ldr r4, [r13, #REG_R4] - ldr r5, [r13, #REG_R5] - ldr r6, [r13, #REG_R6] - ldr r7, [r13, #REG_R7] - ldr r8, [r13, #REG_R8] - ldr r9, [r13, #REG_R9] - ldr r10, [r13, #REG_R10] - ldr r11, [r13, #REG_R11] - ldr r12, [r13, #REG_R12] - ldr sp, [r13, #REG_SP] - ldr lr, [r13, #REG_LR] - add r13,r13,#SIZE_REGS - movs pc,r14 /* return */ - -/* FIXME: _Exception_Handler_Abort is untested */ - .globl _Exception_Handler_Abort -_Exception_Handler_Abort: -/* FIXME: This should use load and store multiple instructions */ - sub r13,r13,#SIZE_REGS - str r0, [r13, #REG_R0] - str r1, [r13, #REG_R1] - str r2, [r13, #REG_R2] - str r3, [r13, #REG_R3] - str r4, [r13, #REG_R4] - str r5, [r13, #REG_R5] - str r6, [r13, #REG_R6] - str r7, [r13, #REG_R7] - str r8, [r13, #REG_R8] - str r9, [r13, #REG_R9] - str r10, [r13, #REG_R10] - str sp, [r13, #REG_R11] - str lr, [r13, #REG_R12] - str lr, [r13, #REG_SP] - str lr, [r13, #REG_LR] - mrs r0, cpsr /* read the status */ - and r0, r0,#0x1f /* we keep the mode as exception number */ - str r0, [r13, #REG_PC] /* we store it in a free place */ - mov r0, r13 /* put frame address in ro (C arg 1) */ - - ldr r1, =_currentExcHandler - ldr lr, =_go_back_2 - ldr pc,[r1] /* call handler */ -_go_back_2: - ldr r0, [r13, #REG_R0] - ldr r1, [r13, #REG_R1] - ldr r2, [r13, #REG_R2] - ldr r3, [r13, #REG_R3] - ldr r4, [r13, #REG_R4] - ldr r5, [r13, #REG_R5] - ldr r6, [r13, #REG_R6] - ldr r7, [r13, #REG_R7] - ldr r8, [r13, #REG_R8] - ldr r9, [r13, #REG_R9] - ldr r10, [r13, #REG_R10] - ldr sp, [r13, #REG_R11] - ldr lr, [r13, #REG_R12] - ldr lr, [r13, #REG_SP] - ldr lr, [r13, #REG_LR] - add r13,r13,#SIZE_REGS - subs pc,r14,#4 /* return */ - diff --git a/c/src/exec/score/cpu/arm/rtems/.cvsignore b/c/src/exec/score/cpu/arm/rtems/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/arm/rtems/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/arm/rtems/score/.cvsignore b/c/src/exec/score/cpu/arm/rtems/score/.cvsignore deleted file mode 100644 index 282522db03..0000000000 --- a/c/src/exec/score/cpu/arm/rtems/score/.cvsignore +++ /dev/null @@ -1,2 +0,0 @@ -Makefile -Makefile.in diff --git a/c/src/exec/score/cpu/arm/rtems/score/arm.h b/c/src/exec/score/cpu/arm/rtems/score/arm.h deleted file mode 100644 index 05aed89892..0000000000 --- a/c/src/exec/score/cpu/arm/rtems/score/arm.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * $Id$ - * - * - * COPYRIGHT (c) 2000 Canon Research Centre France SA. - * Emmanuel Raguet, mailto:raguet@crf.canon.fr - * - * Copyright (c) 2002 Advent Networks, Inc. - * Jay Monkman <jmonkman@adventnetworks.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - */ - -#ifndef _INCLUDE_ARM_h -#define _INCLUDE_ARM_h - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This file contains the information required to build - * RTEMS for a particular member of the "arm" - * family when executing in protected mode. It does - * this by setting variables to indicate which implementation - * dependent features are present in a particular member - * of the family. - */ -#if defined(__arm9__) -# define CPU_MODEL_NAME "arm9" -# define ARM_HAS_FPU 0 -#elif defined(__arm9tdmi__) -# define CPU_MODEL_NAME "arm9tdmi" -# define ARM_HAS_FPU 0 -#elif defined(__arm7__) -# define CPU_MODEL_NAME "arm7" -# define ARM_HAS_FPU 0 -#elif defined(__arm7tdmi__) -# define CPU_MODEL_NAME "arm7tdmi" -# define ARM_HAS_FPU 0 -#elif defined(__arm__) -# define CPU_MODEL_NAME "unknown ARM" -# define ARM_HAS_FPU 0 -#else -# error "Unsupported CPU Model" -#endif - -/* - * Define the name of the CPU family. - */ - -#define CPU_NAME "ARM" - -#ifdef __cplusplus -} -#endif - -#endif /* ! _INCLUDE_ARM_h */ -/* end of include file */ diff --git a/c/src/exec/score/cpu/arm/rtems/score/cpu.h b/c/src/exec/score/cpu/arm/rtems/score/cpu.h deleted file mode 100644 index 7074d0022e..0000000000 --- a/c/src/exec/score/cpu/arm/rtems/score/cpu.h +++ /dev/null @@ -1,962 +0,0 @@ -/* - * This include file contains information pertaining to the ARM - * processor. - * - * COPYRIGHT (c) 2002 Advent Networks, Inc. - * Jay Monkman <jmonkman@adventnetworks.com> - * - * COPYRIGHT (c) 2000 Canon Research Centre France SA. - * Emmanuel Raguet, mailto:raguet@crf.canon.fr - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * $Id$ - */ - -/* FIXME: finish commenting/cleaning up this file */ -#ifndef __CPU_h -#define __CPU_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/arm.h> /* pick up machine definitions */ -#ifndef ASM -#include <rtems/score/types.h> -#endif - -/* conditional compilation parameters */ - -/* - * Should the calls to _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * Basically this is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * [NOTE: In general, the _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls _Thread_Enable_dispatch which in turns calls - * _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely.] - */ - -#define CPU_INLINE_ENABLE_DISPATCH TRUE - -/* - * Should the body of the search loops in _Thread_queue_Enqueue_priority - * be unrolled one time? In unrolled each iteration of the loop examines - * two "nodes" on the chain being searched. Otherwise, only one node - * is examined per iteration. - * - * If TRUE, then the loops are unrolled. - * If FALSE, then the loops are not unrolled. - * - * The primary factor in making this decision is the cost of disabling - * and enabling interrupts (_ISR_Flash) versus the cost of rest of the - * body of the loop. On some CPUs, the flash is more expensive than - * one iteration of the loop body. In this case, it might be desirable - * to unroll the loop. It is important to note that on some CPUs, this - * code is the longest interrupt disable period in RTEMS. So it is - * necessary to strike a balance when setting this parameter. - */ - -#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE - -/* - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in _Interrupt_Manager_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE - -/* - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of CPU_HAS_SOFTWARE_INTERRU - * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - */ - -#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE - -/* - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE - * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. - */ - -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/* - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - */ - -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -/* - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "NO_CPU_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -#if ( ARM_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#else -#define CPU_HARDWARE_FP FALSE -#endif - -#define CPU_SOFTWARE_FP FALSE - -/* - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPU in which this option has been used is the - * HP PA-RISC. The HP C compiler and gcc both implicitly use the - * floating point registers to perform integer multiplies. If - * a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - */ - -#define CPU_ALL_TASKS_ARE_FP FALSE - -/* - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - */ - -#define CPU_IDLE_TASK_IS_FP FALSE - -/* - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - */ - -#define CPU_USE_DEFERRED_FP_SWITCH FALSE - -/* - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * 1. BSP provided - * 2. CPU dependent (if provided) - * 3. generic (if no BSP and no CPU dependent) - */ - -#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE - -/* - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - */ - -#define CPU_STACK_GROWS_UP FALSE - -/* - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * NOTE: Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - */ - -#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32))) - -/* - * Define what is required to specify how the network to host conversion - * routines are handled. - */ - -#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE -#define CPU_BIG_ENDIAN FALSE -#define CPU_LITTLE_ENDIAN TRUE - -/* - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). - */ - -#define CPU_MODES_INTERRUPT_MASK 0x000000c0 - -/* - * Processor defined structures - * - * Examples structures include the descriptor tables from the i386 - * and the processor control structure on the i960ca. - */ - -/* may need to put some structures here. */ - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - */ - -typedef struct { - unsigned32 register_r0; - unsigned32 register_r1; - unsigned32 register_r2; - unsigned32 register_r3; - unsigned32 register_r4; - unsigned32 register_r5; - unsigned32 register_r6; - unsigned32 register_r7; - unsigned32 register_r8; - unsigned32 register_r9; - unsigned32 register_r10; - unsigned32 register_fp; - unsigned32 register_ip; - unsigned32 register_sp; - unsigned32 register_lr; - unsigned32 register_pc; - unsigned32 register_cpsr; -} Context_Control; - -typedef struct { - double some_float_register; -} Context_Control_fp; - -typedef Context_Control CPU_Exception_frame; - -typedef void (*cpuExcHandlerType) (CPU_Exception_frame*); -extern cpuExcHandlerType _currentExcHandler; -extern void rtems_exception_init_mngt(); - -/* - * The following structure defines the set of information saved - * on the current stack by RTEMS upon receipt of each interrupt - * that will lead to re-enter the kernel to signal the thread. - */ - -typedef CPU_Exception_frame CPU_Interrupt_frame; - -/* - * The following table contains the information required to configure - * the ARM processor specific parameters. - */ - -typedef struct { - void (*pretasking_hook)( void ); - void (*predriver_hook)( void ); - void (*postdriver_hook)( void ); - void (*idle_task)( void ); - boolean do_zero_of_workspace; - unsigned32 idle_task_stack_size; - unsigned32 interrupt_stack_size; - unsigned32 extra_mpci_receive_server_stack; - void * (*stack_allocate_hook)( unsigned32 ); - void (*stack_free_hook)( void* ); - /* end of fields required on all CPUs */ - -} rtems_cpu_table; - -/* - * Macros to access required entires in the CPU Table are in - * the file rtems/system.h. - */ - -/* - * Macros to access NO_CPU specific additions to the CPU Table - */ - -/* There are no CPU specific additions to the CPU Table for this port. */ - -/* - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * _CPU_Initialize and copied into the task's FP context area during - * _CPU_Context_Initialize. - */ - -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; - -/* - * On some CPUs, RTEMS supports a software managed interrupt stack. - * This stack is allocated by the Interrupt Manager and the switch - * is performed in _ISR_Handler. These variables contain pointers - * to the lowest and highest addresses in the chunk of memory allocated - * for the interrupt stack. Since it is unknown whether the stack - * grows up or down (in general), this give the CPU dependent - * code the option of picking the version it wants to use. - * - * NOTE: These two variables are required if the macro - * CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. - */ - -SCORE_EXTERN void *_CPU_Interrupt_stack_low; -SCORE_EXTERN void *_CPU_Interrupt_stack_high; - -/* - * With some compilation systems, it is difficult if not impossible to - * call a high-level language routine from assembly language. This - * is especially true of commercial Ada compilers and name mangling - * C++ ones. This variable can be optionally defined by the CPU porter - * and contains the address of the routine _Thread_Dispatch. This - * can make it easier to invoke that routine at the end of the interrupt - * sequence (if a dispatch is necessary). - */ - -SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)(); - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - */ - -/* XXX: if needed, put more variables here */ - -/* - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - */ - -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/* - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - */ - -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/* - * This defines the number of entries in the ISR_Vector_table managed - * by RTEMS. - */ - -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 8 -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/* - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable _ISR_Nest_level. - */ - -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/* - * Should be large enough to run all RTEMS tests. This insures - * that a "reasonable" small application should not have any problems. - */ - -#define CPU_STACK_MINIMUM_SIZE (1024*16) - -/* - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - */ - -#define CPU_ALIGNMENT 4 - -/* - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, - * then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict - * enough for the partition, then this should be set to CPU_ALIGNMENT. - * - * NOTE: This does not have to be a power of 2. It does have to - * be greater or equal to than CPU_ALIGNMENT. - */ - -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/* - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT - * is strict enough for the stack, then this should be set to 0. - * - * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. - */ - -#define CPU_STACK_ALIGNMENT 4 - -/* ISR handler macros */ - -/* - * Support routine to initialize the RTEMS vector table after it is allocated. - */ - -#define _CPU_Initialize_vectors() - -/* - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in _level. - */ - -#define _CPU_ISR_Disable( _level ) \ - do { \ - int reg; \ - asm volatile ("MRS %0, cpsr \n" \ - "ORR %1, %0, #0xc0 \n" \ - "MSR cpsr, %1 \n" \ - "AND %0, %0, #0xc0 \n" \ - : "=r" (_level), "=r" (reg) \ - : "0" (_level), "1" (reg)); \ - } while (0) - -/* - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * _level is not modified. - */ - -#define _CPU_ISR_Enable( _level ) \ - do { \ - int reg; \ - asm volatile ("MRS %0, cpsr \n" \ - "BIC %0, %0, #0xc0 \n" \ - "ORR %0, %0, %2 \n" \ - "MSR cpsr, %0 \n" \ - : "=r" (reg) \ - : "0" (reg), "r" (_level)); \ - } while (0) - -/* - * This temporarily restores the interrupt to _level before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter _level is not - * modified. - */ - -#define _CPU_ISR_Flash( _level ) \ - { \ - int reg1; \ - int reg2; \ - asm volatile ("MRS %0, cpsr \n" \ - "BIC %1, %0, #0xc0 \n" \ - "ORR %1, %1, %4 \n" \ - "MSR cpsr, %1 \n" \ - "MSR cpsr, %0 \n" \ - : "=r" (reg1), "=r" (reg2) \ - : "0" (reg1), "1" (reg2), "r" (_level)); \ - } - -/* - * Map interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * The get routine usually must be implemented as a subroutine. - */ - -#define _CPU_ISR_Set_level( new_level ) \ - { \ - int reg; \ - asm volatile ("MRS %0, cpsr \n" \ - "BIC %0, %0, #0xc0 \n" \ - "ORR %0, %0, %2 \n" \ - "MSR cpsr_c, %0 \n" \ - : "=r" (reg) \ - : "0" (reg), "r" (new_level)); \ - } - - -unsigned32 _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/* Context handler macros */ - -/* - * Initialize the context to a state suitable for starting a - * task after a context restore operation. Generally, this - * involves: - * - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - initializing the floating point context - * - * This routine generally does not set any unnecessary register - * in the context. The state of the "general data" registers is - * undefined at task start time. - * - * NOTE: This is_fp parameter is TRUE if the thread is to be a floating - * point thread. This is typically only used on CPUs where the - * FPU may be easily disabled by software such as on the SPARC - * where the PSR contains an enable FPU bit. - */ - -void _CPU_Context_Initialize( - Context_Control *the_context, - unsigned32 *stack_base, - unsigned32 size, - unsigned32 new_level, - void *entry_point, - boolean is_fp -); - -/* - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. Context_Restore should work most of the time. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - */ - -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/* - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - */ - -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -/* - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other models include (1) not doing anything, and (2) putting - * a "null FP status word" in the correct place in the FP context. - */ - -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \ - } - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/* - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - */ - -#define _CPU_Fatal_halt( _error ) \ - { \ - } - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/* - * This routine sets _output to the bit number of the first bit - * set in _value. _value is of CPU dependent type Priority_Bit_map_control. - * This type may be either 16 or 32 bits wide although only the 16 - * least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * (1) What happens when run on a value of zero? - * (2) Bits may be numbered from MSB to LSB or vice-versa. - * (3) The numbering may be zero or one based. - * (4) The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and - * _CPU_Priority_bits_index(). These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by _CPU_Priority_mask(). - * The basic major and minor values calculated by _Priority_Major() - * and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index() - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for _Priority_Get_highest() to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * - * - a series of 16 bit test instructions - * - a "binary search using if's" - * - _number = 0 - * if _value > 0x00ff - * _value >>=8 - * _number = 8; - * - * if _value > 0x0000f - * _value >=8 - * _number += 4 - * - * _number += bit_set_table[ _value ] - * - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - */ - -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - (_output) = 0; /* do something to prevent warnings */ \ - } - -#endif - -/* end of Bitfield handler macros */ - -/* - * This routine builds the mask which corresponds to the bit fields - * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion - * for that routine. - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#endif - -/* - * This routine translates the bit numbers returned by - * _CPU_Bitfield_Find_first_bit() into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -/* end of Priority handler macros */ - -/* functions */ - -/* - * _CPU_Initialize - * - * This routine performs CPU dependent initialization. - */ - -void _CPU_Initialize( - rtems_cpu_table *cpu_table, - void (*thread_dispatch) -); - -typedef enum { - ARM_EXCEPTION_RESET = 0, - ARM_EXCEPTION_UNDEF = 1, - ARM_EXCEPTION_SWI = 2, - ARM_EXCEPTION_PREF_ABORT = 3, - ARM_EXCEPTION_DATA_ABORT = 4, - ARM_EXCEPTION_RESERVED = 5, - ARM_EXCEPTION_IRQ = 6, - ARM_EXCEPTION_FIQ = 7, - MAX_EXCEPTIONS = 8 -} Arm_symbolic_exception_name; - -/* - * _CPU_ISR_install_vector - * - * This routine installs an interrupt vector. - */ - -void _CPU_ISR_install_vector( - unsigned32 vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/* - * _CPU_Install_interrupt_stack - * - * This routine installs the hardware interrupt stack pointer. - * - * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - */ - -void _CPU_Install_interrupt_stack( void ); - -/* - * _CPU_Thread_Idle_body - * - * This routine is the CPU dependent IDLE thread body. - * - * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - */ - -void _CPU_Thread_Idle_body( void ); - -/* - * _CPU_Context_switch - * - * This routine switches from the run context to the heir context. - */ - -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/* - * _CPU_Context_restore - * - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in _CPU_Context_switch. - * - * NOTE: May be unnecessary to reload some registers. - */ - -void _CPU_Context_restore( - Context_Control *new_context -); - -/* - * _CPU_Context_save_fp - * - * This routine saves the floating point context passed to it. - */ - -void _CPU_Context_save_fp( - void **fp_context_ptr -); - -/* - * _CPU_Context_restore_fp - * - * This routine restores the floating point context passed to it. - */ - -void _CPU_Context_restore_fp( - void **fp_context_ptr -); - -/* The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to insure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - */ - -static inline unsigned int CPU_swap_u32( - unsigned int value -) -{ - unsigned32 byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return( swapped ); -} - -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/c/src/exec/score/cpu/arm/rtems/score/cpu_asm.h b/c/src/exec/score/cpu/arm/rtems/score/cpu_asm.h deleted file mode 100644 index 2c13347578..0000000000 --- a/c/src/exec/score/cpu/arm/rtems/score/cpu_asm.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * $Id$ - * - * Copyright (c) 2002 by Advent Networks, Inc. - * Jay Monkman <jmonkman@adventnetworks.com> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * This file is the include file for cpu_asm.S - * - * - */ - -#ifndef __CPU_ASM_h -#define __CPU_ASM_h - - -/* Registers saved in context switch: */ -.set REG_R0, 0 -.set REG_R1, 4 -.set REG_R2, 8 -.set REG_R3, 12 -.set REG_R4, 16 -.set REG_R5, 20 -.set REG_R6, 24 -.set REG_R7, 28 -.set REG_R8, 32 -.set REG_R9, 36 -.set REG_R10, 40 -.set REG_R11, 44 -.set REG_R12, 48 -.set REG_SP, 52 -.set REG_LR, 56 -.set REG_PC, 60 -.set REG_CPSR, 64 -.set SIZE_REGS, REG_CPSR + 4 - - -#endif diff --git a/c/src/exec/score/cpu/arm/rtems/score/types.h b/c/src/exec/score/cpu/arm/rtems/score/types.h deleted file mode 100644 index 4408046d4e..0000000000 --- a/c/src/exec/score/cpu/arm/rtems/score/types.h +++ /dev/null @@ -1,55 +0,0 @@ -/* armtypes.h - * - * This include file contains type definitions pertaining to the - * arm processor family. - * - * COPYRIGHT (c) 2000 Canon Research Centre France SA. - * Emmanuel Raguet, mailto:raguet@crf.canon.fr - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - */ - -#ifndef __ARM_TYPES_h -#define __ARM_TYPES_h - -#ifndef ASM - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * This section defines the basic types for this processor. - */ - -typedef unsigned char unsigned8; /* unsigned 8-bit integer */ -typedef unsigned short unsigned16; /* unsigned 16-bit integer */ -typedef unsigned int unsigned32; /* unsigned 32-bit integer */ -typedef unsigned long long unsigned64; /* unsigned 64-bit integer */ - -typedef unsigned16 Priority_Bit_map_control; - -typedef signed char signed8; /* 8-bit signed integer */ -typedef signed short signed16; /* 16-bit signed integer */ -typedef signed int signed32; /* 32-bit signed integer */ -typedef signed long long signed64; /* 64 bit signed integer */ - -typedef unsigned32 boolean; /* Boolean value */ - -typedef float single_precision; /* single precision float */ -typedef double double_precision; /* double precision float */ - -typedef void no_cpu_isr; -typedef void ( *no_cpu_isr_entry )( void ); - -#ifdef __cplusplus -} -#endif - -#endif /* !ASM */ - -#endif -/* end of include file */ |