diff options
Diffstat (limited to '')
-rw-r--r-- | bsps/shared/dev/clock/arm-generic-timer.c | 19 | ||||
-rw-r--r-- | bsps/shared/dev/clock/bcm2835-system-timer.c (renamed from bsps/arm/raspberrypi/clock/clockdrv.c) | 30 | ||||
-rw-r--r-- | bsps/shared/dev/clock/clockimpl.h | 54 | ||||
-rw-r--r-- | bsps/shared/dev/clock/xil-ttc.c | 214 |
4 files changed, 266 insertions, 51 deletions
diff --git a/bsps/shared/dev/clock/arm-generic-timer.c b/bsps/shared/dev/clock/arm-generic-timer.c index 1188800170..ba159f6833 100644 --- a/bsps/shared/dev/clock/arm-generic-timer.c +++ b/bsps/shared/dev/clock/arm-generic-timer.c @@ -54,15 +54,12 @@ typedef struct { static arm_gt_clock_context arm_gt_clock_instance; -/* This is defined in dev/clock/clockimpl.h */ -void Clock_isr(rtems_irq_hdl_param arg); - -static void arm_gt_clock_at_tick(void) +static void arm_gt_clock_at_tick(arm_gt_clock_context *ctx) { uint64_t cval; uint32_t interval; - interval = arm_gt_clock_instance.interval; + interval = ctx->interval; cval = arm_gt_clock_get_compare_value(); cval += interval; arm_gt_clock_set_compare_value(cval); @@ -71,7 +68,7 @@ static void arm_gt_clock_at_tick(void) #endif /* ARM_GENERIC_TIMER_UNMASK_AT_TICK */ } -static void arm_gt_clock_handler_install(void) +static void arm_gt_clock_handler_install(rtems_interrupt_handler handler) { rtems_status_code sc; @@ -79,8 +76,8 @@ static void arm_gt_clock_handler_install(void) arm_gt_clock_instance.irq, "Clock", RTEMS_INTERRUPT_UNIQUE, - (rtems_interrupt_handler) Clock_isr, - NULL + handler, + &arm_gt_clock_instance ); if (sc != RTEMS_SUCCESSFUL) { bsp_fatal(BSP_ARM_FATAL_GENERIC_TIMER_CLOCK_IRQ_INSTALL); @@ -185,14 +182,14 @@ RTEMS_SYSINIT_ITEM( RTEMS_SYSINIT_ORDER_FIRST ); -#define Clock_driver_support_at_tick() \ - arm_gt_clock_at_tick() +#define Clock_driver_support_at_tick(arg) \ + arm_gt_clock_at_tick(arg) #define Clock_driver_support_initialize_hardware() \ arm_gt_clock_initialize() #define Clock_driver_support_install_isr(isr) \ - arm_gt_clock_handler_install() + arm_gt_clock_handler_install(isr) /* Include shared source clock driver code */ #include "../../shared/dev/clock/clockimpl.h" diff --git a/bsps/arm/raspberrypi/clock/clockdrv.c b/bsps/shared/dev/clock/bcm2835-system-timer.c index 8d220d51ba..bb8490d03a 100644 --- a/bsps/arm/raspberrypi/clock/clockdrv.c +++ b/bsps/shared/dev/clock/bcm2835-system-timer.c @@ -25,9 +25,6 @@ #include <bsp/raspberrypi.h> #include <rtems/timecounter.h> -/* This is defined in ../../../shared/dev/clock/clockimpl.h */ -void Clock_isr(rtems_irq_hdl_param arg); - static struct timecounter raspberrypi_tc; static uint32_t raspberrypi_clock_get_timecount(struct timecounter *tc) @@ -54,27 +51,18 @@ static void raspberrypi_clock_at_tick(void) } static void raspberrypi_clock_handler_install_isr( - rtems_isr_entry clock_isr + rtems_interrupt_handler clock_isr ) { rtems_status_code sc = RTEMS_SUCCESSFUL; - if (clock_isr != NULL) { - sc = rtems_interrupt_handler_install( - BCM2835_IRQ_ID_GPU_TIMER_M3, - "Clock", - RTEMS_INTERRUPT_UNIQUE, - (rtems_interrupt_handler) clock_isr, - NULL - ); - } else { - /* Remove interrupt handler */ - sc = rtems_interrupt_handler_remove( - BCM2835_IRQ_ID_GPU_TIMER_M3, - (rtems_interrupt_handler) Clock_isr, - NULL - ); - } + sc = rtems_interrupt_handler_install( + BCM2835_IRQ_ID_GPU_TIMER_M3, + "Clock", + RTEMS_INTERRUPT_UNIQUE, + clock_isr, + NULL + ); if ( sc != RTEMS_SUCCESSFUL ) { rtems_fatal_error_occurred(0xdeadbeef); } @@ -94,7 +82,7 @@ static void raspberrypi_clock_initialize_hardware(void) rtems_timecounter_install(&raspberrypi_tc); } -#define Clock_driver_support_at_tick() raspberrypi_clock_at_tick() +#define Clock_driver_support_at_tick(arg) raspberrypi_clock_at_tick() #define Clock_driver_support_initialize_hardware() raspberrypi_clock_initialize_hardware() diff --git a/bsps/shared/dev/clock/clockimpl.h b/bsps/shared/dev/clock/clockimpl.h index e922c0b320..b27f7c15bc 100644 --- a/bsps/shared/dev/clock/clockimpl.h +++ b/bsps/shared/dev/clock/clockimpl.h @@ -42,6 +42,7 @@ #include <bsp.h> #include <rtems/clockdrv.h> #include <rtems/score/percpu.h> +#include <rtems/score/processormaskimpl.h> #include <rtems/score/smpimpl.h> #include <rtems/score/timecounter.h> #include <rtems/score/thread.h> @@ -63,6 +64,13 @@ #error "Fast Idle PLUS n ISRs per tick is not supported" #endif +#if defined(BSP_FEATURE_IRQ_EXTENSION) || \ + (CPU_SIMPLE_VECTORED_INTERRUPTS != TRUE) +typedef void * Clock_isr_argument; +#else +typedef rtems_vector_number Clock_isr_argument; +#endif + /** * @brief Do nothing by default. */ @@ -81,7 +89,7 @@ * @brief Do nothing by default. */ #ifndef Clock_driver_support_at_tick - #define Clock_driver_support_at_tick() + #define Clock_driver_support_at_tick( arg ) do { (void) arg; } while (0) #endif /** @@ -96,8 +104,9 @@ * instead of the default. */ #ifndef Clock_driver_timecounter_tick -static void Clock_driver_timecounter_tick( void ) +static void Clock_driver_timecounter_tick( Clock_isr_argument arg ) { + (void) arg; #if defined(CLOCK_DRIVER_USE_DUMMY_TIMECOUNTER) rtems_clock_tick(); #elif defined(RTEMS_SMP) && defined(CLOCK_DRIVER_USE_ONLY_BOOT_PROCESSOR) @@ -139,25 +148,31 @@ volatile uint32_t Clock_driver_ticks; #error "Clock_driver_support_shutdown_hardware() is no longer supported" #endif +#if CLOCK_DRIVER_USE_FAST_IDLE +static bool _Clock_Has_watchdogs(const Per_CPU_Control *cpu) +{ + size_t i; + + for (i = 0; i < RTEMS_ARRAY_SIZE(cpu->Watchdog.Header); ++i) { + if (_Watchdog_Header_first(&cpu->Watchdog.Header[i]) != NULL) { + return true; + } + } + + return false; +} +#endif + /** * @brief Clock_isr * * This is the clock tick interrupt handler. * - * @param vector Vector number. + * @param arg is the clock interrupt handler argument. */ -#if defined(BSP_FEATURE_IRQ_EXTENSION) || \ - (CPU_SIMPLE_VECTORED_INTERRUPTS != TRUE) -void Clock_isr(void *arg); -void Clock_isr(void *arg) -{ -#else -rtems_isr Clock_isr(rtems_vector_number vector); -rtems_isr Clock_isr( - rtems_vector_number vector -) +void Clock_isr( Clock_isr_argument arg ); +void Clock_isr( Clock_isr_argument arg ) { -#endif /* * Accurate count of ISRs */ @@ -165,7 +180,7 @@ rtems_isr Clock_isr( #if CLOCK_DRIVER_USE_FAST_IDLE { - Clock_driver_timecounter_tick(); + Clock_driver_timecounter_tick( arg ); if (_SMP_Get_processor_maximum() == 1) { struct timecounter *tc; @@ -182,6 +197,7 @@ rtems_isr Clock_isr( cpu_self->thread_dispatch_disable_level == cpu_self->isr_nest_level && cpu_self->heir == cpu_self->executing && cpu_self->executing->is_idle + && _Clock_Has_watchdogs(cpu_self) ) { ISR_lock_Context lock_context; @@ -194,7 +210,7 @@ rtems_isr Clock_isr( } } - Clock_driver_support_at_tick(); + Clock_driver_support_at_tick( arg ); } #else /* @@ -202,14 +218,14 @@ rtems_isr Clock_isr( * * The counter/timer may or may not be set to automatically reload. */ - Clock_driver_support_at_tick(); + Clock_driver_support_at_tick( arg ); #if CLOCK_DRIVER_ISRS_PER_TICK /* * The driver is multiple ISRs per clock tick. */ if ( !Clock_driver_isrs ) { - Clock_driver_timecounter_tick(); + Clock_driver_timecounter_tick( arg ); Clock_driver_isrs = CLOCK_DRIVER_ISRS_PER_TICK_VALUE; } @@ -218,7 +234,7 @@ rtems_isr Clock_isr( /* * The driver is one ISR per clock tick. */ - Clock_driver_timecounter_tick(); + Clock_driver_timecounter_tick( arg ); #endif #endif } diff --git a/bsps/shared/dev/clock/xil-ttc.c b/bsps/shared/dev/clock/xil-ttc.c new file mode 100644 index 0000000000..624845d71c --- /dev/null +++ b/bsps/shared/dev/clock/xil-ttc.c @@ -0,0 +1,214 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDriverClockXilTTC + * + * @brief This source file contains a Clock Driver implementation using the + * Xilinx Triple Timer Counter (TTC). + */ + +/* + * Copyright (C) 2024 embedded brains GmbH & Co. KG + * Copyright (C) 2023 Reflex Aerospace GmbH + * + * Written by Philip Kirkpatrick <p.kirkpatrick@reflexaerospace.com> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <bsp.h> +#include <bsp/irq.h> +#include <bsp/fatal.h> +#include <dev/clock/xttcps_hw.h> +#include <rtems/sysinit.h> +#include <rtems/timecounter.h> + +#if XTTCPS_COUNT_VALUE_MASK != UINT32_MAX +#error "unexpected XTTCPS_COUNT_VALUE_MASK value" +#endif + +/** + * @defgroup RTEMSDriverClockXilTTC \ + * Xilinx Triple Timer Counter (TTC) Clock Driver + * + * @ingroup RTEMSDriverClockImpl + * + * @brief This group contains the Xilinx Triple Timer Counter (TTC) Clock + * Driver implementation. + * + * @{ + */ + +uint32_t _CPU_Counter_frequency( void ) +{ + return XIL_CLOCK_TTC_REFERENCE_CLOCK; +} + +CPU_Counter_ticks _CPU_Counter_read(void) +{ + return XTtcPs_ReadReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_COUNT_VALUE_OFFSET); +} + +static void xil_ttc_initialize(void) +{ + /* Do not use a prescaler to get a high resolution time source */ + XTtcPs_WriteReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_CLK_CNTRL_OFFSET, 0); + + /* Disable interupts */ + XTtcPs_WriteReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_IER_OFFSET, 0); + + /* + * Enable the timer, do not enable waveform output, increment up, use + * overflow mode, enable match mode. + */ + XTtcPs_WriteReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_CNT_CNTRL_OFFSET, + XTTCPS_CNT_CNTRL_EN_WAVE_MASK | XTTCPS_CNT_CNTRL_MATCH_MASK); +} + +RTEMS_SYSINIT_ITEM( + xil_ttc_initialize, + RTEMS_SYSINIT_CPU_COUNTER, + RTEMS_SYSINIT_ORDER_MIDDLE +); + +typedef struct { + struct timecounter base; + uint32_t irq_match_interval; +} xil_ttc_timecounter; + +static xil_ttc_timecounter xil_ttc_clock_instance; + +static uint32_t xil_ttc_get_timecount(struct timecounter *tc) +{ + (void) tc; + return XTtcPs_ReadReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_COUNT_VALUE_OFFSET); +} + +static void xil_ttc_clock_driver_support_initialize_hardware(void) +{ + xil_ttc_timecounter *tc; + uint64_t frequency; + uint32_t irq_match_interval; + uint32_t count; + + tc = &xil_ttc_clock_instance; + frequency = XIL_CLOCK_TTC_REFERENCE_CLOCK; + irq_match_interval = (uint32_t) + ((frequency * rtems_configuration_get_microseconds_per_tick()) / 1000000); + + /* Setup match register to generate clock interrupts */ + count = XTtcPs_ReadReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_COUNT_VALUE_OFFSET); + XTtcPs_WriteReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_MATCH_0_OFFSET, + count + irq_match_interval); + + /* Clear interupts (clear on read) */ + (void) XTtcPs_ReadReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_ISR_OFFSET); + + /* Enable interupt for match register */ + XTtcPs_WriteReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_IER_OFFSET, + XTTCPS_IXR_MATCH_0_MASK); + + /* Install timecounter */ + tc->irq_match_interval = irq_match_interval; + tc->base.tc_counter_mask = UINT32_MAX; + tc->base.tc_frequency = XIL_CLOCK_TTC_REFERENCE_CLOCK; + tc->base.tc_get_timecount = xil_ttc_get_timecount; + tc->base.tc_quality = RTEMS_TIMECOUNTER_QUALITY_CLOCK_DRIVER; + rtems_timecounter_install(&tc->base); +} + +static void xil_ttc_clock_driver_support_at_tick(xil_ttc_timecounter *tc) +{ + uint32_t irq_match_interval; + uint32_t count; + uint32_t match; + + irq_match_interval = tc->irq_match_interval; + + /* Update match register */ + match = XTtcPs_ReadReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_MATCH_0_OFFSET); + match += irq_match_interval; + XTtcPs_WriteReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_MATCH_0_OFFSET, match); + + /* Clear interupts (clear on read) */ + (void) XTtcPs_ReadReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_ISR_OFFSET); + + /* Check that the new match value is in the future */ + count = XTtcPs_ReadReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_COUNT_VALUE_OFFSET); + + while (RTEMS_PREDICT_FALSE(match - count > irq_match_interval)) { + /* + * Tick misses may happen if interrupts are disabled for an extremly long + * period or while debugging. + */ + rtems_timecounter_tick(); + + /* Update match register */ + match += irq_match_interval; + XTtcPs_WriteReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_MATCH_0_OFFSET, match); + + /* Clear interupts (clear on read) */ + (void) XTtcPs_ReadReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_ISR_OFFSET); + + /* Maybe the new match value is now in the future */ + count = XTtcPs_ReadReg(XIL_CLOCK_TTC_BASE_ADDR, XTTCPS_COUNT_VALUE_OFFSET); + } +} + +static rtems_interrupt_entry xil_ttc_interrupt_entry; + +static void xil_ttc_clock_driver_support_install_isr( + rtems_interrupt_handler handler +) +{ + rtems_status_code sc; + + rtems_interrupt_entry_initialize( + &xil_ttc_interrupt_entry, + handler, + &xil_ttc_clock_instance, + "Clock" + ); + sc = rtems_interrupt_entry_install( + XIL_CLOCK_TTC_IRQ, + RTEMS_INTERRUPT_UNIQUE, + &xil_ttc_interrupt_entry + ); + if ( sc != RTEMS_SUCCESSFUL ) { + bsp_fatal(XIL_FATAL_TTC_IRQ_INSTALL); + } +} + +#define Clock_driver_support_at_tick(arg) \ + xil_ttc_clock_driver_support_at_tick(arg) + +#define Clock_driver_support_initialize_hardware \ + xil_ttc_clock_driver_support_initialize_hardware + +#define Clock_driver_support_install_isr(isr) \ + xil_ttc_clock_driver_support_install_isr(isr) + +/** @} */ + +#include "../../../shared/dev/clock/clockimpl.h" |