diff options
Diffstat (limited to 'bsps/sh/gensh2')
-rw-r--r-- | bsps/sh/gensh2/start/bsp_specs | 9 | ||||
-rw-r--r-- | bsps/sh/gensh2/start/cpu_asm.c | 182 | ||||
-rw-r--r-- | bsps/sh/gensh2/start/hw_init.c | 112 | ||||
-rw-r--r-- | bsps/sh/gensh2/start/ispsh7045.c | 310 | ||||
-rw-r--r-- | bsps/sh/gensh2/start/linkcmds | 241 | ||||
-rw-r--r-- | bsps/sh/gensh2/start/linkcmds.ram | 244 | ||||
-rw-r--r-- | bsps/sh/gensh2/start/linkcmds.rom | 248 |
7 files changed, 1346 insertions, 0 deletions
diff --git a/bsps/sh/gensh2/start/bsp_specs b/bsps/sh/gensh2/start/bsp_specs new file mode 100644 index 0000000000..87638cc027 --- /dev/null +++ b/bsps/sh/gensh2/start/bsp_specs @@ -0,0 +1,9 @@ +%rename endfile old_endfile +%rename startfile old_startfile + +*startfile: +%{!qrtems: %(old_startfile)} \ +%{!nostdlib: %{qrtems: crti.o%s crtbegin.o%s}} + +*endfile: +%{!qrtems: %(old_endfile)} %{qrtems: crtend.o%s crtn.o%s} diff --git a/bsps/sh/gensh2/start/cpu_asm.c b/bsps/sh/gensh2/start/cpu_asm.c new file mode 100644 index 0000000000..47bc859dbd --- /dev/null +++ b/bsps/sh/gensh2/start/cpu_asm.c @@ -0,0 +1,182 @@ +/* + * This file contains the basic algorithms for all assembly code used + * in an specific CPU port of RTEMS. These algorithms must be implemented + * in assembly language + * + * NOTE: This port uses a C file with inline assembler instructions + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +/* + * This is supposed to be an assembly file. This means that system.h + * and cpu.h should not be included in a "real" cpu_asm file. An + * implementation in assembly should include "cpu_asm.h" + */ + +#include <rtems/system.h> +#include <rtems/score/cpu.h> +#include <rtems/score/isr.h> +#include <rtems/score/threaddispatch.h> +#include <rtems/score/sh.h> + +#include <rtems/score/ispsh7045.h> +#include <rtems/score/iosh7045.h> +#include <rtems/score/sh_io.h> + +/* from cpu_isps.c */ +extern proc_ptr _Hardware_isr_Table[]; + +#if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) + unsigned long *_old_stack_ptr; +#endif + +register unsigned long *stack_ptr __asm__ ("r15"); + +/* + * sh_set_irq_priority + * + * this function sets the interrupt level of the specified interrupt + * + * parameters: + * - irq : interrupt number + * - prio: priority to set for this interrupt number + * + * returns: 0 if ok + * -1 on error + */ + +unsigned int sh_set_irq_priority( + unsigned int irq, + unsigned int prio ) +{ + uint32_t shiftcount; + uint32_t prioreg; + uint16_t temp16; + ISR_Level level; + + /* + * first check for valid interrupt + */ + if (( irq > 156) || (irq < 64) || (_Hardware_isr_Table[irq] == _dummy_isp)) + return -1; + /* + * check for valid irq priority + */ + if ( prio > 15 ) + return -1; + + /* + * look up appropriate interrupt priority register + */ + if ( irq > 71) + { + irq = irq - 72; + shiftcount = 12 - ((irq & ~0x03) % 16); + + switch( irq / 16) + { + case 0: { prioreg = INTC_IPRC; break;} + case 1: { prioreg = INTC_IPRD; break;} + case 2: { prioreg = INTC_IPRE; break;} + case 3: { prioreg = INTC_IPRF; break;} + case 4: { prioreg = INTC_IPRG; break;} + case 5: { prioreg = INTC_IPRH; break;} + default: return -1; + } + } + else + { + shiftcount = 12 - 4 * ( irq % 4); + if ( irq > 67) + prioreg = INTC_IPRB; + else + prioreg = INTC_IPRA; + } + + /* + * Set the interrupt priority register + */ + _ISR_Local_disable( level ); + + temp16 = read16( prioreg); + temp16 &= ~( 15 << shiftcount); + temp16 |= prio << shiftcount; + write16( temp16, prioreg); + + _ISR_Local_enable( level ); + + return 0; +} + +/* + * This routine provides the RTEMS interrupt management. + */ + +void __ISR_Handler( uint32_t vector) +{ + ISR_Level level; + + _ISR_Local_disable( level ); + + _Thread_Dispatch_disable(); + +#if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) + if ( _ISR_Nest_level == 0 ) + { + /* Install irq stack */ + _old_stack_ptr = stack_ptr; + stack_ptr = _CPU_Interrupt_stack_high; + } + +#endif + + _ISR_Nest_level++; + + _ISR_Local_enable( level ); + + /* call isp */ + if ( _ISR_Vector_table[ vector]) + (*_ISR_Vector_table[ vector ])( vector ); + + _ISR_Local_disable( level ); + + _Thread_Dispatch_unnest( _Per_CPU_Get() ); + + _ISR_Nest_level--; + +#if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) + + if ( _ISR_Nest_level == 0 ) + /* restore old stack pointer */ + stack_ptr = _old_stack_ptr; +#endif + + _ISR_Local_enable( level ); + + if ( _ISR_Nest_level ) + return; + + if ( !_Thread_Dispatch_is_enabled() ) { + return; + } + + if ( _Thread_Dispatch_necessary ) { + _Thread_Dispatch(); + } +} diff --git a/bsps/sh/gensh2/start/hw_init.c b/bsps/sh/gensh2/start/hw_init.c new file mode 100644 index 0000000000..f3cbb54ecf --- /dev/null +++ b/bsps/sh/gensh2/start/hw_init.c @@ -0,0 +1,112 @@ +/* + * hw_init.c: set up sh7045F internal subunits + * Pin and memory assignments assume + * target is Hitachi SH7045F EVB ("lcevb") + * + * Provides two initialization routines: + * A. 'void early_hw_init(void)' for 'start.S' + * sets up hw needed for early RTEMS boot, and + * B. 'void bsp_hw_init(void)' for 'bspstart.c' + * sets up hardware used by this BSP. + * + * Author: John M. Mills (jmills@tga.com) + * COPYRIGHT(c) 2000, TGA Technologies, Inc + * Norcross, GA 30071 U.S.A + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Adapted from Hitachi EVB7045F tutorial files by: + * John M. Mills (jmills@tga.com) + * TGA Technologies, Inc. + * 100 Pinnacle Way, Suite 140 + * Norcross, GA 30071 U.S.A. + * + * + * This file may be copied and distributed in accordance + * the above-referenced license. It is provided for critique and + * developmental purposes without any warranty nor representation + * by the authors or by TGA Technologies. + */ + +#include <bsp.h> + +#include <stdlib.h> + +#include <rtems/libio.h> +#include <rtems/score/sh_io.h> +#include <rtems/score/iosh7045.h> + +/* exported entries */ +extern void bsp_hw_init (void); +extern void early_hw_init (void); + +/* called from 'start.S' on "#ifdef START_HW_INIT" */ +void early_hw_init (void) +{ +#ifdef STANDALONE_EVB + /* STANDALONE_EVB minimally sets up bus and DRAM here */ + /* no STANDALONE_EVB accepts defaults from debug monitor */ + + /* FIXME: replace 'magic numbers' with logical names */ + + write16(0x2020, BSC_BCR1); /* Bus width access - 32-bit on CS1 */ + write16(0xF3DD, BSC_BCR2); /* Idle cycles CS3-CS0 - 0 idle cycles*/ + write16(0xFF3F, BSC_WCR1); /* Waits for CS3-CS0 - 3 waits on CS1 */ + write16(0x000F, BSC_WCR2); /* Waits for DRAM/DMA access - default */ + write16(0x0000, BSC_DCR); /* DRAM control - default */ + write16(0x0000, BSC_RTCSR); /* DRAM refresh - default */ + write16(0x0000, BSC_RTCNT); /* DRAM refresh counter - default*/ + write16(0x0000, BSC_RTCOR); /* DRAM refresh compare match - default */ +#endif + + /* add early-init functions here */ + +}; + +/* to be called from 'bspstart.c' */ +void bsp_hw_init (void) +{ + uint16_t temp16; + +#ifdef STANDALONE_EVB + /* STANDALONE_EVB: sets up PFC */ + /* no STANDALONE_EVB: accepts defaults, adds RESET */ + + /* FIXME: replace 'magic numbers' */ + + write16(0x5000, PFC_PACRH); /* Pin function controller - WRHH, WRHL */ + write16(0x1550, PFC_PACRL1); /* Pin fun. controller - WRH,WRL,RD,CS1 */ + write16(0x0000, PFC_PBCR1); /* Pin function controller - default */ + write16(0x2005, PFC_PBCR2); /* Pin fcn. controller - A18,A17,A16 */ + write16(0xFFFF, PFC_PCCR); /* Pin function controller - A15-A0 */ + write16(0x5555, PFC_PDCRH1); /* Pin function controller - D31-D24 */ + write16(0x5555, PFC_PDCRH2); /* Pin function controller - D23-D16 */ + write16(0xFFFF, PFC_PDCRL); /* Pin function controller - D15-D0 */ + write16(0x0000, PFC_IFCR); /* Pin function controller - default */ + write16(0x0000, PFC_PACRL2); /* default disconnects all I/O pins;*/ + /* [re-connected by DEVICE_open()] */ +#endif + + /* default hardware setup for SH7045F EVB */ + + /* PFC: General I/O except pin 13 (reset): */ + temp16 = read16(PFC_PECR1); + temp16 |= 0x0800; + write16(temp16, PFC_PECR1); + + /* All I/O lines bits 7-0: */ + write16(0x00, PFC_PECR2); + + /* P5 (LED) out, all other pins in: */ + temp16 = read16(PFC_PEIOR); + temp16 |= 0x0020; + write16(temp16, PFC_PEIOR); + +} diff --git a/bsps/sh/gensh2/start/ispsh7045.c b/bsps/sh/gensh2/start/ispsh7045.c new file mode 100644 index 0000000000..4e6dabed3f --- /dev/null +++ b/bsps/sh/gensh2/start/ispsh7045.c @@ -0,0 +1,310 @@ +/* + * This file contains the isp frames for the user interrupts. + * From these procedures __ISR_Handler is called with the vector number + * as argument. + * + * __ISR_Handler is kept in a separate file (cpu_asm.c), because a bug in + * some releases of gcc doesn't properly handle #pragma interrupt, if a + * file contains both isrs and normal functions. + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Modified to reflect isp entries for sh7045 processor: + * John M. Mills (jmills@tga.com) + * TGA Technologies, Inc. + * 100 Pinnacle Way, Suite 140 + * Norcross, GA 30071 U.S.A. + * August, 1999 + * + * This modified file may be copied and distributed in accordance + * the above-referenced license. It is provided for critique and + * developmental purposes without any warranty nor representation + * by the authors or by TGA Technologies. + */ + +#include <rtems/system.h> + +/* + * This is a exception vector table + * + * It has the same structure as the actual vector table (vectab) + */ + + +/* SH-2 ISR Table */ +#include <rtems/score/ispsh7045.h> + +proc_ptr _Hardware_isr_Table[256]={ +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* PWRon Reset, Maual Reset,...*/ +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, +_nmi_isp, _usb_isp, /* irq 11, 12*/ +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, +/* trapa 0 -31 */ +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_irq0_isp, _irq1_isp, _irq2_isp, _irq3_isp, /* external H/W: irq 64-71 */ +_irq4_isp, _irq5_isp, _irq6_isp, _irq7_isp, +_dma0_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* DMAC: irq 72-87*/ +_dma1_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dma2_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dma3_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_mtua0_isp, _mtub0_isp, _mtuc0_isp, _mtud0_isp, /* MTUs: irq 88-127 */ +_mtuv0_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_mtua1_isp, _mtub1_isp, _dummy_isp, _dummy_isp, +_mtuv1_isp, _mtuu1_isp, _dummy_isp, _dummy_isp, +_mtua2_isp, _mtub2_isp, _dummy_isp, _dummy_isp, +_mtuv2_isp, _mtuu2_isp, _dummy_isp, _dummy_isp, +_mtua3_isp, _mtub3_isp, _mtuc3_isp, _mtud3_isp, +_mtuv3_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_mtua4_isp, _mtub4_isp, _mtuc4_isp, _mtud4_isp, +_mtuv4_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_eri0_isp, _rxi0_isp, _txi0_isp, _tei0_isp, /* SCI0-1: irq 128-135*/ +_eri1_isp, _rxi1_isp, _txi1_isp, _tei1_isp, +_adi0_isp, _adi1_isp, _dummy_isp, _dummy_isp, /* ADC0-1: irq 136-139*/ +_dtci_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* DTU: irq 140-143 */ +_cmt0_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* CMT0-1: irq 144-151 */ +_cmt1_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_wdt_isp, /* WDT: irq 152*/ +_bsc_isp, _dummy_isp, _dummy_isp, /* BSC: irq 153-155*/ +_oei_isp, /* I/O Port: irq 156*/ +}; + +#define Str(a)#a + +/* + * Some versions of gcc and all version of egcs at least until egcs-1.1b + * are not able to handle #pragma interrupt correctly if more than 1 isr is + * contained in a file and when optimizing. + * We try to work around this problem by using the macro below. + */ +#define isp( name, number, func)\ +__asm__ (".global _"Str(name)"\n\t"\ + "_"Str(name)": \n\t"\ + " mov.l r0,@-r15 \n\t"\ + " mov.l r1,@-r15 \n\t"\ + " mov.l r2,@-r15 \n\t"\ + " mov.l r3,@-r15 \n\t"\ + " mov.l r4,@-r15 \n\t"\ + " mov.l r5,@-r15 \n\t"\ + " mov.l r6,@-r15 \n\t"\ + " mov.l r7,@-r15 \n\t"\ + " mov.l r14,@-r15 \n\t"\ + " sts.l pr,@-r15 \n\t"\ + " sts.l mach,@-r15 \n\t"\ + " sts.l macl,@-r15 \n\t"\ + " mov r15,r14 \n\t"\ + " mov.l "Str(name)"_v, r2 \n\t"\ + " mov.l "Str(name)"_k, r1\n\t"\ + " jsr @r1 \n\t"\ + " mov r2,r4 \n\t"\ + " mov r14,r15 \n\t"\ + " lds.l @r15+,macl \n\t"\ + " lds.l @r15+,mach \n\t"\ + " lds.l @r15+,pr \n\t"\ + " mov.l @r15+,r14 \n\t"\ + " mov.l @r15+,r7 \n\t"\ + " mov.l @r15+,r6 \n\t"\ + " mov.l @r15+,r5 \n\t"\ + " mov.l @r15+,r4 \n\t"\ + " mov.l @r15+,r3 \n\t"\ + " mov.l @r15+,r2 \n\t"\ + " mov.l @r15+,r1 \n\t"\ + " mov.l @r15+,r0 \n\t"\ + " rte \n\t"\ + " nop \n\t"\ + " .align 2 \n\t"\ + #name"_k: \n\t"\ + ".long "Str(func)"\n\t"\ + #name"_v: \n\t"\ + ".long "Str(number)); + +/************************************************ + * Dummy interrupt service procedure for + * interrupts being not allowed --> Trap 34 + ************************************************/ +__asm__ (" .section .text\n\ +.global __dummy_isp\n\ +__dummy_isp:\n\ + mov.l r14,@-r15\n\ + mov r15, r14\n\ + trapa #34\n\ + mov.l @r15+,r14\n\ + rte\n\ + nop"); + +/******************************************************************* + * ISP Vector Table for sh7045 family of processors * + *******************************************************************/ + + +/***************************** + * Non maskable interrupt + *****************************/ +isp( _nmi_isp, NMI_ISP_V, ___ISR_Handler); + +/***************************** + * User break controller + *****************************/ +isp( _usb_isp, USB_ISP_V, ___ISR_Handler); + +/***************************** + * External interrupts 0-7 + *****************************/ +isp( _irq0_isp, IRQ0_ISP_V, ___ISR_Handler); +isp( _irq1_isp, IRQ1_ISP_V, ___ISR_Handler); +isp( _irq2_isp, IRQ2_ISP_V, ___ISR_Handler); +isp( _irq3_isp, IRQ3_ISP_V, ___ISR_Handler); +isp( _irq4_isp, IRQ4_ISP_V, ___ISR_Handler); +isp( _irq5_isp, IRQ5_ISP_V, ___ISR_Handler); +isp( _irq6_isp, IRQ6_ISP_V, ___ISR_Handler); +isp( _irq7_isp, IRQ7_ISP_V, ___ISR_Handler); + +/***************************** + * DMA - controller + *****************************/ +isp( _dma0_isp, DMA0_ISP_V, ___ISR_Handler); +isp( _dma1_isp, DMA1_ISP_V, ___ISR_Handler); +isp( _dma2_isp, DMA2_ISP_V, ___ISR_Handler); +isp( _dma3_isp, DMA3_ISP_V, ___ISR_Handler); + + +/***************************** + * Match timer unit + *****************************/ + +/***************************** + * Timer 0 + *****************************/ +isp( _mtua0_isp, MTUA0_ISP_V, ___ISR_Handler); +isp( _mtub0_isp, MTUB0_ISP_V, ___ISR_Handler); +isp( _mtuc0_isp, MTUC0_ISP_V, ___ISR_Handler); +isp( _mtud0_isp, MTUD0_ISP_V, ___ISR_Handler); +isp( _mtuv0_isp, MTUV0_ISP_V, ___ISR_Handler); + +/***************************** + * Timer 1 + *****************************/ +isp( _mtua1_isp, MTUA1_ISP_V, ___ISR_Handler); +isp( _mtub1_isp, MTUB1_ISP_V, ___ISR_Handler); +isp( _mtuv1_isp, MTUV1_ISP_V, ___ISR_Handler); +isp( _mtuu1_isp, MTUU1_ISP_V, ___ISR_Handler); + +/***************************** + * Timer 2 + *****************************/ +isp( _mtua2_isp, MTUA2_ISP_V, ___ISR_Handler); +isp( _mtub2_isp, MTUB2_ISP_V, ___ISR_Handler); +isp( _mtuv2_isp, MTUV2_ISP_V, ___ISR_Handler); +isp( _mtuu2_isp, MTUU2_ISP_V, ___ISR_Handler); + +/***************************** + * Timer 3 + *****************************/ +isp( _mtua3_isp, MTUA3_ISP_V, ___ISR_Handler); +isp( _mtub3_isp, MTUB3_ISP_V, ___ISR_Handler); +isp( _mtuc3_isp, MTUC3_ISP_V, ___ISR_Handler); +isp( _mtud3_isp, MTUD3_ISP_V, ___ISR_Handler); +isp( _mtuv3_isp, MTUV3_ISP_V, ___ISR_Handler); + +/***************************** + * Timer 4 + *****************************/ +isp( _mtua4_isp, MTUA4_ISP_V, ___ISR_Handler); +isp( _mtub4_isp, MTUB4_ISP_V, ___ISR_Handler); +isp( _mtuc4_isp, MTUC4_ISP_V, ___ISR_Handler); +isp( _mtud4_isp, MTUD4_ISP_V, ___ISR_Handler); +isp( _mtuv4_isp, MTUV4_ISP_V, ___ISR_Handler); + + +/***************************** + * Serial interfaces + *****************************/ + +/***************************** + * Serial interface 0 + *****************************/ +isp( _eri0_isp, ERI0_ISP_V, ___ISR_Handler); +isp( _rxi0_isp, RXI0_ISP_V, ___ISR_Handler); +isp( _txi0_isp, TXI0_ISP_V, ___ISR_Handler); +isp( _tei0_isp, TEI0_ISP_V, ___ISR_Handler); + +/***************************** + * Serial interface 1 + *****************************/ +isp( _eri1_isp, ERI1_ISP_V, ___ISR_Handler); +isp( _rxi1_isp, RXI1_ISP_V, ___ISR_Handler); +isp( _txi1_isp, TXI1_ISP_V, ___ISR_Handler); +isp( _tei1_isp, TEI1_ISP_V, ___ISR_Handler); + + +/****************************** + * A/D converters + * ADC0-1 + ******************************/ +isp( _adi0_isp, ADI0_ISP_V, ___ISR_Handler); +isp( _adi1_isp, ADI1_ISP_V, ___ISR_Handler); + + +/****************************** + * Data transfer controller + ******************************/ +isp( _dtci_isp, DTC_ISP_V, ___ISR_Handler); + + +/****************************** + * Counter match timer + ******************************/ +isp( _cmt0_isp, CMT0_ISP_V, ___ISR_Handler); +isp( _cmt1_isp, CMT1_ISP_V, ___ISR_Handler); + + +/****************************** + * Watchdog timer + ******************************/ +isp( _wdt_isp, WDT_ISP_V, ___ISR_Handler); + + +/****************************** + * DRAM refresh control unit + * of bus state controller + ******************************/ +isp( _bsc_isp, CMI_ISP_V, ___ISR_Handler); + +/****************************** + * I/O port + ******************************/ +isp( _oei_isp, OEI_ISP_V, ___ISR_Handler); + + +/***************************** + * Parity control unit of + * the bus state controller + * NOT PROVIDED IN SH-2 + *****************************/ +/* isp( _prt_isp, PRT_ISP_V, ___ISR_Handler); */ diff --git a/bsps/sh/gensh2/start/linkcmds b/bsps/sh/gensh2/start/linkcmds new file mode 100644 index 0000000000..2c4d44a941 --- /dev/null +++ b/bsps/sh/gensh2/start/linkcmds @@ -0,0 +1,241 @@ +/* + * This is an adapted linker script from egcs-1.0.1 + * + * Memory layout for an SH7045F with main memory in area 2 + * This memory layout it very similar to that used for Hitachi's + * EVB with CMON in FLASH + * + * NOTE: The ram start address may vary, all other start addresses are fixed + * Not suiteable for gdb's simulator + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Modified to reflect SH7045F processor and EVB: + * John M. Mills (jmills@tga.com) + * TGA Technologies, Inc. + * 100 Pinnacle Way, Suite 140 + * Norcross, GA 30071 U.S.A. + * + * This modified file may be copied and distributed in accordance + * the above-referenced license. It is provided for critique and + * developmental purposes without any warranty nor representation + * by the authors or by TGA Technologies. + */ + +OUTPUT_ARCH(sh) +ENTRY(_start) +STARTUP(start.o) + +/* These assignments load code into SH7045F EVB SRAM for monitor debugging */ + +_RamBase = DEFINED(_RamBase) ? _RamBase : 0x00440000; +_RamSize = DEFINED(_RamSize) ? _RamSize : 512K; +_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x0; + +MEMORY +{ + rom : o = 0x00400000, l = 0x00040000 + ram : o = 0x00440000, l = 0x00080000 + onchip_peri : o = 0xFFFF8000, l = 0x00000800 + onchip_ram : o = 0xFFFFF000, l = 0x00001000 +} + +/* Sections are defined for RAM loading and monitor debugging */ +SECTIONS +{ + /* boot vector table */ + .monvects 0x00400000 (NOLOAD): { + _monvects = . ; + } > rom + + /* monitor play area */ + .monram 0x00440000 (NOLOAD) : + { + _ramstart = .; + } > ram + + /* monitor vector table */ + .vects 0x00442000 (NOLOAD) : { + _vectab = . ; + *(.vects); + } + + /* Read-only sections, merged into text segment: */ + + . = 0x00444000 ; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .gnu.version : { *(.gnu.version) } + .gnu.version_d : { *(.gnu.version_d) } + .gnu.version_r : { *(.gnu.version_r) } + .rela.dyn : + { + *(.rela.init) + *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) + *(.rela.fini) + *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) + *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) + *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) + *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) + *(.rela.ctors) + *(.rela.dtors) + *(.rela.got) + *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) + *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) + *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) + *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) + *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) + } >ram + .rel.text : + { *(.rel.text) *(.rel.gnu.linkonce.t*) } + .rel.data : + { *(.rel.data) *(.rel.gnu.linkonce.d*) } + .rel.rodata : + { *(.rel.rodata*) *(.rel.gnu.linkonce.r*) } + .rel.got : { *(.rel.got) } + .rel.ctors : { *(.rel.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rel.init : { *(.rel.init) } + .rel.fini : { *(.rel.fini) } + .rel.bss : { *(.rel.bss) } + .rel.plt : { *(.rel.plt) } + .plt : { *(.plt) } + .text . : + { + _start = .; + *(.text*) + *(.stub) + + /* + * Special FreeBSD sysctl sections. + */ + . = ALIGN (16); + ___start_set_sysctl_set = .; + *(set_sysc*); /* set_sysctl_* but name is truncated by SH-coff */ + ___stop_set_sysctl_set = ABSOLUTE(.); + *(set_doma*); /* set_domain_* but name is truncated by SH-coff */ + *(set_pseu*); /* set_pseudo_* but name is truncated by SH-coff */ + + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + *(.gnu.linkonce.t*) + } > ram + _etext = .; + PROVIDE (etext = .); + .init . : { KEEP(*(.init)) } > ram =0 + .fini . : { KEEP(*(.fini)) } > ram =0 + .ctors . : { KEEP(*(.ctors)) } > ram =0 + .dtors . : { KEEP(*(.dtors)) } > ram =0 + .rodata . : { *(.rodata*) KEEP (*(SORT(.rtemsroset.*))) *(.gnu.linkonce.r*) } > ram + .rodata1 . : { *(.rodata1) } > ram + .tdata : { + __TLS_Data_begin = .; + *(.tdata .tdata.* .gnu.linkonce.td.*) + __TLS_Data_end = .; + } > ram + .tbss : { + __TLS_BSS_begin = .; + *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) + __TLS_BSS_end = .; + } > ram + __TLS_Data_size = __TLS_Data_end - __TLS_Data_begin; + __TLS_Data_begin = __TLS_Data_size != 0 ? __TLS_Data_begin : __TLS_BSS_begin; + __TLS_Data_end = __TLS_Data_size != 0 ? __TLS_Data_end : __TLS_BSS_begin; + __TLS_BSS_size = __TLS_BSS_end - __TLS_BSS_begin; + __TLS_Size = __TLS_BSS_end - __TLS_Data_begin; + __TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss)); + /* Adjust the address for the data segment. We want to adjust up to + the same address within the page on the next page up. */ + . = ALIGN(128) + (. & (128 - 1)); + .data . : + { + *(.data*) + KEEP (*(SORT(.rtemsrwset.*))) + *(.gcc_exc*) + ___EH_FRAME_BEGIN__ = .; + *(.eh_fram*) + ___EH_FRAME_END__ = .; + LONG(0); + *(.gcc_except_table*) + *(.gnu.linkonce.d*) + CONSTRUCTORS + } > ram + .data1 . : { *(.data1) } + .got . : { *(.got.plt) *(.got) } + .dynamic . : { *(.dynamic) } + /* We want the small data sections together, so single-instruction offsets + can access them all, and initialized data all before uninitialized, so + we can shorten the on-disk segment size. */ + .sdata . : { *(.sdata) } + _edata = .; + PROVIDE (edata = .); + __bss_start = .; + .sbss . : { *(.sbss*) *(.scommon) } + .bss . : + { + *(.dynbss) + *(.bss .bss* .gnu.linkonce.b*) + *(COMMON) + } > ram + _end = . ; + PROVIDE (end = .); + + _WorkAreaBase = . ; + + _CPU_Interrupt_stack_low = 0xFFFFF000; + _CPU_Interrupt_stack_high = 0xFFFFFFFF; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + .stack 0xFFFFFEC0 : { _stack = .; *(.stack) } > onchip_ram + /* These must appear regardless of . */ +} diff --git a/bsps/sh/gensh2/start/linkcmds.ram b/bsps/sh/gensh2/start/linkcmds.ram new file mode 100644 index 0000000000..c5349398ff --- /dev/null +++ b/bsps/sh/gensh2/start/linkcmds.ram @@ -0,0 +1,244 @@ +/* + * This is an adapted linker script from egcs-1.0.1 + * + * Memory layout for an SH7045F with main memory in area 2 + * This memory layout it very similar to that used for Hitachi's + * EVB with CMON in FLASH + * + * NOTE: The ram start address may vary, all other start addresses are fixed + * Not suiteable for gdb's simulator + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Modified to reflect SH7045F processor and EVB: + * John M. Mills (jmills@tga.com) + * TGA Technologies, Inc. + * 100 Pinnacle Way, Suite 140 + * Norcross, GA 30071 U.S.A. + * + * This modified file may be copied and distributed in accordance + * the above-referenced license. It is provided for critique and + * developmental purposes without any warranty nor representation + * by the authors or by TGA Technologies. + */ + +OUTPUT_ARCH(sh) +ENTRY(_start) +STARTUP(start.o) + +/* These assignments load code into SH7045F EVB SRAM for monitor debugging */ +_RamBase = DEFINED(_RamBase) ? _RamBase : 0x00440000; +_RamSize = DEFINED(_RamSize) ? _RamSize : 512K; +_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x0; + +MEMORY +{ + rom : o = 0x00400000, l = 0x00040000 + ram : o = 0x00440000, l = 0x00080000 + onchip_peri : o = 0xFFFF8000, l = 0x00000800 + onchip_ram : o = 0xFFFFF000, l = 0x00001000 +} + +/* Sections are defined for RAM loading and monitor debugging */ +SECTIONS +{ + /* boot vector table */ + .monvects 0x00400000 (NOLOAD): { + _monvects = . ; + } > rom + + /* monitor play area */ + .monram 0x00440000 (NOLOAD) : + { + _ramstart = .; + } > ram + + /* monitor vector table */ + .vects 0x00442000 (NOLOAD) : { + _vectab = . ; + *(.vects); + } + + /* Read-only sections, merged into text segment: */ + + . = 0x00444000 ; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .gnu.version : { *(.gnu.version) } + .gnu.version_d : { *(.gnu.version_d) } + .gnu.version_r : { *(.gnu.version_r) } + .rela.dyn : + { + *(.rela.init) + *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) + *(.rela.fini) + *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) + *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) + *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) + *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) + *(.rela.ctors) + *(.rela.dtors) + *(.rela.got) + *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) + *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) + *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) + *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) + *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) + } >ram + .rel.text : + { *(.rel.text) *(.rel.gnu.linkonce.t*) } + .rel.data : + { *(.rel.data) *(.rel.gnu.linkonce.d*) } + .rel.rodata : + { *(.rel.rodata) *(.rel.gnu.linkonce.r*) } + .rel.got : { *(.rel.got) } + .rel.ctors : { *(.rel.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rel.init : { *(.rel.init) } + .rel.fini : { *(.rel.fini) } + .rel.bss : { *(.rel.bss) } + .rel.plt : { *(.rel.plt) } + .init : { *(.init) } =0 + .plt : { *(.plt) } + .text . : + { + *(.text*) + *(.stub) + + /* + * Special FreeBSD sysctl sections. + */ + . = ALIGN (16); + ___start_set_sysctl_set = .; + *(set_sysc*); /* set_sysctl_* but name is truncated by SH-coff */ + ___stop_set_sysctl_set = ABSOLUTE(.); + *(set_doma*); /* set_domain_* but name is truncated by SH-coff */ + *(set_pseudo_*); + + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + *(.gnu.linkonce.t*) + } > ram + _etext = .; + PROVIDE (etext = .); + .fini . : { *(.fini) } > ram =0 + .rodata . : { *(.rodata) KEEP (*(SORT(.rtemsroset.*))) *(.gnu.linkonce.r*) } > ram + .rodata1 . : { *(.rodata1) } > ram + .tdata : { + __TLS_Data_begin = .; + *(.tdata .tdata.* .gnu.linkonce.td.*) + __TLS_Data_end = .; + } > ram + .tbss : { + __TLS_BSS_begin = .; + *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) + __TLS_BSS_end = .; + } > ram + __TLS_Data_size = __TLS_Data_end - __TLS_Data_begin; + __TLS_Data_begin = __TLS_Data_size != 0 ? __TLS_Data_begin : __TLS_BSS_begin; + __TLS_Data_end = __TLS_Data_size != 0 ? __TLS_Data_end : __TLS_BSS_begin; + __TLS_BSS_size = __TLS_BSS_end - __TLS_BSS_begin; + __TLS_Size = __TLS_BSS_end - __TLS_Data_begin; + __TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss)); + /* Adjust the address for the data segment. We want to adjust up to + the same address within the page on the next page up. */ + . = ALIGN(128) + (. & (128 - 1)); + .data . : + { + *(.data) + KEEP (*(SORT(.rtemsrwset.*))) + *(.gnu.linkonce.d*) + CONSTRUCTORS + } > ram + .data1 . : { *(.data1) } + .ctors . : + { + ___ctors = .; + *(.ctors) + ___ctors_end = .; + } + .dtors . : + { + ___dtors = .; + *(.dtors) + ___dtors_end = .; + } + .got . : { *(.got.plt) *(.got) } + .dynamic . : { *(.dynamic) } + /* We want the small data sections together, so single-instruction offsets + can access them all, and initialized data all before uninitialized, so + we can shorten the on-disk segment size. */ + .sdata . : { *(.sdata) } + _edata = .; + PROVIDE (edata = .); + __bss_start = .; + .sbss . : { *(.sbss*) *(.scommon) } + .bss . : + { + *(.dynbss) + *(.bss .bss* .gnu.linkonce.b*) + *(COMMON) + } > ram + _end = . ; + PROVIDE (end = .); + + _WorkAreaBase = . ; + . = 0x00480000 ; + + _CPU_Interrupt_stack_low = 0xFFFFF000; + _CPU_Interrupt_stack_high = 0xFFFFFFFF; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + .stack 0xFFFFFEC0 : { _stack = .; *(.stack) } > onchip_ram + /* These must appear regardless of . */ +} diff --git a/bsps/sh/gensh2/start/linkcmds.rom b/bsps/sh/gensh2/start/linkcmds.rom new file mode 100644 index 0000000000..4934c10269 --- /dev/null +++ b/bsps/sh/gensh2/start/linkcmds.rom @@ -0,0 +1,248 @@ +/* + * This is an adapted linker script from egcs-1.0.1 + * + * Memory layout for an SH7045F with main memory in area 2 + * This memory layout it very similar to that used for Hitachi's + * EVB with CMON in FLASH + * + * NOTE: The ram start address may vary, all other start addresses are fixed + * Not suiteable for gdb's simulator + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + * + * Modified to reflect SH7045F processor and EVB: + * John M. Mills (jmills@tga.com) + * TGA Technologies, Inc. + * 100 Pinnacle Way, Suite 140 + * Norcross, GA 30071 U.S.A. + * + * This modified file may be copied and distributed in accordance + * the above-referenced license. It is provided for critique and + * developmental purposes without any warranty nor representation + * by the authors or by TGA Technologies. + */ + +OUTPUT_ARCH(sh) +ENTRY(_start) +STARTUP(start.o) + +/* These asignments represent actual SH7045F EVB architecture */ +_RamBase = DEFINED(_RamBase) ? _RamBase : 0x00400000; +_RamSize = DEFINED(_RamSize) ? _RamSize : 0x0008000; +_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x0; + +MEMORY +{ + rom : o = 0x00000000, l = 0x00040000 + ram : o = 0x00400000, l = 0x00080000 + onchip_peri : o = 0xFFFF8000, l = 0x00000800 + onchip_ram : o = 0xFFFFF000, l = 0x00001000 +} + + +/* Sections are defined for RAM loading and monitor debugging */ +SECTIONS +{ + /* boot vector table */ + .monvects 0x00000000 (NOLOAD): { + _monvects = . ; + } > rom + + /* monitor play area */ + .monram 0x00400000 (NOLOAD) : + { + _ramstart = .; + } > ram + + /* monitor vector table */ + .vects 0x00402000 (NOLOAD) : { + _vectab = . ; + *(.vects); + } + + /* Read-only sections, merged into text segment: */ + + . = 0x00404000 ; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .gnu.version : { *(.gnu.version) } + .gnu.version_d : { *(.gnu.version_d) } + .gnu.version_r : { *(.gnu.version_r) } + .rela.dyn : + { + *(.rela.init) + *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) + *(.rela.fini) + *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) + *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) + *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) + *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) + *(.rela.ctors) + *(.rela.dtors) + *(.rela.got) + *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) + *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) + *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) + *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*) + *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) + } >ram + .rel.text : + { *(.rel.text) *(.rel.gnu.linkonce.t*) } + .rel.data : + { *(.rel.data) *(.rel.gnu.linkonce.d*) } + .rel.rodata : + { *(.rel.rodata) *(.rel.gnu.linkonce.r*) } + .rel.got : { *(.rel.got) } + .rel.ctors : { *(.rel.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rel.init : { *(.rel.init) } + .rel.fini : { *(.rel.fini) } + .rel.bss : { *(.rel.bss) } + .rel.plt : { *(.rel.plt) } + .init : { *(.init) } =0 + .plt : { *(.plt) } + .text . : + { + *(.text*) + *(.stub) + + /* + * Special FreeBSD sysctl sections. + */ + . = ALIGN (16); + ___start_set_sysctl_set = .; + *(set_sysc*); /* set_sysctl_* but name is truncated by SH-coff */ + ___stop_set_sysctl_set = ABSOLUTE(.); + *(set_doma*); /* set_domain_* but name is truncated by SH-coff */ + *(set_pseudo_*); + + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + *(.gnu.linkonce.t*) + } > ram + _etext = .; + PROVIDE (etext = .); + .fini . : { *(.fini) } > ram =0 + .rodata . : { *(.rodata) KEEP (*(SORT(.rtemsroset.*))) *(.gnu.linkonce.r*) } > ram + .rodata1 . : { *(.rodata1) } > ram + .tdata : { + __TLS_Data_begin = .; + *(.tdata .tdata.* .gnu.linkonce.td.*) + __TLS_Data_end = .; + } > ram + .tbss : { + __TLS_BSS_begin = .; + *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) + __TLS_BSS_end = .; + } > ram + __TLS_Data_size = __TLS_Data_end - __TLS_Data_begin; + __TLS_Data_begin = __TLS_Data_size != 0 ? __TLS_Data_begin : __TLS_BSS_begin; + __TLS_Data_end = __TLS_Data_size != 0 ? __TLS_Data_end : __TLS_BSS_begin; + __TLS_BSS_size = __TLS_BSS_end - __TLS_BSS_begin; + __TLS_Size = __TLS_BSS_end - __TLS_Data_begin; + __TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss)); + /* Adjust the address for the data segment. We want to adjust up to + the same address within the page on the next page up. */ + . = ALIGN(128) + (. & (128 - 1)); + .data . : + { + *(.data) + KEEP (*(SORT(.rtemsrwset.*))) + *(.gnu.linkonce.d*) + CONSTRUCTORS + } > ram + .data1 . : { *(.data1) } + .ctors . : + { + ___ctors = .; + *(.ctors) + ___ctors_end = .; + } + .dtors . : + { + ___dtors = .; + *(.dtors) + ___dtors_end = .; + } + .got . : { *(.got.plt) *(.got) } + .dynamic . : { *(.dynamic) } + /* We want the small data sections together, so single-instruction offsets + can access them all, and initialized data all before uninitialized, so + we can shorten the on-disk segment size. */ + .sdata . : { *(.sdata) } + _edata = .; + PROVIDE (edata = .); + __bss_start = .; + .sbss . : { *(.sbss*) *(.scommon) } + .bss . : + { + *(.dynbss) + *(.bss .bss* .gnu.linkonce.b*) + *(COMMON) + } > ram + _end = . ; + PROVIDE (end = .); + + _HeapStart = . ; + . = . + 1024 * 20 ; + PROVIDE( _HeapEnd = . ); + + _WorkAreaBase = . ; + + _CPU_Interrupt_stack_low = 0xFFFFF000; + _CPU_Interrupt_stack_high = 0xFFFFFFFF; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + .stack 0xFFFFFEC0 : { _stack = .; *(.stack) } > onchip_ram + /* These must appear regardless of . */ +} |