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-rw-r--r--bsps/sh/gensh1/start/bsp_specs9
-rw-r--r--bsps/sh/gensh1/start/cpu_asm.c181
-rw-r--r--bsps/sh/gensh1/start/ispsh7032.c248
-rw-r--r--bsps/sh/gensh1/start/linkcmds230
4 files changed, 668 insertions, 0 deletions
diff --git a/bsps/sh/gensh1/start/bsp_specs b/bsps/sh/gensh1/start/bsp_specs
new file mode 100644
index 0000000000..87638cc027
--- /dev/null
+++ b/bsps/sh/gensh1/start/bsp_specs
@@ -0,0 +1,9 @@
+%rename endfile old_endfile
+%rename startfile old_startfile
+
+*startfile:
+%{!qrtems: %(old_startfile)} \
+%{!nostdlib: %{qrtems: crti.o%s crtbegin.o%s}}
+
+*endfile:
+%{!qrtems: %(old_endfile)} %{qrtems: crtend.o%s crtn.o%s}
diff --git a/bsps/sh/gensh1/start/cpu_asm.c b/bsps/sh/gensh1/start/cpu_asm.c
new file mode 100644
index 0000000000..99d9cc9a6a
--- /dev/null
+++ b/bsps/sh/gensh1/start/cpu_asm.c
@@ -0,0 +1,181 @@
+/*
+ * This file contains the basic algorithms for all assembly code used
+ * in an specific CPU port of RTEMS. These algorithms must be implemented
+ * in assembly language
+ *
+ * NOTE: This port uses a C file with inline assembler instructions
+ *
+ * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ * Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *
+ * COPYRIGHT (c) 1998.
+ * On-Line Applications Research Corporation (OAR).
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ *
+ */
+
+/*
+ * This is supposed to be an assembly file. This means that system.h
+ * and cpu.h should not be included in a "real" cpu_asm file. An
+ * implementation in assembly should include "cpu_asm.h"
+ */
+
+#include <rtems/system.h>
+#include <rtems/score/percpu.h>
+#include <rtems/score/isr.h>
+#include <rtems/score/threaddispatch.h>
+#include <rtems/score/sh.h>
+#include <rtems/score/ispsh7032.h>
+
+#include <rtems/score/ispsh7032.h>
+#include <rtems/score/iosh7032.h>
+#include <rtems/score/sh_io.h>
+
+/* from cpu_isps.c */
+extern proc_ptr _Hardware_isr_Table[];
+
+#if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
+ unsigned long *_old_stack_ptr;
+#endif
+
+register unsigned long *stack_ptr __asm__ ("r15");
+
+/*
+ * sh_set_irq_priority
+ *
+ * this function sets the interrupt level of the specified interrupt
+ *
+ * parameters:
+ * - irq : interrupt number
+ * - prio: priority to set for this interrupt number
+ *
+ * returns: 0 if ok
+ * -1 on error
+ */
+
+unsigned int sh_set_irq_priority(
+ unsigned int irq,
+ unsigned int prio )
+{
+ uint32_t shiftcount;
+ uint32_t prioreg;
+ uint16_t temp16;
+ ISR_Level level;
+
+ /*
+ * first check for valid interrupt
+ */
+ if (( irq > 113) || (_Hardware_isr_Table[irq] == _dummy_isp))
+ return -1;
+ /*
+ * check for valid irq priority
+ */
+ if ( prio > 15 )
+ return -1;
+
+ /*
+ * look up appropriate interrupt priority register
+ */
+ if ( irq > 71)
+ {
+ irq = irq - 72;
+ shiftcount = 12 - ((irq & ~0x03) % 16);
+
+ switch( irq / 16)
+ {
+ case 0: { prioreg = INTC_IPRC; break;}
+ case 1: { prioreg = INTC_IPRD; break;}
+ case 2: { prioreg = INTC_IPRE; break;}
+ default: return -1;
+ }
+ }
+ else
+ {
+ shiftcount = 12 - 4 * ( irq % 4);
+ if ( irq > 67)
+ prioreg = INTC_IPRB;
+ else
+ prioreg = INTC_IPRA;
+ }
+
+ /*
+ * Set the interrupt priority register
+ */
+ _ISR_Local_disable( level );
+
+ temp16 = read16( prioreg);
+ temp16 &= ~( 15 << shiftcount);
+ temp16 |= prio << shiftcount;
+ write16( temp16, prioreg);
+
+ _ISR_Local_enable( level );
+
+ return 0;
+}
+
+/*
+ * This routine provides the RTEMS interrupt management.
+ */
+
+void __ISR_Handler( uint32_t vector)
+{
+ ISR_Level level;
+
+ _ISR_Local_disable( level );
+
+ _Thread_Dispatch_disable();
+
+#if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
+ if ( _ISR_Nest_level == 0 )
+ {
+ /* Install irq stack */
+ _old_stack_ptr = stack_ptr;
+ stack_ptr = _CPU_Interrupt_stack_high;
+ }
+
+#endif
+
+ _ISR_Nest_level++;
+
+ _ISR_Local_enable( level );
+
+ /* call isp */
+ if ( _ISR_Vector_table[ vector])
+ (*_ISR_Vector_table[ vector ])( vector );
+
+ _ISR_Local_disable( level );
+
+ _Thread_Dispatch_unnest( _Per_CPU_Get() );
+
+ _ISR_Nest_level--;
+
+#if(CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
+
+ if ( _ISR_Nest_level == 0 )
+ /* restore old stack pointer */
+ stack_ptr = _old_stack_ptr;
+#endif
+
+ _ISR_Local_enable( level );
+
+ if ( _ISR_Nest_level )
+ return;
+
+ if ( !_Thread_Dispatch_is_enabled() ) {
+ return;
+ }
+
+ if ( _Thread_Dispatch_necessary ) {
+ _Thread_Dispatch();
+ }
+}
diff --git a/bsps/sh/gensh1/start/ispsh7032.c b/bsps/sh/gensh1/start/ispsh7032.c
new file mode 100644
index 0000000000..05ba2f1e90
--- /dev/null
+++ b/bsps/sh/gensh1/start/ispsh7032.c
@@ -0,0 +1,248 @@
+/*
+ * This file contains the isp frames for the user interrupts.
+ * From these procedures __ISR_Handler is called with the vector number
+ * as argument.
+ *
+ * __ISR_Handler is kept in a separate file (cpu_asm.c), because a bug in
+ * some releases of gcc doesn't properly handle #pragma interrupt, if a
+ * file contains both isrs and normal functions.
+ *
+ * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ * Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE
+ *
+ *
+ * COPYRIGHT (c) 1998.
+ * On-Line Applications Research Corporation (OAR).
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems/system.h>
+#include <rtems/score/ispsh7032.h>
+
+/*
+ * This is an exception vector table
+ *
+ * It has the same structure like the actual vector table (vectab)
+ */
+proc_ptr _Hardware_isr_Table[256]={
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp,
+_nmi_isp, _usb_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp,
+/* trapa 0 -31 */
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+/* irq 64 ... */
+_irq0_isp, _irq1_isp, _irq2_isp, _irq3_isp,
+_irq4_isp, _irq5_isp, _irq6_isp, _irq7_isp,
+_dma0_isp, _dummy_isp, _dma1_isp, _dummy_isp,
+_dma2_isp, _dummy_isp, _dma3_isp, _dummy_isp,
+_imia0_isp, _imib0_isp, _ovi0_isp, _dummy_isp,
+_imia1_isp, _imib1_isp, _ovi1_isp, _dummy_isp,
+_imia2_isp, _imib2_isp, _ovi2_isp, _dummy_isp,
+_imia3_isp, _imib3_isp, _ovi3_isp, _dummy_isp,
+_imia4_isp, _imib4_isp, _ovi4_isp, _dummy_isp,
+_eri0_isp, _rxi0_isp, _txi0_isp, _tei0_isp,
+_eri1_isp, _rxi1_isp, _txi1_isp, _tei1_isp,
+_prt_isp, _adu_isp, _dummy_isp, _dummy_isp,
+_wdt_isp,
+/* 113 */ _dref_isp
+};
+
+#define Str(a)#a
+
+/*
+ * Some versions of gcc and all version of egcs at least until egcs-1.1b
+ * are not able to handle #pragma interrupt correctly if more than 1 isr is
+ * contained in a file and when optimizing.
+ * We try to work around this problem by using the macro below.
+ */
+#define isp( name, number, func)\
+__asm__ (".global _"Str(name)"\n\t" \
+ "_"Str(name)": \n\t" \
+ " mov.l r0,@-r15 \n\t" \
+ " mov.l r1,@-r15 \n\t" \
+ " mov.l r2,@-r15 \n\t" \
+ " mov.l r3,@-r15 \n\t" \
+ " mov.l r4,@-r15 \n\t" \
+ " mov.l r5,@-r15 \n\t" \
+ " mov.l r6,@-r15 \n\t" \
+ " mov.l r7,@-r15 \n\t" \
+ " mov.l r14,@-r15 \n\t" \
+ " sts.l pr,@-r15 \n\t" \
+ " sts.l mach,@-r15 \n\t" \
+ " sts.l macl,@-r15 \n\t" \
+ " mov r15,r14 \n\t" \
+ " mov.l "Str(name)"_k, r1\n\t" \
+ " jsr @r1 \n\t" \
+ " mov #"Str(number)", r4\n\t" \
+ " mov r14,r15 \n\t" \
+ " lds.l @r15+,macl \n\t" \
+ " lds.l @r15+,mach \n\t" \
+ " lds.l @r15+,pr \n\t" \
+ " mov.l @r15+,r14 \n\t" \
+ " mov.l @r15+,r7 \n\t" \
+ " mov.l @r15+,r6 \n\t" \
+ " mov.l @r15+,r5 \n\t" \
+ " mov.l @r15+,r4 \n\t" \
+ " mov.l @r15+,r3 \n\t" \
+ " mov.l @r15+,r2 \n\t" \
+ " mov.l @r15+,r1 \n\t" \
+ " mov.l @r15+,r0 \n\t" \
+ " rte \n\t" \
+ " nop \n\t" \
+ " .align 2 \n\t" \
+ #name"_k: \n\t" \
+ ".long "Str(func));
+
+/************************************************
+ * Dummy interrupt service procedure for
+ * interrupts being not allowed --> Trap 34
+ ************************************************/
+__asm__ (" .section .text\n\
+.global __dummy_isp\n\
+__dummy_isp:\n\
+ mov.l r14,@-r15\n\
+ mov r15, r14\n\
+ trapa #34\n\
+ mov.l @r15+,r14\n\
+ rte\n\
+ nop");
+
+/*****************************
+ * Non maskable interrupt
+ *****************************/
+isp( _nmi_isp, NMI_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * User break controller
+ *****************************/
+isp( _usb_isp, USB_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * External interrupts 0-7
+ *****************************/
+isp( _irq0_isp, IRQ0_ISP_V, ___ISR_Handler);
+isp( _irq1_isp, IRQ1_ISP_V, ___ISR_Handler);
+isp( _irq2_isp, IRQ2_ISP_V, ___ISR_Handler);
+isp( _irq3_isp, IRQ3_ISP_V, ___ISR_Handler);
+isp( _irq4_isp, IRQ4_ISP_V, ___ISR_Handler);
+isp( _irq5_isp, IRQ5_ISP_V, ___ISR_Handler);
+isp( _irq6_isp, IRQ6_ISP_V, ___ISR_Handler);
+isp( _irq7_isp, IRQ7_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * DMA - controller
+ *****************************/
+isp( _dma0_isp, DMA0_ISP_V, ___ISR_Handler);
+isp( _dma1_isp, DMA1_ISP_V, ___ISR_Handler);
+isp( _dma2_isp, DMA2_ISP_V, ___ISR_Handler);
+isp( _dma3_isp, DMA3_ISP_V, ___ISR_Handler);
+
+
+/*****************************
+ * Interrupt timer unit
+ *****************************/
+
+/*****************************
+ * Timer 0
+ *****************************/
+isp( _imia0_isp, IMIA0_ISP_V, ___ISR_Handler);
+isp( _imib0_isp, IMIB0_ISP_V, ___ISR_Handler);
+isp( _ovi0_isp, OVI0_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * Timer 1
+ *****************************/
+isp( _imia1_isp, IMIA1_ISP_V, ___ISR_Handler);
+isp( _imib1_isp, IMIB1_ISP_V, ___ISR_Handler);
+isp( _ovi1_isp, OVI1_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * Timer 2
+ *****************************/
+isp( _imia2_isp, IMIA2_ISP_V, ___ISR_Handler);
+isp( _imib2_isp, IMIB2_ISP_V, ___ISR_Handler);
+isp( _ovi2_isp, OVI2_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * Timer 3
+ *****************************/
+isp( _imia3_isp, IMIA3_ISP_V, ___ISR_Handler);
+isp( _imib3_isp, IMIB3_ISP_V, ___ISR_Handler);
+isp( _ovi3_isp, OVI3_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * Timer 4
+ *****************************/
+isp( _imia4_isp, IMIA4_ISP_V, ___ISR_Handler);
+isp( _imib4_isp, IMIB4_ISP_V, ___ISR_Handler);
+isp( _ovi4_isp, OVI4_ISP_V, ___ISR_Handler);
+
+
+/*****************************
+ * Serial interfaces
+ *****************************/
+
+/*****************************
+ * Serial interface 0
+ *****************************/
+isp( _eri0_isp, ERI0_ISP_V, ___ISR_Handler);
+isp( _rxi0_isp, RXI0_ISP_V, ___ISR_Handler);
+isp( _txi0_isp, TXI0_ISP_V, ___ISR_Handler);
+isp( _tei0_isp, TEI0_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * Serial interface 1
+ *****************************/
+isp( _eri1_isp, ERI1_ISP_V, ___ISR_Handler);
+isp( _rxi1_isp, RXI1_ISP_V, ___ISR_Handler);
+isp( _txi1_isp, TXI1_ISP_V, ___ISR_Handler);
+isp( _tei1_isp, TEI1_ISP_V, ___ISR_Handler);
+
+
+/*****************************
+ * Parity control unit of
+ * the bus state controller
+ *****************************/
+isp( _prt_isp, PRT_ISP_V, ___ISR_Handler);
+
+
+/******************************
+ * Analog digital converter
+ * ADC
+ ******************************/
+isp( _adu_isp, ADU_ISP_V, ___ISR_Handler);
+
+
+/******************************
+ * Watchdog timer
+ ******************************/
+isp( _wdt_isp, WDT_ISP_V, ___ISR_Handler);
+
+
+/******************************
+ * DRAM refresh control unit
+ * of bus state controller
+ ******************************/
+isp( _dref_isp, DREF_ISP_V, ___ISR_Handler);
diff --git a/bsps/sh/gensh1/start/linkcmds b/bsps/sh/gensh1/start/linkcmds
new file mode 100644
index 0000000000..d268d4cfc7
--- /dev/null
+++ b/bsps/sh/gensh1/start/linkcmds
@@ -0,0 +1,230 @@
+/*
+ * This is an adapted linker script from egcs-1.0.1
+ *
+ * Memory layout for an SH 7032 with main memory in area 2
+ * This memory layout it very similar to that used for Hitachi's
+ * EVB with CMON in rom
+ *
+ * NOTE: The ram start address may vary, all other start addresses are fixed
+ * Not suiteable for gdb's simulator
+ *
+ * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ * Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *
+ * COPYRIGHT (c) 1998.
+ * On-Line Applications Research Corporation (OAR).
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+STARTUP(start.o)
+
+_RamBase = DEFINED(_RamBase) ? _RamBase : 0x0a040000;
+_RamSize = DEFINED(_RamSize) ? _RamSize : 512K;
+_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x0;
+
+MEMORY
+{
+ rom : o = 0x00000000, l = 128k
+ onchip_peri : o = 0x05000000, l = 512
+ ram : o = 0x0A040000, l = 512k /* enough to link all tests */
+
+ onchip_ram : o = 0x0f000000, l = 8k
+}
+
+SECTIONS
+{
+ /* boot vector table */
+ .monvects 0x00000000 (NOLOAD): {
+ _monvects = . ;
+ } > rom
+
+ /* monitor play area */
+ .monram 0x0A040000 (NOLOAD) :
+ {
+ _ramstart = .;
+ } > ram
+
+ /* monitor vector table */
+ .vects 0x0A042000 (NOLOAD) : {
+ _vectab = . ;
+ *(.vects);
+ }
+
+ /* Read-only sections, merged into text segment: */
+
+ . = 0x0a044000 ;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .gnu.version : { *(.gnu.version) }
+ .gnu.version_d : { *(.gnu.version_d) }
+ .gnu.version_r : { *(.gnu.version_r) }
+ .rela.dyn :
+ {
+ *(.rela.init)
+ *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
+ *(.rela.fini)
+ *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
+ *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
+ *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
+ *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
+ *(.rela.ctors)
+ *(.rela.dtors)
+ *(.rela.got)
+ *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
+ *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
+ *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
+ *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
+ *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
+ } >ram
+ .rel.text :
+ { *(.rel.text) *(.rel.gnu.linkonce.t*) }
+ .rel.data :
+ { *(.rel.data) *(.rel.gnu.linkonce.d*) }
+ .rel.rodata :
+ { *(.rel.rodata*) *(.rel.gnu.linkonce.r*) }
+ .rel.got : { *(.rel.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rel.init : { *(.rel.init) }
+ .rel.fini : { *(.rel.fini) }
+ .rel.bss : { *(.rel.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .plt : { *(.plt) }
+ .text . :
+ {
+ _start = .;
+ *(.text*)
+ *(.stub)
+
+ /*
+ * Special FreeBSD sysctl sections.
+ */
+ . = ALIGN (16);
+ __start_set_sysctl_set = .;
+ ___start_set_sysctl_set = .;
+ *(set_sysc*); /* set_sysctl_* but name is truncated by SH-coff */
+ __stop_set_sysctl_set = ABSOLUTE(.);
+ ___stop_set_sysctl_set = ABSOLUTE(.);
+ *(set_doma*); /* set_domain_* but name is truncated by SH-coff */
+ *(set_pseu*); /* set_pseudo_* but name is truncated by SH-coff */
+
+ /* .gnu.warning sections are handled specially by elf32.em. */
+ *(.gnu.warning)
+ *(.gnu.linkonce.t*)
+ } > ram
+ _etext = .;
+ PROVIDE (etext = .);
+ .init . : { KEEP(*(.init)) } > ram =0
+ .fini . : { KEEP(*(.fini)) } > ram =0
+ .ctors . : { KEEP(*(.ctors)) } > ram =0
+ .dtors . : { KEEP(*(.dtors)) } > ram =0
+ .rodata . : { *(.rodata*) KEEP (*(SORT(.rtemsroset.*))) *(.gnu.linkonce.r*) } > ram
+ .rodata1 . : { *(.rodata1) } > ram
+ .tdata : {
+ __TLS_Data_begin = .;
+ *(.tdata .tdata.* .gnu.linkonce.td.*)
+ __TLS_Data_end = .;
+ } > ram
+ .tbss : {
+ __TLS_BSS_begin = .;
+ *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
+ __TLS_BSS_end = .;
+ } > ram
+ __TLS_Data_size = __TLS_Data_end - __TLS_Data_begin;
+ __TLS_Data_begin = __TLS_Data_size != 0 ? __TLS_Data_begin : __TLS_BSS_begin;
+ __TLS_Data_end = __TLS_Data_size != 0 ? __TLS_Data_end : __TLS_BSS_begin;
+ __TLS_BSS_size = __TLS_BSS_end - __TLS_BSS_begin;
+ __TLS_Size = __TLS_BSS_end - __TLS_Data_begin;
+ __TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss));
+ /* Adjust the address for the data segment. We want to adjust up to
+ the same address within the page on the next page up. */
+ . = ALIGN(128) + (. & (128 - 1));
+ .data . :
+ {
+ *(.data*)
+ KEEP (*(SORT(.rtemsrwset.*)))
+ *(.gcc_exc*)
+ ___EH_FRAME_BEGIN__ = .;
+ *(.eh_fram*)
+ ___EH_FRAME_END__ = .;
+ LONG(0);
+ *(.gcc_except_table*)
+ *(.gnu.linkonce.d*)
+ CONSTRUCTORS
+ } > ram
+ .data1 . : { *(.data1) }
+ .got . : { *(.got.plt) *(.got) }
+ .dynamic . : { *(.dynamic) }
+ /* We want the small data sections together, so single-instruction offsets
+ can access them all, and initialized data all before uninitialized, so
+ we can shorten the on-disk segment size. */
+ .sdata . : { *(.sdata) }
+ _edata = .;
+ PROVIDE (edata = .);
+ __bss_start = .;
+ .sbss . : { *(.sbss*) *(.scommon) }
+ .bss . :
+ {
+ *(.dynbss)
+ *(.bss .bss* .gnu.linkonce.b*)
+ *(COMMON)
+ } > ram
+ _end = . ;
+ PROVIDE (end = .);
+
+ _WorkAreaBase = . ;
+
+ _CPU_Interrupt_stack_low = 0x0f000000 ;
+ _CPU_Interrupt_stack_high = _CPU_Interrupt_stack_low + 4096 ;
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /* DWARF debug sections.
+ Symbols in the DWARF debugging sections are relative to the beginning
+ of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+
+ stack : { _stack = .; *(.stack) } > onchip_ram
+ /* These must appear regardless of . */
+}
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-04 23:02:43 +0000