diff options
Diffstat (limited to '')
| -rw-r--r-- | bsps/riscv/griscv/clock/clockdrv.c | 4 | ||||
| -rw-r--r-- | bsps/riscv/griscv/console/console.c | 2 | ||||
| -rw-r--r-- | bsps/riscv/griscv/console/printk_support.c | 23 | ||||
| -rw-r--r-- | bsps/riscv/griscv/include/bsp.h | 6 | ||||
| -rw-r--r-- | bsps/riscv/griscv/include/bsp/irq.h | 13 | ||||
| -rw-r--r-- | bsps/riscv/griscv/irq/irq.c | 1 | ||||
| -rw-r--r-- | bsps/riscv/include/grlib/io.h | 210 | ||||
| -rw-r--r-- | bsps/riscv/noel/include/bsp/irq.h | 13 | ||||
| -rw-r--r-- | bsps/riscv/riscv/clock/clockdrv.c | 13 | ||||
| -rw-r--r-- | bsps/riscv/riscv/include/bsp/irq.h | 13 | ||||
| -rw-r--r-- | bsps/riscv/riscv/irq/irq.c | 1 |
11 files changed, 234 insertions, 65 deletions
diff --git a/bsps/riscv/griscv/clock/clockdrv.c b/bsps/riscv/griscv/clock/clockdrv.c index ab82751e69..3174bae468 100644 --- a/bsps/riscv/griscv/clock/clockdrv.c +++ b/bsps/riscv/griscv/clock/clockdrv.c @@ -41,7 +41,7 @@ #include <bsp.h> #include <amba.h> -#include <bsp/irq.h> +#include <bsp/irq-generic.h> #include <bspopts.h> #include <bsp/fatal.h> #include <rtems/rtems/intr.h> @@ -220,7 +220,7 @@ CPU_Counter_ticks _CPU_Counter_read( void ) #define Clock_driver_support_initialize_hardware() \ grlib_clock_initialize() -#define Clock_driver_timecounter_tick() grlib_tc_do_tick() +#define Clock_driver_timecounter_tick(arg) grlib_tc_do_tick() #include "../../../shared/dev/clock/clockimpl.h" diff --git a/bsps/riscv/griscv/console/console.c b/bsps/riscv/griscv/console/console.c index af4c19d4cb..0627be5ee3 100644 --- a/bsps/riscv/griscv/console/console.c +++ b/bsps/riscv/griscv/console/console.c @@ -82,7 +82,7 @@ static int find_matching_apbuart(struct ambapp_dev *dev, int index, void *arg) struct ambapp_apb_info *apb = (struct ambapp_apb_info *)dev->devinfo; /* Extract needed information of one APBUART */ - apbuarts[uarts].regs = (struct apbuart_regs *)apb->start; + apbuarts[uarts].regs = (apbuart *)apb->start; apbuarts[uarts].irq = apb->common.irq; /* Get APBUART core frequency, it is assumed that it is the same * as Bus frequency where the UART is situated diff --git a/bsps/riscv/griscv/console/printk_support.c b/bsps/riscv/griscv/console/printk_support.c index 3a3450551f..f3af16be4d 100644 --- a/bsps/riscv/griscv/console/printk_support.c +++ b/bsps/riscv/griscv/console/printk_support.c @@ -43,9 +43,10 @@ #include <stdio.h> #include <grlib/apbuart.h> #include <grlib/ambapp.h> +#include <grlib/io.h> int grlib_debug_uart_index __attribute__((weak)) = 0; -struct apbuart_regs *grlib_debug_uart = NULL; +apbuart *grlib_debug_uart = NULL; /* Before UART driver has registered (or when no UART is available), calls to * printk that gets to bsp_out_char() will be filling data into the @@ -87,13 +88,17 @@ static void bsp_debug_uart_init(void) VENDOR_GAISLER, GAISLER_APBUART, ambapp_find_by_idx, (void *)&i); if (adev) { + uint32_t ctrl; + /* Found a matching debug console, initialize debug uart if present * for printk */ apb = (struct ambapp_apb_info *)adev->devinfo; - grlib_debug_uart = (struct apbuart_regs *)apb->start; - grlib_debug_uart->ctrl |= APBUART_CTRL_RE | APBUART_CTRL_TE; - grlib_debug_uart->status = 0; + grlib_debug_uart = (apbuart *)apb->start; + ctrl = grlib_load_32(&grlib_debug_uart->ctrl); + ctrl |= APBUART_CTRL_RE | APBUART_CTRL_TE; + grlib_store_32(&grlib_debug_uart->ctrl, ctrl); + grlib_store_32(&grlib_debug_uart->status, 0); } } @@ -107,10 +112,14 @@ RTEMS_SYSINIT_ITEM( static void bsp_out_char(char c) { if (grlib_debug_uart == NULL) { + uint32_t ctrl; + /* Try to assign standard UART address to debug driver to pass some tests */ - grlib_debug_uart = (struct apbuart_regs *) 0x80000100; - grlib_debug_uart->ctrl |= APBUART_CTRL_RE | APBUART_CTRL_TE; - grlib_debug_uart->status = 0; + grlib_debug_uart = (apbuart *) 0x80000100; + ctrl = grlib_load_32(&grlib_debug_uart->ctrl); + ctrl |= APBUART_CTRL_RE | APBUART_CTRL_TE; + grlib_store_32(&grlib_debug_uart->ctrl, ctrl); + grlib_store_32(&grlib_debug_uart->status, 0); /* Local debug buffer when UART driver has not registered */ /* pre_printk_dbgbuf[pre_printk_pos++] = c; diff --git a/bsps/riscv/griscv/include/bsp.h b/bsps/riscv/griscv/include/bsp.h index 9d6fb2a16f..a0aec4f130 100644 --- a/bsps/riscv/griscv/include/bsp.h +++ b/bsps/riscv/griscv/include/bsp.h @@ -69,12 +69,6 @@ extern "C" { /* Maximum supported APBUARTs by BSP */ #define BSP_NUMBER_OF_TERMIOS_PORTS 8 -/* GRLIB driver functions */ - -extern void BSP_shared_interrupt_mask(int irq); -extern void BSP_shared_interrupt_clear(int irq); -extern void BSP_shared_interrupt_unmask(int irq); - /* * Network driver configuration for greth */ diff --git a/bsps/riscv/griscv/include/bsp/irq.h b/bsps/riscv/griscv/include/bsp/irq.h index 9256e4ff3c..43ee019620 100644 --- a/bsps/riscv/griscv/include/bsp/irq.h +++ b/bsps/riscv/griscv/include/bsp/irq.h @@ -40,9 +40,6 @@ #ifndef ASM #include <bsp.h> -#include <rtems/irq.h> -#include <rtems/irq-extension.h> -#include <rtems/score/processormask.h> #define RISCV_INTERRUPT_VECTOR_SOFTWARE 0 @@ -56,16 +53,6 @@ #define BSP_INTERRUPT_VECTOR_COUNT RISCV_INTERRUPT_VECTOR_EXTERNAL(RISCV_MAXIMUM_EXTERNAL_INTERRUPTS) -rtems_status_code bsp_interrupt_set_affinity( - rtems_vector_number vector, - const Processor_mask *affinity -); - -rtems_status_code bsp_interrupt_get_affinity( - rtems_vector_number vector, - Processor_mask *affinity -); - #endif /* ASM */ #endif /* LIBBSP_RISCV_GRISCV_IRQ_H */ diff --git a/bsps/riscv/griscv/irq/irq.c b/bsps/riscv/griscv/irq/irq.c index 507302d4dd..12af7d7b3d 100644 --- a/bsps/riscv/griscv/irq/irq.c +++ b/bsps/riscv/griscv/irq/irq.c @@ -34,7 +34,6 @@ * SUCH DAMAGE. */ -#include <bsp/irq.h> #include <bsp/fatal.h> #include <bsp/irq-generic.h> #include <amba.h> diff --git a/bsps/riscv/include/grlib/io.h b/bsps/riscv/include/grlib/io.h new file mode 100644 index 0000000000..4d5f7d3791 --- /dev/null +++ b/bsps/riscv/include/grlib/io.h @@ -0,0 +1,210 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief This header file defines the register load/store interface. + */ + +/* + * Copyright (C) 2021 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is part of the RTEMS quality process and was automatically + * generated. If you find something that needs to be fixed or + * worded better please post a report or patch to an RTEMS mailing list + * or raise a bug report: + * + * https://www.rtems.org/bugs.html + * + * For information on updating and regenerating please refer to the How-To + * section in the Software Requirements Engineering chapter of the + * RTEMS Software Engineering manual. The manual is provided as a part of + * a release. For development sources please refer to the online + * documentation at: + * + * https://docs.rtems.org + */ + +/* Generated from spec:/bsp/riscv/if/grlib-io-header */ + +#ifndef _GRLIB_IO_H +#define _GRLIB_IO_H + +#include <stdint.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Generated from spec:/bsp/riscv/if/grlib-io-group */ + +/** + * @defgroup RTEMSDeviceGRLIBIO Register Load/Store + * + * @ingroup RTEMSDeviceGRLIB + * + * @brief This group contains the GRLIB register load/store API. + */ + +/* Generated from spec:/bsp/riscv/if/grlib-load-08 */ + +/** + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief Loads the memory-mapped unsigned 8-bit register. + * + * @param address is the address of the memory-mapped unsigned 8-bit register + * to load. + * + * @return Returns the loaded register value. + */ +static inline uint8_t grlib_load_8( const volatile uint8_t *address ) +{ + return *address; +} + +/* Generated from spec:/bsp/riscv/if/grlib-load-16 */ + +/** + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief Loads the memory-mapped unsigned 16-bit register. + * + * @param address is the address of the memory-mapped unsigned 16-bit register + * to load. + * + * @return Returns the loaded register value. + */ +static inline uint16_t grlib_load_16( const volatile uint16_t *address ) +{ + return *address; +} + +/* Generated from spec:/bsp/riscv/if/grlib-load-32 */ + +/** + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief Loads the memory-mapped unsigned 32-bit register. + * + * @param address is the address of the memory-mapped unsigned 32-bit register + * to load. + * + * @return Returns the loaded register value. + */ +static inline uint32_t grlib_load_32( const volatile uint32_t *address ) +{ + return *address; +} + +/* Generated from spec:/bsp/riscv/if/grlib-load-64 */ + +/** + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief Loads the memory-mapped unsigned 64-bit register. + * + * @param address is the address of the memory-mapped unsigned 64-bit register + * to load. + * + * @return Returns the loaded register value. + */ +static inline uint64_t grlib_load_64( const volatile uint64_t *address ) +{ + return *address; +} + +/* Generated from spec:/bsp/riscv/if/grlib-store-08 */ + +/** + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief Stores the value to the memory-mapped unsigned 8-bit register. + * + * @param address is the address of the memory-mapped unsigned 8-bit register. + * + * @param value is the value to store. + */ +static inline void grlib_store_8( volatile uint8_t *address, uint8_t value ) +{ + *address = value; +} + +/* Generated from spec:/bsp/riscv/if/grlib-store-16 */ + +/** + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief Stores the value to the memory-mapped unsigned 16-bit register. + * + * @param address is the address of the memory-mapped unsigned 16-bit register. + * + * @param value is the value to store. + */ +static inline void grlib_store_16( volatile uint16_t *address, uint16_t value ) +{ + *address = value; +} + +/* Generated from spec:/bsp/riscv/if/grlib-store-32 */ + +/** + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief Stores the value to the memory-mapped unsigned 32-bit register. + * + * @param address is the address of the memory-mapped unsigned 32-bit register. + * + * @param value is the value to store. + */ +static inline void grlib_store_32( volatile uint32_t *address, uint32_t value ) +{ + *address = value; +} + +/* Generated from spec:/bsp/riscv/if/grlib-store-64 */ + +/** + * @ingroup RTEMSDeviceGRLIBIO + * + * @brief Stores the value to the memory-mapped unsigned 64-bit register. + * + * @param address is the address of the memory-mapped unsigned 64-bit register. + * + * @param value is the value to store. + */ +static inline void grlib_store_64( volatile uint64_t *address, uint64_t value ) +{ + *address = value; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _GRLIB_IO_H */ diff --git a/bsps/riscv/noel/include/bsp/irq.h b/bsps/riscv/noel/include/bsp/irq.h index 0c0dc1a48e..3bbea3edfe 100644 --- a/bsps/riscv/noel/include/bsp/irq.h +++ b/bsps/riscv/noel/include/bsp/irq.h @@ -42,9 +42,6 @@ #ifndef ASM #include <bsp.h> -#include <rtems/irq.h> -#include <rtems/irq-extension.h> -#include <rtems/score/processormask.h> #define RISCV_INTERRUPT_VECTOR_SOFTWARE 0 @@ -60,16 +57,6 @@ #define BSP_INTERRUPT_CUSTOM_VALID_VECTOR -rtems_status_code bsp_interrupt_set_affinity( - rtems_vector_number vector, - const Processor_mask *affinity -); - -rtems_status_code bsp_interrupt_get_affinity( - rtems_vector_number vector, - Processor_mask *affinity -); - #endif /* ASM */ #endif /* LIBBSP_GENERIC_RISCV_IRQ_H */ diff --git a/bsps/riscv/riscv/clock/clockdrv.c b/bsps/riscv/riscv/clock/clockdrv.c index ebbc9d77d9..d2f8f5da54 100644 --- a/bsps/riscv/riscv/clock/clockdrv.c +++ b/bsps/riscv/riscv/clock/clockdrv.c @@ -47,9 +47,6 @@ #include <libfdt.h> -/* This is defined in dev/clock/clockimpl.h */ -void Clock_isr(void *arg); - typedef struct { struct timecounter base; volatile RISCV_CLINT_regs *clint; @@ -105,7 +102,7 @@ static void riscv_clock_at_tick(riscv_timecounter *tc) riscv_clock_write_mtimecmp(mtimecmp, value); } -static void riscv_clock_handler_install(void) +static void riscv_clock_handler_install(rtems_interrupt_handler handler) { rtems_status_code sc; @@ -113,8 +110,8 @@ static void riscv_clock_handler_install(void) RISCV_INTERRUPT_VECTOR_TIMER, "Clock", RTEMS_INTERRUPT_UNIQUE, - (rtems_interrupt_handler) Clock_isr, - NULL + handler, + &riscv_clock_tc ); if (sc != RTEMS_SUCCESSFUL) { bsp_fatal(RISCV_FATAL_CLOCK_IRQ_INSTALL); @@ -242,11 +239,11 @@ RTEMS_SYSINIT_ITEM( RTEMS_SYSINIT_ORDER_FIRST ); -#define Clock_driver_support_at_tick() riscv_clock_at_tick(&riscv_clock_tc) +#define Clock_driver_support_at_tick(arg) riscv_clock_at_tick(arg) #define Clock_driver_support_initialize_hardware() riscv_clock_initialize() #define Clock_driver_support_install_isr(isr) \ - riscv_clock_handler_install() + riscv_clock_handler_install(isr) #include "../../../shared/dev/clock/clockimpl.h" diff --git a/bsps/riscv/riscv/include/bsp/irq.h b/bsps/riscv/riscv/include/bsp/irq.h index 0c0dc1a48e..3bbea3edfe 100644 --- a/bsps/riscv/riscv/include/bsp/irq.h +++ b/bsps/riscv/riscv/include/bsp/irq.h @@ -42,9 +42,6 @@ #ifndef ASM #include <bsp.h> -#include <rtems/irq.h> -#include <rtems/irq-extension.h> -#include <rtems/score/processormask.h> #define RISCV_INTERRUPT_VECTOR_SOFTWARE 0 @@ -60,16 +57,6 @@ #define BSP_INTERRUPT_CUSTOM_VALID_VECTOR -rtems_status_code bsp_interrupt_set_affinity( - rtems_vector_number vector, - const Processor_mask *affinity -); - -rtems_status_code bsp_interrupt_get_affinity( - rtems_vector_number vector, - Processor_mask *affinity -); - #endif /* ASM */ #endif /* LIBBSP_GENERIC_RISCV_IRQ_H */ diff --git a/bsps/riscv/riscv/irq/irq.c b/bsps/riscv/riscv/irq/irq.c index 4679d5a624..ada418b7fb 100644 --- a/bsps/riscv/riscv/irq/irq.c +++ b/bsps/riscv/riscv/irq/irq.c @@ -36,7 +36,6 @@ * SUCH DAMAGE. */ -#include <bsp/irq.h> #include <bsp/fatal.h> #include <bsp/fdt.h> #include <bsp/irq-generic.h> |