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-rw-r--r--bsps/riscv/riscv/start/bsp_fatal_halt.c17
1 files changed, 13 insertions, 4 deletions
diff --git a/bsps/riscv/riscv/start/bsp_fatal_halt.c b/bsps/riscv/riscv/start/bsp_fatal_halt.c
index d9708661a7..06fffad6df 100644
--- a/bsps/riscv/riscv/start/bsp_fatal_halt.c
+++ b/bsps/riscv/riscv/start/bsp_fatal_halt.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018 embedded brains GmbH
+ * Copyright (c) 2018 embedded brains GmbH & Co. KG
*
* Copyright (c) 2015 University of York.
* Hesham Almatary <hesham@alumni.york.ac.uk>
@@ -38,11 +38,20 @@ void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error )
int node;
volatile uint32_t *sifive_test;
-#if RISCV_ENABLE_HTIF_SUPPORT != 0
- htif_poweroff();
+ fdt = bsp_fdt_get();
+
+#ifdef RISCV_ENABLE_HTIF_SUPPORT
+ node = fdt_node_offset_by_compatible(fdt, -1, "ucb,htif0");
+
+ if (node >= 0) {
+ htif_poweroff();
+ }
+#endif
+
+#if RISCV_ENABLE_MPFS_SUPPORT != 0
+ for(;;);
#endif
- fdt = bsp_fdt_get();
node = fdt_node_offset_by_compatible(fdt, -1, "sifive,test0");
sifive_test = riscv_fdt_get_address(fdt, node);