1 files changed, 37 insertions, 18 deletions

diff --git a/c/src/lib/libcpu/or1k/shared/cache/cache.c b/bsps/or1k/shared/cache/cache.c
index 898955f041..55fa54e62f 100644
--- a/c/src/lib/libcpu/or1k/shared/cache/cache.c
+++ b/bsps/or1k/shared/cache/cache.c
@@ -18,7 +18,24 @@
 #include <rtems/score/interr.h>
 #include <rtems/score/or1k-utility.h>
 #include <rtems/score/percpu.h>
-#include "cache_.h"
+
+#define CPU_DATA_CACHE_ALIGNMENT        32
+#define CPU_INSTRUCTION_CACHE_ALIGNMENT 32
+
+#define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS 1
+#define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS 1
+
+static inline size_t
+_CPU_cache_get_data_cache_size( const uint32_t level )
+{
+  return (level == 0 || level == 1)? 8192 : 0;
+}
+
+static inline size_t
+_CPU_cache_get_instruction_cache_size( const uint32_t level )
+{
+  return (level == 0 || level == 1)? 8192 : 0;
+}
 
 static inline void _CPU_OR1K_Cache_data_block_prefetch(const void *d_addr)
 {
@@ -79,7 +96,7 @@ static inline void _CPU_OR1K_Cache_instruction_block_lock
 
 /* Implement RTEMS cache manager functions */
 
-void _CPU_cache_flush_1_data_line(const void *d_addr)
+static void _CPU_cache_flush_1_data_line(const void *d_addr)
 {
   ISR_Level level;
 
@@ -92,7 +109,7 @@ void _CPU_cache_flush_1_data_line(const void *d_addr)
   _ISR_Local_enable(level);
 }
 
-void _CPU_cache_invalidate_1_data_line(const void *d_addr)
+static void _CPU_cache_invalidate_1_data_line(const void *d_addr)
 {
   ISR_Level level;
 
@@ -103,17 +120,17 @@ void _CPU_cache_invalidate_1_data_line(const void *d_addr)
   _ISR_Local_enable(level);
 }
 
-void _CPU_cache_freeze_data(void)
+static void _CPU_cache_freeze_data(void)
 {
   /* Do nothing */
 }
 
-void _CPU_cache_unfreeze_data(void)
+static void _CPU_cache_unfreeze_data(void)
 {
   /* Do nothing */
 }
 
-void _CPU_cache_invalidate_1_instruction_line(const void *d_addr)
+static void _CPU_cache_invalidate_1_instruction_line(const void *d_addr)
 {
   ISR_Level level;
 
@@ -124,17 +141,17 @@ void _CPU_cache_invalidate_1_instruction_line(const void *d_addr)
   _ISR_Local_enable(level);
 }
 
-void _CPU_cache_freeze_instruction(void)
+static void _CPU_cache_freeze_instruction(void)
 {
   /* Do nothing */
 }
 
-void _CPU_cache_unfreeze_instruction(void)
+static void _CPU_cache_unfreeze_instruction(void)
 {
   /* Do nothing */
 }
 
-void _CPU_cache_flush_entire_data(void)
+static void _CPU_cache_flush_entire_data(void)
 {
   size_t addr;
   ISR_Level level;
@@ -153,7 +170,7 @@ void _CPU_cache_flush_entire_data(void)
   _ISR_Local_enable (level);
 }
 
-void _CPU_cache_invalidate_entire_data(void)
+static void _CPU_cache_invalidate_entire_data(void)
 {
   size_t addr;
   ISR_Level level;
@@ -172,7 +189,7 @@ void _CPU_cache_invalidate_entire_data(void)
   _ISR_Local_enable (level);
 }
 
-void _CPU_cache_invalidate_entire_instruction(void)
+static void _CPU_cache_invalidate_entire_instruction(void)
 {
   size_t addr;
   ISR_Level level;
@@ -205,7 +222,7 @@ void _CPU_cache_invalidate_entire_instruction(void)
  * cache line operation.
  */
 
-void _CPU_cache_flush_data_range(const void *d_addr, size_t n_bytes)
+static void _CPU_cache_flush_data_range(const void *d_addr, size_t n_bytes)
 {
   const void * final_address;
   ISR_Level level;
@@ -242,7 +259,7 @@ void _CPU_cache_flush_data_range(const void *d_addr, size_t n_bytes)
   _ISR_Local_enable (level);
 }
 
-void _CPU_cache_invalidate_data_range(const void *d_addr, size_t n_bytes)
+static void _CPU_cache_invalidate_data_range(const void *d_addr, size_t n_bytes)
 {
   const void * final_address;
   ISR_Level level;
@@ -279,7 +296,7 @@ void _CPU_cache_invalidate_data_range(const void *d_addr, size_t n_bytes)
   _ISR_Local_enable (level);
 }
 
-void _CPU_cache_invalidate_instruction_range(const void *i_addr, size_t n_bytes)
+static void _CPU_cache_invalidate_instruction_range(const void *i_addr, size_t n_bytes)
 {
   const void * final_address;
   ISR_Level level;
@@ -316,7 +333,7 @@ void _CPU_cache_invalidate_instruction_range(const void *i_addr, size_t n_bytes)
   _ISR_Local_enable (level);
 }
 
-void _CPU_cache_enable_data(void)
+static void _CPU_cache_enable_data(void)
 {
   uint32_t sr;
   ISR_Level level;
@@ -329,7 +346,7 @@ void _CPU_cache_enable_data(void)
   _ISR_Local_enable(level);
 }
 
-void _CPU_cache_disable_data(void)
+static void _CPU_cache_disable_data(void)
 {
   uint32_t sr;
   ISR_Level level;
@@ -342,7 +359,7 @@ void _CPU_cache_disable_data(void)
   _ISR_Local_enable(level);
 }
 
-void _CPU_cache_enable_instruction(void)
+static void _CPU_cache_enable_instruction(void)
 {
   uint32_t sr;
   ISR_Level level;
@@ -355,7 +372,7 @@ void _CPU_cache_enable_instruction(void)
   _ISR_Local_enable(level);
 }
 
-void _CPU_cache_disable_instruction(void)
+static void _CPU_cache_disable_instruction(void)
 {
   uint32_t sr;
   ISR_Level level;
@@ -367,3 +384,5 @@ void _CPU_cache_disable_instruction(void)
 
   _ISR_Local_enable(level);
 }
+
+#include "../../../shared/cache/cacheimpl.h"