diff options
Diffstat (limited to 'bsps/microblaze/microblaze_fpga')
| -rw-r--r-- | bsps/microblaze/microblaze_fpga/clock/clock.c | 145 | ||||
| -rw-r--r-- | bsps/microblaze/microblaze_fpga/console/console-io.c | 57 | ||||
| -rw-r--r-- | bsps/microblaze/microblaze_fpga/console/debug-io.c | 66 | ||||
| -rw-r--r-- | bsps/microblaze/microblaze_fpga/include/bsp.h | 53 | ||||
| -rw-r--r-- | bsps/microblaze/microblaze_fpga/include/bsp/intc.h | 74 | ||||
| -rw-r--r-- | bsps/microblaze/microblaze_fpga/include/bsp/irq.h | 49 | ||||
| -rw-r--r-- | bsps/microblaze/microblaze_fpga/include/bsp/timer.h | 69 | ||||
| -rw-r--r-- | bsps/microblaze/microblaze_fpga/include/tm27.h | 58 | ||||
| -rw-r--r-- | bsps/microblaze/microblaze_fpga/irq/irq.c | 168 | ||||
| -rw-r--r-- | bsps/microblaze/microblaze_fpga/start/_exception_handler.S | 52 | ||||
| -rw-r--r-- | bsps/microblaze/microblaze_fpga/start/_hw_exception_handler.S | 52 | ||||
| -rw-r--r-- | bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S | 53 | ||||
| -rw-r--r-- | bsps/microblaze/microblaze_fpga/start/bspreset.c | 44 | ||||
| -rw-r--r-- | bsps/microblaze/microblaze_fpga/start/bspstart.c | 43 | ||||
| -rw-r--r-- | bsps/microblaze/microblaze_fpga/start/crtinit.S | 103 |
15 files changed, 1086 insertions, 0 deletions
diff --git a/bsps/microblaze/microblaze_fpga/clock/clock.c b/bsps/microblaze/microblaze_fpga/clock/clock.c new file mode 100644 index 0000000000..957d0fdadb --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/clock/clock.c @@ -0,0 +1,145 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief MicroBlaze AXI Timer clock support + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <bsp/fatal.h> +#include <bsp/timer.h> + +#include <rtems.h> +#include <rtems/irq-extension.h> +#include <rtems/timecounter.h> + +static rtems_timecounter_simple mblaze_tc; + +static uint32_t microblaze_tc_get( rtems_timecounter_simple *tc ) +{ + volatile Microblaze_Timer *timer = _Microblaze_Timer; + return timer->tcr0; +} + +static bool microblaze_tc_is_pending( rtems_timecounter_simple *tc ) +{ + volatile Microblaze_Timer *timer = _Microblaze_Timer; + return ( timer->tcsr0 & MICROBLAZE_TIMER_TCSR0_T0INT ) != 0; +} + +static uint32_t microblaze_tc_get_timecount( struct timecounter *tc ) +{ + return rtems_timecounter_simple_downcounter_get( + tc, + microblaze_tc_get, + microblaze_tc_is_pending + ); +} + +static void microblaze_clock_initialize( void ) +{ + volatile Microblaze_Timer *timer = _Microblaze_Timer; + /* Set load register to 0 */ + timer->tlr0 = 0; + /* Reset the timer and interrupt */ + timer->tcsr0 = MICROBLAZE_TIMER_TCSR0_T0INT | MICROBLAZE_TIMER_TCSR0_LOAD0; + /* Release the reset */ + timer->tcsr0 = 0; + /* + * Enable interrupt, auto reload mode, external interrupt signal, + * and down counter + */ + timer->tcsr0 = MICROBLAZE_TIMER_TCSR0_ARHT0 | MICROBLAZE_TIMER_TCSR0_ENIT0 | + MICROBLAZE_TIMER_TCSR0_GENT0 | MICROBLAZE_TIMER_TCSR0_UDT0; + + uint64_t us_per_tick = rtems_configuration_get_microseconds_per_tick(); + uint32_t counter_frequency_in_hz = BSP_MICROBLAZE_FPGA_TIMER_FREQUENCY; + uint32_t counter_ticks_per_clock_tick = + ( counter_frequency_in_hz * us_per_tick ) / 1000000; + + /* Set a reset value for the timer counter */ + timer->tlr0 = counter_ticks_per_clock_tick; + uint32_t control_status_reg = timer->tcsr0; + /* Load the reset value into the counter register */ + timer->tcsr0 = MICROBLAZE_TIMER_TCSR0_LOAD0; + /* Enable the timer */ + timer->tcsr0 = control_status_reg | MICROBLAZE_TIMER_TCSR0_ENT0; + + rtems_timecounter_simple_install( + &mblaze_tc, + counter_frequency_in_hz, + counter_ticks_per_clock_tick, + microblaze_tc_get_timecount + ); +} + +static void microblaze_clock_at_tick( rtems_timecounter_simple *tc ) +{ + volatile Microblaze_Timer *timer = _Microblaze_Timer; + if ( ( timer->tcsr0 & MICROBLAZE_TIMER_TCSR0_T0INT ) == 0 ) { + return; + } + /* Clear the interrupt */ + timer->tcsr0 |= MICROBLAZE_TIMER_TCSR0_T0INT; +} + +static void microblaze_tc_tick( void ) +{ + rtems_timecounter_simple_downcounter_tick( + &mblaze_tc, + microblaze_tc_get, + microblaze_clock_at_tick + ); +} + +static void microblaze_clock_handler_install( rtems_interrupt_handler isr ) +{ + rtems_status_code sc = RTEMS_SUCCESSFUL; + + sc = rtems_interrupt_handler_install( + 0, + "Clock", + RTEMS_INTERRUPT_UNIQUE, + isr, + NULL + ); + + if ( sc != RTEMS_SUCCESSFUL ) { + bsp_fatal( MICROBLAZE_FATAL_CLOCK_IRQ_INSTALL ); + } +} + +#define Clock_driver_support_initialize_hardware() microblaze_clock_initialize() +#define Clock_driver_support_install_isr( isr ) \ + microblaze_clock_handler_install( isr ) +#define Clock_driver_timecounter_tick() microblaze_tc_tick() + +/* Include shared source clock driver code */ +#include "../../shared/dev/clock/clockimpl.h" diff --git a/bsps/microblaze/microblaze_fpga/console/console-io.c b/bsps/microblaze/microblaze_fpga/console/console-io.c new file mode 100644 index 0000000000..cb2e367035 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/console/console-io.c @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief MicroBlaze console configuration + */ + +/* + * Copyright (C) 2015 Hesham Almatary + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <bsp/console-termios.h> +#include <dev/serial/uartlite.h> + +#include <bspopts.h> + +uart_lite_context microblaze_qemu_uart_context = { + .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "UARTLITE" ), + .address = BSP_MICROBLAZE_FPGA_UART_BASE, + .initial_baud = 115200 +}; + +const console_device console_device_table[] = { + { + .device_file = "/dev/ttyS0", + .probe = console_device_probe_default, + .handler = µblaze_uart_fns, + .context = µblaze_qemu_uart_context.base + } +}; + +const size_t console_device_count = RTEMS_ARRAY_SIZE( console_device_table ); diff --git a/bsps/microblaze/microblaze_fpga/console/debug-io.c b/bsps/microblaze/microblaze_fpga/console/debug-io.c new file mode 100644 index 0000000000..e88f5468a7 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/console/debug-io.c @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief MicroBlaze debug IO support + */ + +/* + * Copyright (C) 2015 Hesham Almatary + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <dev/serial/uartlite_l.h> +#include <rtems/bspIo.h> + +#include <bspopts.h> + +static void output_char( char c ) +{ + if ( c == '\n' ) { + XUartLite_SendByte( BSP_MICROBLAZE_FPGA_UART_BASE, '\r' ); + } + XUartLite_SendByte( BSP_MICROBLAZE_FPGA_UART_BASE, c ); +} + +static int xUartLite_RecvByte( int minor ) +{ + if ( XUartLite_IsReceiveEmpty( BSP_MICROBLAZE_FPGA_UART_BASE ) ) { + return -1; + } + + return XUartLite_ReadReg( BSP_MICROBLAZE_FPGA_UART_BASE, XUL_RX_FIFO_OFFSET ); +} + +static int get_char( void ) +{ + return xUartLite_RecvByte( 0 ); +} + +BSP_output_char_function_type BSP_output_char = output_char; + +BSP_polling_getchar_function_type BSP_poll_char = get_char; diff --git a/bsps/microblaze/microblaze_fpga/include/bsp.h b/bsps/microblaze/microblaze_fpga/include/bsp.h new file mode 100644 index 0000000000..e83e632553 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/include/bsp.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief Core BSP definitions + */ + +/* + * Copyright (C) 2015 Hesham Almatary + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_MICROBLAZE_FPGA_BSP_H +#define LIBBSP_MICROBLAZE_FPGA_BSP_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include <bspopts.h> +#include <bsp/default-initial-extension.h> + +#include <rtems.h> + +#ifdef __cplusplus +} +#endif + +#endif /* LIBBSP_MICROBLAZE_FPGA_BSP_H */ diff --git a/bsps/microblaze/microblaze_fpga/include/bsp/intc.h b/bsps/microblaze/microblaze_fpga/include/bsp/intc.h new file mode 100644 index 0000000000..df4554386d --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/include/bsp/intc.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief MicroBlaze AXI Interrupt Controller definitions + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_MICROBLAZE_FPGA_INTC_H +#define LIBBSP_MICROBLAZE_FPGA_INTC_H + +#include <bspopts.h> + +#include <bsp/utility.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +typedef struct { + /* Interrupt Status Register */ + uint32_t isr; + uint32_t ipr; + /* Interrupt Enable Register */ + uint32_t ier; + /* Interrupt Acknowledge Register */ + uint32_t iar; + uint32_t sie; + uint32_t cie; + uint32_t ivr; +#define MICROBLAZE_INTC_MER_HIE BSP_BIT32(1) +#define MICROBLAZE_INTC_MER_ME BSP_BIT32(0) + /* Master Enable Register */ + uint32_t mer; + /* Interrupt Mode Register, this is present only for Fast Interrupt */ + uint32_t imr; + /* Interrupt Level Register */ + uint32_t ilr; +} Microblaze_INTC; + +#define _Microblaze_INTC ((volatile Microblaze_INTC *) BSP_MICROBLAZE_FPGA_INTC_BASE) + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_MICROBLAZE_FPGA_INTC_H */ diff --git a/bsps/microblaze/microblaze_fpga/include/bsp/irq.h b/bsps/microblaze/microblaze_fpga/include/bsp/irq.h new file mode 100644 index 0000000000..0a7c211fb0 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/include/bsp/irq.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief BSP IRQ definitions + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_MICROBLAZE_FPGA_IRQ_H +#define LIBBSP_MICROBLAZE_FPGA_IRQ_H + +#ifndef ASM + +#include <rtems.h> +#include <rtems/irq.h> +#include <rtems/irq-extension.h> + +#endif /* ASM */ + +#define BSP_INTERRUPT_VECTOR_COUNT 32 + +#endif /* LIBBSP_MICROBLAZE_FPGA_IRQ_H */ diff --git a/bsps/microblaze/microblaze_fpga/include/bsp/timer.h b/bsps/microblaze/microblaze_fpga/include/bsp/timer.h new file mode 100644 index 0000000000..562fdd79b0 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/include/bsp/timer.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief MicroBlaze AXI Timer definitions + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_MICROBLAZE_FPGA_TIMER_H +#define LIBBSP_MICROBLAZE_FPGA_TIMER_H + +#include <bspopts.h> + +#include <bsp/utility.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +typedef struct { +#define MICROBLAZE_TIMER_TCSR0_T0INT BSP_BIT32(8) +#define MICROBLAZE_TIMER_TCSR0_ENT0 BSP_BIT32(7) +#define MICROBLAZE_TIMER_TCSR0_ENIT0 BSP_BIT32(6) +#define MICROBLAZE_TIMER_TCSR0_LOAD0 BSP_BIT32(5) +#define MICROBLAZE_TIMER_TCSR0_ARHT0 BSP_BIT32(4) +#define MICROBLAZE_TIMER_TCSR0_GENT0 BSP_BIT32(2) +#define MICROBLAZE_TIMER_TCSR0_UDT0 BSP_BIT32(1) + /* Control/Status register */ + uint32_t tcsr0; + /* Load register */ + uint32_t tlr0; + /* Timer counter register */ + uint32_t tcr0; +} Microblaze_Timer; + +#define _Microblaze_Timer ((volatile Microblaze_Timer *) BSP_MICROBLAZE_FPGA_TIMER_BASE) + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_MICROBLAZE_FPGA_TIMER_H */ diff --git a/bsps/microblaze/microblaze_fpga/include/tm27.h b/bsps/microblaze/microblaze_fpga/include/tm27.h new file mode 100644 index 0000000000..f2e384b534 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/include/tm27.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief BSP tm27 header + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Time Test 27 cannot be implemented reliably because the AXI interrupt + * controller is not guaranteed to support software interrupts. + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) /* set_vector( (handler), 6, 1 ) */ + +#define Cause_tm27_intr() /* empty */ + +#define Clear_tm27_intr() /* empty */ + +#define Lower_tm27_intr() /* empty */ + +#endif /* __tm27_h */ diff --git a/bsps/microblaze/microblaze_fpga/irq/irq.c b/bsps/microblaze/microblaze_fpga/irq/irq.c new file mode 100644 index 0000000000..67ddf02079 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/irq/irq.c @@ -0,0 +1,168 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief MicroBlaze interrupt support + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <bsp/intc.h> +#include <bsp/irq-generic.h> + +#include <rtems/score/cpu.h> + +static void ack_interrupt( uint8_t source ) +{ + volatile Microblaze_INTC *intc = _Microblaze_INTC; + intc->iar = 0x1 << source; +} + +rtems_status_code bsp_interrupt_get_attributes( + rtems_vector_number vector, + rtems_interrupt_attributes *attributes +) +{ + attributes->is_maskable = true; + attributes->maybe_enable = true; + attributes->maybe_disable = true; + attributes->can_clear = true; + attributes->cleared_by_acknowledge = true; + + return RTEMS_SUCCESSFUL; +} + +rtems_status_code bsp_interrupt_is_pending( + rtems_vector_number vector, + bool *pending +) +{ + bsp_interrupt_assert( bsp_interrupt_is_valid_vector( vector ) ); + bsp_interrupt_assert( pending != NULL ); + *pending = false; + return RTEMS_UNSATISFIED; +} + +rtems_status_code bsp_interrupt_raise( rtems_vector_number vector ) +{ + bsp_interrupt_assert( bsp_interrupt_is_valid_vector( vector ) ); + return RTEMS_UNSATISFIED; +} + +rtems_status_code bsp_interrupt_clear( rtems_vector_number vector ) +{ + bsp_interrupt_assert( bsp_interrupt_is_valid_vector( vector ) ); + + volatile Microblaze_INTC *intc = _Microblaze_INTC; + intc->iar = 0x1 << vector; + + return RTEMS_SUCCESSFUL; +} + +rtems_status_code bsp_interrupt_vector_is_enabled( + rtems_vector_number vector, + bool *enabled +) +{ + bsp_interrupt_assert( bsp_interrupt_is_valid_vector( vector ) ); + bsp_interrupt_assert( enabled != NULL ); + + volatile Microblaze_INTC *intc = _Microblaze_INTC; + uint32_t mask = 1 << vector; + + *enabled = (intc->ier & mask) != 0; + return RTEMS_SUCCESSFUL; +} + +rtems_status_code bsp_interrupt_vector_enable( rtems_vector_number vector ) +{ + bsp_interrupt_assert( bsp_interrupt_is_valid_vector( vector ) ); + + volatile Microblaze_INTC *intc = _Microblaze_INTC; + uint32_t mask = 1 << vector; + + intc->ier |= mask; + + return RTEMS_SUCCESSFUL; +} + +rtems_status_code bsp_interrupt_vector_disable( rtems_vector_number vector ) +{ + bsp_interrupt_assert( bsp_interrupt_is_valid_vector( vector ) ); + + volatile Microblaze_INTC *intc = _Microblaze_INTC; + uint32_t mask = 1 << vector; + + intc->ier &= ~mask; + + return RTEMS_SUCCESSFUL; +} + +void bsp_interrupt_facility_initialize( void ) +{ + volatile Microblaze_INTC *intc = _Microblaze_INTC; + /* + * Enable HW interrupts on the interrupt controller. This happens before + * interrupts are enabled on the processor. + */ + intc->mer = MICROBLAZE_INTC_MER_ME | MICROBLAZE_INTC_MER_HIE; +} + +void bsp_interrupt_dispatch( uint32_t source ) +{ + volatile Microblaze_INTC *intc = _Microblaze_INTC; + uint32_t vector_number = 0; + + if ( source == 0xFF ) { + /* Read interrupt controller to get the source */ + vector_number = intc->isr; + + /* Handle and the first interrupt that is set */ + uint8_t interrupt_status = 0; + for ( int i = 0; i < 32; i++ ) { + interrupt_status = vector_number >> i & 0x1; + if ( interrupt_status != 0 ) { + /* save current ILR */ + uint32_t interrupt_levels = intc->ilr; + /* set ILR to block out every interrupt less than or equal to priority of i */ + intc->ilr = 0xFFFFFFFF >> (32 - i); + bsp_interrupt_handler_dispatch( i ); + ack_interrupt( i ); + /* restore ILR */ + intc->ilr = interrupt_levels; + break; + } + } + } else { + vector_number = source; + + /* Fast interrupt mode. Handle interrupt. Ack happens automatically */ + bsp_interrupt_handler_dispatch( vector_number ); + } +} diff --git a/bsps/microblaze/microblaze_fpga/start/_exception_handler.S b/bsps/microblaze/microblaze_fpga/start/_exception_handler.S new file mode 100644 index 0000000000..1d96b694a7 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/start/_exception_handler.S @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +/* Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are + met: + + 1. Redistributions source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + 3. Neither the name of Xilinx nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS + IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + + .text + .globl _exception_handler # Exception Handler Label + .align 2 + + _exception_handler: +#ifndef __rtems__ + rtsd r17, 0 + nop +#else /* __rtems__ */ + /* Subtract stack frame */ + addik r1, r1, -52 + + swi r5, r1, 8 + + addi r5, r0, 0xFFFF + + braid _ISR_Handler + nop +#endif /* __rtems__ */ diff --git a/bsps/microblaze/microblaze_fpga/start/_hw_exception_handler.S b/bsps/microblaze/microblaze_fpga/start/_hw_exception_handler.S new file mode 100644 index 0000000000..30436a43e9 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/start/_hw_exception_handler.S @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +/* Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are + met: + + 1. Redistributions source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + 3. Neither the name of Xilinx nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS + IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + + .text + .globl _hw_exception_handler # HW Exception Handler Label + .align 2 + + _hw_exception_handler: +#ifndef __rtems__ + rtsd r17, 0 + nop +#else /* __rtems__ */ + /* Subtract stack frame */ + addik r1, r1, -52 + + swi r5, r1, 8 + + addi r5, r0, 0xFFFF + + braid _ISR_Handler + nop +#endif /* __rtems__ */ diff --git a/bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S b/bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S new file mode 100644 index 0000000000..b817503922 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +/* Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are + met: + + 1. Redistributions source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + 3. Neither the name of Xilinx nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS + IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +*/ + + .text + .globl _interrupt_handler # Interrupt Handler Label + .align 2 + + _interrupt_handler: +#ifndef __rtems__ + rtid r14, 0 + nop +#else /* __rtems__ */ + /* Subtract stack frame */ + addik r1, r1, -52 + + swi r5, r1, 8 + + /* Indicate unknown interrupt source */ + addi r5, r0, 0xFF + + braid _ISR_Handler + nop +#endif /* __rtems__ */ diff --git a/bsps/microblaze/microblaze_fpga/start/bspreset.c b/bsps/microblaze/microblaze_fpga/start/bspreset.c new file mode 100644 index 0000000000..6a7455f522 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/start/bspreset.c @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief BSP Reset + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <rtems.h> +#include <bsp/bootcard.h> + +void bsp_reset( void ) +{ + __asm__ volatile ( + "brai 0xFFFFFFFFFFFFFFFF" + ); +} diff --git a/bsps/microblaze/microblaze_fpga/start/bspstart.c b/bsps/microblaze/microblaze_fpga/start/bspstart.c new file mode 100644 index 0000000000..0caf385b46 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/start/bspstart.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief BSP Startup + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <bsp.h> +#include <bsp/bootcard.h> +#include <bsp/irq-generic.h> + +void bsp_start( void ) +{ + bsp_interrupt_initialize(); +} diff --git a/bsps/microblaze/microblaze_fpga/start/crtinit.S b/bsps/microblaze/microblaze_fpga/start/crtinit.S new file mode 100644 index 0000000000..a9779404b2 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/start/crtinit.S @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +/* Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are + met: + + 1. Redistributions source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + 3. Neither the name of Xilinx nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS + IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + .globl _crtinit + .align 2 + .ent _crtinit + .type _crtinit, @function +_crtinit: + addi r1, r1, -20 /* Save Link register */ + swi r15, r1, 0 + +#ifndef __rtems__ + addi r6, r0, __sbss_start /* clear SBSS */ + addi r7, r0, __sbss_end + rsub r18, r6, r7 + blei r18, .Lendsbss + +.Lloopsbss: + swi r0, r6, 0 + addi r6, r6, 4 + rsub r18, r6, r7 + bgti r18, .Lloopsbss +.Lendsbss: +#endif /* __rtems__ */ + +#ifndef __rtems__ + addi r6, r0, __bss_start /* clear BSS */ + addi r7, r0, __bss_end +#else + addi r6, r0, bsp_section_bss_begin + addi r7, r0, bsp_section_bss_end +#endif /* __rtems__ */ + rsub r18, r6, r7 + blei r18, .Lendbss +.Lloopbss: + swi r0, r6, 0 + addi r6, r6, 4 + rsub r18, r6, r7 + bgti r18, .Lloopbss +.Lendbss: + +#ifndef __rtems__ + brlid r15, _program_init /* Initialize the program */ + nop + + brlid r15, __init /* Invoke language initialization functions */ + nop +#endif /* __rtems__ */ + + addi r6, r0, 0 /* Initialize argc = 1 and argv = NULL and envp = NULL */ + addi r7, r0, 0 +#ifndef __rtems__ + brlid r15, main /* Execute the program */ +#else + brlid r15, boot_card +#endif /* __rtems__ */ + addi r5, r0, 0 + + addik r19, r3, 0 /* Save return value */ + +#ifndef __rtems__ + brlid r15, __fini /* Invoke language cleanup functions */ + nop + + brlid r15, _program_clean /* Cleanup the program */ + nop +#endif /* __rtems__ */ + + lw r15, r1, r0 /* Return back to CRT */ + + addik r3, r19, 0 /* Restore return value */ + rtsd r15, 8 + addi r1, r1, 20 + .end _crtinit |