1 files changed, 17 insertions, 15 deletions

diff --git a/c/src/lib/libcpu/m68k/mcf5282/cache/cachepd.c b/bsps/m68k/shared/cache/cache-mcf5282.c
index e59f213236..259572432a 100644
--- a/c/src/lib/libcpu/m68k/mcf5282/cache/cachepd.c
+++ b/bsps/m68k/shared/cache/cache-mcf5282.c
@@ -6,7 +6,7 @@
 
 #include <rtems.h>
 #include <mcf5282/mcf5282.h>   /* internal MCF5282 modules */
-#include "cache_.h"
+#include "cache.h"
 
 /*
  * CPU-space access
@@ -40,18 +40,18 @@ void mcf5xxx_initialize_cacr(uint32_t cacr)
 /*
  * Cannot be frozen
  */
-void _CPU_cache_freeze_data(void) {}
-void _CPU_cache_unfreeze_data(void) {}
-void _CPU_cache_freeze_instruction(void) {}
-void _CPU_cache_unfreeze_instruction(void) {}
+static void _CPU_cache_freeze_data(void) {}
+static void _CPU_cache_unfreeze_data(void) {}
+static void _CPU_cache_freeze_instruction(void) {}
+static void _CPU_cache_unfreeze_instruction(void) {}
 
 /*
  * Write-through data cache -- flushes are unnecessary
  */
-void _CPU_cache_flush_1_data_line(const void *d_addr) {}
-void _CPU_cache_flush_entire_data(void) {}
+static void _CPU_cache_flush_1_data_line(const void *d_addr) {}
+static void _CPU_cache_flush_entire_data(void) {}
 
-void _CPU_cache_enable_instruction(void)
+static void _CPU_cache_enable_instruction(void)
 {
   rtems_interrupt_level level;
 
@@ -62,7 +62,7 @@ void _CPU_cache_enable_instruction(void)
   rtems_interrupt_enable(level);
 }
 
-void _CPU_cache_disable_instruction(void)
+static void _CPU_cache_disable_instruction(void)
 {
   rtems_interrupt_level level;
 
@@ -72,13 +72,13 @@ void _CPU_cache_disable_instruction(void)
   rtems_interrupt_enable(level);
 }
 
-void _CPU_cache_invalidate_entire_instruction(void)
+static void _CPU_cache_invalidate_entire_instruction(void)
 {
   m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
   NOP;
 }
 
-void _CPU_cache_invalidate_1_instruction_line(const void *addr)
+static void _CPU_cache_invalidate_1_instruction_line(const void *addr)
 {
   /*
    * Top half of cache is I-space
@@ -87,7 +87,7 @@ void _CPU_cache_invalidate_1_instruction_line(const void *addr)
   __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr));
 }
 
-void _CPU_cache_enable_data(void)
+static void _CPU_cache_enable_data(void)
 {
   rtems_interrupt_level level;
 
@@ -97,7 +97,7 @@ void _CPU_cache_enable_data(void)
   rtems_interrupt_enable(level);
 }
 
-void _CPU_cache_disable_data(void)
+static void _CPU_cache_disable_data(void)
 {
   rtems_interrupt_level level;
 
@@ -107,12 +107,12 @@ void _CPU_cache_disable_data(void)
   rtems_interrupt_enable(level);
 }
 
-void _CPU_cache_invalidate_entire_data(void)
+static void _CPU_cache_invalidate_entire_data(void)
 {
   m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
 }
 
-void _CPU_cache_invalidate_1_data_line(const void *addr)
+static void _CPU_cache_invalidate_1_data_line(const void *addr)
 {
   /*
    * Bottom half of cache is D-space
@@ -120,3 +120,5 @@ void _CPU_cache_invalidate_1_data_line(const void *addr)
   addr = (void *)((int)addr & ~0x400);
   __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr));
 }
+
+#include "../../../shared/cache/cacheimpl.h"