1 files changed, 17 insertions, 15 deletions

diff --git a/c/src/lib/libcpu/m68k/mcf5235/cache/cachepd.c b/bsps/m68k/shared/cache/cache-mcf5235.c
index 043908c0e7..35390b02ef 100644
--- a/c/src/lib/libcpu/m68k/mcf5235/cache/cachepd.c
+++ b/bsps/m68k/shared/cache/cache-mcf5235.c
@@ -9,7 +9,7 @@
 
 #include <rtems.h>
 #include <mcf5235/mcf5235.h>
-#include "cache_.h"
+#include "cache.h"
 
 /*
  *  Default value for the cacr is set by the BSP
@@ -19,18 +19,18 @@ extern uint32_t cacr_mode;
 /*
  * Cannot be frozen
  */
-void _CPU_cache_freeze_data(void) {}
-void _CPU_cache_unfreeze_data(void) {}
-void _CPU_cache_freeze_instruction(void) {}
-void _CPU_cache_unfreeze_instruction(void) {}
+static void _CPU_cache_freeze_data(void) {}
+static void _CPU_cache_unfreeze_data(void) {}
+static void _CPU_cache_freeze_instruction(void) {}
+static void _CPU_cache_unfreeze_instruction(void) {}
 
 /*
  * Write-through data cache -- flushes are unnecessary
  */
-void _CPU_cache_flush_1_data_line(const void *d_addr) {}
-void _CPU_cache_flush_entire_data(void) {}
+static void _CPU_cache_flush_1_data_line(const void *d_addr) {}
+static void _CPU_cache_flush_entire_data(void) {}
 
-void _CPU_cache_enable_instruction(void)
+static void _CPU_cache_enable_instruction(void)
 {
     rtems_interrupt_level level;
 
@@ -40,7 +40,7 @@ void _CPU_cache_enable_instruction(void)
     rtems_interrupt_enable(level);
 }
 
-void _CPU_cache_disable_instruction(void)
+static void _CPU_cache_disable_instruction(void)
 {
     rtems_interrupt_level level;
 
@@ -50,12 +50,12 @@ void _CPU_cache_disable_instruction(void)
     rtems_interrupt_enable(level);
 }
 
-void _CPU_cache_invalidate_entire_instruction(void)
+static void _CPU_cache_invalidate_entire_instruction(void)
 {
     m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
 }
 
-void _CPU_cache_invalidate_1_instruction_line(const void *addr)
+static void _CPU_cache_invalidate_1_instruction_line(const void *addr)
 {
     /*
      * Top half of cache is I-space
@@ -64,7 +64,7 @@ void _CPU_cache_invalidate_1_instruction_line(const void *addr)
     __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr));
 }
 
-void _CPU_cache_enable_data(void)
+static void _CPU_cache_enable_data(void)
 {
     rtems_interrupt_level level;
 
@@ -74,7 +74,7 @@ void _CPU_cache_enable_data(void)
     rtems_interrupt_enable(level);
 }
 
-void _CPU_cache_disable_data(void)
+static void _CPU_cache_disable_data(void)
 {
     rtems_interrupt_level level;
 
@@ -84,12 +84,12 @@ void _CPU_cache_disable_data(void)
     rtems_interrupt_enable(level);
 }
 
-void _CPU_cache_invalidate_entire_data(void)
+static void _CPU_cache_invalidate_entire_data(void)
 {
     m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
 }
 
-void _CPU_cache_invalidate_1_data_line(const void *addr)
+static void _CPU_cache_invalidate_1_data_line(const void *addr)
 {
     /*
      * Bottom half of cache is D-space
@@ -97,3 +97,5 @@ void _CPU_cache_invalidate_1_data_line(const void *addr)
     addr = (void *)((int)addr & ~0x400);
     __asm__ volatile ("cpushl %%bc,(%0)" :: "a" (addr));
 }
+
+#include "../../../shared/cache/cacheimpl.h"