diff options
Diffstat (limited to 'bsps/include/fsl/regs-edma.h')
| -rw-r--r-- | bsps/include/fsl/regs-edma.h | 977 |
1 files changed, 343 insertions, 634 deletions
diff --git a/bsps/include/fsl/regs-edma.h b/bsps/include/fsl/regs-edma.h index fda47dc1e6..4afdb9b4e4 100644 --- a/bsps/include/fsl/regs-edma.h +++ b/bsps/include/fsl/regs-edma.h @@ -1,21 +1,32 @@ /** * @file * - * @ingroup RTEMSBSPsPowerPCMPC55XX + * @ingroup RTEMSBSPsSharedFslEDMA */ /* - * Copyright (c) 2011 embedded brains GmbH. All rights reserved. + * Copyright (C) 2011-2020 embedded brains GmbH (http://www.embedded-brains.de) * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ /********************************************************************* @@ -49,647 +60,345 @@ * ********************************************************************/ -#ifndef LIBCPU_POWERPC_MPC55XX_REGS_EDMA_H -#define LIBCPU_POWERPC_MPC55XX_REGS_EDMA_H +#ifndef LIBBSP_SHARED_FSL_REGS_EDMA_H +#define LIBBSP_SHARED_FSL_REGS_EDMA_H #include <stdint.h> - +#include <bsp.h> #include <bspopts.h> #ifdef __cplusplus extern "C" { #endif -/****************************************************************************/ -/* MODULE : eDMA */ -/****************************************************************************/ - struct EDMA_tag { - union EDMA_CR_tag { - uint32_t R; - struct { -#if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567 - uint32_t:14; - uint32_t CX:1; - uint32_t ECX:1; -#else - uint32_t:16; +#if (defined(MPC55XX_CHIP_FAMILY) && \ + (MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567)) + #define EDMA_HAS_CR_EBW 1 + #define EDMA_HAS_CR_CX_ECX 1 + #define EDMA_HAS_CR_EMLM_CLM_HALT_HOE 1 + #define EDMA_HAS_ESR_ECX 1 + #define EDMA_HAS_HRS 1 + #define EDMA_HAS_CPR_DPA 1 #endif - uint32_t GRP3PRI:2; - uint32_t GRP2PRI:2; - uint32_t GRP1PRI:2; - uint32_t GRP0PRI:2; -#if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567 - uint32_t EMLM:1; - uint32_t CLM:1; - uint32_t HALT:1; - uint32_t HOE:1; -#else - uint32_t:4; + +#if defined(LIBBSP_ARM_IMXRT_BSP_H) + #define EDMA_HAS_CR_CX_ECX 1 + #define EDMA_HAS_CR_EMLM_CLM_HALT_HOE 1 + #define EDMA_HAS_CR_ACTIVE 1 + #define EDMA_HAS_CR_VERSION 1 + #define EDMA_HAS_ESR_ECX 1 + #define EDMA_HAS_HRS 1 + #define EDMA_HAS_EARS 1 + #define EDMA_HAS_CPR_DPA 1 #endif - uint32_t ERGA:1; - uint32_t ERCA:1; - uint32_t EDBG:1; - uint32_t EBW:1; - } B; - } CR; /* Control Register */ - - union { - uint32_t R; - struct { - uint32_t VLD:1; -#if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567 - uint32_t:14; - uint32_t ECX:1; -#else - uint32_t:15; + +struct fsl_edma { + uint32_t CR; +#ifdef EDMA_HAS_CR_EBW + #define EDMA_CR_EBW (1 << 0) +#endif +#define EDMA_CR_EDBG (1 << 1) +#define EDMA_CR_ERCA (1 << 2) +#define EDMA_CR_ERGA (1 << 3) +#ifdef EDMA_HAS_CR_EMLM_CLM_HALT_HOE + #define EDMA_CR_HOE (1 << 4) + #define EDMA_CR_HALT (1 << 5) + #define EDMA_CR_CLM (1 << 6) + #define EDMA_CR_EMLM (1 << 7) +#endif +#define EDMA_CR_GRPxPRI_SHIFT(x) (8 + (x) * 2) +#define EDMA_CR_GRPxPRI_MASK(x) (0x3 << EDMA_CR_GRPxPRI_SHIFT(x)) +#define EDMA_CR_GRPxPRI(x,val) (((val) << EDMA_CR_GRPxPRI_SHIFT(x)) & EDMA_CR_GRPxPRI_MASK(x)) +#define EDMA_CR_GRPxPRI_GET(x,reg) (((reg) & EDMA_CR_GRPxPRI_MASK(x)) >> EDMA_CR_GRPxPRI_SHIFT(x)) +#ifdef EDMA_HAS_CR_CX_ECX + #define EDMA_CR_ECX (1 << 16) + #define EDMA_CR_CX (1 << 17) +#endif +#ifdef EDMA_HAS_CR_VERSION + #define EDMA_CR_VERSION_SHIFT (24) + #define EDMA_CR_VERSION_MASK (0x7F << EDMA_CR_VERSION_SHIFT) + #define EDMA_CR_VERSION(val) (((val) << EDMA_CR_VERSION_SHIFT) & EDMA_CR_VERSION_MASK) + #define EDMA_CR_VERSION_GET(reg) (((reg) & EDMA_CR_VERSION_MASK) >> EDMA_CR_VERSION_SHIFT) #endif - uint32_t GPE:1; - uint32_t CPE:1; - uint32_t ERRCHN:6; - uint32_t SAE:1; - uint32_t SOE:1; - uint32_t DAE:1; - uint32_t DOE:1; - uint32_t NCE:1; - uint32_t SGE:1; - uint32_t SBE:1; - uint32_t DBE:1; - } B; - } ESR; /* Error Status Register */ - - union { - uint32_t R; - struct { - uint32_t ERQ63:1; - uint32_t ERQ62:1; - uint32_t ERQ61:1; - uint32_t ERQ60:1; - uint32_t ERQ59:1; - uint32_t ERQ58:1; - uint32_t ERQ57:1; - uint32_t ERQ56:1; - uint32_t ERQ55:1; - uint32_t ERQ54:1; - uint32_t ERQ53:1; - uint32_t ERQ52:1; - uint32_t ERQ51:1; - uint32_t ERQ50:1; - uint32_t ERQ49:1; - uint32_t ERQ48:1; - uint32_t ERQ47:1; - uint32_t ERQ46:1; - uint32_t ERQ45:1; - uint32_t ERQ44:1; - uint32_t ERQ43:1; - uint32_t ERQ42:1; - uint32_t ERQ41:1; - uint32_t ERQ40:1; - uint32_t ERQ39:1; - uint32_t ERQ38:1; - uint32_t ERQ37:1; - uint32_t ERQ36:1; - uint32_t ERQ35:1; - uint32_t ERQ34:1; - uint32_t ERQ33:1; - uint32_t ERQ32:1; - } B; - } ERQRH; /* DMA Enable Request Register High */ - - union { - uint32_t R; - struct { - uint32_t ERQ31:1; - uint32_t ERQ30:1; - uint32_t ERQ29:1; - uint32_t ERQ28:1; - uint32_t ERQ27:1; - uint32_t ERQ26:1; - uint32_t ERQ25:1; - uint32_t ERQ24:1; - uint32_t ERQ23:1; - uint32_t ERQ22:1; - uint32_t ERQ21:1; - uint32_t ERQ20:1; - uint32_t ERQ19:1; - uint32_t ERQ18:1; - uint32_t ERQ17:1; - uint32_t ERQ16:1; - uint32_t ERQ15:1; - uint32_t ERQ14:1; - uint32_t ERQ13:1; - uint32_t ERQ12:1; - uint32_t ERQ11:1; - uint32_t ERQ10:1; - uint32_t ERQ09:1; - uint32_t ERQ08:1; - uint32_t ERQ07:1; - uint32_t ERQ06:1; - uint32_t ERQ05:1; - uint32_t ERQ04:1; - uint32_t ERQ03:1; - uint32_t ERQ02:1; - uint32_t ERQ01:1; - uint32_t ERQ00:1; - } B; - } ERQRL; /* DMA Enable Request Register Low */ - - union { - uint32_t R; - struct { - uint32_t EEI63:1; - uint32_t EEI62:1; - uint32_t EEI61:1; - uint32_t EEI60:1; - uint32_t EEI59:1; - uint32_t EEI58:1; - uint32_t EEI57:1; - uint32_t EEI56:1; - uint32_t EEI55:1; - uint32_t EEI54:1; - uint32_t EEI53:1; - uint32_t EEI52:1; - uint32_t EEI51:1; - uint32_t EEI50:1; - uint32_t EEI49:1; - uint32_t EEI48:1; - uint32_t EEI47:1; - uint32_t EEI46:1; - uint32_t EEI45:1; - uint32_t EEI44:1; - uint32_t EEI43:1; - uint32_t EEI42:1; - uint32_t EEI41:1; - uint32_t EEI40:1; - uint32_t EEI39:1; - uint32_t EEI38:1; - uint32_t EEI37:1; - uint32_t EEI36:1; - uint32_t EEI35:1; - uint32_t EEI34:1; - uint32_t EEI33:1; - uint32_t EEI32:1; - } B; - } EEIRH; /* DMA Enable Error Interrupt Register High */ - - union { - uint32_t R; - struct { - uint32_t EEI31:1; - uint32_t EEI30:1; - uint32_t EEI29:1; - uint32_t EEI28:1; - uint32_t EEI27:1; - uint32_t EEI26:1; - uint32_t EEI25:1; - uint32_t EEI24:1; - uint32_t EEI23:1; - uint32_t EEI22:1; - uint32_t EEI21:1; - uint32_t EEI20:1; - uint32_t EEI19:1; - uint32_t EEI18:1; - uint32_t EEI17:1; - uint32_t EEI16:1; - uint32_t EEI15:1; - uint32_t EEI14:1; - uint32_t EEI13:1; - uint32_t EEI12:1; - uint32_t EEI11:1; - uint32_t EEI10:1; - uint32_t EEI09:1; - uint32_t EEI08:1; - uint32_t EEI07:1; - uint32_t EEI06:1; - uint32_t EEI05:1; - uint32_t EEI04:1; - uint32_t EEI03:1; - uint32_t EEI02:1; - uint32_t EEI01:1; - uint32_t EEI00:1; - } B; - } EEIRL; /* DMA Enable Error Interrupt Register Low */ - - union { /* DMA Set Enable Request Register */ - uint8_t R; - struct { - uint8_t NOP:1; - uint8_t SERQ:7; - } B; - } SERQR; - - union { /* DMA Clear Enable Request Register */ - uint8_t R; - struct { - uint8_t NOP:1; - uint8_t CERQ:7; - } B; - } CERQR; - - union { /* DMA Set Enable Error Interrupt Register */ - uint8_t R; - struct { - uint8_t NOP:1; - uint8_t SEEI:7; - } B; - } SEEIR; - - union { /* DMA Clear Enable Error Interrupt Register */ - uint8_t R; - struct { - uint8_t NOP:1; - uint8_t CEEI:7; - } B; - } CEEIR; - - union { /* DMA Clear Interrupt Request Register */ - uint8_t R; - struct { - uint8_t NOP:1; - uint8_t CINT:7; - } B; - } CIRQR; - - union { /* DMA Clear error Register */ - uint8_t R; - struct { - uint8_t NOP:1; - uint8_t CERR:7; - } B; - } CER; - - union { /* Set Start Bit Register */ - uint8_t R; - struct { - uint8_t NOP:1; - uint8_t SSB:7; - } B; - } SSBR; - - union { /* Clear Done Status Bit Register */ - uint8_t R; - struct { - uint8_t NOP:1; - uint8_t CDSB:7; - } B; - } CDSBR; - - union { - uint32_t R; - struct { - uint32_t INT63:1; - uint32_t INT62:1; - uint32_t INT61:1; - uint32_t INT60:1; - uint32_t INT59:1; - uint32_t INT58:1; - uint32_t INT57:1; - uint32_t INT56:1; - uint32_t INT55:1; - uint32_t INT54:1; - uint32_t INT53:1; - uint32_t INT52:1; - uint32_t INT51:1; - uint32_t INT50:1; - uint32_t INT49:1; - uint32_t INT48:1; - uint32_t INT47:1; - uint32_t INT46:1; - uint32_t INT45:1; - uint32_t INT44:1; - uint32_t INT43:1; - uint32_t INT42:1; - uint32_t INT41:1; - uint32_t INT40:1; - uint32_t INT39:1; - uint32_t INT38:1; - uint32_t INT37:1; - uint32_t INT36:1; - uint32_t INT35:1; - uint32_t INT34:1; - uint32_t INT33:1; - uint32_t INT32:1; - } B; - } IRQRH; /* DMA Interrupt Request High */ - - union { - uint32_t R; - struct { - uint32_t INT31:1; - uint32_t INT30:1; - uint32_t INT29:1; - uint32_t INT28:1; - uint32_t INT27:1; - uint32_t INT26:1; - uint32_t INT25:1; - uint32_t INT24:1; - uint32_t INT23:1; - uint32_t INT22:1; - uint32_t INT21:1; - uint32_t INT20:1; - uint32_t INT19:1; - uint32_t INT18:1; - uint32_t INT17:1; - uint32_t INT16:1; - uint32_t INT15:1; - uint32_t INT14:1; - uint32_t INT13:1; - uint32_t INT12:1; - uint32_t INT11:1; - uint32_t INT10:1; - uint32_t INT09:1; - uint32_t INT08:1; - uint32_t INT07:1; - uint32_t INT06:1; - uint32_t INT05:1; - uint32_t INT04:1; - uint32_t INT03:1; - uint32_t INT02:1; - uint32_t INT01:1; - uint32_t INT00:1; - } B; - } IRQRL; /* DMA Interrupt Request Low */ - - union { - uint32_t R; - struct { - uint32_t ERR63:1; - uint32_t ERR62:1; - uint32_t ERR61:1; - uint32_t ERR60:1; - uint32_t ERR59:1; - uint32_t ERR58:1; - uint32_t ERR57:1; - uint32_t ERR56:1; - uint32_t ERR55:1; - uint32_t ERR54:1; - uint32_t ERR53:1; - uint32_t ERR52:1; - uint32_t ERR51:1; - uint32_t ERR50:1; - uint32_t ERR49:1; - uint32_t ERR48:1; - uint32_t ERR47:1; - uint32_t ERR46:1; - uint32_t ERR45:1; - uint32_t ERR44:1; - uint32_t ERR43:1; - uint32_t ERR42:1; - uint32_t ERR41:1; - uint32_t ERR40:1; - uint32_t ERR39:1; - uint32_t ERR38:1; - uint32_t ERR37:1; - uint32_t ERR36:1; - uint32_t ERR35:1; - uint32_t ERR34:1; - uint32_t ERR33:1; - uint32_t ERR32:1; - } B; - } ERH; /* DMA Error High */ - - union { - uint32_t R; - struct { - uint32_t ERR31:1; - uint32_t ERR30:1; - uint32_t ERR29:1; - uint32_t ERR28:1; - uint32_t ERR27:1; - uint32_t ERR26:1; - uint32_t ERR25:1; - uint32_t ERR24:1; - uint32_t ERR23:1; - uint32_t ERR22:1; - uint32_t ERR21:1; - uint32_t ERR20:1; - uint32_t ERR19:1; - uint32_t ERR18:1; - uint32_t ERR17:1; - uint32_t ERR16:1; - uint32_t ERR15:1; - uint32_t ERR14:1; - uint32_t ERR13:1; - uint32_t ERR12:1; - uint32_t ERR11:1; - uint32_t ERR10:1; - uint32_t ERR09:1; - uint32_t ERR08:1; - uint32_t ERR07:1; - uint32_t ERR06:1; - uint32_t ERR05:1; - uint32_t ERR04:1; - uint32_t ERR03:1; - uint32_t ERR02:1; - uint32_t ERR01:1; - uint32_t ERR00:1; - } B; - } ERL; /* DMA Error Low */ - -#if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567 - union { /* hardware request status high */ - uint32_t R; - struct { - uint32_t HRS63:1; - uint32_t HRS62:1; - uint32_t HRS61:1; - uint32_t HRS60:1; - uint32_t HRS59:1; - uint32_t HRS58:1; - uint32_t HRS57:1; - uint32_t HRS56:1; - uint32_t HRS55:1; - uint32_t HRS54:1; - uint32_t HRS53:1; - uint32_t HRS52:1; - uint32_t HRS51:1; - uint32_t HRS50:1; - uint32_t HRS49:1; - uint32_t HRS48:1; - uint32_t HRS47:1; - uint32_t HRS46:1; - uint32_t HRS45:1; - uint32_t HRS44:1; - uint32_t HRS43:1; - uint32_t HRS42:1; - uint32_t HRS41:1; - uint32_t HRS40:1; - uint32_t HRS39:1; - uint32_t HRS38:1; - uint32_t HRS37:1; - uint32_t HRS36:1; - uint32_t HRS35:1; - uint32_t HRS34:1; - uint32_t HRS33:1; - uint32_t HRS32:1; - } B; - } HRSH; - - union { /* hardware request status low */ - uint32_t R; - struct { - uint32_t HRS31:1; - uint32_t HRS30:1; - uint32_t HRS29:1; - uint32_t HRS28:1; - uint32_t HRS27:1; - uint32_t HRS26:1; - uint32_t HRS25:1; - uint32_t HRS24:1; - uint32_t HRS23:1; - uint32_t HRS22:1; - uint32_t HRS21:1; - uint32_t HRS20:1; - uint32_t HRS19:1; - uint32_t HRS18:1; - uint32_t HRS17:1; - uint32_t HRS16:1; - uint32_t HRS15:1; - uint32_t HRS14:1; - uint32_t HRS13:1; - uint32_t HRS12:1; - uint32_t HRS11:1; - uint32_t HRS10:1; - uint32_t HRS09:1; - uint32_t HRS08:1; - uint32_t HRS07:1; - uint32_t HRS06:1; - uint32_t HRS05:1; - uint32_t HRS04:1; - uint32_t HRS03:1; - uint32_t HRS02:1; - uint32_t HRS01:1; - uint32_t HRS00:1; - } B; - } HRSL; - - uint32_t eDMA_reserved0038[50]; /* 0x0038-0x00FF */ +#ifdef EDMA_HAS_CR_ACTIVE + #define EDMA_CR_ACTIVE (1 << 31) +#endif + + uint32_t ESR; +#define EDMA_ESR_DBE (1 << 0) +#define EDMA_ESR_SBE (1 << 1) +#define EDMA_ESR_SGE (1 << 2) +#define EDMA_ESR_NCE (1 << 3) +#define EDMA_ESR_DOE (1 << 4) +#define EDMA_ESR_DAE (1 << 5) +#define EDMA_ESR_SOE (1 << 6) +#define EDMA_ESR_SAE (1 << 7) +#define EDMA_ESR_ERRCHN_SHIFT (8) +#define EDMA_ESR_ERRCHN_MASK (0x3F << EDMA_ESR_ERRCHN_SHIFT) +#define EDMA_ESR_ERRCHN(val) (((val) << EDMA_ESR_ERRCHN_SHIFT) & EDMA_ESR_ERRCHN_MASK) +#define EDMA_ESR_ERRCHN_GET(reg) (((reg) & EDMA_ESR_ERRCHN_MASK) >> EDMA_ESR_ERRCHN_SHIFT) +#define EDMA_ESR_CPE (1 << 14) +#define EDMA_ESR_GPE (1 << 15) +#ifdef EDMA_HAS_ESR_ECX + #define EDMA_ESR_ECX (1 << 16) +#endif +#define EDMA_ESR_VLD (1 << 31) + + uint32_t ERRQH; +#define EDMA_ERRQH_ERRQ(x) (1 << ((x) - 32)) + + uint32_t ERRQL; +#define EDMA_ERRQL_ERRQ(x) (1 << (x)) + + uint32_t EEIH; +#define EDMA_EEIH_EEI(x) (1 << ((x) - 32)) + + uint32_t EEIL; +#define EDMA_EEIL_EEI(x) (1 << (x)) + +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ + uint8_t SERQR; + uint8_t CERQR; + uint8_t SEEIR; + uint8_t CEEIR; +#elif __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ + uint8_t CEEIR; + uint8_t SEEIR; + uint8_t CERQR; + uint8_t SERQR; +#endif +#define EDMA_SERQR_NOP (1 << 7) +#define EDMA_SERQR_SAER (1 << 6) +#define EDMA_SERQR_SERQ_SHIFT (0) +#define EDMA_SERQR_SERQ_MASK (0x1F << EDMA_CIRQR_SERQ_SHIFT) +#define EDMA_SERQR_SERQ(val) (((val) << EDMA_CIRQR_SERQ_SHIFT) & EDMA_CIRQR_SERQ_MASK) +#define EDMA_SERQR_SERQ_GET(reg) (((reg) & EDMA_CIRQR_SERQ_MASK) >> EDMA_CIRQR_SERQ_SHIFT) +#define EDMA_CERQR_NOP (1 << 7) +#define EDMA_CERQR_CAER (1 << 6) +#define EDMA_CERQR_CERQ_SHIFT (0) +#define EDMA_CERQR_CERQ_MASK (0x1F << EDMA_CIRQR_CERQ_SHIFT) +#define EDMA_CERQR_CERQ(val) (((val) << EDMA_CIRQR_CERQ_SHIFT) & EDMA_CIRQR_CERQ_MASK) +#define EDMA_CERQR_CERQ_GET(reg) (((reg) & EDMA_CIRQR_CERQ_MASK) >> EDMA_CIRQR_CERQ_SHIFT) +#define EDMA_SEEIR_NOP (1 << 7) +#define EDMA_SEEIR_SAEE (1 << 6) +#define EDMA_SEEIR_SEEI_SHIFT (0) +#define EDMA_SEEIR_SEEI_MASK (0x1F << EDMA_CIRQR_SEEI_SHIFT) +#define EDMA_SEEIR_SEEI(val) (((val) << EDMA_CIRQR_SEEI_SHIFT) & EDMA_CIRQR_SEEI_MASK) +#define EDMA_SEEIR_SEEI_GET(reg) (((reg) & EDMA_CIRQR_SEEI_MASK) >> EDMA_CIRQR_SEEI_SHIFT) +#define EDMA_CEEIR_NOP (1 << 7) +#define EDMA_CEEIR_CAEE (1 << 6) +#define EDMA_CEEIR_CEEI_SHIFT (0) +#define EDMA_CEEIR_CEEI_MASK (0x1F << EDMA_CIRQR_CEEI_SHIFT) +#define EDMA_CEEIR_CEEI(val) (((val) << EDMA_CIRQR_CEEI_SHIFT) & EDMA_CIRQR_CEEI_MASK) +#define EDMA_CEEIR_CEEI_GET(reg) (((reg) & EDMA_CIRQR_CEEI_MASK) >> EDMA_CIRQR_CEEI_SHIFT) + +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ + uint8_t CIRQR; + uint8_t CER; + uint8_t SSBR; + uint8_t CDSBR; +#elif __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ + uint8_t CDSBR; + uint8_t SSBR; + uint8_t CER; + uint8_t CIRQR; +#endif +#define EDMA_CIRQR_NOP (1 << 7) +#define EDMA_CIRQR_CAIR (1 << 6) +#define EDMA_CIRQR_CINT_SHIFT (0) +#define EDMA_CIRQR_CINT_MASK (0x1F << EDMA_CIRQR_CINT_SHIFT) +#define EDMA_CIRQR_CINT(val) (((val) << EDMA_CIRQR_CINT_SHIFT) & EDMA_CIRQR_CINT_MASK) +#define EDMA_CIRQR_CINT_GET(reg) (((reg) & EDMA_CIRQR_CINT_MASK) >> EDMA_CIRQR_CINT_SHIFT) +#define EDMA_CER_NOP (1 << 7) +#define EDMA_CER_CAEI (1 << 6) +#define EDMA_CER_CERR_SHIFT (0) +#define EDMA_CER_CERR_MASK (0x1F << EDMA_CIRQR_CERR_SHIFT) +#define EDMA_CER_CERR(val) (((val) << EDMA_CIRQR_CERR_SHIFT) & EDMA_CIRQR_CERR_MASK) +#define EDMA_CER_CERR_GET(reg) (((reg) & EDMA_CIRQR_CERR_MASK) >> EDMA_CIRQR_CERR_SHIFT) +#define EDMA_SSBR_NOP (1 << 7) +#define EDMA_SSBR_SAST (1 << 6) +#define EDMA_SSBR_SSB_SHIFT (0) +#define EDMA_SSBR_SSB_MASK (0x1F << EDMA_CIRQR_SSB_SHIFT) +#define EDMA_SSBR_SSB(val) (((val) << EDMA_CIRQR_SSB_SHIFT) & EDMA_CIRQR_SSB_MASK) +#define EDMA_SSBR_SSB_GET(reg) (((reg) & EDMA_CIRQR_SSB_MASK) >> EDMA_CIRQR_SSB_SHIFT) +#define EDMA_CDSBR_NOP (1 << 7) +#define EDMA_CDSBR_CADN (1 << 6) +#define EDMA_CDSBR_CDSB_SHIFT (0) +#define EDMA_CDSBR_CDSB_MASK (0x1F << EDMA_CIRQR_CDSB_SHIFT) +#define EDMA_CDSBR_CDSB(val) (((val) << EDMA_CIRQR_CDSB_SHIFT) & EDMA_CIRQR_CDSB_MASK) +#define EDMA_CDSBR_CDSB_GET(reg) (((reg) & EDMA_CIRQR_CDSB_MASK) >> EDMA_CIRQR_CDSB_SHIFT) + + uint32_t IRQH; +#define EDMA_IRQH_INT(x) (1 << ((x) - 32)) + + uint32_t IRQL; +#define EDMA_IRQL_INT(x) (1 << ((x))) + + uint32_t ERH; +#define EDMA_ERH_ERR(x) (1 << ((x) - 32)) + + uint32_t ERL; +#define EDMA_ERL_ERR(x) (1 << ((x))) + +#ifdef EDMA_HAS_HRS + uint32_t HRS; +#define EDMA_HRSH_HRS(x) (1 << ((x) - 32)) + + uint32_t HRSL; +#define EDMA_HRSL_HRS(x) (1 << ((x))) #else - uint32_t edma_reserved1[52]; + uint32_t reserved0030[2]; #endif - union { - uint8_t R; - struct { - uint8_t ECP:1; -#if MPC55XX_CHIP_FAMILY == 566 || MPC55XX_CHIP_FAMILY == 567 - uint8_t DPA:1; + uint32_t reserved0038[(0x44-0x38)/4]; + +#ifdef EDMA_HAS_EARS + uint32_t EARSL; +#define EDMA_EARSL_EDREQ(x) (1 << ((x))) /* iMXRT only */ #else - uint8_t:1; + uint32_t reserved0044; +#endif + + uint32_t reserved0048[(0x100-0x48)/4]; + + uint8_t CPR[64]; +#define EDMA_CPR_CHPRI_SHIFT (0) +#define EDMA_CPR_CHPRI_MASK (0xF << EDMA_CPR_CHPRI_SHIFT) +#define EDMA_CPR_CHPRI(val) (((val) << EDMA_CPR_CHPRI_SHIFT) & EDMA_CPR_CHPRI_MASK) +#define EDMA_CPR_CHPRI_GET(reg) (((reg) & EDMA_CPR_CHPRI_MASK) >> EDMA_CPR_CHPRI_SHIFT) +#define EDMA_CPR_GRPPRI_SHIFT (0) +#define EDMA_CPR_GRPPRI_MASK (0xF << EDMA_CPR_GRPPRI_SHIFT) +#define EDMA_CPR_GRPPRI(val) (((val) << EDMA_CPR_GRPPRI_SHIFT) & EDMA_CPR_GRPPRI_MASK) +#define EDMA_CPR_GRPPRI_GET(reg) (((reg) & EDMA_CPR_GRPPRI_MASK) >> EDMA_CPR_GRPPRI_SHIFT) +#ifdef EDMA_HAS_CPR_DPA + #define EDMA_CPR_DPA (1 << 6) #endif - uint8_t GRPPRI:2; - uint8_t CHPRI:4; - } B; - } CPR[64]; - - uint32_t edma_reserved2[944]; - -/****************************************************************************/ -/* DMA2 Transfer Control Descriptor */ -/****************************************************************************/ - struct tcd_t { - uint32_t SADDR; /* source address */ - - /* Source and destination fields */ - union tcd_SDF_tag { - uint32_t R; - struct { - uint16_t SMOD:5; /* source address modulo */ - uint16_t SSIZE:3; /* source transfer size */ - uint16_t DMOD:5; /* destination address modulo */ - uint16_t DSIZE:3; /* destination transfer size */ - int16_t SOFF; /* signed source address offset */ - } B; - } SDF; - - uint32_t NBYTES; /* inner (minor) byte count */ - - int32_t SLAST; /* last destination address adjustment, or - scatter/gather address (if e_sg = 1) */ - - uint32_t DADDR; /* destination address */ - - /* CITER and destination fields */ - union tcd_CDF_tag { - uint32_t R; - struct { - uint16_t CITERE_LINK:1; - uint16_t CITER:15; - int16_t DOFF; /* signed destination address offset */ - } B; - struct { - uint16_t CITERE_LINK:1; - uint16_t CITERLINKCH:6; - uint16_t CITER:9; - int16_t DOFF; - } B_ALT; - struct { - uint16_t CITER; - int16_t DOFF; - } B_NOLINK; - } CDF; - - int32_t DLAST_SGA; - - /* BITER and misc fields */ - union tcd_BMF_tag { - uint32_t R; - struct { - uint32_t BITERE_LINK:1; /* beginning ("major") iteration count */ - uint32_t BITER:15; - uint32_t BWC:2; /* bandwidth control */ - uint32_t MAJORLINKCH:6; /* enable channel-to-channel link */ - uint32_t DONE:1; /* channel done */ - uint32_t ACTIVE:1; /* channel active */ - uint32_t MAJORE_LINK:1; /* enable channel-to-channel link */ - uint32_t E_SG:1; /* enable scatter/gather descriptor */ - uint32_t D_REQ:1; /* disable ipd_req when done */ - uint32_t INT_HALF:1; /* interrupt on citer = (biter >> 1) */ - uint32_t INT_MAJ:1; /* interrupt on major loop completion */ - uint32_t START:1; /* explicit channel start */ - } B; - struct { - uint32_t BITERE_LINK:1; - uint32_t BITERLINKCH:6; - uint32_t BITER:9; - uint32_t BWC:2; - uint32_t MAJORLINKCH:6; - uint32_t DONE:1; - uint32_t ACTIVE:1; - uint32_t MAJORE_LINK:1; - uint32_t E_SG:1; - uint32_t D_REQ:1; - uint32_t INT_HALF:1; - uint32_t INT_MAJ:1; - uint32_t START:1; - } B_ALT; - struct { - uint16_t BITER; - uint16_t BWC:2; - uint16_t MAJORLINKCH:6; - uint16_t DONE:1; - uint16_t ACTIVE:1; - uint16_t MAJORE_LINK:1; - uint16_t E_SG:1; - uint16_t D_REQ:1; - uint16_t INT_HALF:1; - uint16_t INT_MAJ:1; - uint16_t START:1; - } B_NOLINK; - } BMF; - } TCD[64]; /* transfer_control_descriptor */ - }; +#define EDMA_CPR_ECP (1 << 7) + + uint32_t reserved0140[(0x1000-0x140)/4]; + + struct fsl_edma_tcd { + uint32_t SADDR; + uint32_t SDF; +#define EDMA_TCD_SDF_SMOD_SHIFT (27) +#define EDMA_TCD_SDF_SMOD_MASK (0x1F << EDMA_TCD_SDF_SMOD_SHIFT) +#define EDMA_TCD_SDF_SMOD(val) (((val) << EDMA_TCD_SDF_SMOD_SHIFT) & EDMA_TCD_SDF_SMOD_MASK) +#define EDMA_TCD_SDF_SMOD_GET(reg) (((reg) & EDMA_TCD_SDF_SMOD_MASK) >> EDMA_TCD_SDF_SMOD_SHIFT) +#define EDMA_TCD_SDF_SSIZE_SHIFT (24) +#define EDMA_TCD_SDF_SSIZE_MASK (0x7 << EDMA_TCD_SDF_SSIZE_SHIFT) +#define EDMA_TCD_SDF_SSIZE(val) (((val) << EDMA_TCD_SDF_SSIZE_SHIFT) & EDMA_TCD_SDF_SSIZE_MASK) +#define EDMA_TCD_SDF_SSIZE_GET(reg) (((reg) & EDMA_TCD_SDF_SSIZE_MASK) >> EDMA_TCD_SDF_SSIZE_SHIFT) +#define EDMA_TCD_SDF_SSIZE_8BIT EDMA_TCD_SDF_SSIZE(0) +#define EDMA_TCD_SDF_SSIZE_16BIT EDMA_TCD_SDF_SSIZE(1) +#define EDMA_TCD_SDF_SSIZE_32BIT EDMA_TCD_SDF_SSIZE(2) +#define EDMA_TCD_SDF_SSIZE_64BIT EDMA_TCD_SDF_SSIZE(3) +#define EDMA_TCD_SDF_SSIZE_32BYTE EDMA_TCD_SDF_SSIZE(5) +#define EDMA_TCD_SDF_DMOD_SHIFT (19) +#define EDMA_TCD_SDF_DMOD_MASK (0x1F << EDMA_TCD_SDF_DMOD_SHIFT) +#define EDMA_TCD_SDF_DMOD(val) (((val) << EDMA_TCD_SDF_DMOD_SHIFT) & EDMA_TCD_SDF_DMOD_MASK) +#define EDMA_TCD_SDF_DMOD_GET(reg) (((reg) & EDMA_TCD_SDF_DMOD_MASK) >> EDMA_TCD_SDF_DMOD_SHIFT) +#define EDMA_TCD_SDF_DSIZE_SHIFT (16) +#define EDMA_TCD_SDF_DSIZE_MASK (0x7 << EDMA_TCD_SDF_DSIZE_SHIFT) +#define EDMA_TCD_SDF_DSIZE(val) (((val) << EDMA_TCD_SDF_DSIZE_SHIFT) & EDMA_TCD_SDF_DSIZE_MASK) +#define EDMA_TCD_SDF_DSIZE_GET(reg) (((reg) & EDMA_TCD_SDF_DSIZE_MASK) >> EDMA_TCD_SDF_DSIZE_SHIFT) +#define EDMA_TCD_SDF_DSIZE_8BIT EDMA_TCD_SDF_DSIZE(0) +#define EDMA_TCD_SDF_DSIZE_16BIT EDMA_TCD_SDF_DSIZE(1) +#define EDMA_TCD_SDF_DSIZE_32BIT EDMA_TCD_SDF_DSIZE(2) +#define EDMA_TCD_SDF_DSIZE_64BIT EDMA_TCD_SDF_DSIZE(3) +#define EDMA_TCD_SDF_DSIZE_32BYTE EDMA_TCD_SDF_DSIZE(5) +#define EDMA_TCD_SDF_SOFF_SHIFT (0) +#define EDMA_TCD_SDF_SOFF_MASK (0xFFFF << EDMA_TCD_SDF_SOFF_SHIFT) +#define EDMA_TCD_SDF_SOFF(val) (((val) << EDMA_TCD_SDF_SOFF_SHIFT) & EDMA_TCD_SDF_SOFF_MASK) +#define EDMA_TCD_SDF_SOFF_GET(reg) (((reg) & EDMA_TCD_SDF_SOFF_MASK) >> EDMA_TCD_SDF_SOFF_SHIFT) + + uint32_t NBYTES; +#define EDMA_TCD_NBYTES_ALT_NBYTES_SHIFT (0) +#define EDMA_TCD_NBYTES_ALT_NBYTES_MASK (0x3FF << EDMA_TCD_NBYTES_ALT_NBYTES_SHIFT) +#define EDMA_TCD_NBYTES_ALT_NBYTES(val) (((val) << EDMA_TCD_NBYTES_ALT_NBYTES_SHIFT) & EDMA_TCD_NBYTES_ALT_NBYTES_MASK) +#define EDMA_TCD_NBYTES_ALT_MLOFF_SHIFT (10) +#define EDMA_TCD_NBYTES_ALT_MLOFF_MASK (0xFFFFF << EDMA_TCD_NBYTES_ALT_MLOFF_SHIFT) +#define EDMA_TCD_NBYTES_ALT_MLOFF(val) (((val) << EDMA_TCD_NBYTES_ALT_MLOFF_SHIFT) & EDMA_TCD_NBYTES_ALT_MLOFF_MASK) +#define EDMA_TCD_NBYTES_ALT_DMLOE (1 << 30) +#define EDMA_TCD_NBYTES_ALT_SMLOE (1 << 31) + int32_t SLAST; + uint32_t DADDR; + uint32_t CDF; +#define EDMA_TCD_CDF_CITERE_LINK (1 << 31) +#define EDMA_TCD_CDF_CITER_SHIFT (16) +#define EDMA_TCD_CDF_CITER_MASK (0x7FFF << EDMA_TCD_CDF_CITER_SHIFT) +#define EDMA_TCD_CDF_CITER(val) (((val) << EDMA_TCD_CDF_CITER_SHIFT) & EDMA_TCD_CDF_CITER_MASK) +#define EDMA_TCD_CDF_CITER_GET(reg) (((reg) & EDMA_TCD_CDF_CITER_MASK) >> EDMA_TCD_CDF_CITER_SHIFT) +#define EDMA_TCD_CDF_DOFF_SHIFT (0) +#define EDMA_TCD_CDF_DOFF_MASK (0xFFFF << EDMA_TCD_CDF_DOFF_SHIFT) +#define EDMA_TCD_CDF_DOFF(val) (((val) << EDMA_TCD_CDF_DOFF_SHIFT) & EDMA_TCD_CDF_DOFF_MASK) +#define EDMA_TCD_CDF_DOFF_GET(reg) (((reg) & EDMA_TCD_CDF_DOFF_MASK) >> EDMA_TCD_CDF_DOFF_SHIFT) + +#define EDMA_TCD_CDF_ALT_CITERLINKCH_SHIFT (25) +#define EDMA_TCD_CDF_ALT_CITERLINKCH_MASK (0x3F << EDMA_TCD_CDF_ALT_CITERLINKCH_SHIFT) +#define EDMA_TCD_CDF_ALT_CITERLINKCH(val) (((val) << EDMA_TCD_CDF_ALT_CITERLINKCH_SHIFT) & EDMA_TCD_CDF_ALT_CITERLINKCH_MASK) +#define EDMA_TCD_CDF_ALT_CITERLINKCH_GET(reg) (((reg) & EDMA_TCD_CDF_ALT_CITERLINKCH_MASK) >> EDMA_TCD_CDF_ALT_CITERLINKCH_SHIFT) +#define EDMA_TCD_CDF_ALT_CITER_SHIFT (16) +#define EDMA_TCD_CDF_ALT_CITER_MASK (0x1FF << EDMA_TCD_CDF_ALT_CITER_SHIFT) +#define EDMA_TCD_CDF_ALT_CITER(val) (((val) << EDMA_TCD_CDF_ALT_CITER_SHIFT) & EDMA_TCD_CDF_ALT_CITER_MASK) +#define EDMA_TCD_CDF_ALT_CITER_GET(reg) (((reg) & EDMA_TCD_CDF_ALT_CITER_MASK) >> EDMA_TCD_CDF_ALT_CITER_SHIFT) + +#define EDMA_TCD_CDF_NOLINK_CITER_SHIFT (16) +#define EDMA_TCD_CDF_NOLINK_CITER_MASK (0xFFFF << EDMA_TCD_CDF_NOLINK_CITER_SHIFT) +#define EDMA_TCD_CDF_NOLINK_CITER(val) (((val) << EDMA_TCD_CDF_NOLINK_CITER_SHIFT) & EDMA_TCD_CDF_NOLINK_CITER_MASK) +#define EDMA_TCD_CDF_NOLINK_CITER_GET(reg) (((reg) & EDMA_TCD_CDF_NOLINK_CITER_MASK) >> EDMA_TCD_CDF_NOLINK_CITER_SHIFT) + + int32_t DLAST_SGA; + uint32_t BMF; +#define EDMA_TCD_BMF_BITERE_LINK (1 << 31) +#define EDMA_TCD_BMF_BITER_SHIFT (16) +#define EDMA_TCD_BMF_BITER_MASK (0x7FFF << EDMA_TCD_BMF_BITER_SHIFT) +#define EDMA_TCD_BMF_BITER(val) (((val) << EDMA_TCD_BMF_BITER_SHIFT) & EDMA_TCD_BMF_BITER_MASK) +#define EDMA_TCD_BMF_BITER_GET(reg) (((reg) & EDMA_TCD_BMF_BITER_MASK) >> EDMA_TCD_BMF_BITER_SHIFT) +#define EDMA_TCD_BMF_BWC_SHIFT (14) +#define EDMA_TCD_BMF_BWC_MASK (0x3 << EDMA_TCD_BMF_BWC_SHIFT) +#define EDMA_TCD_BMF_BWC(val) (((val) << EDMA_TCD_BMF_BWC_SHIFT) & EDMA_TCD_BMF_BWC_MASK) +#define EDMA_TCD_BMF_BWC_GET(reg) (((reg) & EDMA_TCD_BMF_BWC_MASK) >> EDMA_TCD_BMF_BWC_SHIFT) +#define EDMA_TCD_BMF_MAJORLINKCH_SHIFT (8) +#define EDMA_TCD_BMF_MAJORLINKCH_MASK (0x3F << EDMA_TCD_BMF_MAJORLINKCH_SHIFT) +#define EDMA_TCD_BMF_MAJORLINKCH(val) (((val) << EDMA_TCD_BMF_MAJORLINKCH_SHIFT) & EDMA_TCD_BMF_MAJORLINKCH_MASK) +#define EDMA_TCD_BMF_MAJORLINKCH_GET(reg) (((reg) & EDMA_TCD_BMF_MAJORLINKCH_MASK) >> EDMA_TCD_BMF_MAJORLINKCH_SHIFT) +#define EDMA_TCD_BMF_DONE (1 << 7) +#define EDMA_TCD_BMF_ACTIVE (1 << 6) +#define EDMA_TCD_BMF_MAJORE_LINK (1 << 5) +#define EDMA_TCD_BMF_E_SG (1 << 4) +#define EDMA_TCD_BMF_D_REQ (1 << 3) +#define EDMA_TCD_BMF_INT_HALF (1 << 2) +#define EDMA_TCD_BMF_INT_MAJ (1 << 1) +#define EDMA_TCD_BMF_START (1 << 0) + +#define EDMA_TCD_BMF_ALT_BITERLINKCH_SHIFT (25) +#define EDMA_TCD_BMF_ALT_BITERLINKCH_MASK (0x3F << EDMA_TCD_BMF_ALT_BITERLINKCH_SHIFT) +#define EDMA_TCD_BMF_ALT_BITERLINKCH(val) (((val) << EDMA_TCD_BMF_ALT_BITERLINKCH_SHIFT) & EDMA_TCD_BMF_ALT_BITERLINKCH_MASK) +#define EDMA_TCD_BMF_ALT_BITERLINKCH_GET(reg) (((reg) & EDMA_TCD_BMF_ALT_BITERLINKCH_MASK) >> EDMA_TCD_BMF_ALT_BITERLINKCH_SHIFT) +#define EDMA_TCD_BMF_ALT_BITER_SHIFT (16) +#define EDMA_TCD_BMF_ALT_BITER_MASK (0x1FF << EDMA_TCD_BMF_ALT_BITER_SHIFT) +#define EDMA_TCD_BMF_ALT_BITER(val) (((val) << EDMA_TCD_BMF_ALT_BITER_SHIFT) & EDMA_TCD_BMF_ALT_BITER_MASK) +#define EDMA_TCD_BMF_ALT_BITER_GET(reg) (((reg) & EDMA_TCD_BMF_ALT_BITER_MASK) >> EDMA_TCD_BMF_ALT_BITER_SHIFT) + +#define EDMA_TCD_BMF_NOLINK_BITER_SHIFT (16) +#define EDMA_TCD_BMF_NOLINK_BITER_MASK (0xFFFF << EDMA_TCD_BMF_NOLINK_BITER_SHIFT) +#define EDMA_TCD_BMF_NOLINK_BITER(val) (((val) << EDMA_TCD_BMF_NOLINK_BITER_SHIFT) & EDMA_TCD_BMF_NOLINK_BITER_MASK) +#define EDMA_TCD_BMF_NOLINK_BITER_GET(reg) (((reg) & EDMA_TCD_BMF_NOLINK_BITER_MASK) >> EDMA_TCD_BMF_NOLINK_BITER_SHIFT) + + } TCD[64]; +}; #ifndef __cplusplus - static const struct tcd_t EDMA_TCD_DEFAULT = { - .SADDR = 0, - .SDF = { .R = 0 }, - .NBYTES = 0, - .SLAST = 0, - .DADDR = 0, - .CDF = { .R = 0 }, - .DLAST_SGA = 0, - .BMF = { .R = 0 } - }; +static const struct fsl_edma_tcd EDMA_TCD_DEFAULT = { + .SADDR = 0, + .SDF = 0, + .NBYTES = 0, + .SLAST = 0, + .DADDR = 0, + .CDF = 0, + .DLAST_SGA = 0, + .BMF = 0, +}; #endif /* __cplusplus */ #define EDMA_TCD_BITER_MASK 0x7fff @@ -707,4 +416,4 @@ extern "C" { } #endif /* __cplusplus */ -#endif /* LIBCPU_POWERPC_MPC55XX_REGS_EDMA_H */ +#endif /* LIBBSP_SHARED_FSL_REGS_EDMA_H */ |