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-rw-r--r--bsps/include/dev/irq/arm-gic-irq.h30
-rw-r--r--bsps/include/dev/irq/arm-gic-regs.h17
-rw-r--r--bsps/include/dev/irq/arm-gic-tm27.h65
-rw-r--r--bsps/include/dev/irq/arm-gic.h20
-rw-r--r--bsps/include/dev/irq/arm-gicv3.h15
5 files changed, 95 insertions, 52 deletions
diff --git a/bsps/include/dev/irq/arm-gic-irq.h b/bsps/include/dev/irq/arm-gic-irq.h
index 186ac2de7b..c3615a12a0 100644
--- a/bsps/include/dev/irq/arm-gic-irq.h
+++ b/bsps/include/dev/irq/arm-gic-irq.h
@@ -1,15 +1,16 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/**
- * @file
+ * @file
*
- * @ingroup arm_gic
+ * @ingroup DevIRQGIC
*
- * @brief ARM GIC IRQ
+ * @brief This header file provides interfaces of the ARM Generic Interrupt
+ * Controller (GIC) support.
*/
/*
- * Copyright (c) 2013, 2019 embedded brains GmbH. All rights reserved.
+ * Copyright (C) 2013, 2019 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -38,12 +39,17 @@
#include <bsp.h>
#include <dev/irq/arm-gic.h>
-#include <rtems/score/processormask.h>
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
+/**
+ * @addtogroup DevIRQGIC
+ *
+ * @{
+ */
+
#define ARM_GIC_IRQ_SGI_0 0
#define ARM_GIC_IRQ_SGI_1 1
#define ARM_GIC_IRQ_SGI_2 2
@@ -85,16 +91,6 @@ rtems_status_code arm_gic_irq_get_group(
gic_group *group
);
-rtems_status_code bsp_interrupt_set_affinity(
- rtems_vector_number vector,
- const Processor_mask *affinity
-);
-
-rtems_status_code bsp_interrupt_get_affinity(
- rtems_vector_number vector,
- Processor_mask *affinity
-);
-
void arm_gic_trigger_sgi(rtems_vector_number vector, uint32_t targets);
static inline rtems_status_code arm_gic_irq_generate_software_irq(
@@ -113,9 +109,13 @@ static inline rtems_status_code arm_gic_irq_generate_software_irq(
return sc;
}
+#ifdef RTEMS_SMP
uint32_t arm_gic_irq_processor_count(void);
void arm_gic_irq_initialize_secondary_cpu(void);
+#endif
+
+/** @} */
#ifdef __cplusplus
}
diff --git a/bsps/include/dev/irq/arm-gic-regs.h b/bsps/include/dev/irq/arm-gic-regs.h
index e21f15d016..c03a7a7a07 100644
--- a/bsps/include/dev/irq/arm-gic-regs.h
+++ b/bsps/include/dev/irq/arm-gic-regs.h
@@ -1,15 +1,16 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/**
- * @file
+ * @file
*
- * @ingroup arm_gic
+ * @ingroup DevIRQGIC
*
- * @brief ARM GIC Register definitions
+ * @brief This header file provides interfaces of the ARM Generic Interrupt
+ * Controller (GIC) memory-mapped registers.
*/
/*
- * Copyright (c) 2013, 2019 embedded brains GmbH. All rights reserved.
+ * Copyright (C) 2013, 2019 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -38,6 +39,12 @@
#include <bsp/utility.h>
+/**
+ * @addtogroup DevIRQGIC
+ *
+ * @{
+ */
+
typedef struct {
uint32_t iccicr;
#define GIC_CPUIF_ICCICR_CBPR BSP_BIT32(4)
@@ -225,4 +232,6 @@ typedef struct {
uint32_t icspigrpmodr[64];
} gic_sgi_ppi;
+/** @} */
+
#endif /* LIBBSP_ARM_SHARED_ARM_GIC_REGS_H */
diff --git a/bsps/include/dev/irq/arm-gic-tm27.h b/bsps/include/dev/irq/arm-gic-tm27.h
index 466f40acaf..70e76c7603 100644
--- a/bsps/include/dev/irq/arm-gic-tm27.h
+++ b/bsps/include/dev/irq/arm-gic-tm27.h
@@ -1,15 +1,16 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/**
- * @file
+ * @file
*
- * @ingroup arm_gic
+ * @ingroup DevIRQGIC
*
- * @brief ARM GIC TM27 Support
+ * @brief This header file provides the TM27 support for the ARM Generic
+ * Interrupt Controller (GIC).
*/
/*
- * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved.
+ * Copyright (C) 2013, 2014 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -40,11 +41,11 @@
#ifndef LIBBSP_ARM_SHARED_ARM_GIC_TM27_H
#define LIBBSP_ARM_SHARED_ARM_GIC_TM27_H
-#include <assert.h>
-
#include <bsp.h>
#include <bsp/irq.h>
+#include <rtems/score/assert.h>
+
#define MUST_WAIT_FOR_INTERRUPT 1
#ifndef ARM_GIC_TM27_IRQ_LOW
@@ -55,50 +56,66 @@
#define ARM_GIC_TM27_IRQ_HIGH ARM_GIC_IRQ_SGI_13
#endif
+#define TM27_INTERRUPT_VECTOR_DEFAULT ARM_GIC_TM27_IRQ_LOW
+
#define ARM_GIC_TM27_PRIO_LOW 0x80
#define ARM_GIC_TM27_PRIO_HIGH 0x00
-static inline void Install_tm27_vector(void (*handler)(rtems_vector_number))
+static inline void Install_tm27_vector( rtems_interrupt_handler handler )
{
- rtems_status_code sc = rtems_interrupt_handler_install(
+ static rtems_interrupt_entry entry_low;
+ static rtems_interrupt_entry entry_high;
+ rtems_status_code sc;
+
+ rtems_interrupt_entry_initialize(
+ &entry_low,
+ handler,
+ NULL,
+ "tm27 low"
+ );
+ sc = rtems_interrupt_entry_install(
ARM_GIC_TM27_IRQ_LOW,
- "tm27 low",
RTEMS_INTERRUPT_UNIQUE,
- (rtems_interrupt_handler) handler,
- NULL
+ &entry_low
);
- assert(sc == RTEMS_SUCCESSFUL);
+ _Assert_Unused_variable_equals( sc, RTEMS_SUCCESSFUL );
sc = arm_gic_irq_set_priority(
ARM_GIC_TM27_IRQ_LOW,
ARM_GIC_TM27_PRIO_LOW
);
- assert(sc == RTEMS_SUCCESSFUL);
+ _Assert_Unused_variable_equals( sc, RTEMS_SUCCESSFUL );
- sc = rtems_interrupt_handler_install(
+ rtems_interrupt_entry_initialize(
+ &entry_high,
+ handler,
+ NULL,
+ "tm27 high"
+ );
+ sc = rtems_interrupt_entry_install(
ARM_GIC_TM27_IRQ_HIGH,
- "tm27 high",
RTEMS_INTERRUPT_UNIQUE,
- (rtems_interrupt_handler) handler,
- NULL
+ &entry_high
);
- assert(sc == RTEMS_SUCCESSFUL);
+ _Assert_Unused_variable_equals( sc, RTEMS_SUCCESSFUL );
sc = arm_gic_irq_set_priority(
ARM_GIC_TM27_IRQ_HIGH,
ARM_GIC_TM27_PRIO_HIGH
);
- assert(sc == RTEMS_SUCCESSFUL);
+ _Assert_Unused_variable_equals( sc, RTEMS_SUCCESSFUL );
}
static inline void Cause_tm27_intr(void)
{
- rtems_status_code sc = arm_gic_irq_generate_software_irq(
+ rtems_status_code sc;
+
+ sc = arm_gic_irq_generate_software_irq(
ARM_GIC_TM27_IRQ_LOW,
1U << _SMP_Get_current_processor()
);
- assert(sc == RTEMS_SUCCESSFUL);
+ _Assert_Unused_variable_equals( sc, RTEMS_SUCCESSFUL );
}
static inline void Clear_tm27_intr(void)
@@ -108,11 +125,13 @@ static inline void Clear_tm27_intr(void)
static inline void Lower_tm27_intr(void)
{
- rtems_status_code sc = arm_gic_irq_generate_software_irq(
+ rtems_status_code sc;
+
+ sc = arm_gic_irq_generate_software_irq(
ARM_GIC_TM27_IRQ_HIGH,
1U << _SMP_Get_current_processor()
);
- assert(sc == RTEMS_SUCCESSFUL);
+ _Assert_Unused_variable_equals( sc, RTEMS_SUCCESSFUL );
}
#endif /* LIBBSP_ARM_SHARED_ARM_GIC_TM27_H */
diff --git a/bsps/include/dev/irq/arm-gic.h b/bsps/include/dev/irq/arm-gic.h
index 21986043c4..4e418de68f 100644
--- a/bsps/include/dev/irq/arm-gic.h
+++ b/bsps/include/dev/irq/arm-gic.h
@@ -1,15 +1,16 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/**
- * @file
+ * @file
*
- * @ingroup arm_gic
+ * @ingroup DevIRQGIC
*
- * @brief ARM GIC Support
+ * @brief This header file provides interfaces of the ARM Generic Interrupt
+ * Controller (GIC) support.
*/
/*
- * Copyright (c) 2013, 2019 embedded brains GmbH. All rights reserved.
+ * Copyright (C) 2013, 2019 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -45,11 +46,14 @@ extern "C" {
#endif /* __cplusplus */
/**
- * @defgroup arm_gic ARM GIC
+ * @defgroup DevIRQGIC ARM Generic Interrupt Controller (GIC) Support
*
- * @ingroup RTEMSBSPsARMShared
+ * @ingroup RTEMSImplClassicIntr
*
- * @brief ARM_GIC Support Package
+ * @brief This group contains the Interrupt Manager implementation parts
+ * specific to the ARM Generic Interrupt Controller.
+ *
+ * @{
*/
#define GIC_ID_TO_ONE_BIT_REG_INDEX(id) ((id) >> 5)
@@ -248,6 +252,8 @@ static inline void gic_id_set_handling_model(
dist->icdicfr[i] = icdicfr;
}
+/* @} */
+
#ifdef __cplusplus
}
#endif /* __cplusplus */
diff --git a/bsps/include/dev/irq/arm-gicv3.h b/bsps/include/dev/irq/arm-gicv3.h
index a716ffbca5..8829c32384 100644
--- a/bsps/include/dev/irq/arm-gicv3.h
+++ b/bsps/include/dev/irq/arm-gicv3.h
@@ -3,13 +3,14 @@
/**
* @file
*
- * @ingroup arm_gic
+ * @ingroup DevIRQGIC
*
- * @brief This header file contains interfaces to access an Arm GICv3.
+ * @brief This header file provides interfaces of the ARM Generic Interrupt
+ * Controller (GIC) support specific to the GICv3.
*/
/*
- * Copyright (C) 2022 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2022 embedded brains GmbH & Co. KG
* Copyright (C) 2019 On-Line Applications Research Corporation (OAR)
*
* Redistribution and use in source and binary forms, with or without
@@ -44,6 +45,12 @@
extern "C" {
#endif
+/**
+ * @addtogroup DevIRQGIC
+ *
+ * @{
+ */
+
#define PRIORITY_DEFAULT 127
#define MPIDR_AFFINITY2(val) BSP_FLD64(val, 16, 23)
@@ -387,6 +394,8 @@ static inline void gicv3_get_attributes(
}
}
+/** @} */
+
#ifdef __cplusplus
}
#endif
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-29 18:41:16 +0000