4 files changed, 5 insertions, 28 deletions
diff --git a/c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h b/bsps/arm/shared/cache/cache-cp15.c
index 2ff1ae1f03..17de99eaec 100644
--- a/c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h
+++ b/bsps/arm/shared/cache/cache-cp15.c
@@ -20,11 +20,8 @@
  * http://www.rtems.org/license/LICENSE.
  */
 
-#ifndef LIBBSP_ARM_ARMV467AR_BASIC_CACHE_H
-#define LIBBSP_ARM_ARMV467AR_BASIC_CACHE_H
-
 #include <libcpu/arm-cp15.h>
-#include "../include/arm-cache-l1.h"
+#include "cache-cp15.h"
 
 #define CPU_DATA_CACHE_ALIGNMENT 32
 #define CPU_INSTRUCTION_CACHE_ALIGNMENT 32
@@ -184,4 +181,4 @@ static inline void _CPU_cache_disable_instruction(void)
   rtems_interrupt_local_enable(level);
 }
 
-#endif /* LIBBSP_ARM_ARMV467AR_BASIC_CACHE_H */
+#include "../../shared/cache/cacheimpl.h"
diff --git a/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h b/bsps/arm/shared/cache/cache-cp15.h
index 9caa2685bc..ff01384f4b 100644
--- a/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h
+++ b/bsps/arm/shared/cache/cache-cp15.h
@@ -1,6 +1,4 @@
 /**
- * @file arm-cache-l1.h
- *
  * @ingroup arm_shared
  *
  * @brief Level 1 Cache definitions and functions.
diff --git a/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h b/bsps/arm/shared/cache/cache-l2c-310.c
index 81b34a62fa..6869d205a8 100644
--- a/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
+++ b/bsps/arm/shared/cache/cache-l2c-310.c
@@ -1,6 +1,4 @@
 /**
- * @file cache_.h
- *
  * @ingroup L2C-310_cache
  *
  * @brief Cache definitions and functions.
@@ -53,9 +51,6 @@
  * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03
  */
 
-#ifndef LIBBSP_ARM_SHARED_L2C_310_CACHE_H
-#define LIBBSP_ARM_SHARED_L2C_310_CACHE_H
-
 #include <assert.h>
 #include <bsp.h>
 #include <bsp/fatal.h>
@@ -63,11 +58,8 @@
 #include <rtems/rtems/intr.h>
 #include <bsp/arm-release-id.h>
 #include <bsp/arm-errata.h>
-#include "../include/arm-cache-l1.h"
 
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
+#include "cache-cp15.h"
 
 /* These two defines also ensure that the rtems_cache_* functions have bodies */
 #define CPU_DATA_CACHE_ALIGNMENT ARM_CACHE_L1_CPU_DATA_ALIGNMENT
@@ -1338,11 +1330,4 @@ _CPU_cache_get_instruction_cache_size( const uint32_t level )
   return size;
 }
 
-
-/** @} */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* LIBBSP_ARM_SHARED_L2C_310_CACHE_H */
+#include "../../shared/cache/cacheimpl.h"
diff --git a/c/src/lib/libbsp/arm/shared/armv7m/include/cache_.h b/bsps/arm/shared/cache/cache-v7m.c
index ef94c11734..a73112f12a 100644
--- a/c/src/lib/libbsp/arm/shared/armv7m/include/cache_.h
+++ b/bsps/arm/shared/cache/cache-v7m.c
@@ -12,9 +12,6 @@
  * http://www.rtems.org/license/LICENSE.
  */
 
-#ifndef LIBBSP_ARM_ARMV7M_CACHE__H
-#define LIBBSP_ARM_ARMV7M_CACHE__H
-
 #include <rtems.h>
 #include <chip.h>
 
@@ -141,4 +138,4 @@ static inline void _CPU_cache_disable_instruction(void)
   rtems_interrupt_enable(level);
 }
 
-#endif /* LIBBSP_ARM_ARMV7M_CACHE__H */
+#include "../../shared/cache/cacheimpl.h"