diff options
Diffstat (limited to 'bsps/arm')
| -rw-r--r-- | bsps/arm/atsam/spi/atsam_spi_bus.c | 614 | ||||
| -rw-r--r-- | bsps/arm/atsam/spi/atsam_spi_init.c | 110 | ||||
| -rw-r--r-- | bsps/arm/atsam/spi/sc16is752.c | 85 | ||||
| -rw-r--r-- | bsps/arm/imx/spi/imx-ecspi.c | 449 | ||||
| -rw-r--r-- | bsps/arm/raspberrypi/spi/spi.c | 657 |
5 files changed, 1915 insertions, 0 deletions
diff --git a/bsps/arm/atsam/spi/atsam_spi_bus.c b/bsps/arm/atsam/spi/atsam_spi_bus.c new file mode 100644 index 0000000000..35f44f525d --- /dev/null +++ b/bsps/arm/atsam/spi/atsam_spi_bus.c @@ -0,0 +1,614 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2015, Atmel Corporation */ +/* Copyright (c) 2016, embedded brains GmbH */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#include <bsp/atsam-clock-config.h> +#include <bsp/atsam-spi.h> +#include <bsp/iocopy.h> + +#include <dev/spi/spi.h> + +#include <string.h> + +#define MAX_SPI_FREQUENCY 50000000 + +#define DMA_NR_DESC_PER_DIR 3 +#define DMA_DESC_ALLIGNMENT 4 + +#define DMA_BUF_RX 0 +#define DMA_BUF_TX 1 +#define DMA_BUF_DIRS 2 + +struct atsam_spi_xdma_buf { + LinkedListDescriporView0 desc[DMA_NR_DESC_PER_DIR]; + uint8_t leadbuf[CPU_CACHE_LINE_BYTES]; + uint8_t trailbuf[CPU_CACHE_LINE_BYTES]; +}; + +typedef struct { + spi_bus base; + bool msg_cs_change; + const spi_ioc_transfer *msg_current; + const spi_ioc_transfer *msg_next; + uint32_t msg_todo; + int msg_error; + rtems_id msg_task; + Spid spi; + uint32_t dma_tx_channel; + uint32_t dma_rx_channel; + struct atsam_spi_xdma_buf *dma_bufs; + size_t leadbuf_rx_buffered_len; + size_t trailbuf_rx_buffered_len; + int transfer_in_progress; + bool chip_select_active; + bool chip_select_decode; +} atsam_spi_bus; + +static void atsam_spi_wakeup_task(atsam_spi_bus *bus) +{ + rtems_status_code sc; + + sc = rtems_event_transient_send(bus->msg_task); + assert(sc == RTEMS_SUCCESSFUL); +} + +static uint8_t atsam_calculate_dlybcs(uint16_t delay_in_us) +{ + return ( + (BOARD_MCK / delay_in_us) < 0xFF) ? + (BOARD_MCK / delay_in_us) : 0xFF; +} + +static void atsam_set_phase_and_polarity(uint32_t mode, uint32_t *csr) +{ + uint32_t mode_mask = mode & SPI_MODE_3; + + switch(mode_mask) { + case SPI_MODE_0: + *csr |= SPI_CSR_NCPHA; + break; + case SPI_MODE_1: + break; + case SPI_MODE_2: + *csr |= SPI_CSR_NCPHA; + *csr |= SPI_CSR_CPOL; + break; + case SPI_MODE_3: + *csr |= SPI_CSR_CPOL; + break; + } + *csr |= SPI_CSR_CSAAT; +} + +static void atsam_configure_spi(atsam_spi_bus *bus) +{ + uint8_t delay_cs; + uint32_t csr = 0; + uint32_t mode = 0; + uint32_t cs = bus->base.cs; + + delay_cs = atsam_calculate_dlybcs(bus->base.delay_usecs); + + mode |= SPI_MR_DLYBCS(delay_cs); + mode |= SPI_MR_MSTR; + mode |= SPI_MR_MODFDIS; + if (bus->chip_select_decode) { + mode |= SPI_MR_PCS(bus->base.cs); + mode |= SPI_MR_PCSDEC; + cs /= 4; + } else { + mode |= SPI_PCS(bus->base.cs); + } + + SPID_Configure( + &bus->spi, + bus->spi.pSpiHw, + bus->spi.spiId, + mode, + &XDMAD_Instance + ); + + csr = + SPI_DLYBCT(1000, BOARD_MCK) | + SPI_DLYBS(1000, BOARD_MCK) | + SPI_SCBR(bus->base.speed_hz, BOARD_MCK) | + SPI_CSR_BITS(bus->base.bits_per_word - 8); + + atsam_set_phase_and_polarity(bus->base.mode, &csr); + + SPI_ConfigureNPCS(bus->spi.pSpiHw, cs, csr); +} + +static void atsam_spi_check_alignment_and_set_up_dma_descriptors( + atsam_spi_bus *bus, + struct atsam_spi_xdma_buf *buf, + const uint8_t *start, + size_t len, + bool tx +) +{ + LinkedListDescriporView0 *curdesc = buf->desc; + size_t misaligned_begin; + size_t misaligned_end; + size_t len_main; + const uint8_t *start_main; + const uint8_t *start_trail; + + /* Check alignments. */ + if (len < CPU_CACHE_LINE_BYTES) { + misaligned_begin = len; + misaligned_end = 0; + len_main = 0; + } else { + misaligned_begin = ((uint32_t) start) % CPU_CACHE_LINE_BYTES; + misaligned_end = (((uint32_t) start) + len) % CPU_CACHE_LINE_BYTES; + len_main = len - misaligned_begin - misaligned_end; + } + start_main = start + misaligned_begin; + start_trail = start_main + len_main; + + /* Store length for copying data back. */ + if (!tx) { + bus->leadbuf_rx_buffered_len = misaligned_begin; + bus->trailbuf_rx_buffered_len = misaligned_end; + } + + /* Handle misalignment on begin. */ + if (misaligned_begin != 0) { + if (tx) { + atsam_copy_to_io(buf->leadbuf, start, misaligned_begin); + } + curdesc->mbr_nda = (uint32_t) (&curdesc[1]); + curdesc->mbr_ta = (uint32_t) buf->leadbuf; + curdesc->mbr_ubc = misaligned_begin; + } + + /* Main part */ + if (len_main > 0) { + curdesc->mbr_ubc |= tx ? XDMA_UBC_NSEN_UPDATED : XDMA_UBC_NDEN_UPDATED; + curdesc->mbr_ubc |= XDMA_UBC_NVIEW_NDV0; + curdesc->mbr_ubc |= XDMA_UBC_NDE_FETCH_EN; + ++curdesc; + + curdesc->mbr_nda = (uint32_t) (&curdesc[1]); + curdesc->mbr_ta = (uint32_t) start_main; + curdesc->mbr_ubc = len_main; + if (tx) { + rtems_cache_flush_multiple_data_lines(start_main, len_main); + } else { + rtems_cache_invalidate_multiple_data_lines(start_main, len_main); + } + } + + /* Handle misalignment on end */ + if (misaligned_end != 0) { + curdesc->mbr_ubc |= tx ? XDMA_UBC_NSEN_UPDATED : XDMA_UBC_NDEN_UPDATED; + curdesc->mbr_ubc |= XDMA_UBC_NVIEW_NDV0; + curdesc->mbr_ubc |= XDMA_UBC_NDE_FETCH_EN; + ++curdesc; + + if (tx) { + atsam_copy_to_io(buf->trailbuf, start_trail, misaligned_end); + } + curdesc->mbr_nda = 0; + curdesc->mbr_ta = (uint32_t) buf->trailbuf; + curdesc->mbr_ubc = misaligned_end; + curdesc->mbr_ubc |= XDMA_UBC_NDE_FETCH_DIS; + } +} + +static void atsam_spi_copy_back_rx_after_dma_transfer( + atsam_spi_bus *bus +) +{ + if (bus->leadbuf_rx_buffered_len != 0) { + atsam_copy_from_io( + bus->msg_current->rx_buf, + bus->dma_bufs[DMA_BUF_RX].leadbuf, + bus->leadbuf_rx_buffered_len + ); + } + if (bus->trailbuf_rx_buffered_len != 0) { + atsam_copy_from_io( + bus->msg_current->rx_buf + bus->msg_current->len - + bus->trailbuf_rx_buffered_len, + bus->dma_bufs[DMA_BUF_RX].trailbuf, + bus->trailbuf_rx_buffered_len + ); + } +} + +static void atsam_spi_start_dma_transfer( + atsam_spi_bus *bus, + const spi_ioc_transfer *msg +) +{ + Xdmac *pXdmac = XDMAC; + size_t i; + + atsam_spi_check_alignment_and_set_up_dma_descriptors( + bus, + &bus->dma_bufs[DMA_BUF_RX], + msg->rx_buf, + msg->len, + false + ); + atsam_spi_check_alignment_and_set_up_dma_descriptors( + bus, + &bus->dma_bufs[DMA_BUF_TX], + msg->tx_buf, + msg->len, + true + ); + + XDMAC_SetDescriptorAddr( + pXdmac, + bus->dma_rx_channel, + (uint32_t) bus->dma_bufs[DMA_BUF_RX].desc, + 0 + ); + XDMAC_SetDescriptorControl( + pXdmac, + bus->dma_rx_channel, + XDMAC_CNDC_NDVIEW_NDV0 | + XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED | + XDMAC_CNDC_NDE_DSCR_FETCH_EN + ); + XDMAC_SetDescriptorAddr( + pXdmac, + bus->dma_tx_channel, + (uint32_t) bus->dma_bufs[DMA_BUF_TX].desc, + 0 + ); + XDMAC_SetDescriptorControl( + pXdmac, + bus->dma_tx_channel, + XDMAC_CNDC_NDVIEW_NDV0 | + XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED | + XDMAC_CNDC_NDE_DSCR_FETCH_EN + ); + + XDMAC_StartTransfer(pXdmac, bus->dma_rx_channel); + XDMAC_StartTransfer(pXdmac, bus->dma_tx_channel); +} + +static void atsam_spi_do_transfer( + atsam_spi_bus *bus, + const spi_ioc_transfer *msg +) +{ + if (!bus->chip_select_active){ + Spi *pSpiHw = bus->spi.pSpiHw; + + bus->chip_select_active = true; + + if (bus->chip_select_decode) { + pSpiHw->SPI_MR = (pSpiHw->SPI_MR & ~SPI_MR_PCS_Msk) | SPI_MR_PCS(msg->cs); + } else { + SPI_ChipSelect(pSpiHw, 1 << msg->cs); + } + SPI_Enable(pSpiHw); + } + + atsam_spi_start_dma_transfer(bus, msg); +} + +static int atsam_check_configure_spi(atsam_spi_bus *bus, const spi_ioc_transfer *msg) +{ + if ( + msg->mode != bus->base.mode + || msg->speed_hz != bus->base.speed_hz + || msg->bits_per_word != bus->base.bits_per_word + || msg->cs != bus->base.cs + || msg->delay_usecs != bus->base.delay_usecs + ) { + if ( + msg->bits_per_word < 8 + || msg->bits_per_word > 16 + || msg->mode > 3 + || msg->speed_hz > bus->base.max_speed_hz + ) { + return -EINVAL; + } + + bus->base.mode = msg->mode; + bus->base.speed_hz = msg->speed_hz; + bus->base.bits_per_word = msg->bits_per_word; + bus->base.cs = msg->cs; + bus->base.delay_usecs = msg->delay_usecs; + atsam_configure_spi(bus); + } + + return 0; +} + +static void atsam_spi_setup_transfer(atsam_spi_bus *bus) +{ + uint32_t msg_todo = bus->msg_todo; + + bus->transfer_in_progress = 2; + + if (bus->msg_cs_change) { + bus->chip_select_active = false; + SPI_ReleaseCS(bus->spi.pSpiHw); + SPI_Disable(bus->spi.pSpiHw); + } + + if (msg_todo > 0) { + const spi_ioc_transfer *msg = bus->msg_next; + int error; + + bus->msg_cs_change = msg->cs_change; + bus->msg_next = msg + 1; + bus->msg_current = msg; + bus->msg_todo = msg_todo - 1; + + error = atsam_check_configure_spi(bus, msg); + if (error == 0) { + atsam_spi_do_transfer(bus, msg); + } else { + bus->msg_error = error; + atsam_spi_wakeup_task(bus); + } + } else { + atsam_spi_wakeup_task(bus); + } +} + +static void atsam_spi_dma_callback(uint32_t channel, void *arg) +{ + atsam_spi_bus *bus = (atsam_spi_bus *)arg; + + --bus->transfer_in_progress; + + if (bus->transfer_in_progress == 0) { + atsam_spi_copy_back_rx_after_dma_transfer(bus); + atsam_spi_setup_transfer(bus); + } +} + +static int atsam_spi_transfer( + spi_bus *base, + const spi_ioc_transfer *msgs, + uint32_t msg_count +) +{ + rtems_status_code sc; + atsam_spi_bus *bus = (atsam_spi_bus *)base; + + bus->msg_cs_change = false; + bus->msg_next = &msgs[0]; + bus->msg_current = NULL; + bus->msg_todo = msg_count; + bus->msg_error = 0; + bus->msg_task = rtems_task_self(); + atsam_spi_setup_transfer(bus); + sc = rtems_event_transient_receive(RTEMS_WAIT, RTEMS_NO_TIMEOUT); + assert(sc == RTEMS_SUCCESSFUL); + return bus->msg_error; +} + + +static void atsam_spi_destroy(spi_bus *base) +{ + atsam_spi_bus *bus = (atsam_spi_bus *)base; + eXdmadRC rc; + + rc = XDMAD_SetCallback( + bus->spi.pXdmad, + bus->dma_rx_channel, + XDMAD_DoNothingCallback, + NULL + ); + assert(rc == XDMAD_OK); + + rc = XDMAD_SetCallback( + bus->spi.pXdmad, + bus->dma_tx_channel, + XDMAD_DoNothingCallback, + NULL + ); + assert(rc == XDMAD_OK); + + XDMAD_FreeChannel(bus->spi.pXdmad, bus->dma_rx_channel); + XDMAD_FreeChannel(bus->spi.pXdmad, bus->dma_tx_channel); + + SPI_Disable(bus->spi.pSpiHw); + PMC_DisablePeripheral(bus->spi.spiId); + + rtems_cache_coherent_free(bus->dma_bufs); + + spi_bus_destroy_and_free(&bus->base); +} + +static int atsam_spi_setup(spi_bus *base) +{ + atsam_spi_bus *bus = (atsam_spi_bus *)base; + + if ( + bus->base.speed_hz > MAX_SPI_FREQUENCY || + bus->base.bits_per_word < 8 || + bus->base.bits_per_word > 16 + ) { + return -EINVAL; + } + atsam_configure_spi(bus); + return 0; +} + +static void atsam_spi_init_xdma(atsam_spi_bus *bus) +{ + sXdmadCfg cfg; + uint32_t xdmaInt; + uint8_t channel; + eXdmadRC rc; + uint32_t xdma_cndc; + + bus->dma_bufs = rtems_cache_coherent_allocate( + DMA_BUF_DIRS * sizeof(*(bus->dma_bufs)), + DMA_DESC_ALLIGNMENT, + 0 + ); + assert(bus->dma_bufs != NULL); + + bus->dma_tx_channel = XDMAD_AllocateChannel( + bus->spi.pXdmad, + XDMAD_TRANSFER_MEMORY, + bus->spi.spiId + ); + assert(bus->dma_tx_channel != XDMAD_ALLOC_FAILED); + + bus->dma_rx_channel = XDMAD_AllocateChannel( + bus->spi.pXdmad, + bus->spi.spiId, + XDMAD_TRANSFER_MEMORY + ); + assert(bus->dma_rx_channel != XDMAD_ALLOC_FAILED); + + rc = XDMAD_SetCallback( + bus->spi.pXdmad, + bus->dma_rx_channel, + atsam_spi_dma_callback, + bus + ); + assert(rc == XDMAD_OK); + + rc = XDMAD_SetCallback( + bus->spi.pXdmad, + bus->dma_tx_channel, + atsam_spi_dma_callback, + bus + ); + assert(rc == XDMAD_OK); + + rc = XDMAD_PrepareChannel(bus->spi.pXdmad, bus->dma_rx_channel); + assert(rc == XDMAD_OK); + + rc = XDMAD_PrepareChannel(bus->spi.pXdmad, bus->dma_tx_channel); + assert(rc == XDMAD_OK); + + /* Put all relevant interrupts on */ + xdmaInt = ( + XDMAC_CIE_BIE | + XDMAC_CIE_DIE | + XDMAC_CIE_FIE | + XDMAC_CIE_RBIE | + XDMAC_CIE_WBIE | + XDMAC_CIE_ROIE); + + /* Setup RX */ + memset(&cfg, 0, sizeof(cfg)); + channel = XDMAIF_Get_ChannelNumber(bus->spi.spiId, XDMAD_TRANSFER_RX); + cfg.mbr_sa = (uint32_t)&bus->spi.pSpiHw->SPI_RDR; + cfg.mbr_cfg = + XDMAC_CC_TYPE_PER_TRAN | + XDMAC_CC_MBSIZE_SINGLE | + XDMAC_CC_DSYNC_PER2MEM | + XDMAC_CC_CSIZE_CHK_1 | + XDMAC_CC_DWIDTH_BYTE | + XDMAC_CC_SIF_AHB_IF1 | + XDMAC_CC_DIF_AHB_IF1 | + XDMAC_CC_SAM_FIXED_AM | + XDMAC_CC_DAM_INCREMENTED_AM | + XDMAC_CC_PERID(channel); + xdma_cndc = XDMAC_CNDC_NDVIEW_NDV0 | + XDMAC_CNDC_NDE_DSCR_FETCH_EN | + XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED | + XDMAC_CNDC_NDSUP_SRC_PARAMS_UNCHANGED; + rc = XDMAD_ConfigureTransfer( + bus->spi.pXdmad, + bus->dma_rx_channel, + &cfg, + xdma_cndc, + (uint32_t) bus->dma_bufs[DMA_BUF_RX].desc, + xdmaInt + ); + assert(rc == XDMAD_OK); + + /* Setup TX */ + memset(&cfg, 0, sizeof(cfg)); + channel = XDMAIF_Get_ChannelNumber(bus->spi.spiId, XDMAD_TRANSFER_TX); + cfg.mbr_da = (uint32_t)&bus->spi.pSpiHw->SPI_TDR; + cfg.mbr_cfg = + XDMAC_CC_TYPE_PER_TRAN | + XDMAC_CC_MBSIZE_SINGLE | + XDMAC_CC_DSYNC_MEM2PER | + XDMAC_CC_CSIZE_CHK_1 | + XDMAC_CC_DWIDTH_BYTE | + XDMAC_CC_SIF_AHB_IF1 | + XDMAC_CC_DIF_AHB_IF1 | + XDMAC_CC_SAM_INCREMENTED_AM | + XDMAC_CC_DAM_FIXED_AM | + XDMAC_CC_PERID(channel); + xdma_cndc = XDMAC_CNDC_NDVIEW_NDV0 | + XDMAC_CNDC_NDE_DSCR_FETCH_EN | + XDMAC_CNDC_NDDUP_DST_PARAMS_UNCHANGED | + XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED; + rc = XDMAD_ConfigureTransfer( + bus->spi.pXdmad, + bus->dma_tx_channel, + &cfg, + xdma_cndc, + (uint32_t) bus->dma_bufs[DMA_BUF_TX].desc, + xdmaInt + ); + assert(rc == XDMAD_OK); +} + +int spi_bus_register_atsam( + const char *bus_path, + const atsam_spi_config *config +) +{ + atsam_spi_bus *bus; + + bus = (atsam_spi_bus *) spi_bus_alloc_and_init(sizeof(*bus)); + if (bus == NULL) { + return -1; + } + + bus->base.transfer = atsam_spi_transfer; + bus->base.destroy = atsam_spi_destroy; + bus->base.setup = atsam_spi_setup; + bus->base.max_speed_hz = MAX_SPI_FREQUENCY; + bus->base.bits_per_word = 8; + bus->base.speed_hz = bus->base.max_speed_hz; + bus->base.delay_usecs = 1; + bus->base.cs = 1; + bus->spi.spiId = config->spi_peripheral_id; + bus->spi.pSpiHw = config->spi_regs; + bus->chip_select_decode = config->chip_select_decode; + + PIO_Configure(config->pins, config->pin_count); + PMC_EnablePeripheral(config->spi_peripheral_id); + atsam_configure_spi(bus); + atsam_spi_init_xdma(bus); + + return spi_bus_register(&bus->base, bus_path); +} diff --git a/bsps/arm/atsam/spi/atsam_spi_init.c b/bsps/arm/atsam/spi/atsam_spi_init.c new file mode 100644 index 0000000000..ca18f8ec35 --- /dev/null +++ b/bsps/arm/atsam/spi/atsam_spi_init.c @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2016 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include <bsp/atsam-spi.h> +#include <bsp/spi.h> + +/** SPI0 MISO pin */ +#define PIN_SPI0_MISO {PIO_PD20B_SPI0_MISO, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} +/** SPI0 MOSI pin */ +#define PIN_SPI0_MOSI {PIO_PD21B_SPI0_MOSI, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} +/** SPI0 CS0 pin */ +#define PIN_SPI0_NPCS0 {PIO_PB2D_SPI0_NPCS0, PIOB, ID_PIOB, PIO_PERIPH_D, PIO_DEFAULT} +/** SPI0 CS1_1 pin */ +#define PIN_SPI0_NPCS1_1 {PIO_PA31A_SPI0_NPCS1, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/** SPI0 CS1_2 pin */ +#define PIN_SPI0_NPCS1_2 {PIO_PD25B_SPI0_NPCS1, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} +/** SPI0 CS2 pin */ +#define PIN_SPI0_NPCS2 {PIO_PD12C_SPI0_NPCS2, PIOD, ID_PIOD, PIO_PERIPH_C, PIO_DEFAULT} +/** SPI0 CS3 pin */ +#define PIN_SPI0_NPCS3 {PIO_PD27B_SPI0_NPCS3, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} +/** SPI0 Clock pin */ +#define PIN_SPI0_CLOCK {PIO_PD22B_SPI0_SPCK, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} + +/** SPI1 MISO pin */ +#define PIN_SPI1_MISO {PIO_PC26C_SPI1_MISO, PIOC, ID_PIOC, PIO_PERIPH_C, PIO_DEFAULT} +/** SPI1 MOSI pin */ +#define PIN_SPI1_MOSI {PIO_PC27C_SPI1_MOSI, PIOC, ID_PIOC, PIO_PERIPH_C, PIO_DEFAULT} +/** SPI1 CS0 pin */ +#define PIN_SPI1_NPCS0 {PIO_PC25C_SPI1_NPCS0, PIOC, ID_PIOC, PIO_PERIPH_C, PIO_DEFAULT} +/** SPI1 CS1_1 pin */ +#define PIN_SPI1_NPCS1_1 {PIO_PC28C_SPI1_NPCS1, PIOC, ID_PIOC, PIO_PERIPH_C, PIO_DEFAULT} +/** SPI1 CS1_2 pin */ +#define PIN_SPI1_NPCS1_2 {PIO_PD0C_SPI1_NPCS1, PIOD, ID_PIOD, PIO_PERIPH_C, PIO_DEFAULT} +/** SPI1 CS2_1 pin */ +#define PIN_SPI1_NPCS2_1 {PIO_PC29C_SPI1_NPCS2, PIOC, ID_PIOC, PIO_PERIPH_C, PIO_DEFAULT} +/** SPI1 CS2_2 pin */ +#define PIN_SPI1_NPCS2_2 {PIO_PD1C_SPI1_NPCS2, PIOD, ID_PIOD, PIO_PERIPH_C, PIO_DEFAULT} +/** SPI1 CS3_1 pin */ +#define PIN_SPI1_NPCS3_1 {PIO_PC30C_SPI1_NPCS3, PIOC, ID_PIOC, PIO_PERIPH_C, PIO_DEFAULT} +/** SPI1 CS3_2 pin */ +#define PIN_SPI1_NPCS3_2 {PIO_PD2C_SPI1_NPCS3, PIOD, ID_PIOD, PIO_PERIPH_C, PIO_DEFAULT} +/** SPI1 Clock pin */ +#define PIN_SPI1_CLOCK {PIO_PC24C_SPI1_SPCK, PIOC, ID_PIOC, PIO_PERIPH_C, PIO_DEFAULT} + +int atsam_register_spi_0(void) +{ + static const Pin pins[] = { + PIN_SPI0_MISO, + PIN_SPI0_MOSI, + PIN_SPI0_NPCS0, + PIN_SPI0_NPCS1_1, + PIN_SPI0_NPCS1_2, + PIN_SPI0_NPCS2, + PIN_SPI0_NPCS3, + PIN_SPI0_CLOCK + }; + + static const atsam_spi_config config = { + .spi_peripheral_id = ID_SPI0, + .spi_regs = SPI0, + .pins = pins, + .pin_count = RTEMS_ARRAY_SIZE(pins), + .chip_select_decode = false + }; + + return spi_bus_register_atsam( + ATSAM_SPI_0_BUS_PATH, + &config + ); +} + +int atsam_register_spi_1(void) +{ + static const Pin pins[] = { + PIN_SPI1_MISO, + PIN_SPI1_MOSI, + PIN_SPI1_NPCS0, + PIN_SPI1_NPCS1_1, + PIN_SPI1_NPCS1_2, + PIN_SPI1_NPCS2_1, + PIN_SPI1_NPCS2_2, + PIN_SPI1_NPCS3_1, + PIN_SPI1_NPCS3_2, + PIN_SPI1_CLOCK + }; + + static const atsam_spi_config config = { + .spi_peripheral_id = ID_SPI1, + .spi_regs = SPI1, + .pins = pins, + .pin_count = RTEMS_ARRAY_SIZE(pins), + .chip_select_decode = false + }; + + return spi_bus_register_atsam( + ATSAM_SPI_1_BUS_PATH, + &config + ); +} diff --git a/bsps/arm/atsam/spi/sc16is752.c b/bsps/arm/atsam/spi/sc16is752.c new file mode 100644 index 0000000000..b17f9ffc14 --- /dev/null +++ b/bsps/arm/atsam/spi/sc16is752.c @@ -0,0 +1,85 @@ + +/* + * Copyright (c) 2016 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include <bsp/sc16is752.h> + +#include <rtems/irq-extension.h> + +static void atsam_sc16i752_interrupt(void *arg) +{ + atsam_sc16is752_spi_context *ctx = arg; + + sc16is752_interrupt_handler(&ctx->base.base); + + /* Interrupt Status Register shall be read to clear the interrupt flag */ + ctx->irq_pin.pio->PIO_ISR; +} + +static bool atsam_sc16is752_install_interrupt(sc16is752_context *base) +{ + atsam_sc16is752_spi_context *ctx = (atsam_sc16is752_spi_context *)base; + rtems_status_code sc; + + PIO_Configure(&ctx->irq_pin, 1); + PIO_EnableIt(&ctx->irq_pin); + + sc = rtems_interrupt_server_handler_install( + RTEMS_ID_NONE, + ctx->irq_pin.id, + "Test", + RTEMS_INTERRUPT_SHARED, + atsam_sc16i752_interrupt, + ctx + ); + + return sc == RTEMS_SUCCESSFUL; +} + +static void atsam_sc16is752_remove_interrupt(sc16is752_context *base) +{ + atsam_sc16is752_spi_context *ctx = (atsam_sc16is752_spi_context *)base; + rtems_status_code sc; + + sc = rtems_interrupt_server_handler_remove( + RTEMS_ID_NONE, + ctx->irq_pin.id, + atsam_sc16i752_interrupt, + ctx + ); + assert(sc == RTEMS_SUCCESSFUL); +} + +int atsam_sc16is752_spi_create( + atsam_sc16is752_spi_context *ctx, + const char *device_path, + sc16is752_mode mode, + uint32_t input_frequency, + const char *spi_path, + uint8_t spi_chip_select, + uint32_t spi_speed_hz, + const Pin *irq_pin +) +{ + ctx->base.base.mode = mode; + ctx->base.base.input_frequency = input_frequency; + ctx->base.base.install_irq = atsam_sc16is752_install_interrupt; + ctx->base.base.remove_irq = atsam_sc16is752_remove_interrupt; + ctx->base.spi_path = spi_path; + ctx->base.cs = spi_chip_select; + ctx->base.speed_hz = spi_speed_hz; + ctx->irq_pin = *irq_pin; + + return sc16is752_spi_create(&ctx->base, device_path); +} diff --git a/bsps/arm/imx/spi/imx-ecspi.c b/bsps/arm/imx/spi/imx-ecspi.c new file mode 100644 index 0000000000..9a232c53e9 --- /dev/null +++ b/bsps/arm/imx/spi/imx-ecspi.c @@ -0,0 +1,449 @@ +/* + * Copyright (c) 2017 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include <bsp.h> +#include <bsp/fdt.h> +#include <libfdt.h> +#include <arm/freescale/imx/imx_ccmvar.h> +#include <arm/freescale/imx/imx_ecspireg.h> +#include <dev/spi/spi.h> +#include <rtems/irq-extension.h> +#include <sys/param.h> +#include <sys/endian.h> + +#define IMX_ECSPI_FIFO_SIZE 64 + +typedef struct imx_ecspi_bus imx_ecspi_bus; + +struct imx_ecspi_bus { + spi_bus base; + volatile imx_ecspi *regs; + uint32_t conreg; + uint32_t speed_hz; + uint32_t mode; + uint8_t bits_per_word; + uint8_t cs; + uint32_t msg_todo; + const spi_ioc_transfer *msg; + uint32_t todo; + uint32_t in_transfer; + uint8_t *rx_buf; + const uint8_t *tx_buf; + void (*push)(imx_ecspi_bus *, volatile imx_ecspi *); + void (*pop)(imx_ecspi_bus *, volatile imx_ecspi *); + rtems_id task_id; + rtems_vector_number irq; +}; + +static bool imx_ecspi_is_rx_fifo_not_empty(volatile imx_ecspi *regs) +{ + return (regs->statreg & IMX_ECSPI_RR) != 0; +} + +static void imx_ecspi_reset(volatile imx_ecspi *regs) +{ + while (imx_ecspi_is_rx_fifo_not_empty(regs)) { + regs->rxdata; + } +} + +static void imx_ecspi_done(imx_ecspi_bus *bus) +{ + rtems_event_transient_send(bus->task_id); +} + +#define IMC_ECSPI_PUSH(type) \ +static void imx_ecspi_push_##type(imx_ecspi_bus *bus, volatile imx_ecspi *regs) \ +{ \ + type val = 0; \ + if (bus->tx_buf != NULL) { \ + val = *(type *)bus->tx_buf; \ + bus->tx_buf += sizeof(type); \ + } \ + bus->todo -= sizeof(type); \ + regs->txdata = val; \ +} + +#define IMX_ECSPI_POP(type) \ +static void imx_ecspi_pop_##type(imx_ecspi_bus *bus, volatile imx_ecspi *regs) \ +{ \ + uint32_t val = regs->rxdata; \ + if (bus->rx_buf != NULL) { \ + *(type *)bus->rx_buf = val; \ + bus->rx_buf += sizeof(type); \ + } \ +} + +IMC_ECSPI_PUSH(uint8_t) +IMX_ECSPI_POP(uint8_t) +IMC_ECSPI_PUSH(uint16_t) +IMX_ECSPI_POP(uint16_t) +IMC_ECSPI_PUSH(uint32_t) +IMX_ECSPI_POP(uint32_t) + +static void imx_ecspi_push_uint32_t_swap( + imx_ecspi_bus *bus, + volatile imx_ecspi *regs +) +{ + uint32_t val = 0; + + if (bus->tx_buf != NULL) { + val = bswap32(*(uint32_t *)bus->tx_buf); + bus->tx_buf += sizeof(uint32_t); + } + + bus->todo -= sizeof(uint32_t); + regs->txdata = val; +} + +static void imx_ecspi_pop_uint32_t_swap( + imx_ecspi_bus *bus, + volatile imx_ecspi *regs +) +{ + uint32_t val = regs->rxdata; + + if (bus->rx_buf != NULL) { + *(uint32_t *)bus->rx_buf = bswap32(val); + bus->rx_buf += sizeof(uint32_t); + } +} + +static void imx_ecspi_push(imx_ecspi_bus *bus, volatile imx_ecspi *regs) +{ + while (bus->todo > 0 && bus->in_transfer < IMX_ECSPI_FIFO_SIZE) { + (*bus->push)(bus, regs); + ++bus->in_transfer; + } +} + +static uint32_t imx_ecspi_conreg_divider(imx_ecspi_bus *bus, uint32_t speed_hz) +{ + uint32_t post; + uint32_t pre; + uint32_t clk_in; + + clk_in = bus->base.max_speed_hz; + + if (clk_in > speed_hz) { + post = fls((int) clk_in) - fls((int) speed_hz); + + if (clk_in > (speed_hz << post)) { + ++post; + } + + /* We have 2^4 == 16, use the pre-divider for this factor */ + post = MAX(4, post) - 4; + + if (post <= 0xf) { + pre = howmany(clk_in, speed_hz << post) - 1; + } else { + post = 0xf; + pre = 0xf; + } + } else { + post = 0; + pre = 0; + } + + return IMX_ECSPI_CONREG_POST_DIVIDER(post) + | IMX_ECSPI_CONREG_PRE_DIVIDER(pre); +} + +static void imx_ecspi_config( + imx_ecspi_bus *bus, + volatile imx_ecspi *regs, + uint32_t speed_hz, + uint8_t bits_per_word, + uint32_t mode, + uint8_t cs +) +{ + uint32_t conreg; + uint32_t testreg; + uint32_t configreg; + uint32_t cs_bit; + + conreg = IMX_ECSPI_CONREG_CHANNEL_MODE(0xf) + | IMX_ECSPI_CONREG_SMC | IMX_ECSPI_CONREG_EN; + testreg = regs->testreg; + configreg = regs->configreg; + cs_bit = 1U << cs; + + conreg |= imx_ecspi_conreg_divider(bus, speed_hz); + conreg |= IMX_ECSPI_CONREG_CHANNEL_SELECT(cs); + + configreg |= IMX_ECSPI_CONFIGREG_SS_CTL(cs_bit); + + if ((mode & SPI_CPHA) != 0) { + configreg |= IMX_ECSPI_CONFIGREG_SCLK_PHA(cs_bit); + } else { + configreg &= ~IMX_ECSPI_CONFIGREG_SCLK_PHA(cs_bit); + } + + if ((mode & SPI_CPOL) != 0) { + configreg |= IMX_ECSPI_CONFIGREG_SCLK_POL(cs_bit); + configreg |= IMX_ECSPI_CONFIGREG_SCLK_CTL(cs_bit); + } else { + configreg &= ~IMX_ECSPI_CONFIGREG_SCLK_POL(cs_bit); + configreg &= ~IMX_ECSPI_CONFIGREG_SCLK_CTL(cs_bit); + } + + if ((mode & SPI_CS_HIGH) != 0) { + configreg |= IMX_ECSPI_CONFIGREG_SS_POL(cs_bit); + } else { + configreg &= ~IMX_ECSPI_CONFIGREG_SS_POL(cs_bit); + } + + if ((mode & SPI_LOOP) != 0) { + testreg |= IMX_ECSPI_TESTREG_LBC; + } else { + testreg &= ~IMX_ECSPI_TESTREG_LBC; + } + + regs->conreg = conreg; + regs->testreg = testreg; + regs->configreg = configreg; + + bus->conreg = conreg; + bus->speed_hz = speed_hz; + bus->bits_per_word = bits_per_word; + bus->mode = mode; + bus->cs = cs; + + /* FIXME: Clock change delay */ +} + +static void imx_ecspi_set_push_pop( + imx_ecspi_bus *bus, + uint32_t len, + uint8_t bits_per_word +) +{ + uint32_t conreg; + + conreg = bus->conreg; + + if (len % 4 == 0 && len <= IMX_ECSPI_FIFO_SIZE) { + conreg |= IMX_ECSPI_CONREG_BURST_LENGTH((len * 8) - 1); + + bus->push = imx_ecspi_push_uint32_t_swap; + bus->pop = imx_ecspi_pop_uint32_t_swap; + } else { + conreg |= IMX_ECSPI_CONREG_BURST_LENGTH(bits_per_word - 1); + + if (bits_per_word <= 8) { + bus->push = imx_ecspi_push_uint8_t; + bus->pop = imx_ecspi_pop_uint8_t; + } else if (bits_per_word <= 16) { + bus->push = imx_ecspi_push_uint16_t; + bus->pop = imx_ecspi_pop_uint16_t; + } else { + bus->push = imx_ecspi_push_uint32_t; + bus->pop = imx_ecspi_pop_uint32_t; + } + } + + bus->regs->conreg = conreg; +} + +static void imx_ecspi_next_msg(imx_ecspi_bus *bus, volatile imx_ecspi *regs) +{ + if (bus->msg_todo > 0) { + const spi_ioc_transfer *msg; + + msg = bus->msg; + + if ( + msg->speed_hz != bus->speed_hz + || msg->bits_per_word != bus->bits_per_word + || msg->mode != bus->mode + || msg->cs != bus->cs + ) { + imx_ecspi_config( + bus, + regs, + msg->speed_hz, + msg->bits_per_word, + msg->mode, + msg->cs + ); + } + + bus->todo = msg->len; + bus->rx_buf = msg->rx_buf; + bus->tx_buf = msg->tx_buf; + imx_ecspi_set_push_pop(bus, msg->len, msg->bits_per_word); + imx_ecspi_push(bus, regs); + regs->intreg = IMX_ECSPI_TE; + } else { + regs->intreg = 0; + imx_ecspi_done(bus); + } +} + +static void imx_ecspi_interrupt(void *arg) +{ + imx_ecspi_bus *bus; + volatile imx_ecspi *regs; + + bus = arg; + regs = bus->regs; + + while (imx_ecspi_is_rx_fifo_not_empty(regs)) { + (*bus->pop)(bus, regs); + --bus->in_transfer; + } + + if (bus->todo > 0) { + imx_ecspi_push(bus, regs); + } else if (bus->in_transfer > 0) { + regs->intreg = IMX_ECSPI_RR; + } else { + --bus->msg_todo; + ++bus->msg; + imx_ecspi_next_msg(bus, regs); + } +} + +static int imx_ecspi_transfer( + spi_bus *base, + const spi_ioc_transfer *msgs, + uint32_t n +) +{ + imx_ecspi_bus *bus; + + bus = (imx_ecspi_bus *) base; + + bus->msg_todo = n; + bus->msg = &msgs[0]; + bus->task_id = rtems_task_self(); + + imx_ecspi_next_msg(bus, bus->regs); + rtems_event_transient_receive(RTEMS_WAIT, RTEMS_NO_TIMEOUT); + return 0; +} + +static void imx_ecspi_destroy(spi_bus *base) +{ + imx_ecspi_bus *bus; + + bus = (imx_ecspi_bus *) base; + rtems_interrupt_handler_remove(bus->irq, imx_ecspi_interrupt, bus); + spi_bus_destroy_and_free(&bus->base); +} + +static int imx_ecspi_init(imx_ecspi_bus *bus, const void *fdt, int node) +{ + rtems_status_code sc; + int len; + const uint32_t *val; + + imx_ecspi_config( + bus, + bus->regs, + bus->base.max_speed_hz, + 8, + 0, + 0 + ); + imx_ecspi_reset(bus->regs); + + sc = rtems_interrupt_handler_install( + bus->irq, + "ECSPI", + RTEMS_INTERRUPT_UNIQUE, + imx_ecspi_interrupt, + bus + ); + if (sc != RTEMS_SUCCESSFUL) { + return EAGAIN; + } + + val = fdt_getprop(fdt, node, "pinctrl-0", &len); + if (len == 4) { + imx_iomux_configure_pins(fdt, fdt32_to_cpu(val[0])); + } + + return 0; +} + +static int imx_ecspi_setup(spi_bus *base) +{ + imx_ecspi_bus *bus; + + bus = (imx_ecspi_bus *) base; + + if ( + bus->base.speed_hz > imx_ccm_ipg_hz() + || bus->base.bits_per_word > 32 + ) { + return -EINVAL; + } + + imx_ecspi_config( + bus, + bus->regs, + bus->base.speed_hz, + bus->base.bits_per_word, + bus->base.mode, + bus->base.cs + ); + return 0; +} + +int spi_bus_register_imx(const char *bus_path, const char *alias_or_path) +{ + const void *fdt; + const char *path; + int node; + imx_ecspi_bus *bus; + int eno; + + fdt = bsp_fdt_get(); + path = fdt_get_alias(fdt, alias_or_path); + + if (path == NULL) { + path = alias_or_path; + } + + node = fdt_path_offset(fdt, path); + if (node < 0) { + rtems_set_errno_and_return_minus_one(ENXIO); + } + + bus = (imx_ecspi_bus *) spi_bus_alloc_and_init(sizeof(*bus)); + if (bus == NULL){ + return -1; + } + + bus->base.max_speed_hz = imx_ccm_ipg_hz(); + bus->base.delay_usecs = 1; + bus->regs = imx_get_reg_of_node(fdt, node); + bus->irq = imx_get_irq_of_node(fdt, node, 0); + + eno = imx_ecspi_init(bus, fdt, node); + if (eno != 0) { + (*bus->base.destroy)(&bus->base); + rtems_set_errno_and_return_minus_one(eno); + } + + bus->base.transfer = imx_ecspi_transfer; + bus->base.destroy = imx_ecspi_destroy; + bus->base.setup = imx_ecspi_setup; + + return spi_bus_register(&bus->base, bus_path); +} diff --git a/bsps/arm/raspberrypi/spi/spi.c b/bsps/arm/raspberrypi/spi/spi.c new file mode 100644 index 0000000000..ae77f6272d --- /dev/null +++ b/bsps/arm/raspberrypi/spi/spi.c @@ -0,0 +1,657 @@ +/** + * @file spi.c + * + * @ingroup raspberrypi_spi + * + * @brief Support for the SPI bus on the Raspberry Pi GPIO P1 header (model A/B) + * and GPIO J8 header on model B+. + */ + +/* + * Copyright (c) 2014-2015 Andre Marques <andre.lousa.marques at gmail.com> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +/* + * STATUS: + * - Bi-directional mode untested + * - Write-only devices not supported + */ + +#include <bsp.h> +#include <bsp/raspberrypi.h> +#include <bsp/gpio.h> +#include <bsp/rpi-gpio.h> +#include <bsp/irq.h> +#include <bsp/spi.h> +#include <assert.h> + +#define SPI_POLLING(condition) \ + while ( condition ) { \ + ; \ + } + +/** + * @brief Object containing the SPI bus configuration settings. + * + * Encapsulates the current SPI bus configuration. + */ +typedef struct +{ + int initialized; + uint8_t bytes_per_char; + + /* Shift to be applied on data transfers with + * least significative bit first (LSB) devices. */ + uint8_t bit_shift; + uint32_t dummy_char; + uint32_t current_slave_addr; + rtems_id task_id; + int irq_write; +} rpi_spi_softc_t; + +/** + * @brief Object containing the SPI bus description. + * + * Encapsulates the current SPI bus description. + */ +typedef struct +{ + rtems_libi2c_bus_t bus_desc; + rpi_spi_softc_t softc; +} rpi_spi_desc_t; + +/* If set to FALSE uses 3-wire SPI, with 2 separate data lines (MOSI and MISO), + * if set to TRUE uses 2-wire SPI, where the MOSI data line doubles as the + * slave out (SO) and slave in (SI) data lines. */ +static bool bidirectional = false; + +/* Calculates a clock divider to be used with the GPU core clock rate + * to set a SPI clock rate the closest (<=) to a desired frequency. */ +static rtems_status_code rpi_spi_calculate_clock_divider( + uint32_t clock_hz, + uint16_t *clock_divider +) { + uint16_t divider; + uint32_t clock_rate; + + assert( clock_hz > 0 ); + + /* Calculates an initial clock divider. */ + divider = GPU_CORE_CLOCK_RATE / clock_hz; + + /* Because the divider must be a power of two (as per the BCM2835 datasheet), + * calculate the next greater power of two. */ + --divider; + + divider |= (divider >> 1); + divider |= (divider >> 2); + divider |= (divider >> 4); + divider |= (divider >> 8); + + ++divider; + + clock_rate = GPU_CORE_CLOCK_RATE / divider; + + /* If the resulting clock rate is greater than the desired frequency, + * try the next greater power of two divider. */ + while ( clock_rate > clock_hz ) { + divider = (divider << 1); + + clock_rate = GPU_CORE_CLOCK_RATE / divider; + } + + *clock_divider = divider; + + return RTEMS_SUCCESSFUL; +} + +/** + * @brief Set the SPI bus transfer mode. + * + * @param[in] bushdl Pointer to the libi2c API bus driver data structure. + * @param[in] tfr_mode Pointer to a libi2c API transfer mode data structure. + * + * @retval RTEMS_SUCCESSFUL Successfully setup the bus transfer mode as desired. + * @retval RTEMS_INVALID_NUMBER This can have two meanings: + * 1. The specified number of bytes per char is not + * 8, 16, 24 or 32; + * 2. @see rpi_spi_calculate_clock_divider() + */ +static rtems_status_code rpi_spi_set_tfr_mode( + rtems_libi2c_bus_t *bushdl, + const rtems_libi2c_tfr_mode_t *tfr_mode +) { + rpi_spi_softc_t *softc_ptr = &(((rpi_spi_desc_t *)(bushdl))->softc); + rtems_status_code sc = RTEMS_SUCCESSFUL; + uint16_t clock_divider; + + /* Set the dummy character. */ + softc_ptr->dummy_char = tfr_mode->idle_char; + + /* Calculate the most appropriate clock divider. */ + sc = rpi_spi_calculate_clock_divider(tfr_mode->baudrate, &clock_divider); + + if ( sc != RTEMS_SUCCESSFUL ) { + return sc; + } + + /* Set the bus clock divider. */ + BCM2835_REG(BCM2835_SPI_CLK) = clock_divider; + + /* Calculate how many bytes each character has. + * Only multiples of 8 bits are accepted for the transaction. */ + switch ( tfr_mode->bits_per_char ) { + case 8: + case 16: + case 24: + case 32: + softc_ptr->bytes_per_char = tfr_mode->bits_per_char / 8; + break; + + default: + return RTEMS_INVALID_NUMBER; + } + + /* Check the data mode (most or least significant bit first) and calculate + * the correcting bit shift value to apply on the data before sending. */ + if ( tfr_mode->lsb_first ) { + softc_ptr->bit_shift = 32 - tfr_mode->bits_per_char; + } + /* If MSB first. */ + else { + softc_ptr->bit_shift = 0; + } + + /* Set SPI clock polarity. + * If clock_inv is TRUE, the clock is active high.*/ + if ( tfr_mode->clock_inv ) { + /* Rest state of clock is low. */ + BCM2835_REG(BCM2835_SPI_CS) &= ~(1 << 3); + } + else { + /* Rest state of clock is high. */ + BCM2835_REG(BCM2835_SPI_CS) |= (1 << 3); + } + + /* Set SPI clock phase. + * If clock_phs is true, clock starts toggling + * at the start of the data transfer. */ + if ( tfr_mode->clock_phs ) { + /* First SCLK transition at beginning of data bit. */ + BCM2835_REG(BCM2835_SPI_CS) |= (1 << 2); + } + else { + /* First SCLK transition at middle of data bit. */ + BCM2835_REG(BCM2835_SPI_CS) &= ~(1 << 2); + } + + return sc; +} + +/** + * @brief Reads/writes to/from the SPI bus. + * + * @param[in] bushdl Pointer to the libi2c API bus driver data structure. + * @param[in] rd_buf Read buffer. If not NULL the function will read from + * the bus and store the read on this buffer. + * @param[in] wr_buf Write buffer. If not NULL the function will write the + * contents of this buffer to the bus. + * @param[in] buffer_size Size of the non-NULL buffer. + * + * @retval -1 Could not send/receive data to/from the bus. + * @retval >=0 The number of bytes read/written. + */ +static int rpi_spi_read_write( + rtems_libi2c_bus_t * bushdl, + unsigned char *rd_buf, + const unsigned char *wr_buf, + int buffer_size +) { + rpi_spi_softc_t *softc_ptr = &(((rpi_spi_desc_t *)(bushdl))->softc); + + uint8_t bytes_per_char = softc_ptr->bytes_per_char; + uint8_t bit_shift = softc_ptr->bit_shift; + uint32_t dummy_char = softc_ptr->dummy_char; + + uint32_t bytes_sent = buffer_size; + uint32_t fifo_data; + + /* Clear SPI bus FIFOs. */ + BCM2835_REG(BCM2835_SPI_CS) |= (3 << 4); + + /* Set SPI transfer active. */ + BCM2835_REG(BCM2835_SPI_CS) |= (1 << 7); + + /* If using the SPI bus in interrupt-driven mode. */ +#if SPI_IO_MODE == 1 + softc_ptr->irq_write = 1; + + BCM2835_REG(BCM2835_SPI_CS) |= (1 << 9); + + if ( rtems_event_transient_receive(RTEMS_WAIT, 0) != RTEMS_SUCCESSFUL ) { + rtems_event_transient_clear(); + + return -1; + } + + /* If using the bus in polling mode. */ +#else + /* Poll TXD bit until there is space to write at least one byte + * on the TX FIFO. */ + SPI_POLLING((BCM2835_REG(BCM2835_SPI_CS) & (1 << 18)) == 0); +#endif + + /* While there is data to be transferred. */ + while ( buffer_size >= bytes_per_char ) { + /* If reading from the bus, send a dummy character to the device. */ + if ( rd_buf != NULL ) { + BCM2835_REG(BCM2835_SPI_FIFO) = dummy_char; + } + /* If writing to the bus, move the buffer data to the TX FIFO. */ + else { + switch ( bytes_per_char ) { + case 1: + BCM2835_REG(BCM2835_SPI_FIFO) = (((*wr_buf) & 0xFF) << bit_shift); + break; + + case 2: + BCM2835_REG(BCM2835_SPI_FIFO) = (((*wr_buf) & 0xFFFF) << bit_shift); + break; + + case 3: + BCM2835_REG(BCM2835_SPI_FIFO) = (((*wr_buf) & 0xFFFFFF) << bit_shift); + break; + + case 4: + BCM2835_REG(BCM2835_SPI_FIFO) = ((*wr_buf) << bit_shift); + break; + + default: + return -1; + } + + wr_buf += bytes_per_char; + + buffer_size -= bytes_per_char; + } + + /* If using bi-directional SPI. */ + if ( bidirectional ) { + /* Change bus direction to read from the slave device. */ + BCM2835_REG(BCM2835_SPI_CS) |= (1 << 12); + } + + /* If using the SPI bus in interrupt-driven mode. */ +#if SPI_IO_MODE == 1 + softc_ptr->irq_write = 0; + + BCM2835_REG(BCM2835_SPI_CS) |= (1 << 9); + + if ( rtems_event_transient_receive(RTEMS_WAIT, 0) != RTEMS_SUCCESSFUL ) { + rtems_event_transient_clear(); + + return -1; + } + + /* If using the bus in polling mode. */ +#else + /* Poll the Done bit until the data transfer is complete. */ + SPI_POLLING((BCM2835_REG(BCM2835_SPI_CS) & (1 << 16)) == 0); + + /* Poll the RXD bit until there is at least one byte + * on the RX FIFO to be read. */ + SPI_POLLING((BCM2835_REG(BCM2835_SPI_CS) & (1 << 17)) == 0); +#endif + + /* If writing to the bus, read the dummy char sent by the slave device. */ + if ( rd_buf == NULL ) { + fifo_data = BCM2835_REG(BCM2835_SPI_FIFO) & 0xFF; + } + + /* If reading from the bus, retrieve data from the RX FIFO and + * store it on the buffer. */ + if ( rd_buf != NULL ) { + switch ( bytes_per_char ) { + case 1: + fifo_data = BCM2835_REG(BCM2835_SPI_FIFO) & 0xFF; + (*rd_buf) = (fifo_data >> bit_shift); + break; + + case 2: + fifo_data = BCM2835_REG(BCM2835_SPI_FIFO) & 0xFFFF; + (*rd_buf) = (fifo_data >> bit_shift); + break; + + case 3: + fifo_data = BCM2835_REG(BCM2835_SPI_FIFO) & 0xFFFFFF; + (*rd_buf) = (fifo_data >> bit_shift); + break; + + case 4: + fifo_data = BCM2835_REG(BCM2835_SPI_FIFO); + (*rd_buf) = (fifo_data >> bit_shift); + break; + + default: + return -1; + } + + rd_buf += bytes_per_char; + + buffer_size -= bytes_per_char; + } + + /* If using bi-directional SPI. */ + if ( bidirectional ) { + /* Restore bus direction to write to the slave. */ + BCM2835_REG(BCM2835_SPI_CS) &= ~(1 << 12); + } + } + + /* If using the SPI bus in interrupt-driven mode. */ +#if SPI_IO_MODE == 1 + softc_ptr->irq_write = 1; + + BCM2835_REG(BCM2835_SPI_CS) |= (1 << 9); + + if ( rtems_event_transient_receive(RTEMS_WAIT, 0) != RTEMS_SUCCESSFUL ) { + rtems_event_transient_clear(); + + return -1; + } + + /* If using the bus in polling mode. */ +#else + /* Poll the Done bit until the data transfer is complete. */ + SPI_POLLING((BCM2835_REG(BCM2835_SPI_CS) & (1 << 16)) == 0); +#endif + + bytes_sent -= buffer_size; + + return bytes_sent; +} + +/** + * @brief Handler function that is called on any SPI interrupt. + * + * There are 2 situations that can generate an interrupt: + * + * 1. Transfer (read/write) complete; + * 2. RX FIFO full. + * + * Because the 2. situation is not useful to many applications, + * the only interrupt that is generated and handled is the + * transfer complete interrupt. + * + * The objective of the handler is then, depending on the transfer + * context (reading or writing on the bus), to check if there is enough + * space available on the TX FIFO to send data over the bus (if writing) + * or if the slave device has sent enough data to be fetched from the + * RX FIFO (if reading). + * + * When any of these two conditions occur, disables further interrupts + * to be generated and sends a waking event to the transfer task + * which will allow the following transfer to proceed. + * + * @param[in] arg Void pointer to the bus data structure. + */ +#if SPI_IO_MODE == 1 +static void spi_handler(void* arg) +{ + rpi_spi_softc_t *softc_ptr = (rpi_spi_softc_t *) arg; + + /* If waiting to write to the bus, expect the TXD bit to be set, or + * if waiting to read from the bus, expect the RXD bit to be set + * before sending a waking event to the transfer task. */ + if ( + ( softc_ptr->irq_write == 1 && + (BCM2835_REG(BCM2835_SPI_CS) & (1 << 18)) != 0 + ) || + ( softc_ptr->irq_write == 0 && + (BCM2835_REG(BCM2835_SPI_CS) & (1 << 17)) != 0 + ) + ) { + /* Disable the SPI interrupt generation when a transfer is complete. */ + BCM2835_REG(BCM2835_SPI_CS) &= ~(1 << 9); + + /* Allow the transfer process to continue. */ + rtems_event_transient_send(softc_ptr->task_id); + } +} +#endif + +/** + * @brief Low level function to initialize the SPI bus. + * This function is used by the libi2c API. + * + * @param[in] bushdl Pointer to the libi2c API bus driver data structure. + * + * @retval RTEMS_SUCCESSFUL SPI bus successfully initialized. + * @retval Any other status code @see rtems_interrupt_handler_install(). + */ +static rtems_status_code rpi_libi2c_spi_init(rtems_libi2c_bus_t * bushdl) +{ + rpi_spi_softc_t *softc_ptr = &(((rpi_spi_desc_t *)(bushdl))->softc); + rtems_status_code sc = RTEMS_SUCCESSFUL; + + if ( softc_ptr->initialized == 1 ) { + return sc; + } + + softc_ptr->initialized = 1; + + /* If using the SPI bus in interrupt-driven mode. */ +#if SPI_IO_MODE == 1 + softc_ptr->task_id = rtems_task_self(); + + sc = rtems_interrupt_handler_install( + BCM2835_IRQ_ID_SPI, + NULL, + RTEMS_INTERRUPT_UNIQUE, + (rtems_interrupt_handler) spi_handler, + softc_ptr + ); +#endif + + return sc; +} + +/** + * @brief Low level function that would send a start condition over an I2C bus. + * As it is not required to access a SPI bus it is here just to satisfy + * the libi2c API, which requires this function. + * + * @param[in] bushdl Pointer to the libi2c API bus driver data structure. + * + * @retval RTEMS_SUCCESSFUL + */ +static rtems_status_code rpi_libi2c_spi_send_start(rtems_libi2c_bus_t * bushdl) +{ + return RTEMS_SUCCESSFUL; +} + +/** + * @brief Low level function that terminates a SPI transfer. + * It stops the SPI transfer and unselects the current SPI slave device. + * This function is used by the libi2c API. + * + * @param[in] bushdl Pointer to the libi2c API bus driver data structure. + * + * @retval RTEMS_SUCCESSFUL The slave device has been successfully unselected. + * @retval RTEMS_INVALID_ADDRESS The stored slave address is neither 0 or 1. + */ +static rtems_status_code rpi_libi2c_spi_stop(rtems_libi2c_bus_t * bushdl) +{ + rpi_spi_softc_t *softc_ptr = &(((rpi_spi_desc_t *)(bushdl))->softc); + + uint32_t addr = softc_ptr->current_slave_addr; + uint32_t chip_select_bit = 21 + addr; + + /* Set SPI transfer as not active. */ + BCM2835_REG(BCM2835_SPI_CS) &= ~(1 << 7); + + /* Unselect the active SPI slave. */ + switch ( addr ) { + case 0: + case 1: + BCM2835_REG(BCM2835_SPI_CS) |= (1 << chip_select_bit); + + break; + + default: + return RTEMS_INVALID_ADDRESS; + } + + return RTEMS_SUCCESSFUL; +} + +/** + * @brief Low level function which addresses a SPI slave device. + * This function is used by the libi2c API. + * + * @param[in] bushdl Pointer to the libi2c API bus driver data structure. + * @param[in] addr SPI slave select line address (0 for CE0 or 1 for CE1). + * @param[in] rw This values is unnecessary to address a SPI device and its + * presence here is only to fulfill a libi2c requirement. + * + * @retval RTEMS_SUCCESSFUL The slave device has been successfully addressed. + * @retval RTEMS_INVALID_ADDRESS The received address is neither 0 or 1. + */ +static rtems_status_code rpi_libi2c_spi_send_addr( + rtems_libi2c_bus_t * bushdl, + uint32_t addr, + int rw +) { + rpi_spi_softc_t *softc_ptr = &(((rpi_spi_desc_t *)(bushdl))->softc); + + /* Calculates the bit corresponding to the received address + * on the SPI control register. */ + uint32_t chip_select_bit = 21 + addr; + + /* Save which slave will be currently addressed, + * so it can be unselected later. */ + softc_ptr->current_slave_addr = addr; + + /* Select one of the two available SPI slave address lines. */ + switch ( addr ) { + case 0: + case 1: + BCM2835_REG(BCM2835_SPI_CS) &= ~(1 << chip_select_bit); + break; + + default: + return RTEMS_INVALID_ADDRESS; + } + + return RTEMS_SUCCESSFUL; +} + +/** + * @brief Low level function that reads a number of bytes from the SPI bus + * on to a buffer. + * This function is used by the libi2c API. + * + * @param[in] bushdl Pointer to the libi2c API bus driver data structure. + * @param[in] bytes Buffer where the data read from the bus will be stored. + * @param[in] nbytes Number of bytes to be read from the bus to the bytes buffer. + * + * @retval @see rpi_spi_read_write(). + */ +static int rpi_libi2c_spi_read_bytes( + rtems_libi2c_bus_t * bushdl, + unsigned char *bytes, + int nbytes +) { + return rpi_spi_read_write(bushdl, bytes, NULL, nbytes); +} + +/** + * @brief Low level function that writes a number of bytes from a buffer + * to the SPI bus. + * This function is used by the libi2c API. + * + * @param[in] bushdl Pointer to the libi2c API bus driver data structure. + * @param[in] bytes Buffer with data to send over the SPI bus. + * @param[in] nbytes Number of bytes to be written from the bytes buffer + to the bus. + * + * @retval @see rpi_spi_read_write(). + */ +static int rpi_libi2c_spi_write_bytes( + rtems_libi2c_bus_t * bushdl, + unsigned char *bytes, + int nbytes +) { + return rpi_spi_read_write(bushdl, NULL, bytes, nbytes); +} + +/** + * @brief Low level function that is used to perform ioctl + * operations on the bus. Currently only setups + * the bus transfer mode. + * This function is used by the libi2c API. + * + * @param[in] bushdl Pointer to the libi2c API bus driver data structure. + * @param[in] cmd IOCTL request command. + * @param[in] arg Arguments needed to fulfill the requested IOCTL command. + * + * @retval -1 Unknown request command. + * @retval >=0 @see rpi_spi_set_tfr_mode(). + */ +static int rpi_libi2c_spi_ioctl(rtems_libi2c_bus_t * bushdl, int cmd, void *arg) +{ + switch ( cmd ) { + case RTEMS_LIBI2C_IOCTL_SET_TFRMODE: + return rpi_spi_set_tfr_mode( + bushdl, + (const rtems_libi2c_tfr_mode_t *)arg + ); + default: + return -1; + } + + return 0; +} + +static rtems_libi2c_bus_ops_t rpi_spi_ops = { + .init = rpi_libi2c_spi_init, + .send_start = rpi_libi2c_spi_send_start, + .send_stop = rpi_libi2c_spi_stop, + .send_addr = rpi_libi2c_spi_send_addr, + .read_bytes = rpi_libi2c_spi_read_bytes, + .write_bytes = rpi_libi2c_spi_write_bytes, + .ioctl = rpi_libi2c_spi_ioctl +}; + +static rpi_spi_desc_t rpi_spi_bus_desc = { + { + .ops = &rpi_spi_ops, + .size = sizeof(rpi_spi_bus_desc) + }, + { + .initialized = 0 + } +}; + +int rpi_spi_init(bool bidirectional_mode) +{ + /* Initialize the libi2c API. */ + rtems_libi2c_initialize(); + + /* Enable the SPI interface on the Raspberry Pi. */ + rtems_gpio_initialize(); + + assert ( rpi_gpio_select_spi() == RTEMS_SUCCESSFUL ); + + bidirectional = bidirectional_mode; + + /* Clear SPI control register and clear SPI FIFOs. */ + BCM2835_REG(BCM2835_SPI_CS) = (3 << 4); + + /* Register the SPI bus. */ + return rtems_libi2c_register_bus("/dev/spi", &(rpi_spi_bus_desc.bus_desc)); +} |