diff options
Diffstat (limited to '')
27 files changed, 2121 insertions, 844 deletions
diff --git a/bsps/arm/tms570/start/bspreset.c b/bsps/arm/tms570/start/bspreset.c index daca621c86..67cf96c67c 100644 --- a/bsps/arm/tms570/start/bspreset.c +++ b/bsps/arm/tms570/start/bspreset.c @@ -1,25 +1,47 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * * @ingroup RTEMSBSPsARMTMS570 * - * @brief Reset code. + * @brief This source file contains the bsp_reset() implementation. */ /* - * Copyright (c) 2015 Taller Technologies. + * Copyright (C) 2014 Premysl Houdek <kom541000@gmail.com> + * + * Google Summer of Code 2014 at + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic * - * @author Martin Galvan <martin.galvan@tallertechnologies.com> + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ -#include <bsp.h> #include <bsp/bootcard.h> #include <bsp/tms570.h> -#include <bsp/start.h> +#include <bsp/tms570-pom.h> static void handle_esm_errors(uint32_t esm_irq_channel) { @@ -35,7 +57,14 @@ static void handle_esm_errors(uint32_t esm_irq_channel) void bsp_reset(void) { - uint32_t esm_irq_channel = TMS570_ESM.IOFFHR - 1; + rtems_interrupt_level level; + uint32_t esm_irq_channel; + + rtems_interrupt_disable(level); + (void) level; + + tms570_pom_initialize_and_clear(); + esm_irq_channel = TMS570_ESM.IOFFHR - 1; if (esm_irq_channel) { handle_esm_errors(esm_irq_channel); diff --git a/bsps/arm/tms570/start/bsprestart.c b/bsps/arm/tms570/start/bsprestart.c new file mode 100644 index 0000000000..c989d8fc77 --- /dev/null +++ b/bsps/arm/tms570/start/bsprestart.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (c) 2017 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <bsp.h> + +void bsp_restart( const void *addr ) +{ + rtems_interrupt_level level; + void(*start)(void) = (void(*)(void))(addr); + + rtems_interrupt_disable(level); + (void)level; + rtems_cache_disable_instruction(); + rtems_cache_disable_data(); + + start(); + RTEMS_UNREACHABLE(); +} diff --git a/bsps/arm/tms570/start/bspstart.c b/bsps/arm/tms570/start/bspstart.c index 25ea4e3a17..60ce5345a9 100644 --- a/bsps/arm/tms570/start/bspstart.c +++ b/bsps/arm/tms570/start/bspstart.c @@ -1,13 +1,15 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * * @ingroup RTEMSBSPsARMTMS570 * - * @brief Startup code. + * @brief This source file contains the bsp_start() implementation. */ /* - * Copyright (c) 2014 Premysl Houdek <kom541000@gmail.com> + * Copyright (C) 2014 Premysl Houdek <kom541000@gmail.com> * * Google Summer of Code 2014 at * Czech Technical University in Prague @@ -15,27 +17,39 @@ * 166 36 Praha 6 * Czech Republic * - * Based on LPC24xx and LPC1768 BSP + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ -#include <bsp.h> #include <bsp/tms570-pom.h> #include <bsp/irq-generic.h> -#include <bsp/start.h> #include <bsp/bootcard.h> #include <bsp/linker-symbols.h> -#include <rtems/endian.h> void bsp_start( void ) { void *need_remap_ptr; unsigned int need_remap_int; - tms570_initialize_and_clear(); + tms570_pom_initialize_and_clear(); /* * If RTEMS image does not start at address 0x00000000 diff --git a/bsps/arm/tms570/start/bspstarthooks-hwinit.c b/bsps/arm/tms570/start/bspstarthooks-hwinit.c index 407ab142ff..6407cc4a45 100644 --- a/bsps/arm/tms570/start/bspstarthooks-hwinit.c +++ b/bsps/arm/tms570/start/bspstarthooks-hwinit.c @@ -1,3 +1,44 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This source file contains the bsp_start_hook_0() implementation. + */ + +/* + * Copyright (C) 2023 embedded brains GmbH & Co. KG + * Copyright (C) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz> + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + #include <stdint.h> #include <bsp.h> #include <bsp/start.h> @@ -6,27 +47,38 @@ #include <bsp/tms570_selftest.h> #include <bsp/tms570_selftest_parity.h> #include <bsp/tms570_hwinit.h> +#include <bsp/ti_herc/errata_SSWF021_45.h> -static inline -int tms570_running_from_tcram( void ) -{ - void *fncptr = (void*)bsp_start_hook_0; - return ( fncptr >= (void*)TMS570_TCRAM_START_PTR ) && - ( fncptr < (void*)TMS570_TCRAM_WINDOW_END_PTR ); -} +#define PBIST_March13N_SP 0x00000008U /**< March13 N Algo for 1 Port mem */ -static inline -int tms570_running_from_sdram( void ) +/* Use assembly code to avoid using the stack */ +__attribute__((__naked__)) void bsp_start_hook_0( void ) { - void *fncptr = (void*)bsp_start_hook_0; - return ( ( (void*)fncptr >= (void*)TMS570_SDRAM_START_PTR ) && - ( (void*)fncptr < (void*)TMS570_SDRAM_WINDOW_END_PTR ) ); -} + __asm__ volatile ( + /* Check if we run in SRAM */ + "ldr r0, =#" RTEMS_XSTRING( TMS570_MEMORY_SRAM_ORIGIN ) "\n" + "ldr r1, =#" RTEMS_XSTRING( TMS570_MEMORY_SRAM_SIZE ) "\n" + "sub r0, lr, r0\n" + "cmp r1, r0\n" + "blt 1f\n" -#define PBIST_March13N_SP 0x00000008U /**< March13 N Algo for 1 Port mem */ + /* + * Initialize the SRAM if we are not running in SRAM. While we are called, + * non-volatile register r7 is not used by start.S. + */ + "movs r0, #0x1\n" + "mov r7, lr\n" + "bl tms570_memory_init\n" + "mov lr, r7\n" + + /* Jump to the high level start hook */ + "1: b tms570_start_hook_0\n" + ); +} -BSP_START_TEXT_SECTION void bsp_start_hook_0( void ) +static RTEMS_USED void tms570_start_hook_0( void ) { +#if TMS570_VARIANT == 3137 /* * Work Around for Errata DEVICE#140: ( Only on Rev A silicon) * @@ -38,6 +90,15 @@ BSP_START_TEXT_SECTION void bsp_start_hook_0( void ) if ( TMS570_SYS1.DEVID == 0x802AAD05U ) { _esmCcmErrorsClear_(); } +#endif + +#if TMS570_VARIANT == 4357 + uint32_t pll_result; + + do { + pll_result = _errata_SSWF021_45_both_plls(10); + } while (pll_result != 0 && pll_result != 4); +#endif /* Enable CPU Event Export */ /* This allows the CPU to signal any single-bit or double-bit errors detected @@ -45,58 +106,13 @@ BSP_START_TEXT_SECTION void bsp_start_hook_0( void ) */ _coreEnableEventBusExport_(); +#if TMS570_VARIANT == 3137 /* Workaround for Errata CORTEXR4 66 */ _errata_CORTEXR4_66_(); /* Workaround for Errata CORTEXR4 57 */ _errata_CORTEXR4_57_(); - - /* check for power-on reset condition */ - /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */ - if ( ( TMS570_SYS1.SYSESR & TMS570_SYS1_SYSESR_PORST ) != 0U ) { - /* clear all reset status flags */ - TMS570_SYS1.SYSESR = 0xFFFFU; - - /* continue with normal start-up sequence */ - } - /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */ - else if ( ( TMS570_SYS1.SYSESR & TMS570_SYS1_SYSESR_OSCRST ) != 0U ) { - /* Reset caused due to oscillator failure. - Add user code here to handle oscillator failure */ - } - /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */ - else if ( ( TMS570_SYS1.SYSESR & TMS570_SYS1_SYSESR_WDRST ) != 0U ) { - /* Reset caused due - * 1) windowed watchdog violation - Add user code here to handle watchdog violation. - * 2) ICEPICK Reset - After loading code via CCS / System Reset through CCS - */ - /* Check the WatchDog Status register */ - if ( TMS570_RTI.WDSTATUS != 0U ) { - /* Add user code here to handle watchdog violation. */ - /* Clear the Watchdog reset flag in Exception Status register */ - TMS570_SYS1.SYSESR = TMS570_SYS1_SYSESR_WDRST; - } else { - /* Clear the ICEPICK reset flag in Exception Status register */ - TMS570_SYS1.SYSESR = TMS570_SYS1_SYSESR_WDRST; - } - } - /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */ - else if ( ( TMS570_SYS1.SYSESR & TMS570_SYS1_SYSESR_CPURST ) != 0U ) { - /* Reset caused due to CPU reset. - CPU reset can be caused by CPU self-test completion, or - by toggling the "CPU RESET" bit of the CPU Reset Control Register. */ - - /* clear all reset status flags */ - TMS570_SYS1.SYSESR = TMS570_SYS1_SYSESR_CPURST; - } - /*SAFETYMCUSW 139 S MR:13.7 <APPROVED> "Hardware status bit read check" */ - else if ( ( TMS570_SYS1.SYSESR & TMS570_SYS1_SYSESR_SWRST ) != 0U ) { - /* Reset caused due to software reset. - Add user code to handle software reset. */ - } else { - /* Reset caused by nRST being driven low externally. - Add user code to handle external reset. */ - } +#endif /* * Check if there were ESM group3 errors during power-up. @@ -111,8 +127,20 @@ BSP_START_TEXT_SECTION void bsp_start_hook_0( void ) /*SAFETYMCUSW 5 C MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */ /*SAFETYMCUSW 26 S MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */ /*SAFETYMCUSW 28 D MR:NA <APPROVED> "for(;;) can be removed by adding "# if 0" and "# endif" in the user codes above and below" */ +#if TMS570_VARIANT == 4357 + /* + * During code-loading/debug-resets SR[2][4] may get set (indicates double + * ECC error in internal RAM) ignore for now as its resolved with ESM + * init/reset below. + */ + if ((TMS570_SYS1.SYSESR & TMS570_SYS1_SYSESR_DBGRST) == 0) { + for (;; ) { + } /* Wait */ + } +#else for (;; ) { } /* Wait */ +#endif } /* Initialize System - Clock, Flash settings with Efuse self check */ @@ -131,47 +159,13 @@ BSP_START_TEXT_SECTION void bsp_start_hook_0( void ) tms570_pbist_self_check(); /* Run PBIST on STC ROM */ - tms570_pbist_run( (uint32_t) STC_ROM_PBIST_RAM_GROUP, + tms570_pbist_run_and_check( (uint32_t) STC_ROM_PBIST_RAM_GROUP, ( (uint32_t) PBIST_TripleReadSlow | (uint32_t) PBIST_TripleReadFast ) ); - /* Wait for PBIST for STC ROM to be completed */ - /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ - while ( tms570_pbist_is_test_completed() != TRUE ) { - } /* Wait */ - - /* Check if PBIST on STC ROM passed the self-test */ - if ( tms570_pbist_is_test_passed() != TRUE ) { - /* PBIST and STC ROM failed the self-test. - * Need custom handler to check the memory failure - * and to take the appropriate next step. - */ - tms570_pbist_fail(); - } - - /* Disable PBIST clocks and disable memory self-test mode */ - tms570_pbist_stop(); - /* Run PBIST on PBIST ROM */ - tms570_pbist_run( (uint32_t) PBIST_ROM_PBIST_RAM_GROUP, + tms570_pbist_run_and_check( (uint32_t) PBIST_ROM_PBIST_RAM_GROUP, ( (uint32_t) PBIST_TripleReadSlow | (uint32_t) PBIST_TripleReadFast ) ); - /* Wait for PBIST for PBIST ROM to be completed */ - /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ - while ( tms570_pbist_is_test_completed() != TRUE ) { - } /* Wait */ - - /* Check if PBIST ROM passed the self-test */ - if ( tms570_pbist_is_test_passed() != TRUE ) { - /* PBIST and STC ROM failed the self-test. - * Need custom handler to check the memory failure - * and to take the appropriate next step. - */ - tms570_pbist_fail(); - } - - /* Disable PBIST clocks and disable memory self-test mode */ - tms570_pbist_stop(); - if ( !tms570_running_from_tcram() ) { /* * The next sequence tests TCRAM, main TMS570 system operation RAM area. @@ -199,35 +193,9 @@ BSP_START_TEXT_SECTION void bsp_start_hook_0( void ) * The CPU RAM is a single-port memory. The actual "RAM Group" for all on-chip SRAMs is defined in the * device datasheet. */ - tms570_pbist_run( 0x08300020U, /* ESRAM Single Port PBIST */ + tms570_pbist_run_and_check( 0x08300020U, /* ESRAM Single Port PBIST */ (uint32_t) PBIST_March13N_SP ); - /* Wait for PBIST for CPU RAM to be completed */ - /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ - while ( tms570_pbist_is_test_completed() != TRUE ) { - } /* Wait */ - - /* Check if CPU RAM passed the self-test */ - if ( tms570_pbist_is_test_passed() != TRUE ) { - /* CPU RAM failed the self-test. - * Need custom handler to check the memory failure - * and to take the appropriate next step. - */ - tms570_pbist_fail(); - } - - /* Disable PBIST clocks and disable memory self-test mode */ - tms570_pbist_stop(); - - /* - * Initialize CPU RAM. - * This function uses the system module's hardware for auto-initialization of memories and their - * associated protection schemes. The CPU RAM is initialized by setting bit 0 of the MSIENA register. - * Hence the value 0x1 passed to the function. - * This function will initialize the entire CPU RAM and the corresponding ECC locations. - */ - tms570_memory_init( 0x1U ); - /* * Enable ECC checking for TCRAM accesses. * This function enables the CPU's ECC logic for accesses to B0TCM and B1TCM. @@ -261,6 +229,7 @@ BSP_START_TEXT_SECTION void bsp_start_hook_0( void ) if ( !tms570_running_from_tcram() ) { +#if TMS570_VARIANT == 3137 /* Test the CPU ECC mechanism for RAM accesses. * The checkBxRAMECC functions cause deliberate single-bit and double-bit errors in TCRAM accesses * by corrupting 1 or 2 bits in the ECC. Reading from the TCRAM location with a 2-bit error @@ -269,6 +238,7 @@ BSP_START_TEXT_SECTION void bsp_start_hook_0( void ) * following the one that caused the abort. */ tms570_check_tcram_ecc(); +#endif /* Wait for PBIST for CPU RAM to be completed */ /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ @@ -316,17 +286,18 @@ BSP_START_TEXT_SECTION void bsp_start_hook_0( void ) /* NOTE : Please Refer DEVICE DATASHEET for the list of Supported Memories and their channel numbers. Memory Initialization is perfomed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab. */ - tms570_memory_init( (uint32_t) ( (uint32_t) 1U << 1U ) | /* DMA RAM */ - (uint32_t) ( (uint32_t) 1U << 2U ) | /* VIM RAM */ - (uint32_t) ( (uint32_t) 1U << 5U ) | /* CAN1 RAM */ - (uint32_t) ( (uint32_t) 1U << 6U ) | /* CAN2 RAM */ - (uint32_t) ( (uint32_t) 1U << 10U ) | /* CAN3 RAM */ - (uint32_t) ( (uint32_t) 1U << 8U ) | /* ADC1 RAM */ - (uint32_t) ( (uint32_t) 1U << 14U ) | /* ADC2 RAM */ - (uint32_t) ( (uint32_t) 1U << 3U ) | /* HET1 RAM */ - (uint32_t) ( (uint32_t) 1U << 4U ) | /* HTU1 RAM */ - (uint32_t) ( (uint32_t) 1U << 15U ) | /* HET2 RAM */ - (uint32_t) ( (uint32_t) 1U << 16U ) /* HTU2 RAM */ + tms570_memory_init( + ( UINT32_C(1) << 1 ) | /* DMA RAM */ + ( UINT32_C(1) << 2 ) | /* VIM RAM */ + ( UINT32_C(1) << 5 ) | /* CAN1 RAM */ + ( UINT32_C(1) << 6 ) | /* CAN2 RAM */ + ( UINT32_C(1) << 10 ) | /* CAN3 RAM */ + ( UINT32_C(1) << 8 ) | /* ADC1 RAM */ + ( UINT32_C(1) << 14 ) | /* ADC2 RAM */ + ( UINT32_C(1) << 3 ) | /* HET1 RAM */ + ( UINT32_C(1) << 4 ) | /* HTU1 RAM */ + ( UINT32_C(1) << 15 ) | /* HET2 RAM */ + ( UINT32_C(1) << 16 ) /* HTU2 RAM */ ); /* Disable parity */ @@ -364,6 +335,11 @@ BSP_START_TEXT_SECTION void bsp_start_hook_0( void ) /* Configure system response to error conditions signaled to the ESM group1 */ tms570_esm_init(); + tms570_emif_sdram_init(); + + /* Configures and enables the ARM-core Memory Protection Unit (MPU) */ + _mpuInit_(); + #if 1 /* * Do not depend on link register to be restored to @@ -374,26 +350,6 @@ BSP_START_TEXT_SECTION void bsp_start_hook_0( void ) #endif } -BSP_START_TEXT_SECTION void bsp_start_hook_1( void ) -{ - /* At this point we can use objects outside the .start section */ -#if 0 - /* Do not run attempt to initialize MPU when code is running from SDRAM */ - if ( !tms570_running_from_sdram() ) { - /* - * MPU background areas setting has to be overlaid - * if execution of code is required from external memory/SDRAM. - * This region is non executable by default. - */ - _mpuInit_(); - } -#endif - tms570_emif_sdram_init(); - - bsp_start_copy_sections(); - bsp_start_clear_bss(); -} - /* * Chip specific list of peripherals which should be tested * for functional RAM parity reporting diff --git a/bsps/arm/tms570/start/bspstarthooks.c b/bsps/arm/tms570/start/bspstarthooks.c index f6bf19c754..8dc7fdfdf8 100644 --- a/bsps/arm/tms570/start/bspstarthooks.c +++ b/bsps/arm/tms570/start/bspstarthooks.c @@ -1,14 +1,15 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * * @ingroup RTEMSBSPsARMTMS570 * - * @brief First configurations and initializations to the correct - * functionality of the board. + * @brief This source file contains the bsp_start_hook_1(0 implementation. */ /* - * Copyright (c) 2014 Premysl Houdek <kom541000@gmail.com> + * Copyright (C) 2014 Premysl Houdek <kom541000@gmail.com> * * Google Summer of Code 2014 at * Czech Technical University in Prague @@ -16,26 +17,57 @@ * 166 36 Praha 6 * Czech Republic * - * Based on LPC24xx and LPC1768 BSP - * by embedded brains GmbH & Co. KG and others + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ -#include <bsp.h> #include <bsp/start.h> - -BSP_START_TEXT_SECTION void bsp_start_hook_0( void ) -{ - ; -} +#include <libcpu/arm-cp15.h> BSP_START_TEXT_SECTION void bsp_start_hook_1( void ) { - bsp_start_copy_sections(); + uint32_t ctrl; + size_t size; + + ctrl = arm_cp15_get_control(); + + if ( ( ctrl & ARM_CP15_CTRL_I ) == 0 ) { + rtems_cache_invalidate_entire_instruction(); + ctrl |= ARM_CP15_CTRL_I; + arm_cp15_set_control(ctrl); + } + + if ( ( ctrl & ARM_CP15_CTRL_C ) == 0 ) { + rtems_cache_invalidate_entire_data(); + ctrl |= ARM_CP15_CTRL_C; + arm_cp15_set_control(ctrl); + } + + bsp_start_copy_sections_compact(); bsp_start_clear_bss(); - /* At this point we can use objects outside the .start section */ + size =(size_t) bsp_section_fast_text_size; + RTEMS_OBFUSCATE_VARIABLE( size ); + + if ( size != 0 ) { + rtems_cache_flush_multiple_data_lines( bsp_section_fast_text_begin, size ); + } } diff --git a/bsps/arm/tms570/start/errata_SSWF021_45.c b/bsps/arm/tms570/start/errata_SSWF021_45.c new file mode 100755 index 0000000000..1591e64798 --- /dev/null +++ b/bsps/arm/tms570/start/errata_SSWF021_45.c @@ -0,0 +1,366 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This source file contains errata SSWF021#45 workaround + * implementation. + */ + +/* + * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ +#include <bsp/ti_herc/errata_SSWF021_45.h> +#include <bsp/tms570.h> + +#define SYS_CLKSRC_PLL1 0x00000002U +#define SYS_CLKSRC_PLL2 0x00000040U +#define SYS_CLKCNTRL_PENA 0x00000100U +#define ESM_SR1_PLL1SLIP 0x400U +#define ESM_SR4_PLL2SLIP 0x400U +#define PLL1 0x08 +#define PLL2 0x80 +#define dcc1CNT1_CLKSRC_PLL1 0x0000A000U +#define dcc1CNT1_CLKSRC_PLL2 0x0000A001U + +static uint32_t check_frequency(uint32_t cnt1_clksrc); +static uint32_t disable_plls(uint32_t plls); + +/** @fn uint32_t _errata_SSWF021_45_both_plls(uint32_t count) + * @brief This handles the errata for PLL1 and PLL2. This function is called + * in device startup + * + * @param[in] count : Number of retries until both PLLs are locked + * successfully Minimum value recommended is 5 + * + * @return 0 = Success (the PLL or both PLLs have successfully locked and then + * been disabled) + * 1 = PLL1 failed to successfully lock in "count" tries + * 2 = PLL2 failed to successfully lock in "count" tries + * 3 = Neither PLL1 nor PLL2 successfully locked in "count" tries + * 4 = The workaround function was not able to disable at least one of + * the PLLs. The most likely reason is that a PLL is already being + * used as a clock source. This can be caused by the workaround + * function being called from the wrong place in the code. + */ +uint32_t _errata_SSWF021_45_both_plls(uint32_t count) { + uint32_t failCode, retries, clkCntlSav; + + /* save CLKCNTL */ + clkCntlSav = TMS570_SYS1.CLKCNTL; + /* First set VCLK2 = HCLK */ + TMS570_SYS1.CLKCNTL = clkCntlSav & 0x000F0100U; + /* Now set VCLK = HCLK and enable peripherals */ + TMS570_SYS1.CLKCNTL = SYS_CLKCNTRL_PENA; + failCode = 0U; + for (retries = 0U; (retries < count); retries++) { + failCode = 0U; + /* Disable PLL1 and PLL2 */ + failCode = disable_plls(SYS_CLKSRC_PLL1 | SYS_CLKSRC_PLL2); + if (failCode != 0U) { + break; + } + + /* Clear Global Status Register */ + TMS570_SYS1.GLBSTAT = 0x00000301U; + /* Clear the ESM PLL slip flags */ + TMS570_ESM.SR[0U] = ESM_SR1_PLL1SLIP; + TMS570_ESM.SR4 = ESM_SR4_PLL2SLIP; + /* set both PLLs to OSCIN/1*27/(2*1) */ + TMS570_SYS1.PLLCTL1 = 0x20001A00U; + TMS570_SYS1.PLLCTL2 = 0x3FC0723DU; + TMS570_SYS2.PLLCTL3 = 0x20001A00U; + TMS570_SYS1.CSDISCLR = SYS_CLKSRC_PLL1 | SYS_CLKSRC_PLL2; + /* Check for (PLL1 valid or PLL1 slip) and (PLL2 valid or PLL2 slip) */ + while ((((TMS570_SYS1.CSVSTAT & SYS_CLKSRC_PLL1) == 0U) && + ((TMS570_ESM.SR[0U] & ESM_SR1_PLL1SLIP) == 0U)) || + (((TMS570_SYS1.CSVSTAT & SYS_CLKSRC_PLL2) == 0U) && + ((TMS570_ESM.SR4 & ESM_SR4_PLL2SLIP) == 0U))) { + /* Wait */ + } + /* If PLL1 valid, check the frequency */ + if (((TMS570_ESM.SR[0U] & ESM_SR1_PLL1SLIP) != 0U) || + ((TMS570_SYS1.GLBSTAT & 0x00000300U) != 0U)) { + failCode |= 1U; + } else { + failCode |= check_frequency(dcc1CNT1_CLKSRC_PLL1); + } + /* If PLL2 valid, check the frequency */ + if (((TMS570_ESM.SR4 & ESM_SR4_PLL2SLIP) != 0U) || + ((TMS570_SYS1.GLBSTAT & 0x00000300U) != 0U)) { + failCode |= 2U; + } else { + failCode |= (check_frequency(dcc1CNT1_CLKSRC_PLL2) << 1U); + } + if (failCode == 0U) { + break; + } + } + /* To avoid MISRA violation 382S + (void)missing for discarded return value */ + failCode = disable_plls(SYS_CLKSRC_PLL1 | SYS_CLKSRC_PLL2); + /* restore CLKCNTL, VCLKR and PENA first */ + TMS570_SYS1.CLKCNTL = (clkCntlSav & 0x000F0100U); + /* restore CLKCNTL, VCLK2R */ + TMS570_SYS1.CLKCNTL = clkCntlSav; + return failCode; +} + +/** @fn uint32_t _errata_SSWF021_45_pll1(uint32_t count) + * @brief This handles the errata for PLL1. This function is called in device + * startup + * + * @param[in] count : Number of retries until both PLL1 is locked successfully + * Minimum value recommended is 5 + * + * @return 0 = Success (the PLL or both PLLs have successfully locked and then + * been disabled) + * 1 = PLL1 failed to successfully lock in "count" tries + * 2 = PLL2 failed to successfully lock in "count" tries + * 3 = Neither PLL1 nor PLL2 successfully locked in "count" tries + * 4 = The workaround function was not able to disable at least one of + * the PLLs. The most likely reason is that a PLL is already being + * used as a clock source. This can be caused by the workaround + * function being called from the wrong place in the code. + */ +uint32_t _errata_SSWF021_45_pll1(uint32_t count) { + uint32_t failCode, retries, clkCntlSav; + + /* save CLKCNTL */ + clkCntlSav = TMS570_SYS1.CLKCNTL; + /* First set VCLK2 = HCLK */ + TMS570_SYS1.CLKCNTL = clkCntlSav & 0x000F0100U; + /* Now set VCLK = HCLK and enable peripherals */ + TMS570_SYS1.CLKCNTL = SYS_CLKCNTRL_PENA; + failCode = 0U; + for (retries = 0U; (retries < count); retries++) { + failCode = 0U; + /* Disable PLL1 */ + failCode = disable_plls(SYS_CLKSRC_PLL1); + if (failCode != 0U) { + break; + } + + /* Clear Global Status Register */ + TMS570_SYS1.GLBSTAT = 0x00000301U; + /* Clear the ESM PLL slip flags */ + TMS570_ESM.SR[0U] = ESM_SR1_PLL1SLIP; + /* set PLL1 to OSCIN/1*27/(2*1) */ + TMS570_SYS1.PLLCTL1 = 0x20001A00U; + TMS570_SYS1.PLLCTL2 = 0x3FC0723DU; + TMS570_SYS1.CSDISCLR = SYS_CLKSRC_PLL1; + /* Check for PLL1 valid or PLL1 slip*/ + while (((TMS570_SYS1.CSVSTAT & SYS_CLKSRC_PLL1) == 0U) && + ((TMS570_ESM.SR[0U] & ESM_SR1_PLL1SLIP) == 0U)) { + /* Wait */ + } + /* If PLL1 valid, check the frequency */ + if (((TMS570_ESM.SR[0U] & ESM_SR1_PLL1SLIP) != 0U) || + ((TMS570_SYS1.GLBSTAT & 0x00000300U) != 0U)) { + failCode |= 1U; + } else { + failCode |= check_frequency(dcc1CNT1_CLKSRC_PLL1); + } + if (failCode == 0U) { + break; + } + } + /* To avoid MISRA violation 382S + (void)missing for discarded return value */ + failCode = disable_plls(SYS_CLKSRC_PLL1); + /* restore CLKCNTL, VCLKR and PENA first */ + TMS570_SYS1.CLKCNTL = (clkCntlSav & 0x000F0100U); + /* restore CLKCNTL, VCLK2R */ + TMS570_SYS1.CLKCNTL = clkCntlSav; + return failCode; +} + +/** @fn uint32_t _errata_SSWF021_45_pll2(uint32_t count) + * @brief This handles the errata for PLL2. This function is called in device + * startup + * + * @param[in] count : Number of retries until PLL2 is locked successfully + * Minimum value recommended is 5 + * + * @return 0 = Success (the PLL or both PLLs have successfully locked and then + * been disabled) + * 1 = PLL1 failed to successfully lock in "count" tries + * 2 = PLL2 failed to successfully lock in "count" tries + * 3 = Neither PLL1 nor PLL2 successfully locked in "count" tries + * 4 = The workaround function was not able to disable at least one of + * the PLLs. The most likely reason is that a PLL is already being + * used as a clock source. This can be caused by the workaround + * function being called from the wrong place in the code. + */ +uint32_t _errata_SSWF021_45_pll2(uint32_t count) { + uint32_t failCode, retries, clkCntlSav; + + /* save CLKCNTL */ + clkCntlSav = TMS570_SYS1.CLKCNTL; + /* First set VCLK2 = HCLK */ + TMS570_SYS1.CLKCNTL = clkCntlSav & 0x000F0100U; + /* Now set VCLK = HCLK and enable peripherals */ + TMS570_SYS1.CLKCNTL = SYS_CLKCNTRL_PENA; + failCode = 0U; + for (retries = 0U; (retries < count); retries++) { + failCode = 0U; + /* Disable PLL2 */ + failCode = disable_plls(SYS_CLKSRC_PLL2); + if (failCode != 0U) { + break; + } + + /* Clear Global Status Register */ + TMS570_SYS1.GLBSTAT = 0x00000301U; + /* Clear the ESM PLL slip flags */ + TMS570_ESM.SR4 = ESM_SR4_PLL2SLIP; + /* set PLL2 to OSCIN/1*27/(2*1) */ + TMS570_SYS2.PLLCTL3 = 0x20001A00U; + TMS570_SYS1.CSDISCLR = SYS_CLKSRC_PLL2; + /* Check for PLL2 valid or PLL2 slip */ + while (((TMS570_SYS1.CSVSTAT & SYS_CLKSRC_PLL2) == 0U) && + ((TMS570_ESM.SR4 & ESM_SR4_PLL2SLIP) == 0U)) { + /* Wait */ + } + /* If PLL2 valid, check the frequency */ + if (((TMS570_ESM.SR4 & ESM_SR4_PLL2SLIP) != 0U) || + ((TMS570_SYS1.GLBSTAT & 0x00000300U) != 0U)) { + failCode |= 2U; + } else { + failCode |= (check_frequency(dcc1CNT1_CLKSRC_PLL2) << 1U); + } + if (failCode == 0U) { + break; + } + } + /* To avoid MISRA violation 382S + (void)missing for discarded return value */ + failCode = disable_plls(SYS_CLKSRC_PLL2); + /* restore CLKCNTL, VCLKR and PENA first */ + TMS570_SYS1.CLKCNTL = (clkCntlSav & 0x000F0100U); + /* restore CLKCNTL, VCLK2R */ + TMS570_SYS1.CLKCNTL = clkCntlSav; + return failCode; +} + +/** @fn uint32_t check_frequency(uint32_t cnt1_clksrc) + * @brief This function checks for the PLL frequency. + * + * @param[in] cnt1_clksrc : Clock source for Counter1 + * 0U - PLL1 (clock source 0) + * 1U - PLL2 (clock source 1) + * + * @return DCC Error status + * 0 - DCC error has not occurred + * 1 - DCC error has occurred + */ +static uint32_t check_frequency(uint32_t cnt1_clksrc) { + /* Setup DCC1 */ + /** DCC1 Global Control register configuration */ + TMS570_DCC1.GCTRL = + (uint32_t)0x5U | /** Disable DCC1 */ + (uint32_t)((uint32_t)0x5U << 4U) | /** No Error Interrupt */ + (uint32_t)((uint32_t)0xAU << 8U) | /** Single Shot mode */ + (uint32_t)((uint32_t)0x5U << 12U); /** No Done Interrupt */ + /* Clear ERR and DONE bits */ + TMS570_DCC1.STAT = 3U; + /** DCC1 Clock0 Counter Seed value configuration */ + TMS570_DCC1.CNT0SEED = 68U; + /** DCC1 Clock0 Valid Counter Seed value configuration */ + TMS570_DCC1.VALID0SEED = 4U; + /** DCC1 Clock1 Counter Seed value configuration */ + TMS570_DCC1.CNT1SEED = 972U; + /** DCC1 Clock1 Source 1 Select */ + TMS570_DCC1.CNT1CLKSRC = + (uint32_t)((uint32_t)10U << 12U) | /** DCC Enable / Disable Key */ + (uint32_t)cnt1_clksrc; /** DCC1 Clock Source 1 */ + + TMS570_DCC1.CNT0CLKSRC = + (uint32_t)DCC1_CNT0_OSCIN; /** DCC1 Clock Source 0 */ + + /** DCC1 Global Control register configuration */ + TMS570_DCC1.GCTRL = + (uint32_t)0xAU | /** Enable DCC1 */ + (uint32_t)((uint32_t)0x5U << 4U) | /** No Error Interrupt */ + (uint32_t)((uint32_t)0xAU << 8U) | /** Single Shot mode */ + (uint32_t)((uint32_t)0x5U << 12U); /** No Done Interrupt */ + while (TMS570_DCC1.STAT == 0U) { + /* Wait */ + } + return (TMS570_DCC1.STAT & 0x01U); +} + +/** @fn uint32_t disable_plls(uint32_t plls) + * @brief This function disables plls and clears the respective ESM flags. + * + * @param[in] plls : Clock source for Counter1 + * 2U - PLL1 + * 40U - PLL2 + * + * @return failCode + * 0 = Success (the PLL or both PLLs have successfully locked and + * then been disabled) + * 4 = The workaround function was not able to disable at least one + * of the PLLs. The most likely reason is that a PLL is already being + * used as a clock source. This can be caused by the workaround + * function being called from the wrong place in the code. + */ +static uint32_t disable_plls(uint32_t plls) { + uint32_t timeout, failCode; + + TMS570_SYS1.CSDISSET = plls; + failCode = 0U; + timeout = 0x10U; + timeout--; + while (((TMS570_SYS1.CSVSTAT & (plls)) != 0U) && (timeout != 0U)) { + /* Clear ESM and GLBSTAT PLL slip flags */ + TMS570_SYS1.GLBSTAT = 0x00000300U; + + if ((plls & SYS_CLKSRC_PLL1) == SYS_CLKSRC_PLL1) { + TMS570_ESM.SR[0U] = ESM_SR1_PLL1SLIP; + } + if ((plls & SYS_CLKSRC_PLL2) == SYS_CLKSRC_PLL2) { + TMS570_ESM.SR4 = ESM_SR4_PLL2SLIP; + } + timeout--; + /* Wait */ + } + if (timeout == 0U) { + failCode = 4U; + } else { + failCode = 0U; + } + return failCode; +} diff --git a/bsps/arm/tms570/start/fail_notification.c b/bsps/arm/tms570/start/fail_notification.c index 00276e23d7..54d4e6a37b 100644 --- a/bsps/arm/tms570/start/fail_notification.c +++ b/bsps/arm/tms570/start/fail_notification.c @@ -1,3 +1,45 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This source file contains the default + * bsp_selftest_fail_notification() and + * tms570_memory_port0_fail_notification() implementations. + */ + +/* + * Copyright (C) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz> + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + #include <stdint.h> #include <stdbool.h> #include <bsp/tms570.h> diff --git a/bsps/arm/tms570/start/hwinit-lc4357-hdk.c b/bsps/arm/tms570/start/hwinit-lc4357-hdk.c new file mode 100644 index 0000000000..7c01b8306f --- /dev/null +++ b/bsps/arm/tms570/start/hwinit-lc4357-hdk.c @@ -0,0 +1,329 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This source file contains parts of the system initialization. + */ + +/* + * Copyright (C) 2022 Airbus U.S. Space & Defense, Inc + * Copyright (C) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz> + * Copyright (C) 2009-2015 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include <bsp/tms570.h> +#include <bsp/tms570_hwinit.h> +#include <bsp/tms570-pinmux.h> + +typedef enum Tms570ClockDisableSources { + TMS570_CLKDIS_SRC_OSC = 0x01, ///< External high-speed oscillator as clock source + TMS570_CLKDIS_SRC_PLL1 = 0x02, + TMS570_CLKDIS_SRC_RESERVED = 0x04, ///< reserved. not tied to actual clock source + TMS570_CLKDIS_SRC_EXT_CLK1 = 0x08, + TMS570_CLKDIS_SRC_LOW_FREQ_LPO = 0x10, + TMS570_CLKDIS_SRC_HIGH_FREQ_LPO = 0x20, + TMS570_CLKDIS_SRC_PLL2 = 0x40, + TMS570_CLKDIS_SRC_EXT_CLK2 = 0x80, +} Tms570ClockDisableSources; + +// Source selection for G, H, and V clocks SYS1.GHVSRC reg +typedef enum Tms570GhvClockSources { + TMS570_SYS_CLK_SRC_OSC = 0U, /**< Alias for oscillator clock Source */ + TMS570_SYS_CLK_SRC_PLL1 = 1U, /**< Alias for Pll1 clock Source */ + TMS570_SYS_CLK_SRC_EXTERNAL1 = 3U, /**< Alias for external clock Source */ + TMS570_SYS_CLK_SRC_LPO_LOW = 4U, /**< Alias for low power oscillator low clock Source */ + TMS570_SYS_CLK_SRC_LPO_HIGH = 5U, /**< Alias for low power oscillator high clock Source */ + TMS570_SYS_CLK_SRC_PLL2 = 6U, /**< Alias for Pll2 clock Source */ + TMS570_SYS_CLK_SRC_EXTERNAL2 = 7U, /**< Alias for external 2 clock Source */ + TMS570_SYS_CLK_SRC_VCLK = 9U /**< Alias for synchronous VCLK1 clock Source */ +} Tms570GhvClockSources; + +/* + * The next construct allows to compute values for individual + * PINMMR registers based on the multiple processing + * complete pin functions list at compile time. + * Each line computes 32-bit value which selects function + * of consecutive four pins. Each pin function is defined + * by single byte. + */ +static const uint32_t tms570_pinmmr_init_data[] = { + TMS570_PINMMR_REG_VAL( 0, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 1, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 2, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 3, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 4, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 5, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 6, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 7, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 8, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 9, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 10, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 11, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 12, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 13, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 14, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 15, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 16, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 17, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 18, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 19, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 20, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 21, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 22, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 23, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 24, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 25, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 26, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 27, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 28, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 29, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 30, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 31, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 32, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 33, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 34, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 35, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 36, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 37, TMS570LC4357_PINMMR_DEFAULT_INIT_LIST ), +}; + +void tms570_pinmux_init( void ) +{ + tms570_bsp_pinmmr_config(tms570_pinmmr_init_data, 0, RTEMS_ARRAY_SIZE(tms570_pinmmr_init_data)); + + tms570_pin_config_prepare(); + TMS570_PINMUX[174] = (TMS570_PINMUX[174] & ~(UINT32_C(0x3) << 8)) | (UINT32_C(0x2) << 8); // emif output-enable bit8= 0, bit9= 1 + tms570_pin_config_complete(); +} + +void tms570_emif_sdram_init( void ) +{ + uint32_t dummy; + + /* Do not run attempt to initialize SDRAM when code is running from it */ + if ( tms570_running_from_sdram() ) + return; + + // Following the initialization procedure as described in EMIF-errata #5 for the tms570lc43 + // at EMIF clock rates >= 40Mhz + // Note step one of this procedure is running this EMIF initialization sequence before PLL + // and clocks are mapped/enabled + // For additional details on startup procedure see tms570lc43 TRM s21.2.5.5.B + + // Set SDRAM timings. These are dependent on the EMIF CLK rate, which = VCLK3 + // Set these based on the final EMIF clock rate once PLL & VCLK is enabled + TMS570_EMIF.SDTIMR = (uint32_t)1U << 27U| + (uint32_t)0U << 24U| + (uint32_t)0U << 20U| + (uint32_t)0U << 19U| + (uint32_t)1U << 16U| + (uint32_t)1U << 12U| + (uint32_t)1U << 8U| + (uint32_t)0U << 4U; + + /* Minimum number of ECLKOUT cycles from Self-Refresh exit to any command */ + // Also set this based on the final EMIF clk + TMS570_EMIF.SDSRETR = 2; + // Program the RR Field of SDRCR to provide 200us of initialization time + // Per Errata#5, for EMIF startup, set this based on the non-VLCK3 clk rate. + // The Errata is this register must be calculated as `SDRCR = 200us * EMIF_CLK` + // (typically this would be `SDRCR = (200us * EMIF_CLK) / 8` ) + // Since the PLL's arent enabled yet, EMIF_CLK would be EXT_OSCIN / 2 + TMS570_EMIF.SDRCR = 1600; + + TMS570_EMIF.SDCR = ((uint32_t)0U << 31U)| + ((uint32_t)1U << 14U)| + ((uint32_t)2U << 9U)| + ((uint32_t)1U << 8U)| + ((uint32_t)2U << 4U)| + ((uint32_t)0); // pagesize = 256 + + // Read of SDRAM memory location causes processor to wait until SDRAM Initialization completes + dummy = *(volatile uint32_t*)TMS570_MEMORY_SDRAM_ORIGIN; + (void) dummy; + + // Program the RR field to the default Refresh Interval of the SDRAM + // Program this to the correct interval for the VCLK3/EMIF_CLK rate + // Do this in the typical way per TRM: SDRCR = ((200us * EMIF_CLK) / 8) + 1 + TMS570_EMIF.SDRCR = 1251; + + /* Place the EMIF in Self Refresh Mode For Clock Change */ + /* Must only write to the upper byte of the SDCR to avoid */ + /* a second initialization sequence */ + /* The byte address depends on endian (0x3U in LE, 0x00 in BE32) */ + *((volatile unsigned char *)(&TMS570_EMIF.SDCR) + 0x0U) = 0x80; +} + +/** + * @brief Setup all system PLLs (HCG:setupPLL) + * + */ +void tms570_pll_init( void ) +{ + //based on HalCoGen setupPLL method + uint32_t pll12_dis = TMS570_CLKDIS_SRC_PLL1 | TMS570_CLKDIS_SRC_PLL2; + + /* Disable PLL1 and PLL2 */ + TMS570_SYS1.CSDISSET = pll12_dis; + + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ + while ( ( TMS570_SYS1.CSDIS & pll12_dis ) != pll12_dis ) { + /* Wait */ + } + + /* Clear Global Status Register */ + TMS570_SYS1.GLBSTAT = 0x301U; + + // Configure PLL control registers + + /** - Setup pll control register 1: + * - Disable reset on oscillator slip (ROS) + * - Enable bypass on pll slip + * TODO: desired: switches to OSC when PLL slip detected + * - setup Pll output clock divider to max before Lock + * - Disable reset on oscillator fail + * - Setup reference clock divider + * - Setup Pll multiplier + * + * - PLL1: 16MHz OSC in -> 300MHz PLL1 out + */ + TMS570_SYS1.PLLCTL1 = (TMS570_SYS1_PLLCTL1_ROS * 0) + | (uint32_t)0x40000000U + | TMS570_SYS1_PLLCTL1_PLLDIV(0x1F) + | (TMS570_SYS1_PLLCTL1_ROF * 0) + | TMS570_SYS1_PLLCTL1_REFCLKDIV(4U - 1U) + | TMS570_SYS1_PLLCTL1_PLLMUL((75U - 1U) << 8); + + /** - Setup pll control register 2 + * - Setup spreading rate + * - Setup bandwidth adjustment + * - Setup internal Pll output divider + * - Setup spreading amount + */ + TMS570_SYS1.PLLCTL2 = ((uint32_t)255U << 22U) + | ((uint32_t)7U << 12U) + | ((uint32_t)(1U - 1U) << 9U) + | 61U; + + // Initialize Pll2 + + /** - Setup pll2 control register : + * - setup Pll output clock divider to max before Lock + * - Setup reference clock divider + * - Setup internal Pll output divider + * - Setup Pll multiplier + */ + TMS570_SYS2.PLLCTL3 = TMS570_SYS2_PLLCTL3_ODPLL2(1U - 1U) + | TMS570_SYS2_PLLCTL3_PLLDIV2(0x1FU) + | TMS570_SYS2_PLLCTL3_REFCLKDIV2(8U - 1U) + | TMS570_SYS2_PLLCTL3_PLLMUL2(( 150U - 1U) << 8 ); + + // Enable PLL(s) to start up or Lock + // Enable all clock sources except the following + TMS570_SYS1.CSDIS = (TMS570_CLKDIS_SRC_EXT_CLK2 | TMS570_CLKDIS_SRC_EXT_CLK1 | TMS570_CLKDIS_SRC_RESERVED); +} + +void tms570_map_clock_init(void) +{ + // based on HalCoGen mapClocks method + uint32_t sys_csvstat, sys_csdis; + + TMS570_SYS2.HCLKCNTL = 1U; + + /** @b Initialize @b Clock @b Tree: */ + /** - Disable / Enable clock domain */ + TMS570_SYS1.CDDIS = ( 0U << 4U ) | /* AVCLK 1 ON */ + ( 1U << 5U ) | /* AVCLK 2 OFF */ + ( 0U << 8U ) | /* VCLK3 ON */ + ( 0U << 9U ) | /* VCLK4 ON */ + ( 0U << 10U ) | /* AVCLK 3 ON */ + ( 0U << 11U ); /* AVCLK 4 ON */ + + /* Work Around for Errata SYS#46: + * Despite this being a LS3137 errata, hardware testing on the LC4357 indicates this wait is still necessary + */ + sys_csvstat = TMS570_SYS1.CSVSTAT; + sys_csdis = TMS570_SYS1.CSDIS; + + while ( ( sys_csvstat & ( ( sys_csdis ^ 0xFFU ) & 0xFFU ) ) != + ( ( sys_csdis ^ 0xFFU ) & 0xFFU ) ) { + sys_csvstat = TMS570_SYS1.CSVSTAT; + sys_csdis = TMS570_SYS1.CSDIS; + } + + TMS570_SYS1.GHVSRC = TMS570_SYS1_GHVSRC_GHVWAKE(TMS570_SYS_CLK_SRC_PLL1) + | TMS570_SYS1_GHVSRC_HVLPM(TMS570_SYS_CLK_SRC_PLL1) + | TMS570_SYS1_GHVSRC_GHVSRC(TMS570_SYS_CLK_SRC_PLL1); + + /** - Setup RTICLK1 and RTICLK2 clocks */ + TMS570_SYS1.RCLKSRC = ((uint32_t)1U << 24U) /* RTI2 divider (Not applicable for lock-step device) */ + | ((uint32_t)TMS570_SYS_CLK_SRC_VCLK << 16U) /* RTI2 clock source (Not applicable for lock-step device) Field not in TRM? */ + | ((uint32_t)1U << 8U) /* RTI1 divider */ + | ((uint32_t)TMS570_SYS_CLK_SRC_VCLK << 0U); /* RTI1 clock source */ + + /** - Setup asynchronous peripheral clock sources for AVCLK1 and AVCLK2 */ + TMS570_SYS1.VCLKASRC = TMS570_SYS1_VCLKASRC_VCLKA2S(TMS570_SYS_CLK_SRC_VCLK) + | TMS570_SYS1_VCLKASRC_VCLKA1S(TMS570_SYS_CLK_SRC_VCLK); + + /** - Setup synchronous peripheral clock dividers for VCLK1, VCLK2, VCLK3 */ + + // VCLK2 = PLL1 / HCLK_DIV / 2 = 75MHz + TMS570_SYS1.CLKCNTL = (TMS570_SYS1.CLKCNTL & ~TMS570_SYS1_CLKCNTL_VCLK2R(0xF)) + | TMS570_SYS1_CLKCNTL_VCLK2R(0x1); + // VLCK1 = PLL1 / HCLK_DIV / 2 = 75MHz + TMS570_SYS1.CLKCNTL = (TMS570_SYS1.CLKCNTL & ~TMS570_SYS1_CLKCNTL_VCLKR(0xF)) + | TMS570_SYS1_CLKCNTL_VCLKR(0x1); + + // VCLK3 = PLL1 / HCLK_DIV / 3 = 50MHz + TMS570_SYS2.CLK2CNTRL = (TMS570_SYS2.CLK2CNTRL & ~TMS570_SYS2_CLK2CNTRL_VCLK3R(0xF)) + | TMS570_SYS2_CLK2CNTRL_VCLK3R(0x2); + + TMS570_SYS2.VCLKACON1 = TMS570_SYS2_VCLKACON1_VCLKA4R(1U - 1U) + | (TMS570_SYS2_VCLKACON1_VCLKA4_DIV_CDDIS * 0) + | TMS570_SYS2_VCLKACON1_VCLKA4S(TMS570_SYS_CLK_SRC_VCLK) + | TMS570_SYS2_VCLKACON1_VCLKA3R(1U - 1U) + | (TMS570_SYS2_VCLKACON1_VCLKA3_DIV_CDDIS * 0) + | TMS570_SYS2_VCLKACON1_VCLKA3S(TMS570_SYS_CLK_SRC_VCLK); + + /* Now the PLLs are locked and the PLL outputs can be sped up */ + /* The R-divider was programmed to be 0xF. Now this divider is changed to programmed value */ + TMS570_SYS1.PLLCTL1 = (TMS570_SYS1.PLLCTL1 & 0xE0FFFFFFU) | (uint32_t)((uint32_t)(1U - 1U) << 24U); + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> " Clear and write to the volatile register " */ + TMS570_SYS2.PLLCTL3 = (TMS570_SYS2.PLLCTL3 & 0xE0FFFFFFU) | (uint32_t)((uint32_t)(1U - 1U) << 24U); + + /* Enable/Disable Frequency modulation */ + TMS570_SYS1.PLLCTL2 |= 0x00000000U; +} diff --git a/bsps/arm/tms570/start/hwinit-ls3137-hdk.c b/bsps/arm/tms570/start/hwinit-ls3137-hdk.c new file mode 100644 index 0000000000..1f2bbd96f2 --- /dev/null +++ b/bsps/arm/tms570/start/hwinit-ls3137-hdk.c @@ -0,0 +1,446 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This source file contains parts of the system initialization. + */ + +/* + * Copyright (C) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz> + * Copyright (C) 2009-2015 Texas Instruments Incorporated - www.ti.com + * + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the + * distribution. + * + * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include <bsp/tms570.h> +#include <bsp/tms570_hwinit.h> +#include <bsp/tms570-pinmux.h> + +enum tms570_system_clock_source { + TMS570_SYS_CLK_SRC_OSC = 0U, /**< Alias for oscillator clock Source */ + TMS570_SYS_CLK_SRC_PLL1 = 1U, /**< Alias for Pll1 clock Source */ + TMS570_SYS_CLK_SRC_EXTERNAL1 = 3U, /**< Alias for external clock Source */ + TMS570_SYS_CLK_SRC_LPO_LOW = 4U, /**< Alias for low power oscillator low clock Source */ + TMS570_SYS_CLK_SRC_LPO_HIGH = 5U, /**< Alias for low power oscillator high clock Source */ + TMS570_SYS_CLK_SRC_PLL2 = 6U, /**< Alias for Pll2 clock Source */ + TMS570_SYS_CLK_SRC_EXTERNAL2 = 7U, /**< Alias for external 2 clock Source */ + TMS570_SYS_CLK_SRC_VCLK = 9U /**< Alias for synchronous VCLK1 clock Source */ +}; + +/* + * Definition of fuctions for all pins of TMS570LS3137. + * This setup correctponds to TMS570LS31x HDK Kit + */ + +#define TMS570_PINMMR_INIT_LIST( per_pin_action, common_arg ) \ + per_pin_action( common_arg, TMS570_BALL_W10_GIOB_3 ) \ + per_pin_action( common_arg, TMS570_BALL_A5_GIOA_0 ) \ + per_pin_action( common_arg, TMS570_BALL_C3_MIBSPI3NCS_3 ) \ + per_pin_action( common_arg, TMS570_BALL_B2_MIBSPI3NCS_2 ) \ + per_pin_action( common_arg, TMS570_BALL_C2_GIOA_1 ) \ + per_pin_action( common_arg, TMS570_BALL_E3_HET1_11 ) \ + per_pin_action( common_arg, TMS570_BALL_E5_EMIF_DATA_4 ) \ + per_pin_action( common_arg, TMS570_BALL_F5_EMIF_DATA_5 ) \ + per_pin_action( common_arg, TMS570_BALL_C1_GIOA_2 ) \ + per_pin_action( common_arg, TMS570_BALL_G5_EMIF_DATA_6 ) \ + per_pin_action( common_arg, TMS570_BALL_E1_GIOA_3 ) \ + per_pin_action( common_arg, TMS570_BALL_B5_GIOA_5 ) \ + per_pin_action( common_arg, TMS570_BALL_K5_EMIF_DATA_7 ) \ + per_pin_action( common_arg, TMS570_BALL_B3_HET1_22 ) \ + per_pin_action( common_arg, TMS570_BALL_H3_GIOA_6 ) \ + per_pin_action( common_arg, TMS570_BALL_L5_EMIF_DATA_8 ) \ + per_pin_action( common_arg, TMS570_BALL_M1_GIOA_7 ) \ + per_pin_action( common_arg, TMS570_BALL_M5_EMIF_DATA_9 ) \ + per_pin_action( common_arg, TMS570_BALL_V2_HET1_01 ) \ + per_pin_action( common_arg, TMS570_BALL_U1_HET1_03 ) \ + per_pin_action( common_arg, TMS570_BALL_K18_HET1_00 ) \ + per_pin_action( common_arg, TMS570_BALL_W5_HET1_02 ) \ + per_pin_action( common_arg, TMS570_BALL_V6_HET1_05 ) \ + per_pin_action( common_arg, TMS570_BALL_N5_EMIF_DATA_10 ) \ + per_pin_action( common_arg, TMS570_BALL_T1_HET1_07 ) \ + per_pin_action( common_arg, TMS570_BALL_P5_EMIF_DATA_11 ) \ + per_pin_action( common_arg, TMS570_BALL_V7_HET1_09 ) \ + per_pin_action( common_arg, TMS570_BALL_R5_EMIF_DATA_12 ) \ + per_pin_action( common_arg, TMS570_BALL_R6_EMIF_DATA_13 ) \ + per_pin_action( common_arg, TMS570_BALL_V5_MIBSPI3NCS_1 ) \ + per_pin_action( common_arg, TMS570_BALL_W3_SCIRX ) \ + per_pin_action( common_arg, TMS570_BALL_R7_EMIF_DATA_14 ) \ + per_pin_action( common_arg, TMS570_BALL_N2_SCITX ) \ + per_pin_action( common_arg, TMS570_BALL_G3_MIBSPI1NCS_2 ) \ + per_pin_action( common_arg, TMS570_BALL_N1_HET1_15 ) \ + per_pin_action( common_arg, TMS570_BALL_R8_EMIF_DATA_15 ) \ + per_pin_action( common_arg, TMS570_BALL_R9_ETMTRACECLKIN ) \ + per_pin_action( common_arg, TMS570_BALL_W9_MIBSPI3NENA ) \ + per_pin_action( common_arg, TMS570_BALL_V10_MIBSPI3NCS_0 ) \ + per_pin_action( common_arg, TMS570_BALL_J3_MIBSPI1NCS_3 ) \ + per_pin_action( common_arg, TMS570_BALL_N19_AD1EVT ) \ + per_pin_action( common_arg, TMS570_BALL_N15_EMIF_DATA_3 ) \ + per_pin_action( common_arg, TMS570_BALL_N17_EMIF_nCS_0 ) \ + per_pin_action( common_arg, TMS570_BALL_M15_EMIF_DATA_2 ) \ + per_pin_action( common_arg, TMS570_BALL_K17_EMIF_nCS_3 ) \ + per_pin_action( common_arg, TMS570_BALL_M17_EMIF_nCS_4 ) \ + per_pin_action( common_arg, TMS570_BALL_L15_EMIF_DATA_1 ) \ + per_pin_action( common_arg, TMS570_BALL_P1_HET1_24 ) \ + per_pin_action( common_arg, TMS570_BALL_A14_HET1_26 ) \ + per_pin_action( common_arg, TMS570_BALL_K15_EMIF_DATA_0 ) \ + per_pin_action( common_arg, TMS570_BALL_G19_MIBSPI1NENA ) \ + per_pin_action( common_arg, TMS570_BALL_H18_MIBSPI5NENA ) \ + per_pin_action( common_arg, TMS570_BALL_J18_MIBSPI5SOMI_0 ) \ + per_pin_action( common_arg, TMS570_BALL_J19_MIBSPI5SIMO_0 ) \ + per_pin_action( common_arg, TMS570_BALL_H19_MIBSPI5CLK ) \ + per_pin_action( common_arg, TMS570_BALL_R2_MIBSPI1NCS_0 ) \ + per_pin_action( common_arg, TMS570_BALL_E18_HET1_08 ) \ + per_pin_action( common_arg, TMS570_BALL_K19_HET1_28 ) \ + per_pin_action( common_arg, TMS570_BALL_D17_EMIF_nWE ) \ + per_pin_action( common_arg, TMS570_BALL_D16_EMIF_BA_1 ) \ + per_pin_action( common_arg, TMS570_BALL_C17_EMIF_ADDR_21 ) \ + per_pin_action( common_arg, TMS570_BALL_C16_EMIF_ADDR_20 ) \ + per_pin_action( common_arg, TMS570_BALL_C15_EMIF_ADDR_19 ) \ + per_pin_action( common_arg, TMS570_BALL_D15_EMIF_ADDR_18 ) \ + per_pin_action( common_arg, TMS570_BALL_E13_EMIF_BA_0 ) \ + per_pin_action( common_arg, TMS570_BALL_C14_EMIF_ADDR_17 ) \ + per_pin_action( common_arg, TMS570_BALL_D14_EMIF_ADDR_16 ) \ + per_pin_action( common_arg, TMS570_BALL_E12_EMIF_nOE ) \ + per_pin_action( common_arg, TMS570_BALL_D19_HET1_10 ) \ + per_pin_action( common_arg, TMS570_BALL_E11_EMIF_nDQM_1 ) \ + per_pin_action( common_arg, TMS570_BALL_B4_HET1_12 ) \ + per_pin_action( common_arg, TMS570_BALL_E9_EMIF_ADDR_5 ) \ + per_pin_action( common_arg, TMS570_BALL_C13_EMIF_ADDR_15 ) \ + per_pin_action( common_arg, TMS570_BALL_A11_HET1_14 ) \ + per_pin_action( common_arg, TMS570_BALL_C12_EMIF_ADDR_14 ) \ + per_pin_action( common_arg, TMS570_BALL_M2_GIOB_0 ) \ + per_pin_action( common_arg, TMS570_BALL_E8_EMIF_ADDR_4 ) \ + per_pin_action( common_arg, TMS570_BALL_B11_HET1_30 ) \ + per_pin_action( common_arg, TMS570_BALL_E10_EMIF_nDQM_0 ) \ + per_pin_action( common_arg, TMS570_BALL_E7_EMIF_ADDR_3 ) \ + per_pin_action( common_arg, TMS570_BALL_C11_EMIF_ADDR_13 ) \ + per_pin_action( common_arg, TMS570_BALL_C10_EMIF_ADDR_12 ) \ + per_pin_action( common_arg, TMS570_BALL_F3_MIBSPI1NCS_1 ) \ + per_pin_action( common_arg, TMS570_BALL_C9_EMIF_ADDR_11 ) \ + per_pin_action( common_arg, TMS570_BALL_D5_EMIF_ADDR_1 ) \ + per_pin_action( common_arg, TMS570_BALL_K2_GIOB_1 ) \ + per_pin_action( common_arg, TMS570_BALL_C8_EMIF_ADDR_10 ) \ + per_pin_action( common_arg, TMS570_BALL_C7_EMIF_ADDR_9 ) \ + per_pin_action( common_arg, TMS570_BALL_D4_EMIF_ADDR_0 ) \ + per_pin_action( common_arg, TMS570_BALL_C5_EMIF_ADDR_7 ) \ + per_pin_action( common_arg, TMS570_BALL_C4_EMIF_ADDR_6 ) \ + per_pin_action( common_arg, TMS570_BALL_E6_EMIF_ADDR_2 ) \ + per_pin_action( common_arg, TMS570_BALL_C6_EMIF_ADDR_8 ) \ + per_pin_action( common_arg, TMS570_MMR_SELECT_SPI4CLK ) \ + per_pin_action( common_arg, TMS570_MMR_SELECT_SPI4SIMO ) \ + per_pin_action( common_arg, TMS570_MMR_SELECT_SPI4SOMI ) \ + per_pin_action( common_arg, TMS570_MMR_SELECT_SPI4NENA ) \ + per_pin_action( common_arg, TMS570_MMR_SELECT_SPI4NCS_0 ) \ + per_pin_action( common_arg, TMS570_BALL_A13_HET1_17 ) \ + per_pin_action( common_arg, TMS570_BALL_B13_HET1_19 ) \ + per_pin_action( common_arg, TMS570_BALL_H4_HET1_21 ) \ + per_pin_action( common_arg, TMS570_BALL_J4_HET1_23 ) \ + per_pin_action( common_arg, TMS570_BALL_M3_HET1_25 ) \ + per_pin_action( common_arg, TMS570_BALL_A9_HET1_27 ) \ + per_pin_action( common_arg, TMS570_BALL_A3_HET1_29 ) \ + per_pin_action( common_arg, TMS570_BALL_J17_HET1_31 ) \ + per_pin_action( common_arg, TMS570_BALL_W6_MIBSPI5NCS_2 ) \ + per_pin_action( common_arg, TMS570_BALL_T12_MIBSPI5NCS_3 ) \ + per_pin_action( common_arg, TMS570_BALL_E19_MIBSPI5NCS_0 ) \ + per_pin_action( common_arg, TMS570_BALL_B6_MIBSPI5NCS_1 ) \ + per_pin_action( common_arg, TMS570_BALL_E16_MIBSPI5SIMO_1 ) \ + per_pin_action( common_arg, TMS570_BALL_H17_MIBSPI5SIMO_2 ) \ + per_pin_action( common_arg, TMS570_BALL_G17_MIBSPI5SIMO_3 ) \ + per_pin_action( common_arg, TMS570_BALL_E17_MIBSPI5SOMI_1 ) \ + per_pin_action( common_arg, TMS570_BALL_H16_MIBSPI5SOMI_2 ) \ + per_pin_action( common_arg, TMS570_BALL_G16_MIBSPI5SOMI_3 ) \ + per_pin_action( common_arg, TMS570_BALL_D3_SPI2NENA ) \ + per_pin_action( common_arg, \ + TMS570_MMR_SELECT_EMIF_CLK_SEL | TMS570_PIN_CLEAR_RQ_MASK ) \ + per_pin_action( common_arg, \ + TMS570_BALL_F2_GIOB_2 | TMS570_PIN_CLEAR_RQ_MASK ) \ + per_pin_action( common_arg, \ + TMS570_MMR_SELECT_MII_MODE | TMS570_PIN_CLEAR_RQ_MASK ) \ + per_pin_action( common_arg, TMS570_MMR_SELECT_ADC_TRG1 ) + +/* + * The next construct allows to compute values for individual + * PINMMR registers based on the multiple processing + * complete pin functions list at compile time. + * Each line computes 32-bit value which selects function + * of consecutive four pins. Each pin function is defined + * by single byte. + */ +static const uint32_t tms570_pinmmr_init_data[] = { + TMS570_PINMMR_REG_VAL( 0, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 1, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 2, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 3, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 4, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 5, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 6, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 7, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 8, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 9, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 10, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 11, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 12, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 13, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 14, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 15, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 16, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 17, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 18, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 19, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 20, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 21, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 22, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 23, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 24, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 25, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 26, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 27, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 28, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 29, TMS570_PINMMR_INIT_LIST ), + TMS570_PINMMR_REG_VAL( 30, TMS570_PINMMR_INIT_LIST ), +}; + +/** + * @brief setups pin multiplexer according to precomputed registers values (HCG:muxInit) + */ +void tms570_pinmux_init( void ) +{ + tms570_bsp_pinmmr_config( tms570_pinmmr_init_data, 0, + RTEMS_ARRAY_SIZE( tms570_pinmmr_init_data ) ); +} + +void tms570_emif_sdram_init(void) +{ + uint32_t dummy; + uint32_t sdtimr = 0; + uint32_t sdcr = 0; + + /* Do not run attempt to initialize SDRAM when code is running from it */ + if ( tms570_running_from_sdram() ) + return; + + sdtimr = TMS570_EMIF_SDTIMR_T_RFC_SET( sdtimr, 6 - 1 ); + sdtimr = TMS570_EMIF_SDTIMR_T_RP_SET( sdtimr, 2 - 1 ); + sdtimr = TMS570_EMIF_SDTIMR_T_RCD_SET( sdtimr, 2 - 1 ); + sdtimr = TMS570_EMIF_SDTIMR_T_WR_SET( sdtimr, 2 - 1 ); + sdtimr = TMS570_EMIF_SDTIMR_T_RAS_SET( sdtimr, 4 - 1 ); + sdtimr = TMS570_EMIF_SDTIMR_T_RC_SET( sdtimr, 6 - 1 ); + sdtimr = TMS570_EMIF_SDTIMR_T_RRD_SET( sdtimr, 2 - 1 ); + + TMS570_EMIF.SDTIMR = sdtimr; + + /* Minimum number of ECLKOUT cycles from Self-Refresh exit to any command */ + TMS570_EMIF.SDSRETR = 5; + /* Define the SDRAM refresh period in terms of EMIF_CLK cycles. */ + TMS570_EMIF.SDRCR = 2000; + + /* SR - Self-Refresh mode bit. */ + sdcr |= TMS570_EMIF_SDCR_SR * 0; + /* field: PD - Power Down bit controls entering and exiting of the power-down mode. */ + sdcr |= TMS570_EMIF_SDCR_PD * 0; + /* PDWR - Perform refreshes during power down. */ + sdcr |= TMS570_EMIF_SDCR_PDWR * 0; + /* NM - Narrow mode bit defines whether SDRAM is 16- or 32-bit-wide */ + sdcr |= TMS570_EMIF_SDCR_NM * 1; + /* CL - CAS Latency. */ + sdcr = TMS570_EMIF_SDCR_CL_SET( sdcr, 2 ); + /* CL can only be written if BIT11_9LOCK is simultaneously written with a 1. */ + sdcr |= TMS570_EMIF_SDCR_BIT11_9LOCK * 1; + /* IBANK - Internal SDRAM Bank size. */ + sdcr = TMS570_EMIF_SDCR_IBANK_SET( sdcr, 2 ); /* 4-banks device */ + /* Page Size. This field defines the internal page size of connected SDRAM devices. */ + sdcr = TMS570_EMIF_SDCR_PAGESIZE_SET( sdcr, 0 ); /* elements_256 */ + + TMS570_EMIF.SDCR = sdcr; + + dummy = *(volatile uint32_t*)TMS570_MEMORY_SDRAM_ORIGIN; + (void) dummy; + TMS570_EMIF.SDRCR = 31; + + /* Define the SDRAM refresh period in terms of EMIF_CLK cycles. */ + TMS570_EMIF.SDRCR = 312; +} + +/** + * @brief Setup all system PLLs (HCG:setupPLL) + * + */ +void tms570_pll_init( void ) +{ + uint32_t pll12_dis = 0x42; + + /* Disable PLL1 and PLL2 */ + TMS570_SYS1.CSDISSET = pll12_dis; + + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ + while ( ( TMS570_SYS1.CSDIS & pll12_dis ) != pll12_dis ) { + /* Wait */ + } + + /* Clear Global Status Register */ + TMS570_SYS1.GLBSTAT = TMS570_SYS1_GLBSTAT_FBSLIP | + TMS570_SYS1_GLBSTAT_RFSLIP | + TMS570_SYS1_GLBSTAT_OSCFAIL; + /** - Configure PLL control registers */ + /** @b Initialize @b Pll1: */ + + /* Setup pll control register 1 */ + TMS570_SYS1.PLLCTL1 = TMS570_SYS1_PLLCTL1_ROS * 0 | + TMS570_SYS1_PLLCTL1_MASK_SLIP( 1 ) | + TMS570_SYS1_PLLCTL1_PLLDIV( 0x1f ) | /* max value */ + TMS570_SYS1_PLLCTL1_ROF * 0 | + TMS570_SYS1_PLLCTL1_REFCLKDIV( 6 - 1 ) | + TMS570_SYS1_PLLCTL1_PLLMUL( ( 120 - 1 ) << 8 ); + + /* Setup pll control register 2 */ + TMS570_SYS1.PLLCTL2 = TMS570_SYS1_PLLCTL2_FMENA * 0 | + TMS570_SYS1_PLLCTL2_SPREADINGRATE( 255 ) | + TMS570_SYS1_PLLCTL2_MULMOD( 7 ) | + TMS570_SYS1_PLLCTL2_ODPLL( 2 - 1 ) | + TMS570_SYS1_PLLCTL2_SPR_AMOUNT( 61 ); + + /** @b Initialize @b Pll2: */ + + /* Setup pll2 control register */ + TMS570_SYS2.PLLCTL3 = TMS570_SYS2_PLLCTL3_ODPLL2( 2 - 1 ) | + TMS570_SYS2_PLLCTL3_PLLDIV2( 0x1F ) | /* max value */ + TMS570_SYS2_PLLCTL3_REFCLKDIV2( 6 - 1 ) | + TMS570_SYS2_PLLCTL3_PLLMUL2( ( 120 - 1 ) << 8 ); + + /** - Enable PLL(s) to start up or Lock */ + TMS570_SYS1.CSDIS = 0x00000000 | /* CLKSR0 on */ + 0x00000000 | /* CLKSR1 on */ + 0x00000008 | /* CLKSR3 off */ + 0x00000000 | /* CLKSR4 on */ + 0x00000000 | /* CLKSR5 on */ + 0x00000000 | /* CLKSR6 on */ + 0x00000080; /* CLKSR7 off */ +} + +/** + * @brief Setup chip clocks including to wait for PLLs locks (HCG:mapClocks) + * + */ +/* SourceId : SYSTEM_SourceId_005 */ +/* DesignId : SYSTEM_DesignId_005 */ +/* Requirements : HL_SR469 */ +void tms570_map_clock_init( void ) +{ + uint32_t sys_csvstat, sys_csdis; + + /** @b Initialize @b Clock @b Tree: */ + /** - Disable / Enable clock domain */ + TMS570_SYS1.CDDIS = ( 0U << 4U ) | /* AVCLK 1 OFF */ + ( 0U << 5U ) | /* AVCLK 2 OFF */ + ( 0U << 8U ) | /* VCLK3 OFF */ + ( 0U << 9U ) | /* VCLK4 OFF */ + ( 1U << 10U ) | /* AVCLK 3 OFF */ + ( 0U << 11U ); /* AVCLK 4 OFF */ + + /* Work Around for Errata SYS#46: + * + * Errata Description: + * Clock Source Switching Not Qualified with Clock Source Enable And Clock Source Valid + * Workaround: + * Always check the CSDIS register to make sure the clock source is turned on and check + * the CSVSTAT register to make sure the clock source is valid. Then write to GHVSRC to switch the clock. + */ + /** - Wait for until clocks are locked */ + sys_csvstat = TMS570_SYS1.CSVSTAT; + sys_csdis = TMS570_SYS1.CSDIS; + + while ( ( sys_csvstat & ( ( sys_csdis ^ 0xFFU ) & 0xFFU ) ) != + ( ( sys_csdis ^ 0xFFU ) & 0xFFU ) ) { + sys_csvstat = TMS570_SYS1.CSVSTAT; + sys_csdis = TMS570_SYS1.CSDIS; + } /* Wait */ + + /* Now the PLLs are locked and the PLL outputs can be sped up */ + /* The R-divider was programmed to be 0xF. Now this divider is changed to programmed value */ + TMS570_SYS1.PLLCTL1 = + ( TMS570_SYS1.PLLCTL1 & ~TMS570_SYS1_PLLCTL1_PLLDIV( 0x1F ) ) | + TMS570_SYS1_PLLCTL1_PLLDIV( 1 - 1 ); + /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ + TMS570_SYS2.PLLCTL3 = + ( TMS570_SYS2.PLLCTL3 & ~TMS570_SYS2_PLLCTL3_PLLDIV2( 0x1F ) ) | + TMS570_SYS2_PLLCTL3_PLLDIV2( 1 - 1 ); + + /* Enable/Disable Frequency modulation */ + TMS570_SYS1.PLLCTL2 &= ~TMS570_SYS1_PLLCTL2_FMENA; + + /** - Map device clock domains to desired sources and configure top-level dividers */ + /** - All clock domains are working off the default clock sources until now */ + /** - The below assignments can be easily modified using the HALCoGen GUI */ + + /** - Setup GCLK, HCLK and VCLK clock source for normal operation, power down mode and after wakeup */ + TMS570_SYS1.GHVSRC = TMS570_SYS1_GHVSRC_GHVWAKE( TMS570_SYS_CLK_SRC_OSC ) | + TMS570_SYS1_GHVSRC_HVLPM( TMS570_SYS_CLK_SRC_OSC ) | + TMS570_SYS1_GHVSRC_GHVSRC( TMS570_SYS_CLK_SRC_PLL1 ); + + /** - Setup synchronous peripheral clock dividers for VCLK1, VCLK2, VCLK3 */ + TMS570_SYS1.CLKCNTL = + ( TMS570_SYS1.CLKCNTL & ~TMS570_SYS1_CLKCNTL_VCLK2R( 0xF ) ) | + TMS570_SYS1_CLKCNTL_VCLK2R( 1 ); + + TMS570_SYS1.CLKCNTL = + ( TMS570_SYS1.CLKCNTL & ~TMS570_SYS1_CLKCNTL_VCLKR( 0xF ) ) | + TMS570_SYS1_CLKCNTL_VCLKR( 1 ); + + TMS570_SYS2.CLK2CNTRL = + ( TMS570_SYS2.CLK2CNTRL & ~TMS570_SYS2_CLK2CNTRL_VCLK3R( 0xF ) ) | + TMS570_SYS2_CLK2CNTRL_VCLK3R( 1 ); + + TMS570_SYS2.CLK2CNTRL = ( TMS570_SYS2.CLK2CNTRL & 0xFFFFF0FFU ) | + ( 1U << 8U ); /* FIXME: unknown in manual*/ + + /** - Setup RTICLK1 and RTICLK2 clocks */ + TMS570_SYS1.RCLKSRC = ( 1U << 24U ) | + ( TMS570_SYS_CLK_SRC_VCLK << 16U ) | /* FIXME: not in manual */ + TMS570_SYS1_RCLKSRC_RTI1DIV( 1 ) | + TMS570_SYS1_RCLKSRC_RTI1SRC( TMS570_SYS_CLK_SRC_VCLK ); + + /** - Setup asynchronous peripheral clock sources for AVCLK1 and AVCLK2 */ + TMS570_SYS1.VCLKASRC = + TMS570_SYS1_VCLKASRC_VCLKA2S( TMS570_SYS_CLK_SRC_VCLK ) | + TMS570_SYS1_VCLKASRC_VCLKA1S( TMS570_SYS_CLK_SRC_VCLK ); + + TMS570_SYS2.VCLKACON1 = TMS570_SYS2_VCLKACON1_VCLKA4R( 1 - 1 ) | + TMS570_SYS2_VCLKACON1_VCLKA4_DIV_CDDIS * 0 | + TMS570_SYS2_VCLKACON1_VCLKA4S( + TMS570_SYS_CLK_SRC_VCLK ) | + TMS570_SYS2_VCLKACON1_VCLKA3R( 1 - 1 ) | + TMS570_SYS2_VCLKACON1_VCLKA3_DIV_CDDIS * 0 | + TMS570_SYS2_VCLKACON1_VCLKA3S( + TMS570_SYS_CLK_SRC_VCLK ); +} diff --git a/bsps/arm/tms570/start/init_emif_sdram.c b/bsps/arm/tms570/start/init_emif_sdram.c deleted file mode 100644 index 2ce7946203..0000000000 --- a/bsps/arm/tms570/start/init_emif_sdram.c +++ /dev/null @@ -1,64 +0,0 @@ -/** - * @file - * - * @ingroup RTEMSBSPsARMTMS570 - * - * @brief Initialization of external memory/SDRAM interface. - */ - -#include <stdint.h> -#include <bsp/tms570.h> -#include <bsp/tms570_hwinit.h> - -void tms570_emif_sdram_init( void ) -{ - uint32_t dummy; - uint32_t sdtimr = 0; - uint32_t sdcr = 0; - - /* Do not run attempt to initialize SDRAM when code is running from it */ - if ( ( (void*)tms570_emif_sdram_init >= (void*)TMS570_SDRAM_START_PTR ) && - ( (void*)tms570_emif_sdram_init <= (void*)TMS570_SDRAM_WINDOW_END_PTR ) ) - return; - - sdtimr = TMS570_EMIF_SDTIMR_T_RFC_SET( sdtimr, 6 - 1 ); - sdtimr = TMS570_EMIF_SDTIMR_T_RP_SET( sdtimr, 2 - 1 ); - sdtimr = TMS570_EMIF_SDTIMR_T_RCD_SET( sdtimr, 2 - 1 ); - sdtimr = TMS570_EMIF_SDTIMR_T_WR_SET( sdtimr, 2 - 1 ); - sdtimr = TMS570_EMIF_SDTIMR_T_RAS_SET( sdtimr, 4 - 1 ); - sdtimr = TMS570_EMIF_SDTIMR_T_RC_SET( sdtimr, 6 - 1 ); - sdtimr = TMS570_EMIF_SDTIMR_T_RRD_SET( sdtimr, 2 - 1 ); - - TMS570_EMIF.SDTIMR = sdtimr; - - /* Minimum number of ECLKOUT cycles from Self-Refresh exit to any command */ - TMS570_EMIF.SDSRETR = 5; - /* Define the SDRAM refresh period in terms of EMIF_CLK cycles. */ - TMS570_EMIF.SDRCR = 2000; - - /* SR - Self-Refresh mode bit. */ - sdcr |= TMS570_EMIF_SDCR_SR * 0; - /* field: PD - Power Down bit controls entering and exiting of the power-down mode. */ - sdcr |= TMS570_EMIF_SDCR_PD * 0; - /* PDWR - Perform refreshes during power down. */ - sdcr |= TMS570_EMIF_SDCR_PDWR * 0; - /* NM - Narrow mode bit defines whether SDRAM is 16- or 32-bit-wide */ - sdcr |= TMS570_EMIF_SDCR_NM * 1; - /* CL - CAS Latency. */ - sdcr = TMS570_EMIF_SDCR_CL_SET( sdcr, 2 ); - /* CL can only be written if BIT11_9LOCK is simultaneously written with a 1. */ - sdcr |= TMS570_EMIF_SDCR_BIT11_9LOCK * 1; - /* IBANK - Internal SDRAM Bank size. */ - sdcr = TMS570_EMIF_SDCR_IBANK_SET( sdcr, 2 ); /* 4-banks device */ - /* Page Size. This field defines the internal page size of connected SDRAM devices. */ - sdcr = TMS570_EMIF_SDCR_PAGESIZE_SET( sdcr, 0 ); /* elements_256 */ - - TMS570_EMIF.SDCR = sdcr; - - dummy = *(volatile uint32_t*)TMS570_SDRAM_START_PTR; - (void) dummy; - TMS570_EMIF.SDRCR = 31; - - /* Define the SDRAM refresh period in terms of EMIF_CLK cycles. */ - TMS570_EMIF.SDRCR = 312; -} diff --git a/bsps/arm/tms570/start/init_esm.c b/bsps/arm/tms570/start/init_esm.c index fdc7f94b90..35fd1c8eab 100644 --- a/bsps/arm/tms570/start/init_esm.c +++ b/bsps/arm/tms570/start/init_esm.c @@ -1,9 +1,42 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * * @ingroup RTEMSBSPsARMTMS570 * - * @brief Error signaling module initialization + * @brief This source file contains the error signaling module initialization. + */ + +/* + * Copyright (C) 2022 Airbus U.S. Space & Defense, Inc + * Copyright (C) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz> + * + * Czech Technical University in Prague + * Zikova 1903/4 + * 166 36 Praha 6 + * Czech Republic + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include <stdint.h> @@ -36,8 +69,12 @@ void tms570_esm_init( void ) /** - Reset error pin */ if (TMS570_ESM.EPSR == 0U) { - TMS570_ESM.EKR = 0x00000005U; - } else { + /* + * Per TMS570LC4x Errata DEVICE#60, the error pin cannot be cleared with a + * normal EKR write upon system reset. Put in diagnostic followed by + * normal mode instead. This sequence works also on other chip variants. + */ + TMS570_ESM.EKR = 0x0000000AU; TMS570_ESM.EKR = 0x00000000U; } diff --git a/bsps/arm/tms570/start/init_pinmux.c b/bsps/arm/tms570/start/init_pinmux.c deleted file mode 100644 index e86a115541..0000000000 --- a/bsps/arm/tms570/start/init_pinmux.c +++ /dev/null @@ -1,259 +0,0 @@ -/** - * @file - * - * @ingroup RTEMSBSPsARMTMS570 - * - * @brief Initialize pin multiplexers. - */ -/* - * Copyright (c) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz> - * - * Czech Technical University in Prague - * Zikova 1903/4 - * 166 36 Praha 6 - * Czech Republic - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#include <stdint.h> -#include <bsp/tms570.h> -#include <bsp/tms570-pinmux.h> -#include <rtems.h> -#include <bsp/tms570_hwinit.h> - -/* - * To check that content is right generated use - * - * objdump --section=.rodata -s init_pinmux.o - */ -#if 0 - -/* - * Test of use of the default pins configuration with one line added. - * This can be used to concatenate partial lists but care has to - * be taken to not attempt to override already defined pin. - * This would not work and result in two PINMMR bits set - * for given pine. - */ - -#ifndef TMS570_PINMMR_INIT_LIST - #define TMS570_PINMMR_INIT_LIST(per_pin_action, common_arg) \ - TMS570_PINMMR_DEFAULT_INIT_LIST(per_pin_action, common_arg) \ - per_pin_action(common_arg, TMS570_BALL_E3_HET2_18) -#endif - -#else - -/* - * Definition of fuctions for all pins of TMS570LS3137. - * This setup correctponds to TMS570LS31x HDK Kit - */ - -#define TMS570_PINMMR_INIT_LIST( per_pin_action, common_arg ) \ - per_pin_action( common_arg, TMS570_BALL_W10_GIOB_3 ) \ - per_pin_action( common_arg, TMS570_BALL_A5_GIOA_0 ) \ - per_pin_action( common_arg, TMS570_BALL_C3_MIBSPI3NCS_3 ) \ - per_pin_action( common_arg, TMS570_BALL_B2_MIBSPI3NCS_2 ) \ - per_pin_action( common_arg, TMS570_BALL_C2_GIOA_1 ) \ - per_pin_action( common_arg, TMS570_BALL_E3_HET1_11 ) \ - per_pin_action( common_arg, TMS570_BALL_E5_EMIF_DATA_4 ) \ - per_pin_action( common_arg, TMS570_BALL_F5_EMIF_DATA_5 ) \ - per_pin_action( common_arg, TMS570_BALL_C1_GIOA_2 ) \ - per_pin_action( common_arg, TMS570_BALL_G5_EMIF_DATA_6 ) \ - per_pin_action( common_arg, TMS570_BALL_E1_GIOA_3 ) \ - per_pin_action( common_arg, TMS570_BALL_B5_GIOA_5 ) \ - per_pin_action( common_arg, TMS570_BALL_K5_EMIF_DATA_7 ) \ - per_pin_action( common_arg, TMS570_BALL_B3_HET1_22 ) \ - per_pin_action( common_arg, TMS570_BALL_H3_GIOA_6 ) \ - per_pin_action( common_arg, TMS570_BALL_L5_EMIF_DATA_8 ) \ - per_pin_action( common_arg, TMS570_BALL_M1_GIOA_7 ) \ - per_pin_action( common_arg, TMS570_BALL_M5_EMIF_DATA_9 ) \ - per_pin_action( common_arg, TMS570_BALL_V2_HET1_01 ) \ - per_pin_action( common_arg, TMS570_BALL_U1_HET1_03 ) \ - per_pin_action( common_arg, TMS570_BALL_K18_HET1_00 ) \ - per_pin_action( common_arg, TMS570_BALL_W5_HET1_02 ) \ - per_pin_action( common_arg, TMS570_BALL_V6_HET1_05 ) \ - per_pin_action( common_arg, TMS570_BALL_N5_EMIF_DATA_10 ) \ - per_pin_action( common_arg, TMS570_BALL_T1_HET1_07 ) \ - per_pin_action( common_arg, TMS570_BALL_P5_EMIF_DATA_11 ) \ - per_pin_action( common_arg, TMS570_BALL_V7_HET1_09 ) \ - per_pin_action( common_arg, TMS570_BALL_R5_EMIF_DATA_12 ) \ - per_pin_action( common_arg, TMS570_BALL_R6_EMIF_DATA_13 ) \ - per_pin_action( common_arg, TMS570_BALL_V5_MIBSPI3NCS_1 ) \ - per_pin_action( common_arg, TMS570_BALL_W3_SCIRX ) \ - per_pin_action( common_arg, TMS570_BALL_R7_EMIF_DATA_14 ) \ - per_pin_action( common_arg, TMS570_BALL_N2_SCITX ) \ - per_pin_action( common_arg, TMS570_BALL_G3_MIBSPI1NCS_2 ) \ - per_pin_action( common_arg, TMS570_BALL_N1_HET1_15 ) \ - per_pin_action( common_arg, TMS570_BALL_R8_EMIF_DATA_15 ) \ - per_pin_action( common_arg, TMS570_BALL_R9_ETMTRACECLKIN ) \ - per_pin_action( common_arg, TMS570_BALL_W9_MIBSPI3NENA ) \ - per_pin_action( common_arg, TMS570_BALL_V10_MIBSPI3NCS_0 ) \ - per_pin_action( common_arg, TMS570_BALL_J3_MIBSPI1NCS_3 ) \ - per_pin_action( common_arg, TMS570_BALL_N19_AD1EVT ) \ - per_pin_action( common_arg, TMS570_BALL_N15_EMIF_DATA_3 ) \ - per_pin_action( common_arg, TMS570_BALL_N17_EMIF_nCS_0 ) \ - per_pin_action( common_arg, TMS570_BALL_M15_EMIF_DATA_2 ) \ - per_pin_action( common_arg, TMS570_BALL_K17_EMIF_nCS_3 ) \ - per_pin_action( common_arg, TMS570_BALL_M17_EMIF_nCS_4 ) \ - per_pin_action( common_arg, TMS570_BALL_L15_EMIF_DATA_1 ) \ - per_pin_action( common_arg, TMS570_BALL_P1_HET1_24 ) \ - per_pin_action( common_arg, TMS570_BALL_A14_HET1_26 ) \ - per_pin_action( common_arg, TMS570_BALL_K15_EMIF_DATA_0 ) \ - per_pin_action( common_arg, TMS570_BALL_G19_MIBSPI1NENA ) \ - per_pin_action( common_arg, TMS570_BALL_H18_MIBSPI5NENA ) \ - per_pin_action( common_arg, TMS570_BALL_J18_MIBSPI5SOMI_0 ) \ - per_pin_action( common_arg, TMS570_BALL_J19_MIBSPI5SIMO_0 ) \ - per_pin_action( common_arg, TMS570_BALL_H19_MIBSPI5CLK ) \ - per_pin_action( common_arg, TMS570_BALL_R2_MIBSPI1NCS_0 ) \ - per_pin_action( common_arg, TMS570_BALL_E18_HET1_08 ) \ - per_pin_action( common_arg, TMS570_BALL_K19_HET1_28 ) \ - per_pin_action( common_arg, TMS570_BALL_D17_EMIF_nWE ) \ - per_pin_action( common_arg, TMS570_BALL_D16_EMIF_BA_1 ) \ - per_pin_action( common_arg, TMS570_BALL_C17_EMIF_ADDR_21 ) \ - per_pin_action( common_arg, TMS570_BALL_C16_EMIF_ADDR_20 ) \ - per_pin_action( common_arg, TMS570_BALL_C15_EMIF_ADDR_19 ) \ - per_pin_action( common_arg, TMS570_BALL_D15_EMIF_ADDR_18 ) \ - per_pin_action( common_arg, TMS570_BALL_E13_EMIF_BA_0 ) \ - per_pin_action( common_arg, TMS570_BALL_C14_EMIF_ADDR_17 ) \ - per_pin_action( common_arg, TMS570_BALL_D14_EMIF_ADDR_16 ) \ - per_pin_action( common_arg, TMS570_BALL_E12_EMIF_nOE ) \ - per_pin_action( common_arg, TMS570_BALL_D19_HET1_10 ) \ - per_pin_action( common_arg, TMS570_BALL_E11_EMIF_nDQM_1 ) \ - per_pin_action( common_arg, TMS570_BALL_B4_HET1_12 ) \ - per_pin_action( common_arg, TMS570_BALL_E9_EMIF_ADDR_5 ) \ - per_pin_action( common_arg, TMS570_BALL_C13_EMIF_ADDR_15 ) \ - per_pin_action( common_arg, TMS570_BALL_A11_HET1_14 ) \ - per_pin_action( common_arg, TMS570_BALL_C12_EMIF_ADDR_14 ) \ - per_pin_action( common_arg, TMS570_BALL_M2_GIOB_0 ) \ - per_pin_action( common_arg, TMS570_BALL_E8_EMIF_ADDR_4 ) \ - per_pin_action( common_arg, TMS570_BALL_B11_HET1_30 ) \ - per_pin_action( common_arg, TMS570_BALL_E10_EMIF_nDQM_0 ) \ - per_pin_action( common_arg, TMS570_BALL_E7_EMIF_ADDR_3 ) \ - per_pin_action( common_arg, TMS570_BALL_C11_EMIF_ADDR_13 ) \ - per_pin_action( common_arg, TMS570_BALL_C10_EMIF_ADDR_12 ) \ - per_pin_action( common_arg, TMS570_BALL_F3_MIBSPI1NCS_1 ) \ - per_pin_action( common_arg, TMS570_BALL_C9_EMIF_ADDR_11 ) \ - per_pin_action( common_arg, TMS570_BALL_D5_EMIF_ADDR_1 ) \ - per_pin_action( common_arg, TMS570_BALL_K2_GIOB_1 ) \ - per_pin_action( common_arg, TMS570_BALL_C8_EMIF_ADDR_10 ) \ - per_pin_action( common_arg, TMS570_BALL_C7_EMIF_ADDR_9 ) \ - per_pin_action( common_arg, TMS570_BALL_D4_EMIF_ADDR_0 ) \ - per_pin_action( common_arg, TMS570_BALL_C5_EMIF_ADDR_7 ) \ - per_pin_action( common_arg, TMS570_BALL_C4_EMIF_ADDR_6 ) \ - per_pin_action( common_arg, TMS570_BALL_E6_EMIF_ADDR_2 ) \ - per_pin_action( common_arg, TMS570_BALL_C6_EMIF_ADDR_8 ) \ - per_pin_action( common_arg, TMS570_MMR_SELECT_SPI4CLK ) \ - per_pin_action( common_arg, TMS570_MMR_SELECT_SPI4SIMO ) \ - per_pin_action( common_arg, TMS570_MMR_SELECT_SPI4SOMI ) \ - per_pin_action( common_arg, TMS570_MMR_SELECT_SPI4NENA ) \ - per_pin_action( common_arg, TMS570_MMR_SELECT_SPI4NCS_0 ) \ - per_pin_action( common_arg, TMS570_BALL_A13_HET1_17 ) \ - per_pin_action( common_arg, TMS570_BALL_B13_HET1_19 ) \ - per_pin_action( common_arg, TMS570_BALL_H4_HET1_21 ) \ - per_pin_action( common_arg, TMS570_BALL_J4_HET1_23 ) \ - per_pin_action( common_arg, TMS570_BALL_M3_HET1_25 ) \ - per_pin_action( common_arg, TMS570_BALL_A9_HET1_27 ) \ - per_pin_action( common_arg, TMS570_BALL_A3_HET1_29 ) \ - per_pin_action( common_arg, TMS570_BALL_J17_HET1_31 ) \ - per_pin_action( common_arg, TMS570_BALL_W6_MIBSPI5NCS_2 ) \ - per_pin_action( common_arg, TMS570_BALL_T12_MIBSPI5NCS_3 ) \ - per_pin_action( common_arg, TMS570_BALL_E19_MIBSPI5NCS_0 ) \ - per_pin_action( common_arg, TMS570_BALL_B6_MIBSPI5NCS_1 ) \ - per_pin_action( common_arg, TMS570_BALL_E16_MIBSPI5SIMO_1 ) \ - per_pin_action( common_arg, TMS570_BALL_H17_MIBSPI5SIMO_2 ) \ - per_pin_action( common_arg, TMS570_BALL_G17_MIBSPI5SIMO_3 ) \ - per_pin_action( common_arg, TMS570_BALL_E17_MIBSPI5SOMI_1 ) \ - per_pin_action( common_arg, TMS570_BALL_H16_MIBSPI5SOMI_2 ) \ - per_pin_action( common_arg, TMS570_BALL_G16_MIBSPI5SOMI_3 ) \ - per_pin_action( common_arg, TMS570_BALL_D3_SPI2NENA ) \ - per_pin_action( common_arg, \ - TMS570_MMR_SELECT_EMIF_CLK_SEL | TMS570_PIN_CLEAR_RQ_MASK ) \ - per_pin_action( common_arg, \ - TMS570_BALL_F2_GIOB_2 | TMS570_PIN_CLEAR_RQ_MASK ) \ - per_pin_action( common_arg, \ - TMS570_MMR_SELECT_GMII_SEL | TMS570_PIN_CLEAR_RQ_MASK ) \ - per_pin_action( common_arg, TMS570_MMR_SELECT_ADC_TRG1 ) \ - - -#endif - -/* - * The next construct allows to compute values for individual - * PINMMR registers based on the multiple processing - * complete pin functions list at compile time. - * Each line computes 32-bit value which selects function - * of consecutive four pins. Each pin function is defined - * by single byte. - */ -const uint32_t tms570_pinmmr_init_data[] = { - TMS570_PINMMR_REG_VAL( 0, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 1, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 2, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 3, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 4, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 5, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 6, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 7, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 8, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 9, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 10, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 11, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 12, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 13, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 14, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 15, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 16, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 17, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 18, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 19, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 20, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 21, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 22, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 23, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 24, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 25, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 26, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 27, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 28, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 29, TMS570_PINMMR_INIT_LIST ), - TMS570_PINMMR_REG_VAL( 30, TMS570_PINMMR_INIT_LIST ), -}; - -/** - * @brief setups pin multiplexer according to precomputed registers values (HCG:muxInit) - */ -void tms570_pinmux_init( void ) -{ - tms570_bsp_pinmmr_config( tms570_pinmmr_init_data, 0, - RTEMS_ARRAY_SIZE( tms570_pinmmr_init_data ) ); -} - -#if 0 - -/* - * Alternative option how to set function of individual pins - * or use list for one by one setting. This is much slower - * and consumes more memory to hold complete list. - * - * On the other hand this solution can be used for configuration - * or reconfiguration of some shorter groups of pins at runtime. - * - */ - -const uint32_t tms570_pinmmr_init_list[] = { - TMS570_PINMMR_COMA_LIST( TMS570_PINMMR_INIT_LIST ) -}; - -void tms570_pinmux_init_by_list( void ) -{ - int pincnt = RTEMS_ARRAY_SIZE( tms570_pinmmr_init_list ); - const uint32_t *pinfnc = tms570_pinmmr_init_list; - - while ( pincnt-- ) - tms570_bsp_pin_config_one( *(pinfnc++) ); -} -#endif diff --git a/bsps/arm/tms570/start/init_system.c b/bsps/arm/tms570/start/init_system.c index 690ee9ba1c..4d2c2ef29f 100644 --- a/bsps/arm/tms570/start/init_system.c +++ b/bsps/arm/tms570/start/init_system.c @@ -1,9 +1,15 @@ -/** @file +/* SPDX-License-Identifier: BSD-3-Clause */ - based on Ti HalCoGen generated file +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This source file contains parts of the system initialization. */ /* + * Copyright (C) 2022 Airbus U.S. Space & Defense, Inc * Copyright (C) 2009-2015 Texas Instruments Incorporated - www.ti.com * * @@ -45,62 +51,6 @@ #include <bsp/tms570_hwinit.h> /** - * @brief Setup all system PLLs (HCG:setupPLL) - * - */ -void tms570_pll_init( void ) -{ - uint32_t pll12_dis = 0x42; - - /* Disable PLL1 and PLL2 */ - TMS570_SYS1.CSDISSET = pll12_dis; - - /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ - while ( ( TMS570_SYS1.CSDIS & pll12_dis ) != pll12_dis ) { - /* Wait */ - } - - /* Clear Global Status Register */ - TMS570_SYS1.GLBSTAT = TMS570_SYS1_GLBSTAT_FBSLIP | - TMS570_SYS1_GLBSTAT_RFSLIP | - TMS570_SYS1_GLBSTAT_OSCFAIL; - /** - Configure PLL control registers */ - /** @b Initialize @b Pll1: */ - - /* Setup pll control register 1 */ - TMS570_SYS1.PLLCTL1 = TMS570_SYS1_PLLCTL1_ROS * 0 | - TMS570_SYS1_PLLCTL1_MASK_SLIP( 1 ) | - TMS570_SYS1_PLLCTL1_PLLDIV( 0x1f ) | /* max value */ - TMS570_SYS1_PLLCTL1_ROF * 0 | - TMS570_SYS1_PLLCTL1_REFCLKDIV( 6 - 1 ) | - TMS570_SYS1_PLLCTL1_PLLMUL( ( 120 - 1 ) << 8 ); - - /* Setup pll control register 2 */ - TMS570_SYS1.PLLCTL2 = TMS570_SYS1_PLLCTL2_FMENA * 0 | - TMS570_SYS1_PLLCTL2_SPREADINGRATE( 255 ) | - TMS570_SYS1_PLLCTL2_MULMOD( 7 ) | - TMS570_SYS1_PLLCTL2_ODPLL( 2 - 1 ) | - TMS570_SYS1_PLLCTL2_SPR_AMOUNT( 61 ); - - /** @b Initialize @b Pll2: */ - - /* Setup pll2 control register */ - TMS570_SYS2.PLLCTL3 = TMS570_SYS2_PLLCTL3_ODPLL2( 2 - 1 ) | - TMS570_SYS2_PLLCTL3_PLLDIV2( 0x1F ) | /* max value */ - TMS570_SYS2_PLLCTL3_REFCLKDIV2( 6 - 1 ) | - TMS570_SYS2_PLLCTL3_PLLMUL2( ( 120 - 1 ) << 8 ); - - /** - Enable PLL(s) to start up or Lock */ - TMS570_SYS1.CSDIS = 0x00000000 | /* CLKSR0 on */ - 0x00000000 | /* CLKSR1 on */ - 0x00000008 | /* CLKSR3 off */ - 0x00000000 | /* CLKSR4 on */ - 0x00000000 | /* CLKSR5 on */ - 0x00000000 | /* CLKSR6 on */ - 0x00000080; /* CLKSR7 off */ -} - -/** * @brief Adjust Low-Frequency (LPO) oscilator (HCG:trimLPO) * */ @@ -125,17 +75,6 @@ enum tms570_flash_power_modes { TMS570_FLASH_SYS_ACTIVE = 3U /**< Alias for flash bank power mode active */ }; -enum tms570_system_clock_source { - TMS570_SYS_CLK_SRC_OSC = 0U, /**< Alias for oscillator clock Source */ - TMS570_SYS_CLK_SRC_PLL1 = 1U, /**< Alias for Pll1 clock Source */ - TMS570_SYS_CLK_SRC_EXTERNAL1 = 3U, /**< Alias for external clock Source */ - TMS570_SYS_CLK_SRC_LPO_LOW = 4U, /**< Alias for low power oscillator low clock Source */ - TMS570_SYS_CLK_SRC_LPO_HIGH = 5U, /**< Alias for low power oscillator high clock Source */ - TMS570_SYS_CLK_SRC_PLL2 = 6U, /**< Alias for Pll2 clock Source */ - TMS570_SYS_CLK_SRC_EXTERNAL2 = 7U, /**< Alias for external 2 clock Source */ - TMS570_SYS_CLK_SRC_VCLK = 9U /**< Alias for synchronous VCLK1 clock Source */ -}; - /** * @brief Setup Flash memory parameters and timing (HCG:setupFlash) * @@ -182,113 +121,28 @@ void tms570_periph_init( void ) /** - Release peripherals from reset and enable clocks to all peripherals */ /** - Power-up all peripherals */ - TMS570_PCR.PSPWRDWNCLR0 = 0xFFFFFFFFU; - TMS570_PCR.PSPWRDWNCLR1 = 0xFFFFFFFFU; - TMS570_PCR.PSPWRDWNCLR2 = 0xFFFFFFFFU; - TMS570_PCR.PSPWRDWNCLR3 = 0xFFFFFFFFU; + TMS570_PCR1.PSPWRDWNCLR0 = 0xFFFFFFFFU; + TMS570_PCR1.PSPWRDWNCLR1 = 0xFFFFFFFFU; + TMS570_PCR1.PSPWRDWNCLR2 = 0xFFFFFFFFU; + TMS570_PCR1.PSPWRDWNCLR3 = 0xFFFFFFFFU; + +#if TMS570_VARIANT == 4357 + TMS570_PCR2.PSPWRDWNCLR0 = 0xFFFFFFFFU; + TMS570_PCR2.PSPWRDWNCLR1 = 0xFFFFFFFFU; + TMS570_PCR2.PSPWRDWNCLR2 = 0xFFFFFFFFU; + TMS570_PCR2.PSPWRDWNCLR3 = 0xFFFFFFFFU; + + TMS570_PCR3.PSPWRDWNCLR0 = 0xFFFFFFFFU; + TMS570_PCR3.PSPWRDWNCLR1 = 0xFFFFFFFFU; + TMS570_PCR3.PSPWRDWNCLR2 = 0xFFFFFFFFU; + TMS570_PCR3.PSPWRDWNCLR3 = 0xFFFFFFFFU; +#endif /** - Enable Peripherals */ TMS570_SYS1.CLKCNTL |= TMS570_SYS1_CLKCNTL_PENA; } /** - * @brief Setup chip clocks including to wait for PLLs locks (HCG:mapClocks) - * - */ -/* SourceId : SYSTEM_SourceId_005 */ -/* DesignId : SYSTEM_DesignId_005 */ -/* Requirements : HL_SR469 */ -void tms570_map_clock_init( void ) -{ - uint32_t sys_csvstat, sys_csdis; - - /** @b Initialize @b Clock @b Tree: */ - /** - Disable / Enable clock domain */ - TMS570_SYS1.CDDIS = ( 0U << 4U ) | /* AVCLK 1 OFF */ - ( 0U << 5U ) | /* AVCLK 2 OFF */ - ( 0U << 8U ) | /* VCLK3 OFF */ - ( 0U << 9U ) | /* VCLK4 OFF */ - ( 1U << 10U ) | /* AVCLK 3 OFF */ - ( 0U << 11U ); /* AVCLK 4 OFF */ - - /* Work Around for Errata SYS#46: - * - * Errata Description: - * Clock Source Switching Not Qualified with Clock Source Enable And Clock Source Valid - * Workaround: - * Always check the CSDIS register to make sure the clock source is turned on and check - * the CSVSTAT register to make sure the clock source is valid. Then write to GHVSRC to switch the clock. - */ - /** - Wait for until clocks are locked */ - sys_csvstat = TMS570_SYS1.CSVSTAT; - sys_csdis = TMS570_SYS1.CSDIS; - - while ( ( sys_csvstat & ( ( sys_csdis ^ 0xFFU ) & 0xFFU ) ) != - ( ( sys_csdis ^ 0xFFU ) & 0xFFU ) ) { - sys_csvstat = TMS570_SYS1.CSVSTAT; - sys_csdis = TMS570_SYS1.CSDIS; - } /* Wait */ - - /* Now the PLLs are locked and the PLL outputs can be sped up */ - /* The R-divider was programmed to be 0xF. Now this divider is changed to programmed value */ - TMS570_SYS1.PLLCTL1 = - ( TMS570_SYS1.PLLCTL1 & ~TMS570_SYS1_PLLCTL1_PLLDIV( 0x1F ) ) | - TMS570_SYS1_PLLCTL1_PLLDIV( 1 - 1 ); - /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "LDRA Tool issue" */ - TMS570_SYS2.PLLCTL3 = - ( TMS570_SYS2.PLLCTL3 & ~TMS570_SYS2_PLLCTL3_PLLDIV2( 0x1F ) ) | - TMS570_SYS2_PLLCTL3_PLLDIV2( 1 - 1 ); - - /* Enable/Disable Frequency modulation */ - TMS570_SYS1.PLLCTL2 &= ~TMS570_SYS1_PLLCTL2_FMENA; - - /** - Map device clock domains to desired sources and configure top-level dividers */ - /** - All clock domains are working off the default clock sources until now */ - /** - The below assignments can be easily modified using the HALCoGen GUI */ - - /** - Setup GCLK, HCLK and VCLK clock source for normal operation, power down mode and after wakeup */ - TMS570_SYS1.GHVSRC = TMS570_SYS1_GHVSRC_GHVWAKE( TMS570_SYS_CLK_SRC_OSC ) | - TMS570_SYS1_GHVSRC_HVLPM( TMS570_SYS_CLK_SRC_OSC ) | - TMS570_SYS1_GHVSRC_GHVSRC( TMS570_SYS_CLK_SRC_PLL1 ); - - /** - Setup synchronous peripheral clock dividers for VCLK1, VCLK2, VCLK3 */ - TMS570_SYS1.CLKCNTL = - ( TMS570_SYS1.CLKCNTL & ~TMS570_SYS1_CLKCNTL_VCLK2R( 0xF ) ) | - TMS570_SYS1_CLKCNTL_VCLK2R( 1 ); - - TMS570_SYS1.CLKCNTL = - ( TMS570_SYS1.CLKCNTL & ~TMS570_SYS1_CLKCNTL_VCLKR( 0xF ) ) | - TMS570_SYS1_CLKCNTL_VCLKR( 1 ); - - TMS570_SYS2.CLK2CNTRL = - ( TMS570_SYS2.CLK2CNTRL & ~TMS570_SYS2_CLK2CNTRL_VCLK3R( 0xF ) ) | - TMS570_SYS2_CLK2CNTRL_VCLK3R( 1 ); - - TMS570_SYS2.CLK2CNTRL = ( TMS570_SYS2.CLK2CNTRL & 0xFFFFF0FFU ) | - ( 1U << 8U ); /* FIXME: unknown in manual*/ - - /** - Setup RTICLK1 and RTICLK2 clocks */ - TMS570_SYS1.RCLKSRC = ( 1U << 24U ) | - ( TMS570_SYS_CLK_SRC_VCLK << 16U ) | /* FIXME: not in manual */ - TMS570_SYS1_RCLKSRC_RTI1DIV( 1 ) | - TMS570_SYS1_RCLKSRC_RTI1SRC( TMS570_SYS_CLK_SRC_VCLK ); - - /** - Setup asynchronous peripheral clock sources for AVCLK1 and AVCLK2 */ - TMS570_SYS1.VCLKASRC = - TMS570_SYS1_VCLKASRC_VCLKA2S( TMS570_SYS_CLK_SRC_VCLK ) | - TMS570_SYS1_VCLKASRC_VCLKA1S( TMS570_SYS_CLK_SRC_VCLK ); - - TMS570_SYS2.VCLKACON1 = TMS570_SYS2_VCLKACON1_VCLKA4R( 1 - 1 ) | - TMS570_SYS2_VCLKACON1_VCLKA4_DIV_CDDIS * 0 | - TMS570_SYS2_VCLKACON1_VCLKA4S( - TMS570_SYS_CLK_SRC_VCLK ) | - TMS570_SYS2_VCLKACON1_VCLKA3R( 1 - 1 ) | - TMS570_SYS2_VCLKACON1_VCLKA3_DIV_CDDIS * 0 | - TMS570_SYS2_VCLKACON1_VCLKA3S( - TMS570_SYS_CLK_SRC_VCLK ); -} - -/** * @brief TMS570 system hardware initialization (HCG:systemInit) * */ diff --git a/bsps/arm/tms570/start/linkcmds.tms570ls3137_hdk_with_loader b/bsps/arm/tms570/start/linkcmds.tms570lc4357_hdk index aa0000379d..70f60662a6 100644 --- a/bsps/arm/tms570/start/linkcmds.tms570ls3137_hdk_with_loader +++ b/bsps/arm/tms570/start/linkcmds.tms570lc4357_hdk @@ -1,11 +1,4 @@ - -MEMORY { - ROM_BOOT(RX) : ORIGIN = 0x00000000, LENGTH = 256k - ROM_INT (RX) : ORIGIN = 0x00040000, LENGTH = 3M-256k - RAM_INT_VEC : ORIGIN = 0x08000000, LENGTH = 256 - RAM_INT (AIWX) : ORIGIN = 0x08000100, LENGTH = 256k - 256 - RAM_EXT (AIWX) : ORIGIN = 0x80000000, LENGTH = 8M -} +INCLUDE linkcmds.memory REGION_ALIAS ("REGION_START", ROM_INT); REGION_ALIAS ("REGION_VECTOR", RAM_INT); @@ -25,6 +18,7 @@ REGION_ALIAS ("REGION_STACK", RAM_INT); REGION_ALIAS ("REGION_NOCACHE", RAM_INT); REGION_ALIAS ("REGION_NOCACHE_LOAD", RAM_INT); -bsp_int_vec_overlay_start = ORIGIN(RAM_INT_VEC); +bsp_vector_table_in_start_section = 1; +bsp_int_vec_overlay_start = ORIGIN(ROM_INT) + 64; INCLUDE linkcmds.armv4 diff --git a/bsps/arm/tms570/start/linkcmds.tms570lc4357_hdk_sdram b/bsps/arm/tms570/start/linkcmds.tms570lc4357_hdk_sdram new file mode 100644 index 0000000000..b6a76ff407 --- /dev/null +++ b/bsps/arm/tms570/start/linkcmds.tms570lc4357_hdk_sdram @@ -0,0 +1,30 @@ +INCLUDE linkcmds.memory + +REGION_ALIAS ("REGION_START", RAM_EXT); +REGION_ALIAS ("REGION_VECTOR", RAM_EXT); +REGION_ALIAS ("REGION_TEXT", RAM_EXT); +REGION_ALIAS ("REGION_TEXT_LOAD", RAM_EXT); +REGION_ALIAS ("REGION_RODATA", RAM_EXT); +REGION_ALIAS ("REGION_RODATA_LOAD", RAM_EXT); +REGION_ALIAS ("REGION_DATA", RAM_EXT); +REGION_ALIAS ("REGION_DATA_LOAD", RAM_EXT); +REGION_ALIAS ("REGION_FAST_TEXT", RAM_EXT); +REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM_EXT); +REGION_ALIAS ("REGION_FAST_DATA", RAM_INT); +REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM_EXT); +REGION_ALIAS ("REGION_BSS", RAM_EXT); +REGION_ALIAS ("REGION_WORK", RAM_EXT); +REGION_ALIAS ("REGION_STACK", RAM_EXT); +REGION_ALIAS ("REGION_NOCACHE", RAM_EXT); +REGION_ALIAS ("REGION_NOCACHE_LOAD", RAM_EXT); + +bsp_vector_table_in_start_section = 1; + +SECTIONS { + .int_vec_overlay : ALIGN_WITH_INPUT { + bsp_int_vec_overlay_start = .; + . += 256; + } > RAM_INT AT > RAM_INT +} + +INCLUDE linkcmds.armv4 diff --git a/bsps/arm/tms570/start/linkcmds.tms570ls3137_hdk b/bsps/arm/tms570/start/linkcmds.tms570ls3137_hdk index ca68617231..70f60662a6 100644 --- a/bsps/arm/tms570/start/linkcmds.tms570ls3137_hdk +++ b/bsps/arm/tms570/start/linkcmds.tms570ls3137_hdk @@ -1,10 +1,4 @@ - -MEMORY { - ROM_INT (RX) : ORIGIN = 0x00000000, LENGTH = 3M - RAM_INT_VEC : ORIGIN = 0x08000000, LENGTH = 256 - RAM_INT (AIWX) : ORIGIN = 0x08000100, LENGTH = 256k - 256 - RAM_EXT (AIWX) : ORIGIN = 0x80000000, LENGTH = 8M -} +INCLUDE linkcmds.memory REGION_ALIAS ("REGION_START", ROM_INT); REGION_ALIAS ("REGION_VECTOR", RAM_INT); @@ -24,6 +18,7 @@ REGION_ALIAS ("REGION_STACK", RAM_INT); REGION_ALIAS ("REGION_NOCACHE", RAM_INT); REGION_ALIAS ("REGION_NOCACHE_LOAD", RAM_INT); -bsp_int_vec_overlay_start = ORIGIN(RAM_INT_VEC); +bsp_vector_table_in_start_section = 1; +bsp_int_vec_overlay_start = ORIGIN(ROM_INT) + 64; INCLUDE linkcmds.armv4 diff --git a/bsps/arm/tms570/start/linkcmds.tms570ls3137_hdk_intram b/bsps/arm/tms570/start/linkcmds.tms570ls3137_hdk_intram index ca216204dc..6060eec80c 100644 --- a/bsps/arm/tms570/start/linkcmds.tms570ls3137_hdk_intram +++ b/bsps/arm/tms570/start/linkcmds.tms570ls3137_hdk_intram @@ -1,10 +1,4 @@ - -MEMORY { - ROM_INT (RX) : ORIGIN = 0x00000000, LENGTH = 3M - RAM_INT_VEC : ORIGIN = 0x08000000, LENGTH = 256 - RAM_INT (AIWX) : ORIGIN = 0x08000100, LENGTH = 256k - 256 - RAM_EXT (AIW) : ORIGIN = 0x80000000, LENGTH = 8M -} +INCLUDE linkcmds.memory REGION_ALIAS ("REGION_START", RAM_INT); REGION_ALIAS ("REGION_VECTOR", RAM_INT); @@ -24,6 +18,13 @@ REGION_ALIAS ("REGION_STACK", RAM_INT); REGION_ALIAS ("REGION_NOCACHE", RAM_INT); REGION_ALIAS ("REGION_NOCACHE_LOAD", RAM_INT); -bsp_int_vec_overlay_start = ORIGIN(RAM_INT_VEC); +bsp_vector_table_in_start_section = 1; + +SECTIONS { + .int_vec_overlay : ALIGN_WITH_INPUT { + bsp_int_vec_overlay_start = .; + . += 256; + } > RAM_INT AT > RAM_INT +} INCLUDE linkcmds.armv4 diff --git a/bsps/arm/tms570/start/linkcmds.tms570ls3137_hdk_sdram b/bsps/arm/tms570/start/linkcmds.tms570ls3137_hdk_sdram index 1bf4a1cae1..b6a76ff407 100644 --- a/bsps/arm/tms570/start/linkcmds.tms570ls3137_hdk_sdram +++ b/bsps/arm/tms570/start/linkcmds.tms570ls3137_hdk_sdram @@ -1,10 +1,4 @@ - -MEMORY { - ROM_INT (RX) : ORIGIN = 0x00000000, LENGTH = 3M - RAM_INT_VEC : ORIGIN = 0x08000000, LENGTH = 256 - RAM_INT (AIWX) : ORIGIN = 0x08000100, LENGTH = 256k - 256 - RAM_EXT (AIWX) : ORIGIN = 0x80000000, LENGTH = 8M -} +INCLUDE linkcmds.memory REGION_ALIAS ("REGION_START", RAM_EXT); REGION_ALIAS ("REGION_VECTOR", RAM_EXT); @@ -16,7 +10,7 @@ REGION_ALIAS ("REGION_DATA", RAM_EXT); REGION_ALIAS ("REGION_DATA_LOAD", RAM_EXT); REGION_ALIAS ("REGION_FAST_TEXT", RAM_EXT); REGION_ALIAS ("REGION_FAST_TEXT_LOAD", RAM_EXT); -REGION_ALIAS ("REGION_FAST_DATA", RAM_EXT); +REGION_ALIAS ("REGION_FAST_DATA", RAM_INT); REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM_EXT); REGION_ALIAS ("REGION_BSS", RAM_EXT); REGION_ALIAS ("REGION_WORK", RAM_EXT); @@ -24,6 +18,13 @@ REGION_ALIAS ("REGION_STACK", RAM_EXT); REGION_ALIAS ("REGION_NOCACHE", RAM_EXT); REGION_ALIAS ("REGION_NOCACHE_LOAD", RAM_EXT); -bsp_int_vec_overlay_start = ORIGIN(RAM_INT_VEC); +bsp_vector_table_in_start_section = 1; + +SECTIONS { + .int_vec_overlay : ALIGN_WITH_INPUT { + bsp_int_vec_overlay_start = .; + . += 256; + } > RAM_INT AT > RAM_INT +} INCLUDE linkcmds.armv4 diff --git a/bsps/arm/tms570/start/pinmux.c b/bsps/arm/tms570/start/pinmux.c index 6aec5f7c32..16eb41a129 100644 --- a/bsps/arm/tms570/start/pinmux.c +++ b/bsps/arm/tms570/start/pinmux.c @@ -1,13 +1,16 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * * @ingroup RTEMSBSPsARMTMS570 * - * @brief I/O Multiplexing Module (IOMM) basic support + * @brief This source file contains the I/O Multiplexing Module (IOMM) support + * implementation. */ /* - * Copyright (c) 2015 Premysl Houdek <kom541000@gmail.com> + * Copyright (C) 2015 Premysl Houdek <kom541000@gmail.com> * * Google Summer of Code 2014 at * Czech Technical University in Prague @@ -15,17 +18,45 @@ * 166 36 Praha 6 * Czech Republic * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include <bsp/tms570.h> #include <bsp/tms570-pinmux.h> #include <bsp/irq.h> -uint32_t tms570_bsp_pinmmr_kick_key0 = 0x83E70B13U; -uint32_t tms570_bsp_pinmmr_kick_key1 = 0x95A4F1E0U; +RTEMS_STATIC_ASSERT( + TMS570_PIN_CLEAR_RQ_MASK == TMS570_PIN_FNC_CLEAR << TMS570_PIN_FNC_SHIFT, + TMS570_PIN_CONFIG +); + +static inline void +tms570_bsp_pin_to_pinmmrx(volatile uint32_t **pinmmrx, uint32_t *pin_shift, + uint32_t config) +{ + uint32_t pin_num = (config & TMS570_PIN_NUM_MASK) >> TMS570_PIN_NUM_SHIFT; + *pinmmrx = TMS570_PINMUX + (pin_num >> 2); + *pin_shift = (pin_num & 0x3)*8; +} /** * @brief select desired function of pin/ball @@ -110,33 +141,11 @@ void tms570_bsp_pin_config_one(uint32_t pin_num_and_fnc) { rtems_interrupt_level intlev; - uint32_t pin_in_alt; rtems_interrupt_disable(intlev); - - TMS570_IOMM.KICK_REG0 = tms570_bsp_pinmmr_kick_key0; - TMS570_IOMM.KICK_REG1 = tms570_bsp_pinmmr_kick_key1; - - pin_in_alt = pin_num_and_fnc & TMS570_PIN_IN_ALT_MASK; - if ( pin_in_alt ) { - pin_in_alt >>= TMS570_PIN_IN_ALT_SHIFT; - if ( pin_in_alt & TMS570_PIN_CLEAR_RQ_MASK ) { - tms570_bsp_pin_clear_function(pin_in_alt, TMS570_PIN_FNC_AUTO); - } else { - tms570_bsp_pin_set_function(pin_in_alt, TMS570_PIN_FNC_AUTO); - } - } - - pin_num_and_fnc &= TMS570_PIN_NUM_FNC_MASK; - if ( pin_num_and_fnc & TMS570_PIN_CLEAR_RQ_MASK ) { - tms570_bsp_pin_clear_function(pin_num_and_fnc, TMS570_PIN_FNC_AUTO); - } else { - tms570_bsp_pin_set_function(pin_num_and_fnc, TMS570_PIN_FNC_AUTO); - } - - TMS570_IOMM.KICK_REG0 = 0; - TMS570_IOMM.KICK_REG1 = 0; - + tms570_pin_config_prepare(); + tms570_pin_config_apply(pin_num_and_fnc); + tms570_pin_config_complete(); rtems_interrupt_enable(intlev); } @@ -167,29 +176,75 @@ tms570_bsp_pinmmr_config(const uint32_t *pinmmr_values, int reg_start, int reg_c if ( reg_count <= 0) return; - TMS570_IOMM.KICK_REG0 = tms570_bsp_pinmmr_kick_key0; - TMS570_IOMM.KICK_REG1 = tms570_bsp_pinmmr_kick_key1; + tms570_pin_config_prepare(); - pinmmrx = (&TMS570_IOMM.PINMUX.PINMMR0) + reg_start; + pinmmrx = TMS570_PINMUX + reg_start; pval = pinmmr_values; cnt = reg_count; do { - *pinmmrx = *pinmmrx & *pval; + *pinmmrx = *pval; pinmmrx++; pval++; } while( --cnt ); - pinmmrx = (&TMS570_IOMM.PINMUX.PINMMR0) + reg_start; - pval = pinmmr_values; - cnt = reg_count; + tms570_pin_config_complete(); +} - do { - *pinmmrx = *pval; - pinmmrx++; - pval++; - } while( --cnt ); +void tms570_pin_config_prepare(void) +{ + TMS570_IOMM.KICK_REG0 = 0x83E70B13U; + TMS570_IOMM.KICK_REG1 = 0x95A4F1E0U; +} + +static void +tms570_pin_set_function(uint32_t config) +{ + volatile uint32_t *pinmmrx; + uint32_t pin_shift; + uint32_t pin_fnc; + uint32_t bit; + uint32_t val; + + tms570_bsp_pin_to_pinmmrx(&pinmmrx, &pin_shift, config); + pin_fnc = (config & TMS570_PIN_FNC_MASK) >> TMS570_PIN_FNC_SHIFT; + bit = 1U << (pin_fnc + pin_shift); + val = *pinmmrx; + val &= ~(0xffU << pin_shift); + + if ((config & TMS570_PIN_CLEAR_RQ_MASK) == 0) { + val |= bit; + } + + *pinmmrx = val; +} + +void tms570_pin_config_apply(uint32_t config) +{ + uint32_t pin_in_alt; + uint32_t pin_num_and_fnc; + pin_in_alt = config & TMS570_PIN_IN_ALT_MASK; + if (pin_in_alt != 0) { + pin_in_alt >>= TMS570_PIN_IN_ALT_SHIFT; + tms570_pin_set_function(pin_in_alt); + } + + pin_num_and_fnc = config & TMS570_PIN_NUM_FNC_MASK; + tms570_pin_set_function(pin_num_and_fnc); +} + +void tms570_pin_config_array_apply(const uint32_t *config, size_t count) +{ + size_t i; + + for (i = 0; i < count; ++i) { + tms570_pin_config_apply(config[i]); + } +} + +void tms570_pin_config_complete(void) +{ TMS570_IOMM.KICK_REG0 = 0; TMS570_IOMM.KICK_REG1 = 0; } diff --git a/bsps/arm/tms570/start/tms570-pom.c b/bsps/arm/tms570/start/tms570-pom.c index 8f31d01b77..f1a6d2d4af 100644 --- a/bsps/arm/tms570/start/tms570-pom.c +++ b/bsps/arm/tms570/start/tms570-pom.c @@ -1,22 +1,42 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * * @ingroup RTEMSBSPsARMTMS570 * - * @brief TMS570 Parameter Overlay Module functions definitions. + * @brief This source file contains the Parameter Overlay Module (POM) support + * implementation. */ - /* - * Copyright (c) 2014 Pavel Pisa <pisa@cmp.felk.cvut.cz> +/* + * Copyright (C) 2014 Pavel Pisa <pisa@cmp.felk.cvut.cz> * * Czech Technical University in Prague * Zikova 1903/4 * 166 36 Praha 6 * Czech Republic * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include <stdint.h> @@ -66,7 +86,7 @@ uint32_t pom_global_overlay_target_address_start = * * @retval Void */ -void tms570_initialize_and_clear(void) +void tms570_pom_initialize_and_clear(void) { int i; @@ -87,7 +107,12 @@ void tms570_initialize_and_clear(void) */ void tms570_pom_remap(void) { - uint32_t vec_overlay_start = pom_global_overlay_target_address_start; + void *vec_overlay_start = (void *) pom_global_overlay_target_address_start; + void *addr_tab = (char *) bsp_start_vector_table_begin + 64; + + if (vec_overlay_start == addr_tab) { + return; + } /* * Copy RTEMS the first level exception processing code @@ -99,7 +124,10 @@ void tms570_pom_remap(void) * table found in * c/src/lib/libbsp/arm/shared/start/start.S */ - memcpy((void*)vec_overlay_start, bsp_start_vector_table_begin, 64); + rtems_cache_invalidate_multiple_data_lines(addr_tab, 64); + memcpy(vec_overlay_start, addr_tab, 64); + rtems_cache_flush_multiple_data_lines(vec_overlay_start, 64); + rtems_cache_invalidate_multiple_instruction_lines(vec_overlay_start, 64); #if 0 { diff --git a/bsps/arm/tms570/start/tms570_selftest.c b/bsps/arm/tms570/start/tms570_selftest.c index 6f3e553acd..99b8718a4a 100644 --- a/bsps/arm/tms570/start/tms570_selftest.c +++ b/bsps/arm/tms570/start/tms570_selftest.c @@ -1,11 +1,16 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + /** * @file * * @ingroup RTEMSBSPsARMTMS570 * - * @brief TMS570 selftest support functions implementation. + * @brief This source file contains the selftest support implementation. */ + /* + * Copyright (C) 2023 embedded brains GmbH & Co. KG + * Copyright (C) 2022 Airbus U.S. Space & Defense, Inc * Copyright (C) 2009-2015 Texas Instruments Incorporated - www.ti.com * * @@ -46,6 +51,32 @@ #include <bsp/tms570_selftest.h> #include <bsp/tms570_hwinit.h> +/* + * According to the TMS570LS3137 (HCLK max 180MHz, VCLK max 100MHz) and + * TMS570LC4357 (GCLK1 max 300MHz, VCLK max 110MHz, HCLK max 150MHz) + * datasheets, the PBIST ROM clock frequency is limited to 90MHz. + * + * For LS3137 PBIST ROM clock frequency = HCLK / (1 << MSTGCR[9:8]) + * + * For LC4357 PBIST ROM clock frequency = GCLK1 / (1 << MSTGCR[9:8]) + */ +#if TMS570_VARIANT == 4357 +#define MSTGCR_ENABLE_MEMORY_SELF_TEST 0x0000020a +#define MSTGCR_DISABLE_MEMORY_SELF_TEST 0x00000205 +#define PBIST_RESET_DELAY (64 * 4) +#else +#define MSTGCR_ENABLE_MEMORY_SELF_TEST 0x0000010a +#define MSTGCR_DISABLE_MEMORY_SELF_TEST 0x00000105 +#define PBIST_RESET_DELAY (32 * 2) +#endif + +static void tms570_pbist_reset_delay( void ) +{ + for ( int i = 0; i < PBIST_RESET_DELAY; ++i ) { + __asm__ volatile ( "" ); + } +} + /** * @brief Checks to see if the EFUSE Stuck at zero test is completed successfully (HCG:efcStuckZeroTest). / @@ -229,7 +260,6 @@ uint32_t tms570_efc_check( void ) /* Requirements : HL_SR399 */ void tms570_pbist_self_check( void ) { - volatile uint32_t i = 0U; uint32_t PBIST_wait_done_loop = 0U; /* Run a diagnostic check on the memory self-test controller */ @@ -238,15 +268,14 @@ void tms570_pbist_self_check( void ) /* Disable PBIST clocks and ROM clock */ TMS570_PBIST.PACT = 0x0U; - /* PBIST ROM clock frequency = HCLK frequency /2 */ /* Disable memory self controller */ - TMS570_SYS1.MSTGCR = 0x00000105U; + TMS570_SYS1.MSTGCR = MSTGCR_DISABLE_MEMORY_SELF_TEST; /* Disable Memory Initialization controller */ TMS570_SYS1.MINITGCR = 0x5U; /* Enable memory self controller */ - TMS570_SYS1.MSTGCR = 0x0000010AU; + TMS570_SYS1.MSTGCR = MSTGCR_ENABLE_MEMORY_SELF_TEST; /* Clear PBIST Done */ TMS570_SYS1.MSTCGSTAT = 0x1U; @@ -254,14 +283,10 @@ void tms570_pbist_self_check( void ) /* Enable PBIST controller */ TMS570_SYS1.MSIENA = 0x1U; - /* wait for 32 VBUS clock cycles at least, based on HCLK to VCLK ratio */ - /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */ - /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */ - for ( i = 0U; i < ( 32U + ( 32U * 1U ) ); i++ ) { /* Wait */ - } + tms570_pbist_reset_delay(); /* Enable PBIST clocks and ROM clock */ - TMS570_PBIST.PACT = 0x3U; + TMS570_PBIST.PACT = 0x1U; /* CPU control of PBIST */ TMS570_PBIST.DLR = 0x10U; @@ -328,11 +353,8 @@ void tms570_pbist_run( uint32_t algomask ) { - volatile uint32_t i = 0U; - - /* PBIST ROM clock frequency = HCLK frequency /2 */ /* Disable memory self controller */ - TMS570_SYS1.MSTGCR = 0x00000105U; + TMS570_SYS1.MSTGCR = MSTGCR_DISABLE_MEMORY_SELF_TEST; /* Disable Memory Initialization controller */ TMS570_SYS1.MINITGCR = 0x5U; @@ -341,16 +363,12 @@ void tms570_pbist_run( TMS570_SYS1.MSIENA = 0x1U; /* Enable memory self controller */ - TMS570_SYS1.MSTGCR = 0x0000010AU; + TMS570_SYS1.MSTGCR = MSTGCR_ENABLE_MEMORY_SELF_TEST; - /* wait for 32 VBUS clock cycles at least, based on HCLK to VCLK ratio */ - /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */ - /*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */ - for ( i = 0U; i < ( 32U + ( 32U * 1U ) ); i++ ) { /* Wait */ - } + tms570_pbist_reset_delay(); /* Enable PBIST clocks and ROM clock */ - TMS570_PBIST.PACT = 0x3U; + TMS570_PBIST.PACT = 0x1U; /* Select all algorithms to be tested */ TMS570_PBIST.ALGO = algomask; @@ -424,6 +442,33 @@ bool tms570_pbist_is_test_passed( void ) } /** + * Helper method that will run a pbist test and blocks until it finishes + * Reduces code duplication in start system start hooks + */ +void tms570_pbist_run_and_check(uint32_t raminfoL, uint32_t algomask) +{ + /* Run PBIST on region */ + tms570_pbist_run(raminfoL, algomask); + + /* Wait for PBIST for region to be completed */ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ + while (!tms570_pbist_is_test_completed()) { + } /* Wait */ + + /* Check if PBIST on region passed the self-test */ + if (!tms570_pbist_is_test_passed()) { + /* PBIST and region failed the self-test. + * Need custom handler to check the memory failure + * and to take the appropriate next step. + */ + tms570_pbist_fail(); + } + + /* Disable PBIST clocks and disable memory self-test mode */ + tms570_pbist_stop(); +} + +/** * @brief Checks to see if the PBIST Port test is completed successfully (HCG:pbistPortTestStatus) * @param[in] port - Select the port to get the status. * @return 1 if PBIST Port test completed successfully, otherwise 0. @@ -490,21 +535,27 @@ void tms570_pbist_fail( void ) /* SourceId : SELFTEST_SourceId_002 */ /* DesignId : SELFTEST_DesignId_004 */ /* Requirements : HL_SR396 */ -void tms570_memory_init( uint32_t ram ) +__attribute__((__naked__)) void tms570_memory_init( uint32_t ram ) { - /* Enable Memory Hardware Initialization */ - TMS570_SYS1.MINITGCR = 0xAU; - - /* Enable Memory Hardware Initialization for selected RAM's */ - TMS570_SYS1.MSIENA = ram; - - /* Wait until Memory Hardware Initialization complete */ - /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ - while ( ( TMS570_SYS1.MSTCGSTAT & 0x00000100U ) != 0x00000100U ) { - } /* Wait */ - - /* Disable Memory Hardware Initialization */ - TMS570_SYS1.MINITGCR = 0x5U; + __asm__ volatile ( + /* Load memory controller base address */ + "ldr r1, =#0xffffff00\n" + /* Enable Memory Hardware Initialization (MINITGCR) */ + "movs r2, #0xa\n" + "str r2, [r1, #0x5c]\n" + /* Enable Memory Hardware Initialization for selected RAM's (MSIENA) */ + "str r0, [r1, #0x60]\n" + /* Wait until Memory Hardware Initialization completes (MSTCGSTAT) */ + /*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */ + "1: ldr r2, [r1, #0x68]\n" + "tst r2, #0x100\n" + "beq 1b\n" + /* Disable Memory Hardware Initialization (MINITGCR) */ + "movs r2, #0x5\n" + "str r2, [r1, #0x5c]\n" + /* Return */ + "bx lr\n" + ); } volatile uint32_t *const diff --git a/bsps/arm/tms570/start/tms570_selftest_par_can.c b/bsps/arm/tms570/start/tms570_selftest_par_can.c index 7f622c38a8..65c7348763 100644 --- a/bsps/arm/tms570/start/tms570_selftest_par_can.c +++ b/bsps/arm/tms570/start/tms570_selftest_par_can.c @@ -1,24 +1,45 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * * @ingroup RTEMSBSPsARMTMS570 * - * @brief Test CAN module parity based protection logic to work. + * @brief This source file contains the CAN module parity based protection + * support. + * + * Algorithms are based on Ti manuals and Ti HalCoGen generated + * code. */ + /* - * Copyright (c) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz> + * Copyright (C) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz> * * Czech Technical University in Prague * Zikova 1903/4 * 166 36 Praha 6 * Czech Republic * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * Algorithms are based on Ti manuals and Ti HalCoGen generated - * code. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include <stdint.h> diff --git a/bsps/arm/tms570/start/tms570_selftest_par_mibspi.c b/bsps/arm/tms570/start/tms570_selftest_par_mibspi.c index 0acac1f0e6..67ed1a978b 100644 --- a/bsps/arm/tms570/start/tms570_selftest_par_mibspi.c +++ b/bsps/arm/tms570/start/tms570_selftest_par_mibspi.c @@ -1,24 +1,45 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * * @ingroup RTEMSBSPsARMTMS570 * - * @brief Test MibSPI module parity based protection logic to work. + * @brief This source file contains the MibSPI module parity based protection + * support. + * + * Algorithms are based on Ti manuals and Ti HalCoGen generated + * code. */ + /* - * Copyright (c) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz> + * Copyright (C) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz> * * Czech Technical University in Prague * Zikova 1903/4 * 166 36 Praha 6 * Czech Republic * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * Algorithms are based on Ti manuals and Ti HalCoGen generated - * code. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include <stdint.h> diff --git a/bsps/arm/tms570/start/tms570_selftest_par_std.c b/bsps/arm/tms570/start/tms570_selftest_par_std.c index 60bc35d422..da82f47a94 100644 --- a/bsps/arm/tms570/start/tms570_selftest_par_std.c +++ b/bsps/arm/tms570/start/tms570_selftest_par_std.c @@ -1,24 +1,45 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * * @ingroup RTEMSBSPsARMTMS570 * - * @brief Generic parity based protection logic check applicable to HETx, HTUx, ADC, DMA and VIM. + * @brief This source file contains the HETx, HTUx, ADC, DMA and VIM module + * parity based protection support. + * + * Algorithms are based on Ti manuals and Ti HalCoGen generated + * code. */ + /* - * Copyright (c) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz> + * Copyright (C) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz> * * Czech Technical University in Prague * Zikova 1903/4 * 166 36 Praha 6 * Czech Republic * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * Algorithms are based on Ti manuals and Ti HalCoGen generated - * code. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include <stdint.h> diff --git a/bsps/arm/tms570/start/tms570_selftest_parity.c b/bsps/arm/tms570/start/tms570_selftest_parity.c index 8152180eee..0ceec446d3 100644 --- a/bsps/arm/tms570/start/tms570_selftest_parity.c +++ b/bsps/arm/tms570/start/tms570_selftest_parity.c @@ -1,21 +1,42 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * * @ingroup RTEMSBSPsARMTMS570 * - * @brief Check of module parity based protection logic to work. + * @brief This source file contains parts of the parity based protection + * support. */ + /* - * Copyright (c) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz> + * Copyright (C) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz> * * Czech Technical University in Prague * Zikova 1903/4 * 166 36 Praha 6 * Czech Republic * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include <stdint.h> diff --git a/bsps/arm/tms570/start/tms570_sys_core.S b/bsps/arm/tms570/start/tms570_sys_core.S index de44cf0d10..83dee26ec8 100644 --- a/bsps/arm/tms570/start/tms570_sys_core.S +++ b/bsps/arm/tms570/start/tms570_sys_core.S @@ -1,3 +1,13 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsARMTMS570 + * + * @brief This source file contains the parts of the system initialization. + */ + /*-------------------------------------------------------------------------- tms570_sys_core.S @@ -572,4 +582,206 @@ _errata_CORTEXR4_66_: mcr p15, #0, r0, c1, c0, #1 @ Write Auxiliary Control register pop {r0} bx lr + /*-------------------------------------------------------------------------------*/ +@ Initialize Mpu: pulled from LC4357 R5f Halcogen generation + + .weak _mpuInit_ + .type _mpuInit_, %function + +_mpuInit_: + @ Disable mpu + mrc p15, #0, r0, c1, c0, #0 + bic r0, r0, #1 + dsb + mcr p15, #0, r0, c1, c0, #0 + isb + @ Disable background region + mrc p15, #0, r0, c1, c0, #0 + bic r0, r0, #0x20000 + mcr p15, #0, r0, c1, c0, #0 + @ Setup region 1 + mov r0, #0 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r1Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x0008 + orr r0, r0, #0x1000 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((1 << 15) + (1 << 14) + (1 << 13) + (1 << 12) + (1 << 11) + (1 << 10) + (1 << 9) + (1 << 8) + (0x1F << 1) + (1)) + mcr p15, #0, r0, c6, c1, #2 + @ Setup region 2 + mov r0, #1 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r2Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x0002 + orr r0, r0, #0x0600 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x15 << 1) + (1)) + mcr p15, #0, r0, c6, c1, #2 + @ Setup region 3 - Internal RAM + mov r0, #2 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r3Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x000B + orr r0, r0, #0x0300 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x12 << 1) + (1)) + mcr p15, #0, r0, c6, c1, #2 + @ Setup region 4 + mov r0, #3 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r4Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x0010 + orr r0, r0, #0x1300 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (1 << 10) + (1 << 9) + (1 << 8) + (0x1A << 1) + (1)) + mcr p15, #0, r0, c6, c1, #2 + @ Setup region 5 + mov r0, #4 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r5Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x0000 + orr r0, r0, #0x0300 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((1 << 15) + (1 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x1B << 1) + (1)) + mcr p15, #0, r0, c6, c1, #2 + @ Setup region 6 - EMIF CS0 == External SDRAM + mov r0, #5 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r6Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x0002 + orr r0, r0, #0x0300 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x1A << 1) + (1)) + mcr p15, #0, r0, c6, c1, #2 + @ Setup region 7 + mov r0, #6 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r7Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x0008 + orr r0, r0, #0x1200 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x16 << 1) + (1)) + mcr p15, #0, r0, c6, c1, #2 + @ Setup region 8 + mov r0, #7 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r8Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x0010 + orr r0, r0, #0x1200 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x04 << 1) + (0)) + mcr p15, #0, r0, c6, c1, #2 + @ Setup region 9 + mov r0, #8 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r9Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x0006 + orr r0, r0, #0x1200 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x04 << 1) + (0)) + mcr p15, #0, r0, c6, c1, #2 + @ Setup region 10 + mov r0, #9 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r10Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x000C + orr r0, r0, #0x1300 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x04 << 1) + (0)) + mcr p15, #0, r0, c6, c1, #2 + @ Setup region 11 + mov r0, #10 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r11Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x0006 + orr r0, r0, #0x0600 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x04 << 1) + (0)) + mcr p15, #0, r0, c6, c1, #2 + @ Setup region 12 + mov r0, #11 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r12Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x0006 + orr r0, r0, #0x1600 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x04 << 1) + (0)) + mcr p15, #0, r0, c6, c1, #2 + @ Setup region 13 + mov r0, #12 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r13Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x0006 + orr r0, r0, #0x1600 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x04 << 1) + (0)) + mcr p15, #0, r0, c6, c1, #2 + @ Setup region 14 + mov r0, #13 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r14Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x0006 + orr r0, r0, #0x1600 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x04 << 1) + (0)) + mcr p15, #0, r0, c6, c1, #2 + @ Setup region 15 + mov r0, #14 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r15Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x0006 + orr r0, r0, #0x1600 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x04 << 1) + (0)) + mcr p15, #0, r0, c6, c1, #2 + @ Setup region 16 + mov r0, #15 + mcr p15, #0, r0, c6, c2, #0 + ldr r0, r16Base + mcr p15, #0, r0, c6, c1, #0 + mov r0, #0x0010 + orr r0, r0, #0x1200 + mcr p15, #0, r0, c6, c1, #4 + movw r0, #((0 << 15) + (0 << 14) + (0 << 13) + (0 << 12) + (0 << 11) + (0 << 10) + (0 << 9) + (0 << 8) + (0x12 << 1) + (1)) + mcr p15, #0, r0, c6, c1, #2 + + @ Enable mpu + mrc p15, #0, r0, c1, c0, #0 + orr r0, r0, #1 + dsb + mcr p15, #0, r0, c1, c0, #0 + isb + bx lr + +r1Base: .word 0x00000000 +r2Base: .word 0x00000000 +r3Base: .word 0x08000000 +r4Base: .word 0xF8000000 +r5Base: .word 0x60000000 +r6Base: .word 0x80000000 +r7Base: .word 0xF0000000 +r8Base: .word 0x00000000 +r9Base: .word 0x00000000 +r10Base: .word 0x00000000 +r11Base: .word 0x00000000 +r12Base: .word 0x00000000 +r13Base: .word 0x00000000 +r14Base: .word 0x00000000 +r15Base: .word 0x00000000 +r16Base: .word 0xFFF80000 diff --git a/bsps/arm/tms570/start/tms570_tcram_tests.c b/bsps/arm/tms570/start/tms570_tcram_tests.c index e920717cd8..edfd441874 100644 --- a/bsps/arm/tms570/start/tms570_tcram_tests.c +++ b/bsps/arm/tms570/start/tms570_tcram_tests.c @@ -1,26 +1,24 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + /** * @file * * @ingroup RTEMSBSPsARMTMS570 * - * @brief TCRAM selftest function. + * @brief This source file contains TCRAM selftest functions. */ + /* - * Copyright (c) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz> + * Copyright (C) 2016 Pavel Pisa <pisa@cmp.felk.cvut.cz> * * Czech Technical University in Prague * Zikova 1903/4 * 166 36 Praha 6 * Czech Republic * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - * * Algorithms are based on Ti manuals and Ti HalCoGen generated * code available under following copyright. - */ -/* + * * Copyright (C) 2009-2015 Texas Instruments Incorporated - www.ti.com * * @@ -59,6 +57,8 @@ #include <bsp/tms570_selftest.h> #include <bsp/tms570_hwinit.h> +#if TMS570_VARIANT == 3137 + #define tcramA1bitError (*(volatile uint32_t *)(0x08400000U)) #define tcramA2bitError (*(volatile uint32_t *)(0x08400010U)) @@ -183,3 +183,5 @@ void tms570_check_tcram_ecc( void ) tcramA2bit = tcramA2_bk; tcramB2bit = tcramB2_bk; } + +#endif /* TMS570_VARIANT */ |