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-rw-r--r--bsps/arm/stm32h7/start/bsp_specs0
-rw-r--r--bsps/arm/stm32h7/start/bspstart.c2
-rw-r--r--bsps/arm/stm32h7/start/bspstarthooks.c48
-rw-r--r--bsps/arm/stm32h7/start/ext-mem-ctl.c951
-rw-r--r--bsps/arm/stm32h7/start/getentropy-rng.c2
-rw-r--r--bsps/arm/stm32h7/start/mpu-config.c9
-rw-r--r--bsps/arm/stm32h7/start/stm32h7-config-clk.c45
-rw-r--r--bsps/arm/stm32h7/start/stm32h7-config-fls.c4
-rw-r--r--bsps/arm/stm32h7/start/stm32h7-config-osc.c52
-rw-r--r--bsps/arm/stm32h7/start/stm32h7-config-per.c62
-rw-r--r--bsps/arm/stm32h7/start/stm32h7-config-pwr.c2
-rw-r--r--bsps/arm/stm32h7/start/stm32h7-hal-eth.c6
-rw-r--r--bsps/arm/stm32h7/start/stm32h7-hal-sdmmc.c4
-rw-r--r--bsps/arm/stm32h7/start/stm32h7-hal-uart.c2
-rw-r--r--bsps/arm/stm32h7/start/stm32h7-hal.c22
-rw-r--r--bsps/arm/stm32h7/start/system_stm32h7xx.c416
16 files changed, 526 insertions, 1101 deletions
diff --git a/bsps/arm/stm32h7/start/bsp_specs b/bsps/arm/stm32h7/start/bsp_specs
deleted file mode 100644
index e69de29bb2..0000000000
--- a/bsps/arm/stm32h7/start/bsp_specs
+++ /dev/null
diff --git a/bsps/arm/stm32h7/start/bspstart.c b/bsps/arm/stm32h7/start/bspstart.c
index cdc23d4911..b275e2bfbe 100644
--- a/bsps/arm/stm32h7/start/bspstart.c
+++ b/bsps/arm/stm32h7/start/bspstart.c
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
- * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2020 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/bsps/arm/stm32h7/start/bspstarthooks.c b/bsps/arm/stm32h7/start/bspstarthooks.c
index dcd4b0bef2..ac0f712e31 100644
--- a/bsps/arm/stm32h7/start/bspstarthooks.c
+++ b/bsps/arm/stm32h7/start/bspstarthooks.c
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
- * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2020 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -41,9 +41,9 @@ void HAL_MspInit(void)
__HAL_RCC_SYSCFG_CLK_ENABLE();
}
-static void init_power(void)
+void stm32h7_init_power(void)
{
- HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
+ HAL_PWREx_ConfigSupply(STM32H7_PWR_SUPPLY);
__HAL_PWR_VOLTAGESCALING_CONFIG(stm32h7_config_pwr_regulator_voltagescaling);
while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {
@@ -51,7 +51,7 @@ static void init_power(void)
}
}
-static void init_oscillator(void)
+void stm32h7_init_oscillator(void)
{
HAL_StatusTypeDef status;
@@ -61,7 +61,7 @@ static void init_oscillator(void)
}
}
-static void init_clocks(void)
+void stm32h7_init_clocks(void)
{
HAL_StatusTypeDef status;
@@ -74,7 +74,7 @@ static void init_clocks(void)
}
}
-static void init_peripheral_clocks(void)
+void stm32h7_init_peripheral_clocks(void)
{
HAL_StatusTypeDef status;
@@ -84,39 +84,3 @@ static void init_peripheral_clocks(void)
}
}
-void bsp_start_hook_0(void)
-{
- if ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN) == 0) {
- /*
- * Only perform the low-level initialization if necessary. An initialized
- * FMC indicates that a boot loader already performed the low-level
- * initialization.
- */
- SystemInit();
- init_power();
- init_oscillator();
- init_clocks();
- init_peripheral_clocks();
- HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1);
- HAL_Init();
- SystemInit_ExtMemCtl();
- }
-
- if ((SCB->CCR & SCB_CCR_IC_Msk) == 0) {
- SCB_EnableICache();
- }
-
- if ((SCB->CCR & SCB_CCR_DC_Msk) == 0) {
- SCB_EnableDCache();
- }
-
- _ARMV7M_MPU_Setup(stm32h7_config_mpu_region, stm32h7_config_mpu_region_count);
-}
-
-void bsp_start_hook_1(void)
-{
- bsp_start_copy_sections_compact();
- SCB_CleanDCache();
- SCB_InvalidateICache();
- bsp_start_clear_bss();
-}
diff --git a/bsps/arm/stm32h7/start/ext-mem-ctl.c b/bsps/arm/stm32h7/start/ext-mem-ctl.c
index 4088010696..a2ab9d8f1f 100644
--- a/bsps/arm/stm32h7/start/ext-mem-ctl.c
+++ b/bsps/arm/stm32h7/start/ext-mem-ctl.c
@@ -1,473 +1,478 @@
-/**
- ******************************************************************************
- * @file system_stm32h7xx.c
- * @author MCD Application Team
- * @brief CMSIS Cortex-M Device Peripheral Access Layer System Source File.
- *
- * This file provides two functions and one global variable to be called from
- * user application:
- * - SystemInit(): This function is called at startup just after reset and
- * before branch to main program. This call is made inside
- * the "startup_stm32h7xx.s" file.
- *
- * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
- * by the user application to setup the SysTick
- * timer or configure other parameters.
- *
- * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
- * be called whenever the core clock is changed
- * during program execution.
- *
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-#include <stm32h7xx_hal.h>
-
-#define DATA_IN_ExtSRAM
-#define DATA_IN_ExtSDRAM
-
-void SystemInit_ExtMemCtl(void)
-{
-
- #define FMC_BMAP_Value 0x02000000 /* FMC Bank Mapping 2 (SDRAM Bank2 remapped) */
-
- __IO uint32_t tmp = 0;
-
-
- /********** SDRAM + SRAM ***********************************************************************/
-
- #if defined (DATA_IN_ExtSDRAM) && defined (DATA_IN_ExtSRAM)
-
- register uint32_t tmpreg = 0, timeout = 0xFFFF;
- register __IO uint32_t index;
-
- /*-- I/O Ports Configuration ------------------------------------------------------*/
-
- /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
- RCC->AHB4ENR |= 0x000001F8;
-
- /* Delay after an RCC peripheral clock enabling */
- tmp = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);
-
- /* Connect PDx pins to FMC Alternate function */
- GPIOD->AFR[0] = 0x00CC00CC;
- GPIOD->AFR[1] = 0xCCCCCCCC;
- /* Configure PDx pins in Alternate function mode */
- GPIOD->MODER = 0xAAAAFAFA;
- /* Configure PDx pins speed to VERY_HIGH */
- GPIOD->OSPEEDR = 0xFFFFFF0F;
- /* Configure PDx pins Output type to push-pull */
- GPIOD->OTYPER = 0x00000000;
- /* Configure PDx pins in Pull-up */
- GPIOD->PUPDR = 0x55550505;
-
- /* Connect PEx pins to FMC Alternate function */
- GPIOE->AFR[0] = 0xC00CC0CC;
- GPIOE->AFR[1] = 0xCCCCCCCC;
- /* Configure PEx pins in Alternate function mode */
- GPIOE->MODER = 0xAAAABEBA;
- /* Configure PEx pins speed to VERY_HIGH */
- GPIOE->OSPEEDR = 0xFFFFFFFF;
- /* Configure PEx pins Output type to push-pull */
- GPIOE->OTYPER = 0x00000000;
- /* Configure PEx pins in Pull-up */
- GPIOE->PUPDR = 0x55554145;
-
- /* Connect PFx pins to FMC Alternate function */
- GPIOF->AFR[0] = 0x00CCCCCC;
- GPIOF->AFR[1] = 0xCCCCC000;
- /* Configure PFx pins in Alternate function mode */
- GPIOF->MODER = 0xAABFFAAA;
- /* Configure PFx pins speed to VERY_HIGH */
- GPIOF->OSPEEDR = 0xFFC00FFF;
- /* Configure PFx pins Output type to push-pull */
- GPIOF->OTYPER = 0x00000000;
- /* Configure PFx pins in Pull-up */
- GPIOF->PUPDR = 0x55400555;
-
- /* Connect PGx pins to FMC Alternate function */
- GPIOG->AFR[0] = 0x00CCCCCC;
- GPIOG->AFR[1] = 0xC0000C0C;
- /* Configure PGx pins in Alternate function mode */
- GPIOG->MODER = 0xBFEEFAAA;
- /* Configure PGx pins speed to VERY_HIGH */
- GPIOG->OSPEEDR = 0xC0330FFF;
- /* Configure PGx pins Output type to push-pull */
- GPIOG->OTYPER = 0x00000000;
- /* Configure PGx pins in Pull-up */
- GPIOG->PUPDR = 0x40110555;
-
- /* Connect PHx pins to FMC Alternate function */
- GPIOH->AFR[0] = 0xCCC00000;
- GPIOH->AFR[1] = 0xCCCCCCCC;
- /* Configure PHx pins in Alternate function mode */
- GPIOH->MODER = 0xAAAAABFF;
- /* Configure PHx pins speed to VERY_HIGH */
- GPIOH->OSPEEDR = 0xFFFFFC00;
- /* Configure PHx pins Output type to push-pull */
- GPIOH->OTYPER = 0x00000000;
- /* Configure PHx pins in Pull-up */
- GPIOH->PUPDR = 0x55555400;
-
- /* Connect PIx pins to FMC Alternate function */
- GPIOI->AFR[0] = 0xCCCCCCCC;
- GPIOI->AFR[1] = 0x00000CC0;
- /* Configure PIx pins in Alternate function mode */
- GPIOI->MODER = 0xFFEBAAAA;
- /* Configure PIx pins speed to VERY_HIGH */
- GPIOI->OSPEEDR = 0x003CFFFF;
- /* Configure PIx pins Output type to push-pull */
- GPIOI->OTYPER = 0x00000000;
- /* Configure PIx pins in Pull-up */
- GPIOI->PUPDR = 0x00145555;
-
- /*-- FMC Configuration ------------------------------------------------------*/
-
- /* Enable the FMC/FSMC interface clock */
- (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN));
-
- /* Configure and enable Bank1_SRAM2 */
- FMC_Bank1_R->BTCR[4] = 0x00001091;
- FMC_Bank1_R->BTCR[5] = 0x00110212;
- FMC_Bank1E_R->BWTR[4] = 0x0FFFFFFF;
-
- /* SDRAM Timing and access interface configuration */
-
- /*SDBank = FMC_SDRAM_BANK2
-
- ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_9 CC
- RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12 RR
- MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_32 MM
- InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4 N
- CASLatency = FMC_SDRAM_CAS_LATENCY_2 LL // 2 oder 3, s.u.
- WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE W
- SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2 KK
- ReadBurst = FMC_SDRAM_RBURST_ENABLE B
- ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0 PP
-
- LoadToActiveDelay = 2 -> 1 LLLL TMRD
- ExitSelfRefreshDelay = 6 -> 5 EEEE TXSR
- SelfRefreshTime = 4 -> 3 SSSS TRAS
- RowCycleDelay = 6 -> 5 RRRR TRC
- WriteRecoveryTime = 2 -> 1 WWWW TWR
- RPDelay = 2 -> 1 PPPP TRP
- RCDDelay = 2 -> 1 CCCC TRCD */
-
- FMC_Bank5_6_R->SDCR[0] = 0x00005965; // 0000 0000 0000 0000 0101 1001 0110 0101 Bank 1
- // PPB KKWL LNMM RRCC
- FMC_Bank5_6_R->SDCR[1] = 0x00005965; // 0000 0000 0000 0000 0101 1001 0110 0101 Bank 2 // CAS Latency = 2
- // WL LNMM RRCC
-
- FMC_Bank5_6_R->SDTR[0] = 0x00105000; // 0000 0000 0001 0000 0101 0000 0000 0000 Bank 1 // Original,
- // CCCC PPPP WWWW RRRR SSSS EEEE LLLL // mit CAS Latency = 2 (s.o.)
- FMC_Bank5_6_R->SDTR[1] = 0x01010351; // 0000 0001 0000 0001 0000 0011 0101 0001 Bank 2
- // CCCC WWWW SSSS EEEE LLLL
- #if 0
- FMC_Bank5_6_R->SDTR[0] = 0x00206000; // 0000 0000 0010 0000 0110 0000 0000 0000 Bank 1 // Original + 1 bei allen Werten,
- // CCCC PPPP WWWW RRRR SSSS EEEE LLLL // mit CAS Latency = 3 (s.o.)
- FMC_Bank5_6_R->SDTR[1] = 0x02020462; // 0000 0010 0000 0010 0000 0100 0110 0010 Bank 2
- // CCCC WWWW SSSS EEEE LLLL
- #endif
-
- #if 0
- FMC_Bank5_6_R->SDTR[0] = 0x00209000; // 0000 0000 0010 0000 1001 0000 0000 0000 Bank 1 // Versuch anhand ISSI-Datenblatt,
- // CCCC PPPP WWWW RRRR SSSS EEEE LLLL // mit CAS Latency = 3 (s.o.)
- FMC_Bank5_6_R->SDTR[1] = 0x020306B1; // 0000 0010 0000 0011 0000 0110 1011 0001 Bank 2
- // CCCC WWWW SSSS EEEE LLLL
- #endif
-
- /* SDRAM initialization sequence */
-
- /* Clock enable command */
- FMC_Bank5_6_R->SDCMR = 0x00000009;
- tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
- while ((tmpreg != 0) && (timeout-- > 0))
- {
- tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
- }
-
- /* Delay */
- for (index=0; index<1000; index++);
-
- /* PALL command */
- FMC_Bank5_6_R->SDCMR = 0x0000000A;
- timeout = 0xFFFF;
- while ((tmpreg != 0) && (timeout-- > 0))
- {
- tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
- }
-
- FMC_Bank5_6_R->SDCMR = 0x000000EB;
- timeout = 0xFFFF;
- while ((tmpreg != 0) && (timeout-- > 0))
- {
- tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
- }
-
- FMC_Bank5_6_R->SDCMR = 0x0004400C;
- timeout = 0xFFFF;
- while ((tmpreg != 0) && (timeout-- > 0))
- {
- tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
- }
-
- /* Set refresh count */
- tmpreg = FMC_Bank5_6_R->SDRTR;
- FMC_Bank5_6_R->SDRTR = (tmpreg | (0x00000603 << 1));
-
- /* Disable write protection */
- tmpreg = FMC_Bank5_6_R->SDCR[1];
- FMC_Bank5_6_R->SDCR[1] = (tmpreg & 0xFFFFFDFF);
-
- /* Configure FMC Bank Mapping */
- FMC_Bank1_R->BTCR[0] |= FMC_BMAP_Value;
-
- /* FMC controller Enable */
- FMC_Bank1_R->BTCR[0] |= 0x80000000;
-
-
- /********** SDRAM only *************************************************************************/
-
- #elif defined (DATA_IN_ExtSDRAM)
-
- register uint32_t tmpreg = 0, timeout = 0xFFFF;
- register __IO uint32_t index;
-
- /*-- I/O Ports Configuration ------------------------------------------------------*/
-
- /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
- RCC->AHB4ENR |= 0x000001F8;
-
- /* Connect PDx pins to FMC Alternate function */
- GPIOD->AFR[0] = 0x000000CC;
- GPIOD->AFR[1] = 0xCC000CCC;
- /* Configure PDx pins in Alternate function mode */
- GPIOD->MODER = 0xAFEAFFFA;
- /* Configure PDx pins speed to 100 MHz */
- GPIOD->OSPEEDR = 0xF03F000F;
- /* Configure PDx pins Output type to push-pull */
- GPIOD->OTYPER = 0x00000000;
- /* Configure PDx pins in Pull-up */
- GPIOD->PUPDR = 0x50150005;
-
- /* Connect PEx pins to FMC Alternate function */
- GPIOE->AFR[0] = 0xC00000CC;
- GPIOE->AFR[1] = 0xCCCCCCCC;
- /* Configure PEx pins in Alternate function mode */
- GPIOE->MODER = 0xAAAABFFA;
- /* Configure PEx pins speed to 100 MHz */
- GPIOE->OSPEEDR = 0xFFFFC00F;
- /* Configure PEx pins Output type to push-pull */
- GPIOE->OTYPER = 0x00000000;
- /* Configure PEx pins in Pull-up */
- GPIOE->PUPDR = 0x55554005;
-
- /* Connect PFx pins to FMC Alternate function */
- GPIOF->AFR[0] = 0x00CCCCCC;
- GPIOF->AFR[1] = 0xCCCCC000;
- /* Configure PFx pins in Alternate function mode */
- GPIOF->MODER = 0xAABFFAAA;
- /* Configure PFx pins speed to 100 MHz */
- GPIOF->OSPEEDR = 0xFFC00FFF;
- /* Configure PFx pins Output type to push-pull */
- GPIOF->OTYPER = 0x00000000;
- /* Configure PFx pins in Pull-up */
- GPIOF->PUPDR = 0x55400555;
-
- /* Connect PGx pins to FMC Alternate function */
- GPIOG->AFR[0] = 0x00CCCCCC;
- GPIOG->AFR[1] = 0xC000000C;
- /* Configure PGx pins in Alternate function mode */
- GPIOG->MODER = 0xBFFEFAAA;
- /* Configure PGx pins speed to 100 MHz */
- GPIOG->OSPEEDR = 0xC0030FFF;
- /* Configure PGx pins Output type to push-pull */
- GPIOG->OTYPER = 0x00000000;
- /* Configure PGx pins in Pull-up */
- GPIOG->PUPDR = 0x40010555;
-
- /* Connect PHx pins to FMC Alternate function */
- GPIOH->AFR[0] = 0xCCC00000;
- GPIOH->AFR[1] = 0xCCCCCCCC;
- /* Configure PHx pins in Alternate function mode */
- GPIOH->MODER = 0xAAAAABFF;
- /* Configure PHx pins speed to 100 MHz */
- GPIOH->OSPEEDR = 0xFFFFFC00;
- /* Configure PHx pins Output type to push-pull */
- GPIOH->OTYPER = 0x00000000;
- /* Configure PHx pins in Pull-up */
- GPIOH->PUPDR = 0x55555400;
-
- /* Connect PIx pins to FMC Alternate function */
- GPIOI->AFR[0] = 0xCCCCCCCC;
- GPIOI->AFR[1] = 0x00000CC0;
- /* Configure PIx pins in Alternate function mode */
- GPIOI->MODER = 0xFFEBAAAA;
- /* Configure PIx pins speed to 100 MHz */
- GPIOI->OSPEEDR = 0x003CFFFF;
- /* Configure PIx pins Output type to push-pull */
- GPIOI->OTYPER = 0x00000000;
- /* Configure PIx pins in Pull-up */
- GPIOI->PUPDR = 0x00145555;
-
- /*-- FMC Configuration ------------------------------------------------------*/
-
- /* Enable the FMC interface clock */
- (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN));
-
- /* SDRAM Timing and access interface configuration */
-
- /*LoadToActiveDelay = 2
- ExitSelfRefreshDelay = 6
- SelfRefreshTime = 4
- RowCycleDelay = 6
- WriteRecoveryTime = 2
- RPDelay = 2
- RCDDelay = 2
- SDBank = FMC_SDRAM_BANK2
- ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_9
- RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12
- MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_32
- InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4
- CASLatency = FMC_SDRAM_CAS_LATENCY_2
- WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE
- SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2
- ReadBurst = FMC_SDRAM_RBURST_ENABLE
- ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0*/
-
- FMC_Bank5_6_R->SDCR[0] = 0x00001800;
- FMC_Bank5_6_R->SDCR[1] = 0x00000165;
- FMC_Bank5_6_R->SDTR[0] = 0x00105000;
- FMC_Bank5_6_R->SDTR[1] = 0x01010351;
-
- /* SDRAM initialization sequence */
- /* Clock enable command */
- FMC_Bank5_6_R->SDCMR = 0x00000009;
- tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
- while ((tmpreg != 0) && (timeout-- > 0))
- {
- tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
- }
-
- /* Delay */
- for (index=0; index<1000; index++);
-
- /* PALL command */
- FMC_Bank5_6_R->SDCMR = 0x0000000A;
- timeout = 0xFFFF;
- while ((tmpreg != 0) && (timeout-- > 0))
- {
- tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
- }
-
- FMC_Bank5_6_R->SDCMR = 0x000000EB;
- timeout = 0xFFFF;
- while ((tmpreg != 0) && (timeout-- > 0))
- {
- tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
- }
-
- FMC_Bank5_6_R->SDCMR = 0x0004400C;
- timeout = 0xFFFF;
- while ((tmpreg != 0) && (timeout-- > 0))
- {
- tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
- }
- /* Set refresh count */
- tmpreg = FMC_Bank5_6_R->SDRTR;
- FMC_Bank5_6_R->SDRTR = (tmpreg | (0x00000603<<1));
-
- /* Disable write protection */
- tmpreg = FMC_Bank5_6_R->SDCR[1];
- FMC_Bank5_6_R->SDCR[1] = (tmpreg & 0xFFFFFDFF);
-
- /* FMC controller Enable */
- FMC_Bank1_R->BTCR[0] |= 0x80000000;
-
- /********** SRAM only **************************************************************************/
-
- #elif defined(DATA_IN_ExtSRAM)
-
- /*-- I/O Ports Configuration -----------------------------------------------------*/
-
- /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
- RCC->AHB4ENR |= 0x00000078;
-
- /* Connect PDx pins to FMC Alternate function */
- GPIOD->AFR[0] = 0x00CC00CC;
- GPIOD->AFR[1] = 0xCCCCCCCC;
- /* Configure PDx pins in Alternate function mode */
- GPIOD->MODER = 0xAAAAFABA;
- /* Configure PDx pins speed to 100 MHz */
- GPIOD->OSPEEDR = 0xFFFF0F0F;
- /* Configure PDx pins Output type to push-pull */
- GPIOD->OTYPER = 0x00000000;
- /* Configure PDx pins in Pull-up */
- GPIOD->PUPDR = 0x55550505;
-
- /* Connect PEx pins to FMC Alternate function */
- GPIOE->AFR[0] = 0xC00CC0CC;
- GPIOE->AFR[1] = 0xCCCCCCCC;
- /* Configure PEx pins in Alternate function mode */
- GPIOE->MODER = 0xAAAABEBA;
- /* Configure PEx pins speed to 100 MHz */
- GPIOE->OSPEEDR = 0xFFFFC3CF;
- /* Configure PEx pins Output type to push-pull */
- GPIOE->OTYPER = 0x00000000;
- /* Configure PEx pins in Pull-up */
- GPIOE->PUPDR = 0x55554145;
-
- /* Connect PFx pins to FMC Alternate function */
- GPIOF->AFR[0] = 0x00CCCCCC;
- GPIOF->AFR[1] = 0xCCCC0000;
- /* Configure PFx pins in Alternate function mode */
- GPIOF->MODER = 0xAAFFFAAA;
- /* Configure PFx pins speed to 100 MHz */
- GPIOF->OSPEEDR = 0xFF000FFF;
- /* Configure PFx pins Output type to push-pull */
- GPIOF->OTYPER = 0x00000000;
- /* Configure PFx pins in Pull-up */
- GPIOF->PUPDR = 0x55000555;
-
- /* Connect PGx pins to FMC Alternate function */
- GPIOG->AFR[0] = 0x00CCCCCC;
- GPIOG->AFR[1] = 0x00000C00;
- /* Configure PGx pins in Alternate function mode */
- GPIOG->MODER = 0xFFEFFAAA;
- /* Configure PGx pins speed to 100 MHz */
- GPIOG->OSPEEDR = 0x00300FFF;
- /* Configure PGx pins Output type to push-pull */
- GPIOG->OTYPER = 0x00000000;
- /* Configure PGx pins in Pull-up */
- GPIOG->PUPDR = 0x00100555;
-
- /*-- FMC/FSMC Configuration --------------------------------------------------*/
-
- /* Enable the FMC/FSMC interface clock */
- (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN));
-
- /* Configure and enable Bank1_SRAM2 */
- FMC_Bank1_R->BTCR[4] = 0x00001091;
- FMC_Bank1_R->BTCR[5] = 0x00110212;
- FMC_Bank1E_R->BWTR[4] = 0x0FFFFFFF;
-
- /* FMC controller Enable */
- FMC_Bank1_R->BTCR[0] |= 0x80000000;
-
- #endif /* DATA_IN_ExtSRAM */
-
- (void)(tmp);
-
-}
+/**
+ ******************************************************************************
+ * @file system_stm32h7xx.c
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M Device Peripheral Access Layer System Source File.
+ *
+ * This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32h7xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+#include <stm32h7xx_hal.h>
+
+#define DATA_IN_ExtSRAM
+#define DATA_IN_ExtSDRAM
+
+void SystemInit_ExtMemCtl(void)
+{
+
+ #define FMC_BMAP_Value 0x02000000 /* FMC Bank Mapping 2 (SDRAM Bank2 remapped) */
+
+ __IO uint32_t tmp = 0;
+
+
+ /********** SDRAM + SRAM ***********************************************************************/
+
+ #if defined (DATA_IN_ExtSDRAM) && defined (DATA_IN_ExtSRAM)
+
+ register uint32_t tmpreg = 0, timeout = 0xFFFF;
+ register __IO uint32_t index;
+
+ /*-- I/O Ports Configuration ------------------------------------------------------*/
+
+ /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
+ RCC->AHB4ENR |= 0x000001F8;
+
+ /* Delay after an RCC peripheral clock enabling */
+ tmp = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);
+
+ /* Connect PDx pins to FMC Alternate function */
+ GPIOD->AFR[0] = 0x00CC00CC;
+ GPIOD->AFR[1] = 0xCCCCCCCC;
+ /* Configure PDx pins in Alternate function mode */
+ GPIOD->MODER = 0xAAAAFAFA;
+ /* Configure PDx pins speed to 100 MHz */
+ GPIOD->OSPEEDR = 0xFFFF0F0F;
+ /* Configure PDx pins Output type to push-pull */
+ GPIOD->OTYPER = 0x00000000;
+ /* Configure PDx pins in Pull-up */
+ GPIOD->PUPDR = 0x55550505;
+
+ /* Connect PEx pins to FMC Alternate function */
+ GPIOE->AFR[0] = 0xC00CC0CC;
+ GPIOE->AFR[1] = 0xCCCCCCCC;
+ /* Configure PEx pins in Alternate function mode */
+ GPIOE->MODER = 0xAAAABEBA;
+ /* Configure PEx pins speed to 100 MHz */
+ GPIOE->OSPEEDR = 0xFFFFC3CF;
+ /* Configure PEx pins Output type to push-pull */
+ GPIOE->OTYPER = 0x00000000;
+ /* Configure PEx pins in Pull-up */
+ GPIOE->PUPDR = 0x55554145;
+
+ /* Connect PFx pins to FMC Alternate function */
+ GPIOF->AFR[0] = 0x00CCCCCC;
+ GPIOF->AFR[1] = 0xCCCCC000;
+ /* Configure PFx pins in Alternate function mode */
+ GPIOF->MODER = 0xAABFFAAA;
+ /* Configure PFx pins speed to 100 MHz */
+ GPIOF->OSPEEDR = 0xFFC00FFF;
+ /* Configure PFx pins Output type to push-pull */
+ GPIOF->OTYPER = 0x00000000;
+ /* Configure PFx pins in Pull-up */
+ GPIOF->PUPDR = 0x55400555;
+
+ /* Connect PGx pins to FMC Alternate function */
+ GPIOG->AFR[0] = 0x00CCCCCC;
+ GPIOG->AFR[1] = 0xC0000C0C;
+ /* Configure PGx pins in Alternate function mode */
+ GPIOG->MODER = 0xBFEEFAAA;
+ /* Configure PGx pins speed to 100 MHz */
+ GPIOG->OSPEEDR = 0xC0330FFF;
+ /* Configure PGx pins Output type to push-pull */
+ GPIOG->OTYPER = 0x00000000;
+ /* Configure PGx pins in Pull-up */
+ GPIOG->PUPDR = 0x40110555;
+
+ /* Connect PHx pins to FMC Alternate function */
+ GPIOH->AFR[0] = 0xCCC00000;
+ GPIOH->AFR[1] = 0xCCCCCCCC;
+ /* Configure PHx pins in Alternate function mode */
+ GPIOH->MODER = 0xAAAAABFF;
+ /* Configure PHx pins speed to 100 MHz */
+ GPIOH->OSPEEDR = 0xFFFFFC00;
+ /* Configure PHx pins Output type to push-pull */
+ GPIOH->OTYPER = 0x00000000;
+ /* Configure PHx pins in Pull-up */
+ GPIOH->PUPDR = 0x55555400;
+
+ /* Connect PIx pins to FMC Alternate function */
+ GPIOI->AFR[0] = 0xCCCCCCCC;
+ GPIOI->AFR[1] = 0x00000CC0;
+ /* Configure PIx pins in Alternate function mode */
+ GPIOI->MODER = 0xFFEBAAAA;
+ /* Configure PIx pins speed to 100 MHz */
+ GPIOI->OSPEEDR = 0x003CFFFF;
+ /* Configure PIx pins Output type to push-pull */
+ GPIOI->OTYPER = 0x00000000;
+ /* Configure PIx pins in Pull-up */
+ GPIOI->PUPDR = 0x00145555;
+
+ /*-- FMC Configuration ------------------------------------------------------*/
+
+ /* Enable the FMC/FSMC interface clock */
+ (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN));
+
+ /* Configure and enable Bank1_SRAM2 */
+ FMC_Bank1_R->BTCR[4] = 0x00001091;
+ FMC_Bank1_R->BTCR[5] = 0x00110212;
+ FMC_Bank1E_R->BWTR[4] = 0x0FFFFFFF;
+
+ /* SDRAM Timing and access interface configuration */
+
+ /*SDBank = FMC_SDRAM_BANK2
+
+ ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_9 CC
+ RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12 RR
+ MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_32 MM
+ InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4 N
+ CASLatency = FMC_SDRAM_CAS_LATENCY_2 LL // 2 oder 3, s.u.
+ WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE W
+ SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2 KK
+ ReadBurst = FMC_SDRAM_RBURST_ENABLE B
+ ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0 PP
+
+ LoadToActiveDelay = 2 -> 1 LLLL TMRD
+ ExitSelfRefreshDelay = 6 -> 5 EEEE TXSR
+ SelfRefreshTime = 4 -> 3 SSSS TRAS
+ RowCycleDelay = 6 -> 5 RRRR TRC
+ WriteRecoveryTime = 2 -> 1 WWWW TWR
+ RPDelay = 2 -> 1 PPPP TRP
+ RCDDelay = 2 -> 1 CCCC TRCD */
+ #if 0
+ FMC_Bank5_6_R->SDCR[0] = 0x00005965; // 0000 0000 0000 0000 0101 1001 0110 0101 Bank 1
+ // PPB KKWL LNMM RRCC
+ FMC_Bank5_6_R->SDCR[1] = 0x00005965; // 0000 0000 0000 0000 0101 1001 0110 0101 Bank 2 // CAS Latency = 2
+ // WL LNMM RRCC
+
+ FMC_Bank5_6_R->SDTR[0] = 0x00105000; // 0000 0000 0001 0000 0101 0000 0000 0000 Bank 1 // Original,
+ // CCCC PPPP WWWW RRRR SSSS EEEE LLLL // mit CAS Latency = 2 (s.o.)
+ FMC_Bank5_6_R->SDTR[1] = 0x01010351; // 0000 0001 0000 0001 0000 0011 0101 0001 Bank 2
+ // CCCC WWWW SSSS EEEE LLLL
+ #endif
+ #if 0
+ FMC_Bank5_6_R->SDTR[0] = 0x00206000; // 0000 0000 0010 0000 0110 0000 0000 0000 Bank 1 // Original + 1 bei allen Werten,
+ // CCCC PPPP WWWW RRRR SSSS EEEE LLLL // mit CAS Latency = 3 (s.o.)
+ FMC_Bank5_6_R->SDTR[1] = 0x02020462; // 0000 0010 0000 0010 0000 0100 0110 0010 Bank 2
+ // CCCC WWWW SSSS EEEE LLLL
+ #endif
+
+ #if 0
+ FMC_Bank5_6_R->SDTR[0] = 0x00209000; // 0000 0000 0010 0000 1001 0000 0000 0000 Bank 1 // Versuch anhand ISSI-Datenblatt,
+ // CCCC PPPP WWWW RRRR SSSS EEEE LLLL // mit CAS Latency = 3 (s.o.)
+ FMC_Bank5_6_R->SDTR[1] = 0x020306B1; // 0000 0010 0000 0011 0000 0110 1011 0001 Bank 2
+ // CCCC WWWW SSSS EEEE LLLL
+ #endif
+ FMC_Bank5_6_R->SDCR[0] = 0x00001800;
+ FMC_Bank5_6_R->SDCR[1] = 0x00000165;
+ FMC_Bank5_6_R->SDTR[0] = 0x00105000;
+ FMC_Bank5_6_R->SDTR[1] = 0x01010351;
+
+ /* SDRAM initialization sequence */
+
+ /* Clock enable command */
+ FMC_Bank5_6_R->SDCMR = 0x00000009;
+ tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
+ while ((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
+ }
+
+ /* Delay */
+ for (index=0; index<1000; index++);
+
+ /* PALL command */
+ FMC_Bank5_6_R->SDCMR = 0x0000000A;
+ timeout = 0xFFFF;
+ while ((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
+ }
+
+ FMC_Bank5_6_R->SDCMR = 0x000000EB;
+ timeout = 0xFFFF;
+ while ((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
+ }
+
+ FMC_Bank5_6_R->SDCMR = 0x0004400C;
+ timeout = 0xFFFF;
+ while ((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
+ }
+
+ /* Set refresh count */
+ tmpreg = FMC_Bank5_6_R->SDRTR;
+ FMC_Bank5_6_R->SDRTR = (tmpreg | (0x00000603 << 1));
+
+ /* Disable write protection */
+ tmpreg = FMC_Bank5_6_R->SDCR[1];
+ FMC_Bank5_6_R->SDCR[1] = (tmpreg & 0xFFFFFDFF);
+
+ /* Configure FMC Bank Mapping */
+ FMC_Bank1_R->BTCR[0] |= FMC_BMAP_Value;
+
+ /* FMC controller Enable */
+ FMC_Bank1_R->BTCR[0] |= 0x80000000;
+
+
+ /********** SDRAM only *************************************************************************/
+
+ #elif defined (DATA_IN_ExtSDRAM)
+
+ register uint32_t tmpreg = 0, timeout = 0xFFFF;
+ register __IO uint32_t index;
+
+ /*-- I/O Ports Configuration ------------------------------------------------------*/
+
+ /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
+ RCC->AHB4ENR |= 0x000001F8;
+
+ /* Connect PDx pins to FMC Alternate function */
+ GPIOD->AFR[0] = 0x000000CC;
+ GPIOD->AFR[1] = 0xCC000CCC;
+ /* Configure PDx pins in Alternate function mode */
+ GPIOD->MODER = 0xAFEAFFFA;
+ /* Configure PDx pins speed to 100 MHz */
+ GPIOD->OSPEEDR = 0xF03F000F;
+ /* Configure PDx pins Output type to push-pull */
+ GPIOD->OTYPER = 0x00000000;
+ /* Configure PDx pins in Pull-up */
+ GPIOD->PUPDR = 0x50150005;
+
+ /* Connect PEx pins to FMC Alternate function */
+ GPIOE->AFR[0] = 0xC00000CC;
+ GPIOE->AFR[1] = 0xCCCCCCCC;
+ /* Configure PEx pins in Alternate function mode */
+ GPIOE->MODER = 0xAAAABFFA;
+ /* Configure PEx pins speed to 100 MHz */
+ GPIOE->OSPEEDR = 0xFFFFC00F;
+ /* Configure PEx pins Output type to push-pull */
+ GPIOE->OTYPER = 0x00000000;
+ /* Configure PEx pins in Pull-up */
+ GPIOE->PUPDR = 0x55554005;
+
+ /* Connect PFx pins to FMC Alternate function */
+ GPIOF->AFR[0] = 0x00CCCCCC;
+ GPIOF->AFR[1] = 0xCCCCC000;
+ /* Configure PFx pins in Alternate function mode */
+ GPIOF->MODER = 0xAABFFAAA;
+ /* Configure PFx pins speed to 100 MHz */
+ GPIOF->OSPEEDR = 0xFFC00FFF;
+ /* Configure PFx pins Output type to push-pull */
+ GPIOF->OTYPER = 0x00000000;
+ /* Configure PFx pins in Pull-up */
+ GPIOF->PUPDR = 0x55400555;
+
+ /* Connect PGx pins to FMC Alternate function */
+ GPIOG->AFR[0] = 0x00CCCCCC;
+ GPIOG->AFR[1] = 0xC000000C;
+ /* Configure PGx pins in Alternate function mode */
+ GPIOG->MODER = 0xBFFEFAAA;
+ /* Configure PGx pins speed to 100 MHz */
+ GPIOG->OSPEEDR = 0xC0030FFF;
+ /* Configure PGx pins Output type to push-pull */
+ GPIOG->OTYPER = 0x00000000;
+ /* Configure PGx pins in Pull-up */
+ GPIOG->PUPDR = 0x40010555;
+
+ /* Connect PHx pins to FMC Alternate function */
+ GPIOH->AFR[0] = 0xCCC00000;
+ GPIOH->AFR[1] = 0xCCCCCCCC;
+ /* Configure PHx pins in Alternate function mode */
+ GPIOH->MODER = 0xAAAAABFF;
+ /* Configure PHx pins speed to 100 MHz */
+ GPIOH->OSPEEDR = 0xFFFFFC00;
+ /* Configure PHx pins Output type to push-pull */
+ GPIOH->OTYPER = 0x00000000;
+ /* Configure PHx pins in Pull-up */
+ GPIOH->PUPDR = 0x55555400;
+
+ /* Connect PIx pins to FMC Alternate function */
+ GPIOI->AFR[0] = 0xCCCCCCCC;
+ GPIOI->AFR[1] = 0x00000CC0;
+ /* Configure PIx pins in Alternate function mode */
+ GPIOI->MODER = 0xFFEBAAAA;
+ /* Configure PIx pins speed to 100 MHz */
+ GPIOI->OSPEEDR = 0x003CFFFF;
+ /* Configure PIx pins Output type to push-pull */
+ GPIOI->OTYPER = 0x00000000;
+ /* Configure PIx pins in Pull-up */
+ GPIOI->PUPDR = 0x00145555;
+
+ /*-- FMC Configuration ------------------------------------------------------*/
+
+ /* Enable the FMC interface clock */
+ (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN));
+
+ /* SDRAM Timing and access interface configuration */
+
+ /*LoadToActiveDelay = 2
+ ExitSelfRefreshDelay = 6
+ SelfRefreshTime = 4
+ RowCycleDelay = 6
+ WriteRecoveryTime = 2
+ RPDelay = 2
+ RCDDelay = 2
+ SDBank = FMC_SDRAM_BANK2
+ ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_9
+ RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12
+ MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_32
+ InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4
+ CASLatency = FMC_SDRAM_CAS_LATENCY_2
+ WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE
+ SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2
+ ReadBurst = FMC_SDRAM_RBURST_ENABLE
+ ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0*/
+
+ FMC_Bank5_6_R->SDCR[0] = 0x00001800;
+ FMC_Bank5_6_R->SDCR[1] = 0x00000165;
+ FMC_Bank5_6_R->SDTR[0] = 0x00105000;
+ FMC_Bank5_6_R->SDTR[1] = 0x01010351;
+
+ /* SDRAM initialization sequence */
+ /* Clock enable command */
+ FMC_Bank5_6_R->SDCMR = 0x00000009;
+ tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
+ while ((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
+ }
+
+ /* Delay */
+ for (index=0; index<1000; index++);
+
+ /* PALL command */
+ FMC_Bank5_6_R->SDCMR = 0x0000000A;
+ timeout = 0xFFFF;
+ while ((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
+ }
+
+ FMC_Bank5_6_R->SDCMR = 0x000000EB;
+ timeout = 0xFFFF;
+ while ((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
+ }
+
+ FMC_Bank5_6_R->SDCMR = 0x0004400C;
+ timeout = 0xFFFF;
+ while ((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6_R->SDSR & 0x00000020;
+ }
+ /* Set refresh count */
+ tmpreg = FMC_Bank5_6_R->SDRTR;
+ FMC_Bank5_6_R->SDRTR = (tmpreg | (0x00000603<<1));
+
+ /* Disable write protection */
+ tmpreg = FMC_Bank5_6_R->SDCR[1];
+ FMC_Bank5_6_R->SDCR[1] = (tmpreg & 0xFFFFFDFF);
+
+ /* FMC controller Enable */
+ FMC_Bank1_R->BTCR[0] |= 0x80000000;
+
+ /********** SRAM only **************************************************************************/
+
+ #elif defined(DATA_IN_ExtSRAM)
+
+ /*-- I/O Ports Configuration -----------------------------------------------------*/
+
+ /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+ RCC->AHB4ENR |= 0x00000078;
+
+ /* Connect PDx pins to FMC Alternate function */
+ GPIOD->AFR[0] = 0x00CC00CC;
+ GPIOD->AFR[1] = 0xCCCCCCCC;
+ /* Configure PDx pins in Alternate function mode */
+ GPIOD->MODER = 0xAAAAFABA;
+ /* Configure PDx pins speed to 100 MHz */
+ GPIOD->OSPEEDR = 0xFFFF0F0F;
+ /* Configure PDx pins Output type to push-pull */
+ GPIOD->OTYPER = 0x00000000;
+ /* Configure PDx pins in Pull-up */
+ GPIOD->PUPDR = 0x55550505;
+
+ /* Connect PEx pins to FMC Alternate function */
+ GPIOE->AFR[0] = 0xC00CC0CC;
+ GPIOE->AFR[1] = 0xCCCCCCCC;
+ /* Configure PEx pins in Alternate function mode */
+ GPIOE->MODER = 0xAAAABEBA;
+ /* Configure PEx pins speed to 100 MHz */
+ GPIOE->OSPEEDR = 0xFFFFC3CF;
+ /* Configure PEx pins Output type to push-pull */
+ GPIOE->OTYPER = 0x00000000;
+ /* Configure PEx pins in Pull-up */
+ GPIOE->PUPDR = 0x55554145;
+
+ /* Connect PFx pins to FMC Alternate function */
+ GPIOF->AFR[0] = 0x00CCCCCC;
+ GPIOF->AFR[1] = 0xCCCC0000;
+ /* Configure PFx pins in Alternate function mode */
+ GPIOF->MODER = 0xAAFFFAAA;
+ /* Configure PFx pins speed to 100 MHz */
+ GPIOF->OSPEEDR = 0xFF000FFF;
+ /* Configure PFx pins Output type to push-pull */
+ GPIOF->OTYPER = 0x00000000;
+ /* Configure PFx pins in Pull-up */
+ GPIOF->PUPDR = 0x55000555;
+
+ /* Connect PGx pins to FMC Alternate function */
+ GPIOG->AFR[0] = 0x00CCCCCC;
+ GPIOG->AFR[1] = 0x00000C00;
+ /* Configure PGx pins in Alternate function mode */
+ GPIOG->MODER = 0xFFEFFAAA;
+ /* Configure PGx pins speed to 100 MHz */
+ GPIOG->OSPEEDR = 0x00300FFF;
+ /* Configure PGx pins Output type to push-pull */
+ GPIOG->OTYPER = 0x00000000;
+ /* Configure PGx pins in Pull-up */
+ GPIOG->PUPDR = 0x00100555;
+
+ /*-- FMC/FSMC Configuration --------------------------------------------------*/
+
+ /* Enable the FMC/FSMC interface clock */
+ (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN));
+
+ /* Configure and enable Bank1_SRAM2 */
+ FMC_Bank1_R->BTCR[4] = 0x00001091;
+ FMC_Bank1_R->BTCR[5] = 0x00110212;
+ FMC_Bank1E_R->BWTR[4] = 0x0FFFFFFF;
+
+ /* FMC controller Enable */
+ FMC_Bank1_R->BTCR[0] |= 0x80000000;
+
+ #endif /* DATA_IN_ExtSRAM */
+
+ (void)(tmp);
+
+}
diff --git a/bsps/arm/stm32h7/start/getentropy-rng.c b/bsps/arm/stm32h7/start/getentropy-rng.c
index 7f75c2e915..948f4fab18 100644
--- a/bsps/arm/stm32h7/start/getentropy-rng.c
+++ b/bsps/arm/stm32h7/start/getentropy-rng.c
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
- * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2020 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/bsps/arm/stm32h7/start/mpu-config.c b/bsps/arm/stm32h7/start/mpu-config.c
index 8140e73c37..472acc3ffa 100644
--- a/bsps/arm/stm32h7/start/mpu-config.c
+++ b/bsps/arm/stm32h7/start/mpu-config.c
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
- * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2020 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -45,6 +45,13 @@ const ARMV7M_MPU_Region_config stm32h7_config_mpu_region [] = {
| ARMV7M_MPU_RASR_TEX(0x1) | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B
| ARMV7M_MPU_RASR_ENABLE,
}, {
+ .begin = stm32h7_memory_sdram_2_begin,
+ .end = stm32h7_memory_sdram_2_end,
+ .rasr = ARMV7M_MPU_RASR_XN
+ | ARMV7M_MPU_RASR_AP(0x3)
+ | ARMV7M_MPU_RASR_TEX(0x1) | ARMV7M_MPU_RASR_C | ARMV7M_MPU_RASR_B
+ | ARMV7M_MPU_RASR_ENABLE,
+ }, {
.begin = bsp_section_start_begin,
.end = bsp_section_text_end,
.rasr = ARMV7M_MPU_RASR_AP(0x5)
diff --git a/bsps/arm/stm32h7/start/stm32h7-config-clk.c b/bsps/arm/stm32h7/start/stm32h7-config-clk.c
deleted file mode 100644
index 3e7c930201..0000000000
--- a/bsps/arm/stm32h7/start/stm32h7-config-clk.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause */
-
-/*
- * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <stm32h7/hal.h>
-
-const RCC_ClkInitTypeDef stm32h7_config_clocks = {
- .ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
- | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
- | RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1,
- .SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK,
- .SYSCLKDivider = RCC_SYSCLK_DIV1,
- .AHBCLKDivider = RCC_HCLK_DIV2,
- .APB3CLKDivider = RCC_APB3_DIV2,
- .APB1CLKDivider = RCC_APB1_DIV2,
- .APB2CLKDivider = RCC_APB2_DIV2,
- .APB4CLKDivider = RCC_APB4_DIV2
-};
diff --git a/bsps/arm/stm32h7/start/stm32h7-config-fls.c b/bsps/arm/stm32h7/start/stm32h7-config-fls.c
index f2d10d2410..96d9eccef9 100644
--- a/bsps/arm/stm32h7/start/stm32h7-config-fls.c
+++ b/bsps/arm/stm32h7/start/stm32h7-config-fls.c
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
- * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2020 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -31,4 +31,4 @@
#include <stm32h7/hal.h>
-const uint32_t stm32h7_config_flash_latency = FLASH_LATENCY_4;
+const uint32_t stm32h7_config_flash_latency = STM32H7_FLASH_LATENCY;
diff --git a/bsps/arm/stm32h7/start/stm32h7-config-osc.c b/bsps/arm/stm32h7/start/stm32h7-config-osc.c
deleted file mode 100644
index b639c7ca36..0000000000
--- a/bsps/arm/stm32h7/start/stm32h7-config-osc.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause */
-
-/*
- * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <stm32h7/hal.h>
-
-const RCC_OscInitTypeDef stm32h7_config_oscillator = {
- .OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE
- | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_HSI48,
- .HSEState = RCC_HSE_ON,
- .LSEState = RCC_LSE_ON,
- .HSIState = RCC_HSI_DIV1,
- .HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT,
- .HSI48State = RCC_HSI48_ON,
- .PLL.PLLState = RCC_PLL_ON,
- .PLL.PLLSource = RCC_PLLSOURCE_HSE,
- .PLL.PLLM = 5,
- .PLL.PLLN = 192,
- .PLL.PLLP = 2,
- .PLL.PLLQ = 12,
- .PLL.PLLR = 2,
- .PLL.PLLRGE = RCC_PLL1VCIRANGE_2,
- .PLL.PLLVCOSEL = RCC_PLL1VCOWIDE,
- .PLL.PLLFRACN = 0
-};
diff --git a/bsps/arm/stm32h7/start/stm32h7-config-per.c b/bsps/arm/stm32h7/start/stm32h7-config-per.c
deleted file mode 100644
index 79aa1494dd..0000000000
--- a/bsps/arm/stm32h7/start/stm32h7-config-per.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* SPDX-License-Identifier: BSD-2-Clause */
-
-/*
- * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include <stm32h7/hal.h>
-
-const RCC_PeriphCLKInitTypeDef stm32h7_config_peripheral_clocks = {
- .PeriphClockSelection = RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3
- | RCC_PERIPHCLK_FDCAN | RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1
- | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_FMC | RCC_PERIPHCLK_RNG,
- .PLL2.PLL2M = 3,
- .PLL2.PLL2N = 48,
- .PLL2.PLL2P = 1,
- .PLL2.PLL2Q = 2,
- .PLL2.PLL2R = 2,
- .PLL2.PLL2RGE = RCC_PLL2VCIRANGE_3,
- .PLL2.PLL2VCOSEL = RCC_PLL2VCOWIDE,
- .PLL2.PLL2FRACN = 0,
- .PLL3.PLL3M = 25,
- .PLL3.PLL3N = 192,
- .PLL3.PLL3P = 2,
- .PLL3.PLL3Q = 4,
- .PLL3.PLL3R = 2,
- .PLL3.PLL3RGE = RCC_PLL3VCIRANGE_0,
- .PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE,
- .PLL3.PLL3FRACN = 0,
- .FmcClockSelection = RCC_FMCCLKSOURCE_PLL2,
- .FdcanClockSelection = RCC_FDCANCLKSOURCE_PLL,
- .Usart234578ClockSelection = RCC_USART234578CLKSOURCE_D2PCLK1,
- .Usart16ClockSelection = RCC_USART16CLKSOURCE_D2PCLK2,
- .I2c123ClockSelection = RCC_I2C123CLKSOURCE_D2PCLK1,
- .UsbClockSelection = RCC_USBCLKSOURCE_PLL3,
- .RTCClockSelection = RCC_RTCCLKSOURCE_LSE,
- .RngClockSelection = RCC_RNGCLKSOURCE_HSI48
-};
diff --git a/bsps/arm/stm32h7/start/stm32h7-config-pwr.c b/bsps/arm/stm32h7/start/stm32h7-config-pwr.c
index 3fcdeba2e8..88761dd7f0 100644
--- a/bsps/arm/stm32h7/start/stm32h7-config-pwr.c
+++ b/bsps/arm/stm32h7/start/stm32h7-config-pwr.c
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
- * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2020 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/bsps/arm/stm32h7/start/stm32h7-hal-eth.c b/bsps/arm/stm32h7/start/stm32h7-hal-eth.c
index b9dac6d7f9..08d7c08269 100644
--- a/bsps/arm/stm32h7/start/stm32h7-hal-eth.c
+++ b/bsps/arm/stm32h7/start/stm32h7-hal-eth.c
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
- * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2020 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -33,6 +33,8 @@
#include <bspopts.h>
+#ifndef STM32H7B3xxQ
+
static const stm32h7_gpio_config gpiog = {
.regs = GPIOG,
.config = {
@@ -94,3 +96,5 @@ HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
stm32h7_gpio_init(&gpiob);
#endif
}
+
+#endif
diff --git a/bsps/arm/stm32h7/start/stm32h7-hal-sdmmc.c b/bsps/arm/stm32h7/start/stm32h7-hal-sdmmc.c
index 2bbc4ff953..272d38c0c1 100644
--- a/bsps/arm/stm32h7/start/stm32h7-hal-sdmmc.c
+++ b/bsps/arm/stm32h7/start/stm32h7-hal-sdmmc.c
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
- * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2020 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -76,7 +76,7 @@ static const stm32h7_gpio_config gpiod = {
};
void
-HAL_SD_MspInit(SD_HandleTypeDef *hsd)
+HAL_SD_MspInit(SD_HandleTypeDef *hsd)
{
stm32h7_clk_enable(STM32H7_MODULE_SDMMC1);
stm32h7_gpio_init(&gpiob);
diff --git a/bsps/arm/stm32h7/start/stm32h7-hal-uart.c b/bsps/arm/stm32h7/start/stm32h7-hal-uart.c
index 1cc94b22e3..5c44086626 100644
--- a/bsps/arm/stm32h7/start/stm32h7-hal-uart.c
+++ b/bsps/arm/stm32h7/start/stm32h7-hal-uart.c
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
- * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2020 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
diff --git a/bsps/arm/stm32h7/start/stm32h7-hal.c b/bsps/arm/stm32h7/start/stm32h7-hal.c
index d042a5b8c9..2e2fb4af07 100644
--- a/bsps/arm/stm32h7/start/stm32h7-hal.c
+++ b/bsps/arm/stm32h7/start/stm32h7-hal.c
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*
- * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ * Copyright (C) 2020 embedded brains GmbH & Co. KG
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -132,13 +132,23 @@ static const stm32h7_clk_info stm32h7_clk[] = {
[STM32H7_MODULE_USART10] = { NULL, 0 },
#endif
[STM32H7_MODULE_RNG] = { &RCC->AHB2ENR, RCC_AHB2ENR_RNGEN },
+#ifdef RCC_AHB1ENR_ETH1MACEN
[STM32H7_MODULE_ETH1MAC] = { &RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN },
+#endif
+#ifdef RCC_AHB1ENR_ETH1TXEN
[STM32H7_MODULE_ETH1TX] = { &RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN },
+#endif
+#ifdef RCC_AHB1ENR_ETH1RXEN
[STM32H7_MODULE_ETH1RX] = { &RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN },
+#endif
[STM32H7_MODULE_USB1_OTG] = { &RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN },
[STM32H7_MODULE_USB1_OTG_ULPI] = { &RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN },
+#ifdef RCC_AHB1ENR_USB20TGHSEN
[STM32H7_MODULE_USB2_OTG] = { &RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN },
+#endif
+#ifdef RCC_AHB1ENR_USB20TGHSULPIEN
[STM32H7_MODULE_USB2_OTG_ULPI] = { &RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN },
+#endif
[STM32H7_MODULE_SDMMC1] = { &RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN },
[STM32H7_MODULE_SDMMC2] = { &RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN },
};
@@ -205,13 +215,23 @@ static const stm32h7_clk_info stm32h7_clk_low_power[] = {
[STM32H7_MODULE_USART10] = { NULL, 0 },
#endif
[STM32H7_MODULE_RNG] = { &RCC->AHB2LPENR, RCC_AHB2LPENR_RNGLPEN },
+#ifdef RCC_AHB1LPENR_ETH1MACLPEN
[STM32H7_MODULE_ETH1MAC] = { &RCC->AHB1LPENR, RCC_AHB1LPENR_ETH1MACLPEN },
+#endif
+#ifdef RCC_AHB1LPENR_ETH1TXLPEN
[STM32H7_MODULE_ETH1TX] = { &RCC->AHB1LPENR, RCC_AHB1LPENR_ETH1TXLPEN },
+#endif
+#ifdef RCC_AHB1LPENR_ETH1RXLPEN
[STM32H7_MODULE_ETH1RX] = { &RCC->AHB1LPENR, RCC_AHB1LPENR_ETH1RXLPEN },
+#endif
[STM32H7_MODULE_USB1_OTG] = { &RCC->AHB1LPENR, RCC_AHB1LPENR_USB1OTGHSLPEN },
[STM32H7_MODULE_USB1_OTG_ULPI] = { &RCC->AHB1LPENR, RCC_AHB1LPENR_USB1OTGHSULPILPEN },
+#ifdef RCC_AHB1LPENR_USB2OTGHSLPEN
[STM32H7_MODULE_USB2_OTG] = { &RCC->AHB1LPENR, RCC_AHB1LPENR_USB2OTGHSLPEN },
+#endif
+#ifdef RCC_AHB1LPENR_USB2OTGHSULPILPEN
[STM32H7_MODULE_USB2_OTG_ULPI] = { &RCC->AHB1LPENR, RCC_AHB1LPENR_USB2OTGHSULPILPEN },
+#endif
[STM32H7_MODULE_SDMMC1] = { &RCC->AHB3LPENR, RCC_AHB3LPENR_SDMMC1LPEN },
[STM32H7_MODULE_SDMMC2] = { &RCC->AHB2LPENR, RCC_AHB2LPENR_SDMMC2LPEN },
};
diff --git a/bsps/arm/stm32h7/start/system_stm32h7xx.c b/bsps/arm/stm32h7/start/system_stm32h7xx.c
deleted file mode 100644
index 092d853720..0000000000
--- a/bsps/arm/stm32h7/start/system_stm32h7xx.c
+++ /dev/null
@@ -1,416 +0,0 @@
-/**
- ******************************************************************************
- * @file system_stm32h7xx.c
- * @author MCD Application Team
- * @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File.
- *
- * This file provides two functions and one global variable to be called from
- * user application:
- * - SystemInit(): This function is called at startup just after reset and
- * before branch to main program. This call is made inside
- * the "startup_stm32h7xx.s" file.
- *
- * - SystemCoreClock variable: Contains the core clock, it can be used
- * by the user application to setup the SysTick
- * timer or configure other parameters.
- *
- * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
- * be called whenever the core clock is changed
- * during program execution.
- *
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32h7xx_system
- * @{
- */
-
-/** @addtogroup STM32H7xx_System_Private_Includes
- * @{
- */
-
-#include "stm32h7xx.h"
-#include <math.h>
-#ifdef __rtems__
-#include <bsp/linker-symbols.h>
-#endif /* __rtems__ */
-#if !defined (HSE_VALUE)
-#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined (CSI_VALUE)
- #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* CSI_VALUE */
-
-#if !defined (HSI_VALUE)
- #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-
-/**
- * @}
- */
-
-/** @addtogroup STM32H7xx_System_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32H7xx_System_Private_Defines
- * @{
- */
-
-/************************* Miscellaneous Configuration ************************/
-/*!< Uncomment the following line if you need to use initialized data in D2 domain SRAM (AHB SRAM) */
-/* #define DATA_IN_D2_SRAM */
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
- Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field.
- This value must be a multiple of 0x200. */
-/******************************************************************************/
-
-/**
- * @}
- */
-
-/** @addtogroup STM32H7xx_System_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32H7xx_System_Private_Variables
- * @{
- */
- /* This variable is updated in three ways:
- 1) by calling CMSIS function SystemCoreClockUpdate()
- 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
- 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
- Note: If you use this function to configure the system clock; then there
- is no need to call the 2 first functions listed above, since SystemCoreClock
- variable is updated automatically.
- */
-#ifndef __rtems__
- uint32_t SystemCoreClock = 64000000;
- uint32_t SystemD2Clock = 64000000;
-#else /* __rtems__ */
- RTEMS_SECTION(".rtemsstack") uint32_t SystemCoreClock;
- RTEMS_SECTION(".rtemsstack") uint32_t SystemD2Clock;
-#endif /* __rtems__ */
- const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
-
-/**
- * @}
- */
-
-/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32H7xx_System_Private_Functions
- * @{
- */
-
-/**
- * @brief Setup the microcontroller system
- * Initialize the FPU setting and vector table location
- * configuration.
- * @param None
- * @retval None
- */
-void SystemInit (void)
-{
-#if defined (DATA_IN_D2_SRAM)
- __IO uint32_t tmpreg;
-#endif /* DATA_IN_D2_SRAM */
-
- /* FPU settings ------------------------------------------------------------*/
- #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
- #endif
- /* Reset the RCC clock configuration to the default reset state ------------*/
- /* Set HSION bit */
- RCC->CR |= RCC_CR_HSION;
-
- /* Reset CFGR register */
- RCC->CFGR = 0x00000000;
-
- /* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */
- RCC->CR &= 0xEAF6ED7FU;
-
-#if defined(D3_SRAM_BASE)
- /* Reset D1CFGR register */
- RCC->D1CFGR = 0x00000000;
-
- /* Reset D2CFGR register */
- RCC->D2CFGR = 0x00000000;
-
- /* Reset D3CFGR register */
- RCC->D3CFGR = 0x00000000;
-#else
- /* Reset CDCFGR1 register */
- RCC->CDCFGR1 = 0x00000000;
-
- /* Reset CDCFGR2 register */
- RCC->CDCFGR2 = 0x00000000;
-
- /* Reset SRDCFGR register */
- RCC->SRDCFGR = 0x00000000;
-#endif
- /* Reset PLLCKSELR register */
- RCC->PLLCKSELR = 0x00000000;
-
- /* Reset PLLCFGR register */
- RCC->PLLCFGR = 0x00000000;
- /* Reset PLL1DIVR register */
- RCC->PLL1DIVR = 0x00000000;
- /* Reset PLL1FRACR register */
- RCC->PLL1FRACR = 0x00000000;
-
- /* Reset PLL2DIVR register */
- RCC->PLL2DIVR = 0x00000000;
-
- /* Reset PLL2FRACR register */
-
- RCC->PLL2FRACR = 0x00000000;
- /* Reset PLL3DIVR register */
- RCC->PLL3DIVR = 0x00000000;
-
- /* Reset PLL3FRACR register */
- RCC->PLL3FRACR = 0x00000000;
-
- /* Reset HSEBYP bit */
- RCC->CR &= 0xFFFBFFFFU;
-
- /* Disable all interrupts */
- RCC->CIER = 0x00000000;
-
-#if (STM32H7_DEV_ID == 0x450UL)
- /* dual core CM7 or single core line */
- if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
- {
- /* if stm32h7 revY*/
- /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
- *((__IO uint32_t*)0x51008108) = 0x000000001U;
- }
-#endif
-
-#ifndef __rtems__
-#if defined (DATA_IN_D2_SRAM)
- /* in case of initialized data in D2 SRAM (AHB SRAM) , enable the D2 SRAM clock (AHB SRAM clock) */
-#if defined(RCC_AHB2ENR_D2SRAM3EN)
- RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
-#elif defined(RCC_AHB2ENR_D2SRAM2EN)
- RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN);
-#else
- RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);
-#endif /* RCC_AHB2ENR_D2SRAM3EN */
-
- tmpreg = RCC->AHB2ENR;
- (void) tmpreg;
-#endif /* DATA_IN_D2_SRAM */
-#else /* __rtems__ */
- RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
- RCC->AHB2ENR;
-#endif /* __rtems__ */
-
-#ifndef __rtems__
-#if defined(DUAL_CORE) && defined(CORE_CM4)
- /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = D2_AHBSRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
- SCB->VTOR = FLASH_BANK2_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif /* VECT_TAB_SRAM */
-
-#else
-
- /* Configure the Vector Table location add offset address for cortex-M7 ------------------*/
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal AXI-RAM */
-#else
- SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-
-#endif /*DUAL_CORE && CORE_CM4*/
-#else /* __rtems__ */
- SCB->VTOR = (uint32_t) bsp_start_vector_table_begin;
-#endif /* __rtems__ */
-
-}
-
-/**
- * @brief Update SystemCoreClock variable according to Clock Register Values.
- * The SystemCoreClock variable contains the core clock , it can
- * be used by the user application to setup the SysTick timer or configure
- * other parameters.
- *
- * @note Each time the core clock changes, this function must be called
- * to update SystemCoreClock variable value. Otherwise, any configuration
- * based on this variable will be incorrect.
- *
- * @note - The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- *
- * - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
- * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
- * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
- * - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*),
- * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
- *
- * (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
- * 4 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- * (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
- * 64 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- *
- * (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value
- * 25 MHz), user has to ensure that HSE_VALUE is same as the real
- * frequency of the crystal used. Otherwise, this function may
- * have wrong result.
- *
- * - The result of this function could be not correct when using fractional
- * value for HSE crystal.
- * @param None
- * @retval None
- */
-void SystemCoreClockUpdate (void)
-{
- uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
- uint32_t common_system_clock;
- float_t fracn1, pllvco;
-
-
- /* Get SYSCLK source -------------------------------------------------------*/
-
- switch (RCC->CFGR & RCC_CFGR_SWS)
- {
- case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
- common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
- break;
-
- case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */
- common_system_clock = CSI_VALUE;
- break;
-
- case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
- common_system_clock = HSE_VALUE;
- break;
-
- case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */
-
- /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
- SYSCLK = PLL_VCO / PLLR
- */
- pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
- pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ;
- pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
- fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
-
- if (pllm != 0U)
- {
- switch (pllsource)
- {
- case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */
-
- hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
- pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
-
- break;
-
- case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */
- pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
- break;
-
- case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */
- pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
- break;
-
- default:
- pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
- break;
- }
- pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
- common_system_clock = (uint32_t)(float_t)(pllvco/(float_t)pllp);
- }
- else
- {
- common_system_clock = 0U;
- }
- break;
-
- default:
- common_system_clock = CSI_VALUE;
- break;
- }
-
- /* Compute SystemClock frequency --------------------------------------------------*/
-#if defined (RCC_D1CFGR_D1CPRE)
- tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
-
- /* common_system_clock frequency : CM7 CPU frequency */
- common_system_clock >>= tmp;
-
- /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */
- SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
-
-#else
- tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos];
-
- /* common_system_clock frequency : CM7 CPU frequency */
- common_system_clock >>= tmp;
-
- /* SystemD2Clock frequency : AXI and AHBs Clock frequency */
- SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
-
-#endif
-
-#if defined(DUAL_CORE) && defined(CORE_CM4)
- SystemCoreClock = SystemD2Clock;
-#else
- SystemCoreClock = common_system_clock;
-#endif /* DUAL_CORE && CORE_CM4 */
-}
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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