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-rw-r--r--bsps/arm/stm32h7/include/bsp.h54
-rw-r--r--bsps/arm/stm32h7/include/bsp/irq.h43
-rw-r--r--bsps/arm/stm32h7/include/chip.h34
-rw-r--r--bsps/arm/stm32h7/include/stm32h7/hal.h147
-rw-r--r--bsps/arm/stm32h7/include/stm32h7/memory.h103
-rw-r--r--bsps/arm/stm32h7/include/stm32h7xx.h3
-rw-r--r--bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h493
-rw-r--r--bsps/arm/stm32h7/include/system_stm32h7xx.h3
-rw-r--r--bsps/arm/stm32h7/include/tm27.h1
9 files changed, 881 insertions, 0 deletions
diff --git a/bsps/arm/stm32h7/include/bsp.h b/bsps/arm/stm32h7/include/bsp.h
new file mode 100644
index 0000000000..06c4e678aa
--- /dev/null
+++ b/bsps/arm/stm32h7/include/bsp.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_ARM_STM32H7_BSP_H
+#define LIBBSP_ARM_STM32H7_BSP_H
+
+#include <bspopts.h>
+#include <bsp/default-initial-extension.h>
+
+#include <rtems.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define BSP_FEATURE_IRQ_EXTENSION
+
+#define BSP_ARMV7M_IRQ_PRIORITY_DEFAULT (13 << 4)
+
+#define BSP_ARMV7M_SYSTICK_PRIORITY (14 << 4)
+
+#define BSP_ARMV7M_SYSTICK_FREQUENCY stm32h7_systick_frequency()
+
+uint32_t stm32h7_systick_frequency(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LIBBSP_ARM_STM32H7_BSP_H */
diff --git a/bsps/arm/stm32h7/include/bsp/irq.h b/bsps/arm/stm32h7/include/bsp/irq.h
new file mode 100644
index 0000000000..b3ff7a9621
--- /dev/null
+++ b/bsps/arm/stm32h7/include/bsp/irq.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_ARM_STM32H7_IRQ_H
+#define LIBBSP_ARM_STM32H7_IRQ_H
+
+#ifndef ASM
+
+#include <rtems.h>
+#include <rtems/irq.h>
+#include <rtems/irq-extension.h>
+
+#endif /* ASM */
+
+#define BSP_INTERRUPT_VECTOR_MIN 0
+
+#define BSP_INTERRUPT_VECTOR_MAX 239
+
+#endif /* LIBBSP_ARM_STM32H7_IRQ_H */
diff --git a/bsps/arm/stm32h7/include/chip.h b/bsps/arm/stm32h7/include/chip.h
new file mode 100644
index 0000000000..26b067a3b7
--- /dev/null
+++ b/bsps/arm/stm32h7/include/chip.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_ARM_STM32H7_CHIP_H
+#define LIBBSP_ARM_STM32H7_CHIP_H
+
+#include <stm32h7xx.h>
+#include <core_cm7.h>
+
+#endif /* LIBBSP_ARM_STM32H7_CHIP_H */
diff --git a/bsps/arm/stm32h7/include/stm32h7/hal.h b/bsps/arm/stm32h7/include/stm32h7/hal.h
new file mode 100644
index 0000000000..fe37f03c04
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7/hal.h
@@ -0,0 +1,147 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_ARM_STM32H7_STM32H7_HAL_H
+#define LIBBSP_ARM_STM32H7_STM32H7_HAL_H
+
+#include <stm32h7xx_hal.h>
+
+#include <rtems/termiostypes.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ STM32H7_MODULE_INVALID,
+ STM32H7_MODULE_GPIOA,
+ STM32H7_MODULE_GPIOB,
+ STM32H7_MODULE_GPIOC,
+ STM32H7_MODULE_GPIOD,
+ STM32H7_MODULE_GPIOE,
+ STM32H7_MODULE_GPIOF,
+ STM32H7_MODULE_GPIOG,
+ STM32H7_MODULE_GPIOH,
+ STM32H7_MODULE_GPIOI,
+ STM32H7_MODULE_GPIOJ,
+ STM32H7_MODULE_GPIOK,
+ STM32H7_MODULE_USART1,
+ STM32H7_MODULE_USART2,
+ STM32H7_MODULE_USART3,
+ STM32H7_MODULE_UART4,
+ STM32H7_MODULE_UART5,
+ STM32H7_MODULE_USART6,
+ STM32H7_MODULE_UART7,
+ STM32H7_MODULE_UART8,
+ STM32H7_MODULE_UART9,
+ STM32H7_MODULE_USART10,
+ STM32H7_MODULE_RNG,
+ STM32H7_MODULE_ETH1MAC,
+ STM32H7_MODULE_ETH1TX,
+ STM32H7_MODULE_ETH1RX,
+ STM32H7_MODULE_USB1_OTG,
+ STM32H7_MODULE_USB1_OTG_ULPI,
+ STM32H7_MODULE_USB2_OTG,
+ STM32H7_MODULE_USB2_OTG_ULPI
+} stm32h7_module_index;
+
+stm32h7_module_index stm32h7_get_module_index(const void *regs);
+
+void stm32h7_clk_enable(stm32h7_module_index index);
+
+void stm32h7_clk_disable(stm32h7_module_index index);
+
+void stm32h7_clk_low_power_enable(stm32h7_module_index index);
+
+void stm32h7_clk_low_power_disable(stm32h7_module_index index);
+
+typedef struct {
+ GPIO_TypeDef *regs;
+ GPIO_InitTypeDef config;
+} stm32h7_gpio_config;
+
+void stm32h7_gpio_init(const stm32h7_gpio_config *config);
+
+typedef struct {
+ stm32h7_gpio_config gpio;
+ rtems_vector_number irq;
+ uint8_t device_index;
+} stm32h7_uart_config;
+
+typedef struct {
+ UART_HandleTypeDef uart;
+ bool transmitting;
+ rtems_termios_device_context device;
+ const stm32h7_uart_config *config;
+} stm32h7_uart_context;
+
+static inline stm32h7_uart_context *stm32h7_uart_get_context(
+ rtems_termios_device_context *base
+)
+{
+ return RTEMS_CONTAINER_OF(base, stm32h7_uart_context, device);
+}
+
+void stm32h7_uart_polled_write(rtems_termios_device_context *base, char c);
+
+int stm32h7_uart_polled_read(rtems_termios_device_context *base);
+
+extern stm32h7_uart_context stm32h7_usart1_instance;
+
+extern stm32h7_uart_context stm32h7_usart2_instance;
+
+extern stm32h7_uart_context stm32h7_usart3_instance;
+
+extern stm32h7_uart_context stm32h7_uart4_instance;
+
+extern stm32h7_uart_context stm32h7_uart5_instance;
+
+extern stm32h7_uart_context stm32h7_usart6_instance;
+
+extern stm32h7_uart_context stm32h7_uart7_instance;
+
+extern stm32h7_uart_context stm32h7_uart8_instance;
+
+extern stm32h7_uart_context stm32h7_uart9_instance;
+
+extern stm32h7_uart_context stm32h7_usart10_instance;
+
+extern const uint32_t stm32h7_config_pwr_regulator_voltagescaling;
+
+extern const RCC_OscInitTypeDef stm32h7_config_oscillator;
+
+extern const RCC_ClkInitTypeDef stm32h7_config_clocks;
+
+extern const uint32_t stm32h7_config_flash_latency;
+
+extern const RCC_PeriphCLKInitTypeDef stm32h7_config_peripheral_clocks;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LIBBSP_ARM_STM32H7_STM32H7_HAL_H */
diff --git a/bsps/arm/stm32h7/include/stm32h7/memory.h b/bsps/arm/stm32h7/include/stm32h7/memory.h
new file mode 100644
index 0000000000..27f57fd6a6
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7/memory.h
@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/*
+ * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SMEMORYL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_ARM_STM32H7_STM32H7_MEMORY_H
+#define LIBBSP_ARM_STM32H7_STM32H7_MEMORY_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern char stm32h7_memory_null_begin[];
+extern char stm32h7_memory_null_end[];
+extern char stm32h7_memory_null_size[];
+
+extern char stm32h7_memory_itcm_begin[];
+extern char stm32h7_memory_itcm_end[];
+extern char stm32h7_memory_itcm_size[];
+
+extern char stm32h7_memory_flash_begin[];
+extern char stm32h7_memory_flash_end[];
+extern char stm32h7_memory_flash_size[];
+
+extern char stm32h7_memory_dtcm_begin[];
+extern char stm32h7_memory_dtcm_end[];
+extern char stm32h7_memory_dtcm_size[];
+
+extern char stm32h7_memory_sram_axi_begin[];
+extern char stm32h7_memory_sram_axi_end[];
+extern char stm32h7_memory_sram_axi_size[];
+
+extern char stm32h7_memory_sram_1_begin[];
+extern char stm32h7_memory_sram_1_end[];
+extern char stm32h7_memory_sram_1_size[];
+
+extern char stm32h7_memory_sram_2_begin[];
+extern char stm32h7_memory_sram_2_end[];
+extern char stm32h7_memory_sram_2_size[];
+
+extern char stm32h7_memory_sram_3_begin[];
+extern char stm32h7_memory_sram_3_end[];
+extern char stm32h7_memory_sram_3_size[];
+
+extern char stm32h7_memory_sram_4_begin[];
+extern char stm32h7_memory_sram_4_end[];
+extern char stm32h7_memory_sram_4_size[];
+
+extern char stm32h7_memory_sram_backup_begin[];
+extern char stm32h7_memory_sram_backup_end[];
+extern char stm32h7_memory_sram_backup_size[];
+
+extern char stm32h7_memory_peripheral_begin[];
+extern char stm32h7_memory_peripheral_end[];
+extern char stm32h7_memory_peripheral_size[];
+
+extern char stm32h7_memory_nor_begin[];
+extern char stm32h7_memory_nor_end[];
+extern char stm32h7_memory_nor_size[];
+
+extern char stm32h7_memory_sdram_1_begin[];
+extern char stm32h7_memory_sdram_1_end[];
+extern char stm32h7_memory_sdram_1_size[];
+
+extern char stm32h7_memory_nand_begin[];
+extern char stm32h7_memory_nand_end[];
+extern char stm32h7_memory_nand_size[];
+
+extern char stm32h7_memory_quadspi_begin[];
+extern char stm32h7_memory_quadspi_end[];
+extern char stm32h7_memory_quadspi_size[];
+
+extern char stm32h7_memory_sdram_2_begin[];
+extern char stm32h7_memory_sdram_2_end[];
+extern char stm32h7_memory_sdram_2_size[];
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LIBBSP_ARM_STM32H7_STM32H7_MEMORY_H */
diff --git a/bsps/arm/stm32h7/include/stm32h7xx.h b/bsps/arm/stm32h7/include/stm32h7xx.h
index f6296181be..36d3012af4 100644
--- a/bsps/arm/stm32h7/include/stm32h7xx.h
+++ b/bsps/arm/stm32h7/include/stm32h7xx.h
@@ -38,6 +38,9 @@
#ifndef STM32H7xx_H
#define STM32H7xx_H
+#ifdef __rtems__
+#include <bspopts.h>
+#endif /* __rtems__ */
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h
new file mode 100644
index 0000000000..d423e4f782
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_conf.h
@@ -0,0 +1,493 @@
+/**
+ ******************************************************************************
+ * @file stm32h7xx_hal_conf.h
+ * @author MCD Application Team
+ * @brief HAL configuration file.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+ * All rights reserved.</center></h2>
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32H7xx_HAL_CONF_H
+#define __STM32H7xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+#define HAL_MODULE_ENABLED
+
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_FDCAN_MODULE_ENABLED
+#define HAL_CEC_MODULE_ENABLED
+#define HAL_COMP_MODULE_ENABLED
+#define HAL_CRC_MODULE_ENABLED
+#define HAL_CRYP_MODULE_ENABLED
+#define HAL_DAC_MODULE_ENABLED
+#define HAL_DCMI_MODULE_ENABLED
+#define HAL_DMA2D_MODULE_ENABLED
+#define HAL_ETH_MODULE_ENABLED
+#define HAL_NAND_MODULE_ENABLED
+#define HAL_NOR_MODULE_ENABLED
+#define HAL_OTFDEC_MODULE_ENABLED
+#define HAL_SRAM_MODULE_ENABLED
+#define HAL_SDRAM_MODULE_ENABLED
+#define HAL_HASH_MODULE_ENABLED
+#define HAL_HRTIM_MODULE_ENABLED
+#define HAL_HSEM_MODULE_ENABLED
+#define HAL_GFXMMU_MODULE_ENABLED
+#define HAL_JPEG_MODULE_ENABLED
+#define HAL_OPAMP_MODULE_ENABLED
+#define HAL_OSPI_MODULE_ENABLED
+#define HAL_OSPI_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED
+#define HAL_SMBUS_MODULE_ENABLED
+#define HAL_IWDG_MODULE_ENABLED
+#define HAL_LPTIM_MODULE_ENABLED
+#define HAL_LTDC_MODULE_ENABLED
+#define HAL_QSPI_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_SAI_MODULE_ENABLED
+#define HAL_SD_MODULE_ENABLED
+#define HAL_MMC_MODULE_ENABLED
+#define HAL_SPDIFRX_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_SWPMI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
+#define HAL_IRDA_MODULE_ENABLED
+#define HAL_SMARTCARD_MODULE_ENABLED
+#define HAL_WWDG_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+#define HAL_HCD_MODULE_ENABLED
+#define HAL_DFSDM_MODULE_ENABLED
+#define HAL_DSI_MODULE_ENABLED
+#define HAL_JPEG_MODULE_ENABLED
+#define HAL_MDIOS_MODULE_ENABLED
+#define HAL_PSSI_MODULE_ENABLED
+#define HAL_DTS_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_MDMA_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_HSEM_MODULE_ENABLED
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSE is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSE_VALUE)
+#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz : FPGA case fixed to 60MHZ */
+#endif /* HSE_VALUE */
+
+#if !defined (HSE_STARTUP_TIMEOUT)
+ #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal oscillator (CSI) default value.
+ * This value is the default CSI value after Reset.
+ */
+#if !defined (CSI_VALUE)
+ #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* CSI_VALUE */
+
+/**
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSI is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @brief External Low Speed oscillator (LSE) value.
+ * This value is used by the UART, RTC HAL module to compute the system frequency
+ */
+#if !defined (LSE_VALUE)
+ #define LSE_VALUE ((uint32_t)32768U) /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+#if !defined (LSE_STARTUP_TIMEOUT)
+ #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief External clock source for I2S peripheral
+ * This value is used by the I2S HAL module to compute the I2S clock source
+ * frequency, this source is inserted directly through I2S_CKIN pad.
+ */
+#if !defined (EXTERNAL_CLOCK_VALUE)
+ #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External clock in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+ === you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+ * @brief This is the HAL system configuration section
+ */
+#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY ((uint32_t)0U) /*!< tick interrupt priority */
+#define USE_RTOS 0U
+#define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */
+
+#define USE_HAL_ADC_REGISTER_CALLBACKS 0
+#define USE_HAL_CEC_REGISTER_CALLBACKS 0
+#define USE_HAL_COMP_REGISTER_CALLBACKS 0
+#define USE_HAL_CRYP_REGISTER_CALLBACKS 0
+#define USE_HAL_DAC_REGISTER_CALLBACKS 0
+#define USE_HAL_DCMI_REGISTER_CALLBACKS 0
+#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0
+#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0
+#define USE_HAL_DSI_REGISTER_CALLBACKS 0
+#define USE_HAL_DTS_REGISTER_CALLBACKS 0
+#define USE_HAL_ETH_REGISTER_CALLBACKS 0
+#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0
+#define USE_HAL_NAND_REGISTER_CALLBACKS 0
+#define USE_HAL_NOR_REGISTER_CALLBACKS 0
+#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0
+#define USE_HAL_SRAM_REGISTER_CALLBACKS 0
+#define USE_HAL_HASH_REGISTER_CALLBACKS 0
+#define USE_HAL_HCD_REGISTER_CALLBACKS 0
+#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0
+#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0
+#define USE_HAL_I2C_REGISTER_CALLBACKS 0
+#define USE_HAL_I2S_REGISTER_CALLBACKS 0
+#define USE_HAL_IRDA_REGISTER_CALLBACKS 0
+#define USE_HAL_JPEG_REGISTER_CALLBACKS 0
+#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0
+#define USE_HAL_LTDC_REGISTER_CALLBACKS 0
+#define USE_HAL_MDIOS_REGISTER_CALLBACKS 0
+#define USE_HAL_MMC_REGISTER_CALLBACKS 0
+#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0
+#define USE_HAL_OSPI_REGISTER_CALLBACKS 0
+#define USE_HAL_OTFDEC_REGISTER_CALLBACKS 0
+#define USE_HAL_PCD_REGISTER_CALLBACKS 0
+#define USE_HAL_QSPI_REGISTER_CALLBACKS 0
+#define USE_HAL_RNG_REGISTER_CALLBACKS 0
+#define USE_HAL_RTC_REGISTER_CALLBACKS 0
+#define USE_HAL_SAI_REGISTER_CALLBACKS 0
+#define USE_HAL_SD_REGISTER_CALLBACKS 0
+#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0
+#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0
+#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0
+#define USE_HAL_SPI_REGISTER_CALLBACKS 0
+#define USE_HAL_SWPMI_REGISTER_CALLBACKS 0
+#define USE_HAL_TIM_REGISTER_CALLBACKS 0
+#define USE_HAL_UART_REGISTER_CALLBACKS 0
+#define USE_HAL_USART_REGISTER_CALLBACKS 0
+#define USE_HAL_WWDG_REGISTER_CALLBACKS 0
+
+/* ########################### Ethernet Configuration ######################### */
+#define ETH_TX_DESC_CNT 4 /* number of Ethernet Tx DMA descriptors */
+#define ETH_RX_DESC_CNT 4 /* number of Ethernet Rx DMA descriptors */
+
+#define ETH_MAC_ADDR0 ((uint8_t)0x02)
+#define ETH_MAC_ADDR1 ((uint8_t)0x00)
+#define ETH_MAC_ADDR2 ((uint8_t)0x00)
+#define ETH_MAC_ADDR3 ((uint8_t)0x00)
+#define ETH_MAC_ADDR4 ((uint8_t)0x00)
+#define ETH_MAC_ADDR5 ((uint8_t)0x00)
+
+/* ########################## Assert Selection ############################## */
+/**
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * HAL drivers code
+ */
+/* #define USE_FULL_ASSERT 1U */
+
+/* Includes ------------------------------------------------------------------*/
+/**
+ * @brief Include module's header file
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+ #include "stm32h7xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+ #include "stm32h7xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+ #include "stm32h7xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_MDMA_MODULE_ENABLED
+ #include "stm32h7xx_hal_mdma.h"
+#endif /* HAL_MDMA_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32h7xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+ #include "stm32h7xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+ #include "stm32h7xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DSI_MODULE_ENABLED
+ #include "stm32h7xx_hal_dsi.h"
+#endif /* HAL_DSI_MODULE_ENABLED */
+
+#ifdef HAL_DFSDM_MODULE_ENABLED
+ #include "stm32h7xx_hal_dfsdm.h"
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+ #include "stm32h7xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+ #include "stm32h7xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+ #include "stm32h7xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+ #include "stm32h7xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_FDCAN_MODULE_ENABLED
+ #include "stm32h7xx_hal_fdcan.h"
+#endif /* HAL_FDCAN_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+ #include "stm32h7xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+ #include "stm32h7xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+ #include "stm32h7xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+ #include "stm32h7xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+ #include "stm32h7xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+ #include "stm32h7xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_GFXMMU_MODULE_ENABLED
+ #include "stm32h7xx_hal_gfxmmu.h"
+#endif /* HAL_GFXMMU_MODULE_ENABLED */
+
+#ifdef HAL_HRTIM_MODULE_ENABLED
+ #include "stm32h7xx_hal_hrtim.h"
+#endif /* HAL_HRTIM_MODULE_ENABLED */
+
+#ifdef HAL_HSEM_MODULE_ENABLED
+ #include "stm32h7xx_hal_hsem.h"
+#endif /* HAL_HSEM_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+ #include "stm32h7xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+ #include "stm32h7xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+ #include "stm32h7xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32h7xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32h7xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32h7xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_JPEG_MODULE_ENABLED
+ #include "stm32h7xx_hal_jpeg.h"
+#endif /* HAL_JPEG_MODULE_ENABLED */
+
+#ifdef HAL_MDIOS_MODULE_ENABLED
+ #include "stm32h7xx_hal_mdios.h"
+#endif /* HAL_MDIOS_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+ #include "stm32h7xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#include "stm32h7xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+#include "stm32h7xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_OPAMP_MODULE_ENABLED
+#include "stm32h7xx_hal_opamp.h"
+#endif /* HAL_OPAMP_MODULE_ENABLED */
+
+#ifdef HAL_OSPI_MODULE_ENABLED
+ #include "stm32h7xx_hal_ospi.h"
+#endif /* HAL_OSPI_MODULE_ENABLED */
+
+#ifdef HAL_OTFDEC_MODULE_ENABLED
+#include "stm32h7xx_hal_otfdec.h"
+#endif /* HAL_OTFDEC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32h7xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32h7xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RAMECC_MODULE_ENABLED
+ #include "stm32h7xx_hal_ramecc.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32h7xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32h7xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32h7xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32h7xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+ #include "stm32h7xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32h7xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+ #include "stm32h7xx_hal_spdifrx.h"
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+
+#ifdef HAL_SWPMI_MODULE_ENABLED
+ #include "stm32h7xx_hal_swpmi.h"
+#endif /* HAL_SWPMI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32h7xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32h7xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32h7xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32h7xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32h7xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32h7xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32h7xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32h7xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32h7xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_PSSI_MODULE_ENABLED
+ #include "stm32h7xx_hal_pssi.h"
+#endif /* HAL_PSSI_MODULE_ENABLED */
+
+#ifdef HAL_DTS_MODULE_ENABLED
+ #include "stm32h7xx_hal_dts.h"
+#endif /* HAL_DTS_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+ void assert_failed(uint8_t* file, uint32_t line);
+#else
+ #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32H7xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/bsps/arm/stm32h7/include/system_stm32h7xx.h b/bsps/arm/stm32h7/include/system_stm32h7xx.h
index dd75af67ff..ca0f335f7e 100644
--- a/bsps/arm/stm32h7/include/system_stm32h7xx.h
+++ b/bsps/arm/stm32h7/include/system_stm32h7xx.h
@@ -85,6 +85,9 @@ extern const uint8_t D1CorePrescTable[16] ; /*!< D1CorePrescTable prescalers ta
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
+#ifdef __rtems__
+extern void SystemInit_ExtMemCtl(void);
+#endif /* __rtems__ */
/**
* @}
*/
diff --git a/bsps/arm/stm32h7/include/tm27.h b/bsps/arm/stm32h7/include/tm27.h
new file mode 100644
index 0000000000..0dfa7bf628
--- /dev/null
+++ b/bsps/arm/stm32h7/include/tm27.h
@@ -0,0 +1 @@
+#include <rtems/tm27-default.h>
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-27 05:50:45 +0000