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Diffstat (limited to 'bsps/arm/stm32f4/include/bsp/stm32_usart.h')
| -rw-r--r-- | bsps/arm/stm32f4/include/bsp/stm32_usart.h | 110 |
1 files changed, 110 insertions, 0 deletions
diff --git a/bsps/arm/stm32f4/include/bsp/stm32_usart.h b/bsps/arm/stm32f4/include/bsp/stm32_usart.h new file mode 100644 index 0000000000..c9c269533f --- /dev/null +++ b/bsps/arm/stm32f4/include/bsp/stm32_usart.h @@ -0,0 +1,110 @@ +/** + * @file + * @ingroup stm32_usart + * @brief STM32 USART support + */ + +/* + * Copyright (c) 2012 Sebastian Huber. All rights reserved. + * + * embedded brains GmbH + * Obere Lagerstr. 30 + * 82178 Puchheim + * Germany + * <rtems@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#ifndef LIBBSP_ARM_STM32F4_STM32_USART_H +#define LIBBSP_ARM_STM32F4_STM32_USART_H + +#include <bsp/utility.h> + +/** + * @defgroup stm32_usart STM32 USART Support + * @ingroup stm32f4_usart + * @brief STM32 USART Support + * @{ + */ + +typedef struct { + uint32_t sr; +#define STM32F4_USART_SR_CTS BSP_BIT32(9) +#define STM32F4_USART_SR_LBD BSP_BIT32(8) +#define STM32F4_USART_SR_TXE BSP_BIT32(7) +#define STM32F4_USART_SR_TC BSP_BIT32(6) +#define STM32F4_USART_SR_RXNE BSP_BIT32(5) +#define STM32F4_USART_SR_IDLE BSP_BIT32(4) +#define STM32F4_USART_SR_ORE BSP_BIT32(3) +#define STM32F4_USART_SR_NF BSP_BIT32(2) +#define STM32F4_USART_SR_FE BSP_BIT32(1) +#define STM32F4_USART_SR_PE BSP_BIT32(0) + uint32_t dr; +#define STM32F4_USART_DR(val) BSP_FLD32(val, 0, 7) +#define STM32F4_USART_DR_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define STM32F4_USART_DR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) + uint32_t bbr; +#define STM32F4_USART_BBR_DIV_MANTISSA(val) BSP_FLD32(val, 4, 15) +#define STM32F4_USART_BBR_DIV_MANTISSA_GET(reg) BSP_FLD32GET(reg, 4, 15) +#define STM32F4_USART_BBR_DIV_MANTISSA_SET(reg, val) BSP_FLD32SET(reg, val, 4, 15) +#define STM32F4_USART_BBR_DIV_FRACTION(val) BSP_FLD32(val, 0, 3) +#define STM32F4_USART_BBR_DIV_FRACTION_GET(reg) BSP_FLD32GET(reg, 0, 3) +#define STM32F4_USART_BBR_DIV_FRACTION_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) + uint32_t cr1; +#define STM32F4_USART_CR1_OVER8 BSP_BIT32(15) +#define STM32F4_USART_CR1_UE BSP_BIT32(13) +#define STM32F4_USART_CR1_M BSP_BIT32(12) +#define STM32F4_USART_CR1_WAKE BSP_BIT32(11) +#define STM32F4_USART_CR1_PCE BSP_BIT32(10) +#define STM32F4_USART_CR1_PS BSP_BIT32(9) +#define STM32F4_USART_CR1_PEIE BSP_BIT32(8) +#define STM32F4_USART_CR1_TXEIE BSP_BIT32(7) +#define STM32F4_USART_CR1_TCIE BSP_BIT32(6) +#define STM32F4_USART_CR1_RXNEIE BSP_BIT32(5) +#define STM32F4_USART_CR1_IDLEIE BSP_BIT32(4) +#define STM32F4_USART_CR1_TE BSP_BIT32(3) +#define STM32F4_USART_CR1_RE BSP_BIT32(2) +#define STM32F4_USART_CR1_RWU BSP_BIT32(1) +#define STM32F4_USART_CR1_SBK BSP_BIT32(0) + uint32_t cr2; +#define STM32F4_USART_CR2_LINEN BSP_BIT32(14) +#define STM32F4_USART_CR2_STOP(val) BSP_FLD32(val, 12, 13) +#define STM32F4_USART_CR2_STOP_GET(reg) BSP_FLD32GET(reg, 12, 13) +#define STM32F4_USART_CR2_STOP_SET(reg, val) BSP_FLD32SET(reg, val, 12, 13) +#define STM32F4_USART_CR2_CLKEN BSP_BIT32(11) +#define STM32F4_USART_CR2_CPOL BSP_BIT32(10) +#define STM32F4_USART_CR2_CPHA BSP_BIT32(9) +#define STM32F4_USART_CR2_LBCL BSP_BIT32(8) +#define STM32F4_USART_CR2_LBDIE BSP_BIT32(6) +#define STM32F4_USART_CR2_LBDL BSP_BIT32(5) +#define STM32F4_USART_CR2_ADD(val) BSP_FLD32(val, 0, 3) +#define STM32F4_USART_CR2_ADD_GET(reg) BSP_FLD32GET(reg, 0, 3) +#define STM32F4_USART_CR2_ADD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) + uint32_t cr3; +#define STM32F4_USART_CR3_ONEBIT BSP_BIT32(11) +#define STM32F4_USART_CR3_CTSIE BSP_BIT32(10) +#define STM32F4_USART_CR3_CTSE BSP_BIT32(9) +#define STM32F4_USART_CR3_RTSE BSP_BIT32(8) +#define STM32F4_USART_CR3_DMAT BSP_BIT32(7) +#define STM32F4_USART_CR3_DMAR BSP_BIT32(6) +#define STM32F4_USART_CR3_SCEN BSP_BIT32(5) +#define STM32F4_USART_CR3_NACK BSP_BIT32(4) +#define STM32F4_USART_CR3_HDSEL BSP_BIT32(3) +#define STM32F4_USART_CR3_IRLP BSP_BIT32(2) +#define STM32F4_USART_CR3_IREN BSP_BIT32(1) +#define STM32F4_USART_CR3_EIE BSP_BIT32(0) + uint32_t gtpr; +#define STM32F4_USART_GTPR_GT(val) BSP_FLD32(val, 8, 15) +#define STM32F4_USART_GTPR_GT_GET(reg) BSP_FLD32GET(reg, 8, 15) +#define STM32F4_USART_GTPR_GT_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15) +#define STM32F4_USART_GTPR_PSC(val) BSP_FLD32(val, 0, 7) +#define STM32F4_USART_GTPR_PSC_GET(reg) BSP_FLD32GET(reg, 0, 7) +#define STM32F4_USART_GTPR_PSC_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) +} stm32f4_usart; + +/** @} */ + +#endif /* LIBBSP_ARM_STM32F4_STM32_USART_H */ |