diff options
Diffstat (limited to '')
-rw-r--r-- | bsps/arm/shared/start/arm-a9mpcore-smp.c | 43 |
1 files changed, 33 insertions, 10 deletions
diff --git a/bsps/arm/shared/start/arm-a9mpcore-smp.c b/bsps/arm/shared/start/arm-a9mpcore-smp.c index a9970b952c..c99f68f9cf 100644 --- a/bsps/arm/shared/start/arm-a9mpcore-smp.c +++ b/bsps/arm/shared/start/arm-a9mpcore-smp.c @@ -1,9 +1,28 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* - * Copyright (c) 2013, 2018 embedded brains GmbH. All rights reserved. + * Copyright (C) 2013, 2018 embedded brains GmbH & Co. KG + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #include <rtems/score/smpimpl.h> @@ -22,20 +41,24 @@ uint32_t _CPU_SMP_Initialize(void) return arm_gic_irq_processor_count(); } +static rtems_interrupt_entry arm_a9mpcore_ipi_entry = + RTEMS_INTERRUPT_ENTRY_INITIALIZER( + bsp_inter_processor_interrupt, + NULL, + "IPI" + ); + void _CPU_SMP_Finalize_initialization(uint32_t cpu_count) { if (cpu_count > 0) { rtems_status_code sc; - sc = rtems_interrupt_handler_install( + sc = rtems_interrupt_entry_install( ARM_GIC_IRQ_SGI_0, - "IPI", RTEMS_INTERRUPT_UNIQUE, - bsp_inter_processor_interrupt, - NULL + &arm_a9mpcore_ipi_entry ); - _Assert(sc == RTEMS_SUCCESSFUL); - (void) sc; + _Assert_Unused_variable_equals(sc, RTEMS_SUCCESSFUL); #if defined(BSP_DATA_CACHE_ENABLED) || defined(BSP_INSTRUCTION_CACHE_ENABLED) /* Enable unified L2 cache */ |