1 files changed, 49 insertions, 4 deletions
diff --git a/bsps/arm/shared/cache/cache-cp15.c b/bsps/arm/shared/cache/cache-cp15.c
index 9a58146277..d78ec4feb4 100644
--- a/bsps/arm/shared/cache/cache-cp15.c
+++ b/bsps/arm/shared/cache/cache-cp15.c
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
 /**
  * @file
  *
@@ -7,11 +9,28 @@
  */
 
 /*
- * Copyright (C) 2009, 2018 embedded brains GmbH
+ * Copyright (C) 2009, 2018 embedded brains GmbH & Co. KG
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
  */
 
 #include <libcpu/arm-cp15.h>
@@ -181,6 +200,7 @@ static inline void _CPU_cache_disable_instruction(void)
   rtems_interrupt_local_enable(level);
 }
 
+#if __ARM_ARCH >= 6
 static inline size_t arm_cp15_get_cache_size(
   uint32_t level,
   uint32_t which
@@ -219,5 +239,30 @@ static inline size_t _CPU_cache_get_instruction_cache_size(uint32_t level)
 {
   return arm_cp15_get_cache_size(level, ARM_CP15_CACHE_CSS_ID_INSTRUCTION);
 }
+#else
+static inline size_t _CPU_cache_get_data_cache_size(uint32_t level)
+{
+  uint32_t cache_type;
+
+  if (level > 0) {
+    return 0;
+  }
+
+  cache_type = arm_cp15_get_cache_type();
+  return 1U << (((cache_type >> (12 + 6)) & 0xf) + 9);
+}
+
+static inline size_t _CPU_cache_get_instruction_cache_size(uint32_t level)
+{
+  uint32_t cache_type;
+
+  if (level > 0) {
+    return 0;
+  }
+
+  cache_type = arm_cp15_get_cache_type();
+  return 1U << (((cache_type >> (0 + 6)) & 0xf) + 9);
+}
+#endif
 
 #include "../../shared/cache/cacheimpl.h"