diff options
Diffstat (limited to '')
| -rw-r--r-- | bsps/arm/imxrt/mcux-sdk/drivers/flexcan/fsl_flexcan.c | 4613 | ||||
| -rw-r--r-- | bsps/arm/imxrt/mcux-sdk/drivers/flexcan/fsl_flexcan.h | 2241 | ||||
| -rw-r--r-- | bsps/arm/imxrt/mcux-sdk/drivers/flexcan/fsl_flexcan_edma.h | 188 |
3 files changed, 7042 insertions, 0 deletions
diff --git a/bsps/arm/imxrt/mcux-sdk/drivers/flexcan/fsl_flexcan.c b/bsps/arm/imxrt/mcux-sdk/drivers/flexcan/fsl_flexcan.c new file mode 100644 index 0000000000..280a472e65 --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/drivers/flexcan/fsl_flexcan.c @@ -0,0 +1,4613 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2023 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexcan.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcan" +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) +#define RXINTERMISSION (CAN_DBG1_CFSM(0x2f)) +#define TXINTERMISSION (CAN_DBG1_CFSM(0x14)) +#define BUSIDLE (CAN_DBG1_CFSM(0x02)) +#define CBN_VALUE3 (CAN_DBG1_CBN(0x03)) +#define DELAY_BUSIDLE (200) +#endif + +/* According to CiA doc 1301 v1.0.0, specified data/nominal phase sample point postion for CAN FD at 80 MHz. */ +#define IDEAL_DATA_SP_1 (800U) +#define IDEAL_DATA_SP_2 (750U) +#define IDEAL_DATA_SP_3 (700U) +#define IDEAL_DATA_SP_4 (625U) +#define IDEAL_NOMINAL_SP (800U) + +/* According to CiA doc 301 v4.2.0 and previous version. */ +#define IDEAL_SP_LOW (750U) +#define IDEAL_SP_MID (800U) +#define IDEAL_SP_HIGH (875U) + +#define IDEAL_SP_FACTOR (1000U) + +/* Define the max value of bit timing segments when use different timing register. */ +#define MAX_PROPSEG (CAN_CTRL1_PROPSEG_MASK >> CAN_CTRL1_PROPSEG_SHIFT) +#define MAX_PSEG1 (CAN_CTRL1_PSEG1_MASK >> CAN_CTRL1_PSEG1_SHIFT) +#define MAX_PSEG2 (CAN_CTRL1_PSEG2_MASK >> CAN_CTRL1_PSEG2_SHIFT) +#define MAX_RJW (CAN_CTRL1_RJW_MASK >> CAN_CTRL1_RJW_SHIFT) +#define MAX_PRESDIV (CAN_CTRL1_PRESDIV_MASK >> CAN_CTRL1_PRESDIV_SHIFT) +#define CTRL1_MAX_TIME_QUANTA (1U + MAX_PROPSEG + 1U + MAX_PSEG1 + 1U + MAX_PSEG2 + 1U) +#define CTRL1_MIN_TIME_QUANTA (8U) + +#define MAX_EPROPSEG (CAN_CBT_EPROPSEG_MASK >> CAN_CBT_EPROPSEG_SHIFT) +#define MAX_EPSEG1 (CAN_CBT_EPSEG1_MASK >> CAN_CBT_EPSEG1_SHIFT) +#define MAX_EPSEG2 (CAN_CBT_EPSEG2_MASK >> CAN_CBT_EPSEG2_SHIFT) +#define MAX_ERJW (CAN_CBT_ERJW_MASK >> CAN_CBT_ERJW_SHIFT) +#define MAX_EPRESDIV (CAN_CBT_EPRESDIV_MASK >> CAN_CBT_EPRESDIV_SHIFT) +#define CBT_MAX_TIME_QUANTA (1U + MAX_EPROPSEG + 1U + MAX_EPSEG1 + 1U + MAX_EPSEG2 + 1U) +#define CBT_MIN_TIME_QUANTA (8U) + +#define MAX_FPROPSEG (CAN_FDCBT_FPROPSEG_MASK >> CAN_FDCBT_FPROPSEG_SHIFT) +#define MAX_FPSEG1 (CAN_FDCBT_FPSEG1_MASK >> CAN_FDCBT_FPSEG1_SHIFT) +#define MAX_FPSEG2 (CAN_FDCBT_FPSEG2_MASK >> CAN_FDCBT_FPSEG2_SHIFT) +#define MAX_FRJW (CAN_FDCBT_FRJW_MASK >> CAN_FDCBT_FRJW_SHIFT) +#define MAX_FPRESDIV (CAN_FDCBT_FPRESDIV_MASK >> CAN_FDCBT_FPRESDIV_SHIFT) +#define FDCBT_MAX_TIME_QUANTA (1U + MAX_FPROPSEG + 0U + MAX_FPSEG1 + 1U + MAX_FPSEG2 + 1U) +#define FDCBT_MIN_TIME_QUANTA (5U) + +#define MAX_TDCOFF ((uint32_t)CAN_FDCTRL_TDCOFF_MASK >> CAN_FDCTRL_TDCOFF_SHIFT) + +#define MAX_NTSEG1 (CAN_ENCBT_NTSEG1_MASK >> CAN_ENCBT_NTSEG1_SHIFT) +#define MAX_NTSEG2 (CAN_ENCBT_NTSEG2_MASK >> CAN_ENCBT_NTSEG2_SHIFT) +#define MAX_NRJW (CAN_ENCBT_NRJW_MASK >> CAN_ENCBT_NRJW_SHIFT) +#define MAX_ENPRESDIV (CAN_EPRS_ENPRESDIV_MASK >> CAN_EPRS_ENPRESDIV_SHIFT) +#define ENCBT_MAX_TIME_QUANTA (1U + MAX_NTSEG1 + 1U + MAX_NTSEG2 + 1U) +#define ENCBT_MIN_TIME_QUANTA (8U) + +#define MAX_DTSEG1 (CAN_EDCBT_DTSEG1_MASK >> CAN_EDCBT_DTSEG1_SHIFT) +#define MAX_DTSEG2 (CAN_EDCBT_DTSEG2_MASK >> CAN_EDCBT_DTSEG2_SHIFT) +#define MAX_DRJW (CAN_EDCBT_DRJW_MASK >> CAN_EDCBT_DRJW_SHIFT) +#define MAX_EDPRESDIV (CAN_EPRS_EDPRESDIV_MASK >> CAN_EPRS_EDPRESDIV_SHIFT) +#define EDCBT_MAX_TIME_QUANTA (1U + MAX_DTSEG1 + 1U + MAX_DTSEG2 + 1U) +#define EDCBT_MIN_TIME_QUANTA (5U) + +#define MAX_ETDCOFF ((uint32_t)CAN_ETDC_ETDCOFF_MASK >> CAN_ETDC_ETDCOFF_SHIFT) + +/* TSEG1 corresponds to the sum of xPROPSEG and xPSEG1, TSEG2 corresponds to the xPSEG2 value. */ +#define MIN_TIME_SEGMENT1 (2U) +#define MIN_TIME_SEGMENT2 (2U) + +/* Define maximum CAN and CAN FD bit rate supported by FLEXCAN. */ +#define MAX_CANFD_BITRATE (8000000U) +#define MAX_CAN_BITRATE (1000000U) + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595) +#define CAN_ESR1_FLTCONF_BUSOFF CAN_ESR1_FLTCONF(2U) +#endif + +/* Define the range of memory that needs to be initialized when the device has memory error detection feature. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) +#define CAN_INIT_RXFIR ((uintptr_t)base + 0x4Cu) +#define CAN_INIT_MEMORY_BASE_1 (uint32_t *)((uintptr_t)base + (uintptr_t)FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_1) +#define CAN_INIT_MEMORY_SIZE_1 FSL_FEATURE_FLEXCAN_INIT_MEMORY_SIZE_1 +#define CAN_INIT_MEMORY_BASE_2 (uint32_t *)((uintptr_t)base + (uintptr_t)FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_2) +#define CAN_INIT_MEMORY_SIZE_2 FSL_FEATURE_FLEXCAN_INIT_MEMORY_SIZE_2 +#endif + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#ifndef CAN_CLOCK_CHECK_NO_AFFECTS +/* If no define such MACRO, it mean that the CAN in current device have no clock affect issue. */ +#define CAN_CLOCK_CHECK_NO_AFFECTS (true) +#endif /* CAN_CLOCK_CHECK_NO_AFFECTS */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/*! @brief FlexCAN Internal State. */ +enum _flexcan_state +{ + kFLEXCAN_StateIdle = 0x0, /*!< MB/RxFIFO idle.*/ + kFLEXCAN_StateRxData = 0x1, /*!< MB receiving.*/ + kFLEXCAN_StateRxRemote = 0x2, /*!< MB receiving remote reply.*/ + kFLEXCAN_StateTxData = 0x3, /*!< MB transmitting.*/ + kFLEXCAN_StateTxRemote = 0x4, /*!< MB transmitting remote request.*/ + kFLEXCAN_StateRxFifo = 0x5, /*!< RxFIFO receiving.*/ +}; + +/*! @brief FlexCAN message buffer CODE for Rx buffers. */ +enum _flexcan_mb_code_rx +{ + kFLEXCAN_RxMbInactive = 0x0, /*!< MB is not active.*/ + kFLEXCAN_RxMbFull = 0x2, /*!< MB is full.*/ + kFLEXCAN_RxMbEmpty = 0x4, /*!< MB is active and empty.*/ + kFLEXCAN_RxMbOverrun = 0x6, /*!< MB is overwritten into a full buffer.*/ + kFLEXCAN_RxMbBusy = 0x8, /*!< FlexCAN is updating the contents of the MB, The CPU must not access the MB.*/ + kFLEXCAN_RxMbRanswer = 0xA, /*!< A frame was configured to recognize a Remote Request Frame and transmit a + Response Frame in return.*/ + kFLEXCAN_RxMbNotUsed = 0xF, /*!< Not used.*/ +}; + +/*! @brief FlexCAN message buffer CODE FOR Tx buffers. */ +enum _flexcan_mb_code_tx +{ + kFLEXCAN_TxMbInactive = 0x8, /*!< MB is not active.*/ + kFLEXCAN_TxMbAbort = 0x9, /*!< MB is aborted.*/ + kFLEXCAN_TxMbDataOrRemote = 0xC, /*!< MB is a TX Data Frame(when MB RTR = 0) or MB is a TX Remote Request + Frame (when MB RTR = 1).*/ + kFLEXCAN_TxMbTanswer = 0xE, /*!< MB is a TX Response Request Frame from an incoming Remote Request Frame.*/ + kFLEXCAN_TxMbNotUsed = 0xF, /*!< Not used.*/ +}; + +/* Typedef for interrupt handler. */ +typedef void (*flexcan_isr_t)(CAN_Type *base, flexcan_handle_t *handle); + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +#if !defined(NDEBUG) +/*! + * @brief Check if Message Buffer is occupied by Rx FIFO. + * + * This function check if Message Buffer is occupied by Rx FIFO. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The FlexCAN Message Buffer index. + * @return TRUE if the index MB is occupied by Rx FIFO, FALSE if the index MB not occupied by Rx FIFO. + */ +static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx); +#endif + +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) +/*! + * @brief Get the first valid Message buffer ID of give FlexCAN instance. + * + * This function is a helper function for Errata 5641 workaround. + * + * @param base FlexCAN peripheral base address. + * @return The first valid Message Buffer Number. + */ +static uint8_t FLEXCAN_GetFirstValidMb(CAN_Type *base); +#endif + +/*! + * @brief Reset the FlexCAN Instance. + * + * Restores the FlexCAN module to reset state, notice that this function + * will set all the registers to reset state so the FlexCAN module can not work + * after calling this API. + * + * @param base FlexCAN peripheral base address. + */ +static void FLEXCAN_Reset(CAN_Type *base); + +/*! + * @brief Calculates the segment values for a single bit time for classical CAN. + * + * This function use to calculates the Classical CAN segment values which will be set in CTRL1/CBT/ENCBT register. + * + * @param base FlexCAN peripheral base address. + * @param tqNum Number of time quantas per bit, range in 8 ~ 25 when use CTRL1, range in 8 ~ 129 when use CBT, range in + * 8 ~ 385 when use ENCBT. param pTimingConfig Pointer to the FlexCAN timing configuration structure. + */ +static void FLEXCAN_GetSegments(CAN_Type *base, + uint32_t bitRate, + uint32_t tqNum, + flexcan_timing_config_t *pTimingConfig); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Get Mailbox offset number by dword. + * + * This function gets the offset number of the specified mailbox. + * Mailbox is not consecutive between memory regions when payload is not 8 bytes + * so need to calculate the specified mailbox address. + * For example, in the first memory region, MB[0].CS address is 0x4002_4080. For 32 bytes + * payload frame, the second mailbox is ((1/12)*512 + 1%12*40)/4 = 10, meaning 10 dword + * after the 0x4002_4080, which is actually the address of mailbox MB[1].CS. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx Mailbox index. + */ +static uint32_t FLEXCAN_GetFDMailboxOffset(CAN_Type *base, uint8_t mbIdx); + +/*! + * @brief Calculates the segment values for a single bit time for CAN FD data phase. + * + * This function use to calculates the CAN FD data phase segment values which will be set in CFDCBT/EDCBT + * register. + * + * @param bitRateFD Data phase bit rate + * @param tqNum Number of time quanta per bit + * @param pTimingConfig Pointer to the FlexCAN timing configuration structure. + */ +static void FLEXCAN_FDGetSegments(uint32_t bitRateFD, uint32_t tqNum, flexcan_timing_config_t *pTimingConfig); + +/*! + * @brief Calculates the improved timing values by specific bit rate for CAN FD nominal phase. + * + * This function use to calculates the CAN FD nominal phase timing values according to the given nominal phase bit rate. + * The Calculated timing values will be set in CBT/ENCBT registers. The calculation is based on the recommendation of + * the CiA 1301 v1.0.0 document. + * + * @param bitRate The CAN FD nominal phase speed in bps defined by user, should be less than or equal to 1Mbps. + * @param sourceClock_Hz The Source clock frequency in Hz. + * @param pTimingConfig Pointer to the FlexCAN timing configuration structure. + * + * @return TRUE if timing configuration found, FALSE if failed to find configuration. + */ +static bool FLEXCAN_CalculateImprovedNominalTimingValues(uint32_t bitRate, + uint32_t sourceClock_Hz, + flexcan_timing_config_t *pTimingConfig); + +#endif + +/*! + * @brief Check unhandle interrupt events + * + * @param base FlexCAN peripheral base address. + * @return TRUE if unhandled interrupt action exist, FALSE if no unhandlered interrupt action exist. + */ +static bool FLEXCAN_CheckUnhandleInterruptEvents(CAN_Type *base); + +/*! + * @brief Sub Handler Data Trasfered Events + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param pResult Pointer to the Handle result. + * + * @return the status after handle each data transfered event. + */ +static status_t FLEXCAN_SubHandlerForDataTransfered(CAN_Type *base, flexcan_handle_t *handle, uint32_t *pResult); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * @brief Sub Handler Ehanced Rx FIFO event + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param flags FlexCAN interrupt flags. + * + * @return the status after handle Ehanced Rx FIFO event. + */ +static status_t FLEXCAN_SubHandlerForEhancedRxFifo(CAN_Type *base, flexcan_handle_t *handle, uint64_t flags); +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/* Array of FlexCAN peripheral base address. */ +static CAN_Type *const s_flexcanBases[] = CAN_BASE_PTRS; + +/* Array of FlexCAN IRQ number. */ +static const IRQn_Type s_flexcanRxWarningIRQ[] = CAN_Rx_Warning_IRQS; +static const IRQn_Type s_flexcanTxWarningIRQ[] = CAN_Tx_Warning_IRQS; +static const IRQn_Type s_flexcanWakeUpIRQ[] = CAN_Wake_Up_IRQS; +static const IRQn_Type s_flexcanErrorIRQ[] = CAN_Error_IRQS; +static const IRQn_Type s_flexcanBusOffIRQ[] = CAN_Bus_Off_IRQS; +static const IRQn_Type s_flexcanMbIRQ[] = CAN_ORed_Message_buffer_IRQS; + +/* Array of FlexCAN handle. */ +static flexcan_handle_t *s_flexcanHandle[ARRAY_SIZE(s_flexcanBases)]; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/* Array of FlexCAN clock name. */ +static const clock_ip_name_t s_flexcanClock[] = FLEXCAN_CLOCKS; +#if defined(FLEXCAN_PERIPH_CLOCKS) +/* Array of FlexCAN serial clock name. */ +static const clock_ip_name_t s_flexcanPeriphClock[] = FLEXCAN_PERIPH_CLOCKS; +#endif /* FLEXCAN_PERIPH_CLOCKS */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/* FlexCAN ISR for transactional APIs. */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +static flexcan_isr_t s_flexcanIsr = (flexcan_isr_t)DefaultISR; +#else +static flexcan_isr_t s_flexcanIsr; +#endif + +/******************************************************************************* + * Implementation of 32-bit memset + ******************************************************************************/ + +static void flexcan_memset(void *s, uint32_t c, size_t n) +{ + size_t m; + uint32_t *ptr = s; + + m = n / sizeof(*ptr); + + while ((m--) != (size_t)0) + { + *ptr++ = c; + } +} + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * brief Get the FlexCAN instance from peripheral base address. + * + * param base FlexCAN peripheral base address. + * return FlexCAN instance. + */ +uint32_t FLEXCAN_GetInstance(CAN_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_flexcanBases); instance++) + { + if (s_flexcanBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_flexcanBases)); + + return instance; +} + +/*! + * brief Enter FlexCAN Freeze Mode. + * + * This function makes the FlexCAN work under Freeze Mode. + * + * param base FlexCAN peripheral base address. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595) +void FLEXCAN_EnterFreezeMode(CAN_Type *base) +{ + uint32_t u32TimeoutCount = 0U; + uint32_t u32TempMCR = 0U; + uint32_t u32TempIMASK1 = 0U; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint32_t u32TempIMASK2 = 0U; +#endif + + /* Step1: set FRZ enable in MCR. */ + base->MCR |= CAN_MCR_FRZ_MASK; + + /* Step2: to check if MDIS bit set in MCR. if yes, clear it. */ + if (0U != (base->MCR & CAN_MCR_MDIS_MASK)) + { + base->MCR &= ~CAN_MCR_MDIS_MASK; + } + + /* Step3: polling LPMACK. */ + u32TimeoutCount = (uint32_t)FLEXCAN_WAIT_TIMEOUT; + while ((0U == (base->MCR & CAN_MCR_LPMACK_MASK)) && (u32TimeoutCount > 0U)) + { + u32TimeoutCount--; + } + + /* Step4: to check FLTCONF in ESR1 register */ + if (0U == (base->ESR1 & CAN_ESR1_FLTCONF_BUSOFF)) + { + /* Step5B: Set Halt bits. */ + base->MCR |= CAN_MCR_HALT_MASK; + + /* Step6B: Poll the MCR register until the Freeze Acknowledge (FRZACK) bit is set, timeout need more than 178 + * CAN bit length, so 20 multiply timeout is enough. */ + u32TimeoutCount = (uint32_t)FLEXCAN_WAIT_TIMEOUT * 20U; + while ((0U == (base->MCR & CAN_MCR_FRZACK_MASK)) && (u32TimeoutCount > 0U)) + { + u32TimeoutCount--; + } + } + else + { + /* backup MCR and IMASK register. Errata document not descript it, but we need backup for step 8A and 9A. */ + u32TempMCR = base->MCR; + u32TempIMASK1 = base->IMASK1; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + u32TempIMASK2 = base->IMASK2; +#endif + + /* Step5A: Set the Soft Reset bit ((SOFTRST) in the MCR.*/ + base->MCR |= CAN_MCR_SOFTRST_MASK; + + /* Step6A: Poll the MCR register until the Soft Reset (SOFTRST) bit is cleared. */ + u32TimeoutCount = (uint32_t)FLEXCAN_WAIT_TIMEOUT; + while ((CAN_MCR_SOFTRST_MASK == (base->MCR & CAN_MCR_SOFTRST_MASK)) && (u32TimeoutCount > 0U)) + { + u32TimeoutCount--; + } + + /* Step7A: Poll the MCR register until the Freeze Acknowledge (FRZACK) bit is set. */ + u32TimeoutCount = (uint32_t)FLEXCAN_WAIT_TIMEOUT; + while ((0U == (base->MCR & CAN_MCR_FRZACK_MASK)) && (u32TimeoutCount > 0U)) + { + u32TimeoutCount--; + } + + /* Step8A: reconfig MCR. */ + base->MCR = u32TempMCR; + + /* Step9A: reconfig IMASK. */ + base->IMASK1 = u32TempIMASK1; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + base->IMASK2 = u32TempIMASK2; +#endif + } +} +#elif (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_8341) +void FLEXCAN_EnterFreezeMode(CAN_Type *base) +{ + uint32_t u32TimeoutCount = 0U; + uint32_t u32TempMCR = 0U; + uint32_t u32TempIMASK1 = 0U; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint32_t u32TempIMASK2 = 0U; +#endif + + /* Step1: set FRZ and HALT bit enable in MCR. */ + base->MCR |= CAN_MCR_FRZ_MASK; + base->MCR |= CAN_MCR_HALT_MASK; + + /* Step2: to check if MDIS bit set in MCR. if yes, clear it. */ + if (0U != (base->MCR & CAN_MCR_MDIS_MASK)) + { + base->MCR &= ~CAN_MCR_MDIS_MASK; + } + + /* Step3: Poll the MCR register until the Freeze Acknowledge (FRZACK) bit is set. */ + u32TimeoutCount = (uint32_t)FLEXCAN_WAIT_TIMEOUT * 100U; + while ((0U == (base->MCR & CAN_MCR_FRZACK_MASK)) && (u32TimeoutCount > 0U)) + { + u32TimeoutCount--; + } + + /* Step4: check whether the timeout reached. if no skip step5 to step8. */ + if (0U == u32TimeoutCount) + { + /* backup MCR and IMASK register. Errata document not descript it, but we need backup for step 8A and 9A. */ + u32TempMCR = base->MCR; + u32TempIMASK1 = base->IMASK1; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + u32TempIMASK2 = base->IMASK2; +#endif + /* Step5: Set the Soft Reset bit ((SOFTRST) in the MCR.*/ + base->MCR |= CAN_MCR_SOFTRST_MASK; + + /* Step6: Poll the MCR register until the Soft Reset (SOFTRST) bit is cleared. */ + while (CAN_MCR_SOFTRST_MASK == (base->MCR & CAN_MCR_SOFTRST_MASK)) + { + } + + /* Step7: reconfig MCR. */ + base->MCR = u32TempMCR; + + /* Step8: reconfig IMASK. */ + base->IMASK1 = u32TempIMASK1; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + base->IMASK2 = u32TempIMASK2; +#endif + } +} +#else +void FLEXCAN_EnterFreezeMode(CAN_Type *base) +{ + /* Set Freeze, Halt bits. */ + base->MCR |= CAN_MCR_FRZ_MASK; + base->MCR |= CAN_MCR_HALT_MASK; + while (0U == (base->MCR & CAN_MCR_FRZACK_MASK)) + { + } +} +#endif + +/*! + * brief Exit FlexCAN Freeze Mode. + * + * This function makes the FlexCAN leave Freeze Mode. + * + * param base FlexCAN peripheral base address. + */ +void FLEXCAN_ExitFreezeMode(CAN_Type *base) +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + /* Clean FlexCAN Access With Non-Correctable Error Interrupt Flag to avoid be put in freeze mode. */ + FLEXCAN_ClearStatusFlags(base, (uint64_t)kFLEXCAN_FlexCanAccessNonCorrectableErrorIntFlag | + (uint64_t)kFLEXCAN_FlexCanAccessNonCorrectableErrorOverrunFlag); +#endif + + /* Clear Freeze, Halt bits. */ + base->MCR &= ~CAN_MCR_HALT_MASK; + base->MCR &= ~CAN_MCR_FRZ_MASK; + + /* Wait until the FlexCAN Module exit freeze mode. */ + while (0U != (base->MCR & CAN_MCR_FRZACK_MASK)) + { + } +} + +#if !defined(NDEBUG) +/*! + * brief Check if Message Buffer is occupied by Rx FIFO. + * + * This function check if Message Buffer is occupied by Rx FIFO. + * + * param base FlexCAN peripheral base address. + * param mbIdx The FlexCAN Message Buffer index. + * return TRUE if the index MB is occupied by Rx FIFO, FALSE if the index MB not occupied by Rx FIFO. + */ +static bool FLEXCAN_IsMbOccupied(CAN_Type *base, uint8_t mbIdx) +{ + uint8_t lastOccupiedMb; + bool fgRet; + + /* Is Rx FIFO enabled? */ + if (0U != (base->MCR & CAN_MCR_RFEN_MASK)) + { + /* Get RFFN value. */ + lastOccupiedMb = (uint8_t)((base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT); + /* Calculate the number of last Message Buffer occupied by Rx FIFO. */ + lastOccupiedMb = ((lastOccupiedMb + 1U) * 2U) + 5U; + +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) + /* the first valid MB should be occupied by ERRATA 5461 or 5829. */ + lastOccupiedMb += 1U; +#endif + fgRet = (mbIdx <= lastOccupiedMb); + } + else + { +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) + if (0U == mbIdx) + { + fgRet = true; + } + else +#endif + { + fgRet = false; + } + } + + return fgRet; +} +#endif + +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) +/*! + * brief Get the first valid Message buffer ID of give FlexCAN instance. + * + * This function is a helper function for Errata 5641 workaround. + * + * param base FlexCAN peripheral base address. + * return The first valid Message Buffer Number. + */ +static uint8_t FLEXCAN_GetFirstValidMb(CAN_Type *base) +{ + uint8_t firstValidMbNum; + + if (0U != (base->MCR & CAN_MCR_RFEN_MASK)) + { + firstValidMbNum = (uint8_t)((base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT); + firstValidMbNum = ((firstValidMbNum + 1U) * 2U) + 6U; + } + else + { + firstValidMbNum = 0U; + } + + return firstValidMbNum; +} +#endif + +/*! + * brief Reset the FlexCAN Instance. + * + * Restores the FlexCAN module to reset state, notice that this function + * will set all the registers to reset state so the FlexCAN module can not work + * after calling this API. + * + * param base FlexCAN peripheral base address. + */ +static void FLEXCAN_Reset(CAN_Type *base) +{ + /* The module must should be first exit from low power + * mode, and then soft reset can be applied. + */ + assert(0U == (base->MCR & CAN_MCR_MDIS_MASK)); + + uint8_t i; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) + if (0 != (FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(base))) + { + /* De-assert DOZE Enable Bit. */ + base->MCR &= ~CAN_MCR_DOZE_MASK; + } +#endif + + /* Wait until FlexCAN exit from any Low Power Mode. */ + while (0U != (base->MCR & CAN_MCR_LPMACK_MASK)) + { + } + + /* Assert Soft Reset Signal. */ + base->MCR |= CAN_MCR_SOFTRST_MASK; + /* Wait until FlexCAN reset completes. */ + while (0U != (base->MCR & CAN_MCR_SOFTRST_MASK)) + { + } + +/* Reset MCR register. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER) && FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER) + base->MCR |= CAN_MCR_WRNEN_MASK | CAN_MCR_WAKSRC_MASK | + CAN_MCR_MAXMB((uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1U); +#else + base->MCR |= + CAN_MCR_WRNEN_MASK | CAN_MCR_MAXMB((uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base) - 1U); +#endif + + /* Reset CTRL1 and CTRL2 register, default to eanble SMP feature which enable three sample point to determine the + * received bit's value of the. */ + base->CTRL1 = CAN_CTRL1_SMP_MASK; + base->CTRL2 = CAN_CTRL2_TASD(0x16) | CAN_CTRL2_RRS_MASK | CAN_CTRL2_EACEN_MASK; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + /* Enable unrestricted write access to FlexCAN memory. */ + base->CTRL2 |= CAN_CTRL2_WRMFRZ_MASK; + /* Do memory initialization for all FlexCAN RAM in order to have the parity bits in memory properly + updated. */ + *(volatile uint32_t *)CAN_INIT_RXFIR = 0x0U; + flexcan_memset(CAN_INIT_MEMORY_BASE_1, 0, CAN_INIT_MEMORY_SIZE_1); + flexcan_memset(CAN_INIT_MEMORY_BASE_2, 0, CAN_INIT_MEMORY_SIZE_2); + /* Disable unrestricted write access to FlexCAN memory. */ + base->CTRL2 &= ~CAN_CTRL2_WRMFRZ_MASK; + + /* Clean all memory error flags. */ + FLEXCAN_ClearStatusFlags(base, (uint64_t)kFLEXCAN_AllMemoryErrorFlag); +#else + /* Only need clean all Message Buffer memory. */ + flexcan_memset((void *)&base->MB[0], 0, sizeof(base->MB)); +#endif + + /* Clean all individual Rx Mask of Message Buffers. */ + for (i = 0; i < (uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); i++) + { + base->RXIMR[i] = 0x3FFFFFFF; + } + + /* Clean Global Mask of Message Buffers. */ + base->RXMGMASK = 0x3FFFFFFF; + /* Clean Global Mask of Message Buffer 14. */ + base->RX14MASK = 0x3FFFFFFF; + /* Clean Global Mask of Message Buffer 15. */ + base->RX15MASK = 0x3FFFFFFF; + /* Clean Global Mask of Rx FIFO. */ + base->RXFGMASK = 0x3FFFFFFF; +} + +/*! + * brief Set bit rate of FlexCAN classical CAN frame or CAN FD frame nominal phase. + * + * This function set the bit rate of classical CAN frame or CAN FD frame nominal phase base on + * FLEXCAN_CalculateImprovedTimingValues() API calculated timing values. + * + * note Calling FLEXCAN_SetBitRate() overrides the bit rate set in FLEXCAN_Init(). + * + * param base FlexCAN peripheral base address. + * param sourceClock_Hz Source Clock in Hz. + * param bitRate_Bps Bit rate in Bps. + * return kStatus_Success - Set CAN baud rate (only Nominal phase) successfully. + */ +status_t FLEXCAN_SetBitRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t bitRate_Bps) +{ + flexcan_timing_config_t timingCfg; + status_t result = kStatus_Fail; + + if (FLEXCAN_CalculateImprovedTimingValues(base, bitRate_Bps, sourceClock_Hz, &timingCfg)) + { + FLEXCAN_SetTimingConfig(base, &timingCfg); + result = kStatus_Success; + } + + return result; +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Set bit rate of FlexCAN FD frame. + * + * This function set the baud rate of FLEXCAN FD base on FLEXCAN_FDCalculateImprovedTimingValues() API calculated timing + * values. + * + * @param base FlexCAN peripheral base address. + * @param sourceClock_Hz Source Clock in Hz. + * @param bitRateN_Bps Nominal bit Rate in Bps. + * @param bitRateD_Bps Data bit Rate in Bps. + * @return kStatus_Success - Set CAN FD bit rate (include Nominal and Data phase) successfully. + */ +status_t FLEXCAN_SetFDBitRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t bitRateN_Bps, uint32_t bitRateD_Bps) +{ + flexcan_timing_config_t timingCfg; + status_t result = kStatus_Fail; + + if (FLEXCAN_FDCalculateImprovedTimingValues(base, bitRateN_Bps, bitRateD_Bps, sourceClock_Hz, &timingCfg)) + { + FLEXCAN_SetFDTimingConfig(base, &timingCfg); + result = kStatus_Success; + } + + return result; +} +#endif + +/*! + * brief Initializes a FlexCAN instance. + * + * This function initializes the FlexCAN module with user-defined settings. + * This example shows how to set up the flexcan_config_t parameters and how + * to call the FLEXCAN_Init function by passing in these parameters. + * code + * flexcan_config_t flexcanConfig; + * flexcanConfig.clkSrc = kFLEXCAN_ClkSrc0; + * flexcanConfig.bitRate = 1000000U; + * flexcanConfig.maxMbNum = 16; + * flexcanConfig.enableLoopBack = false; + * flexcanConfig.enableSelfWakeup = false; + * flexcanConfig.enableIndividMask = false; + * flexcanConfig.disableSelfReception = false; + * flexcanConfig.enableListenOnlyMode = false; + * flexcanConfig.enableDoze = false; + * flexcanConfig.timingConfig = timingConfig; + * FLEXCAN_Init(CAN0, &flexcanConfig, 40000000UL); + * endcode + * + * param base FlexCAN peripheral base address. + * param pConfig Pointer to the user-defined configuration structure. + * param sourceClock_Hz FlexCAN Protocol Engine clock source frequency in Hz. + */ +void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *pConfig, uint32_t sourceClock_Hz) +{ + /* Assertion. */ + assert(NULL != pConfig); + assert((pConfig->maxMbNum > 0U) && + (pConfig->maxMbNum <= (uint8_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base))); + + uint32_t mcrTemp; + uint32_t ctrl1Temp; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + uint32_t instance; +#endif + flexcan_timing_config_t timingCfg = pConfig->timingConfig; + /* FlexCAN classical CAN frame or CAN FD frame nominal phase timing setting formula: + * quantum = 1 + (phaseSeg1 + 1) + (phaseSeg2 + 1) + (propSeg + 1); + */ + uint32_t quantum = (1U + ((uint32_t)timingCfg.phaseSeg1 + 1U) + ((uint32_t)timingCfg.phaseSeg2 + 1U) + + ((uint32_t)timingCfg.propSeg + 1U)); + uint32_t tqFre = pConfig->bitRate * quantum; + uint16_t maxDivider; + + /* Assertion: Check bit rate value. */ + assert((pConfig->bitRate != 0U) && (pConfig->bitRate <= 1000000U) && (tqFre <= sourceClock_Hz)); +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base)) + { +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) + assert((tqFre * MAX_ENPRESDIV) >= sourceClock_Hz); + maxDivider = MAX_ENPRESDIV; +#else + assert((tqFre * MAX_EPRESDIV) >= sourceClock_Hz); + maxDivider = MAX_EPRESDIV; +#endif + } + else + { + assert((tqFre * MAX_PRESDIV) >= sourceClock_Hz); + maxDivider = MAX_PRESDIV; + } +#else + assert((tqFre * MAX_PRESDIV) >= sourceClock_Hz); + maxDivider = MAX_PRESDIV; +#endif + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + instance = FLEXCAN_GetInstance(base); + /* Enable FlexCAN clock. */ + (void)CLOCK_EnableClock(s_flexcanClock[instance]); + /* + * Check the CAN clock in this device whether affected by Other clock gate + * If it affected, we'd better to change other clock source, + * If user insist on using that clock source, user need open these gate at same time, + * In this scene, User need to care the power consumption. + */ + assert(CAN_CLOCK_CHECK_NO_AFFECTS); +#if defined(FLEXCAN_PERIPH_CLOCKS) + /* Enable FlexCAN serial clock. */ + (void)CLOCK_EnableClock(s_flexcanPeriphClock[instance]); +#endif /* FLEXCAN_PERIPH_CLOCKS */ +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +#if defined(CAN_CTRL1_CLKSRC_MASK) +#if (defined(FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE) && FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE) + if (0 == FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(base)) +#endif /* FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE */ + { + /* Disable FlexCAN Module. */ + FLEXCAN_Enable(base, false); + + /* Protocol-Engine clock source selection, This bit must be set + * when FlexCAN Module in Disable Mode. + */ + base->CTRL1 = (kFLEXCAN_ClkSrc0 == pConfig->clkSrc) ? (base->CTRL1 & ~CAN_CTRL1_CLKSRC_MASK) : + (base->CTRL1 | CAN_CTRL1_CLKSRC_MASK); + } +#endif /* CAN_CTRL1_CLKSRC_MASK */ + + /* Enable FlexCAN Module for configuration. */ + FLEXCAN_Enable(base, true); + + /* Reset to known status. */ + FLEXCAN_Reset(base); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + /* Enable to update in MCER. */ + base->CTRL2 |= CAN_CTRL2_ECRWRE_MASK; + base->MECR &= ~CAN_MECR_ECRWRDIS_MASK; + + /* Enable/Disable Memory Error Detection and Correction.*/ + base->MECR = (pConfig->enableMemoryErrorControl) ? (base->MECR & ~CAN_MECR_ECCDIS_MASK) : + (base->MECR | CAN_MECR_ECCDIS_MASK); + + /* Enable/Disable Non-Correctable Errors In FlexCAN Access Put Device In Freeze Mode. */ + base->MECR = (pConfig->enableNonCorrectableErrorEnterFreeze) ? (base->MECR | CAN_MECR_NCEFAFRZ_MASK) : + (base->MECR & ~CAN_MECR_NCEFAFRZ_MASK); + /* Lock MCER register. */ + base->CTRL2 &= ~CAN_CTRL2_ECRWRE_MASK; +#endif + + /* Save current CTRL1 value and enable to enter Freeze mode(enabled by default). */ + ctrl1Temp = base->CTRL1; + + /* Save current MCR value and enable to enter Freeze mode(enabled by default). */ + mcrTemp = base->MCR; + + /* Enable Loop Back Mode? */ + ctrl1Temp = (pConfig->enableLoopBack) ? (ctrl1Temp | CAN_CTRL1_LPB_MASK) : (ctrl1Temp & ~CAN_CTRL1_LPB_MASK); + + /* Enable Timer Sync? */ + ctrl1Temp = (pConfig->enableTimerSync) ? (ctrl1Temp | CAN_CTRL1_TSYN_MASK) : (ctrl1Temp & ~CAN_CTRL1_TSYN_MASK); + + /* Enable Listen Only Mode? */ + ctrl1Temp = (pConfig->enableListenOnlyMode) ? ctrl1Temp | CAN_CTRL1_LOM_MASK : ctrl1Temp & ~CAN_CTRL1_LOM_MASK; + +#if !(defined(FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT) + /* Enable Supervisor Mode? */ + mcrTemp = (pConfig->enableSupervisorMode) ? mcrTemp | CAN_MCR_SUPV_MASK : mcrTemp & ~CAN_MCR_SUPV_MASK; +#endif + + /* Set the maximum number of Message Buffers */ + mcrTemp = (mcrTemp & ~CAN_MCR_MAXMB_MASK) | CAN_MCR_MAXMB((uint32_t)pConfig->maxMbNum - 1U); + + /* Enable Self Wake Up Mode and configure the wake up source. */ + mcrTemp = (pConfig->enableSelfWakeup) ? (mcrTemp | CAN_MCR_SLFWAK_MASK) : (mcrTemp & ~CAN_MCR_SLFWAK_MASK); + mcrTemp = (kFLEXCAN_WakeupSrcFiltered == pConfig->wakeupSrc) ? (mcrTemp | CAN_MCR_WAKSRC_MASK) : + (mcrTemp & ~CAN_MCR_WAKSRC_MASK); +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) + /* Enable Pretended Networking Mode? When Pretended Networking mode is set, Self Wake Up feature must be disabled.*/ + mcrTemp = (pConfig->enablePretendedeNetworking) ? ((mcrTemp & ~CAN_MCR_SLFWAK_MASK) | CAN_MCR_PNET_EN_MASK) : + (mcrTemp & ~CAN_MCR_PNET_EN_MASK); +#endif + + /* Enable Individual Rx Masking and Queue feature? */ + mcrTemp = (pConfig->enableIndividMask) ? (mcrTemp | CAN_MCR_IRMQ_MASK) : (mcrTemp & ~CAN_MCR_IRMQ_MASK); + + /* Disable Self Reception? */ + mcrTemp = (pConfig->disableSelfReception) ? mcrTemp | CAN_MCR_SRXDIS_MASK : mcrTemp & ~CAN_MCR_SRXDIS_MASK; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) + if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(base)) + { + /* Enable Doze Mode? */ + mcrTemp = (pConfig->enableDoze) ? (mcrTemp | CAN_MCR_DOZE_MASK) : (mcrTemp & ~CAN_MCR_DOZE_MASK); + } +#endif + + /* Write back CTRL1 Configuration to register. */ + base->CTRL1 = ctrl1Temp; + + /* Write back MCR Configuration to register. */ + base->MCR = mcrTemp; + + /* Check whether Nominal Bit Rate Prescaler is overflow. */ + if ((sourceClock_Hz / tqFre - 1U) > maxDivider) + { + timingCfg.preDivider = maxDivider; + } + else + { + timingCfg.preDivider = (uint16_t)(sourceClock_Hz / tqFre) - 1U; + } + + /* Update actual timing characteristic. */ + FLEXCAN_SetTimingConfig(base, &timingCfg); +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Initializes a FlexCAN instance. + * + * This function initializes the FlexCAN module with user-defined settings. + * This example shows how to set up the flexcan_config_t parameters and how + * to call the FLEXCAN_FDInit function by passing in these parameters. + * code + * flexcan_config_t flexcanConfig; + * flexcanConfig.clkSrc = kFLEXCAN_ClkSrc0; + * flexcanConfig.bitRate = 1000000U; + * flexcanConfig.bitRateFD = 2000000U; + * flexcanConfig.maxMbNum = 16; + * flexcanConfig.enableLoopBack = false; + * flexcanConfig.enableSelfWakeup = false; + * flexcanConfig.enableIndividMask = false; + * flexcanConfig.disableSelfReception = false; + * flexcanConfig.enableListenOnlyMode = false; + * flexcanConfig.enableDoze = false; + * flexcanConfig.timingConfig = timingConfig; + * FLEXCAN_FDInit(CAN0, &flexcanConfig, 80000000UL, kFLEXCAN_16BperMB, true); + * endcode + * + * param base FlexCAN peripheral base address. + * param pConfig Pointer to the user-defined configuration structure. + * param sourceClock_Hz FlexCAN Protocol Engine clock source frequency in Hz. + * param dataSize FlexCAN Message Buffer payload size. The actual transmitted or received CAN FD frame data size needs + * to be less than or equal to this value. + * param brs True if bit rate switch is enabled in FD mode. + */ +void FLEXCAN_FDInit( + CAN_Type *base, const flexcan_config_t *pConfig, uint32_t sourceClock_Hz, flexcan_mb_size_t dataSize, bool brs) +{ + assert((uint32_t)dataSize <= 3U); + assert(((pConfig->bitRate < pConfig->bitRateFD) && brs) || ((pConfig->bitRate == pConfig->bitRateFD) && (!brs))); + + uint32_t fdctrl = 0U; + flexcan_timing_config_t timingCfg = pConfig->timingConfig; + /* FlexCAN FD frame data phase timing setting formula: + * quantum = 1 + (fphaseSeg1 + 1) + (fphaseSeg2 + 1) + fpropSeg; + */ + uint32_t quantum = (1U + ((uint32_t)timingCfg.fphaseSeg1 + 1U) + ((uint32_t)timingCfg.fphaseSeg2 + 1U) + + (uint32_t)timingCfg.fpropSeg); + uint32_t tqFre = pConfig->bitRateFD * quantum; + uint16_t maxDivider; + + /* Check bit rate value. */ + assert((pConfig->bitRateFD <= 8000000U) && (tqFre <= sourceClock_Hz)); +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) + assert((tqFre * MAX_EDPRESDIV) >= sourceClock_Hz); + maxDivider = MAX_EDPRESDIV; +#else + assert((tqFre * MAX_FPRESDIV) >= sourceClock_Hz); + maxDivider = MAX_FPRESDIV; +#endif + + /* Initialization of classical CAN. */ + FLEXCAN_Init(base, pConfig, sourceClock_Hz); + + /* Check whether Data Bit Rate Prescaler is overflow. */ + if ((sourceClock_Hz / tqFre - 1U) > maxDivider) + { + timingCfg.fpreDivider = maxDivider; + } + else + { + timingCfg.fpreDivider = (uint16_t)(sourceClock_Hz / tqFre) - 1U; + } + + /* Update actual timing characteristic. */ + FLEXCAN_SetFDTimingConfig(base, &timingCfg); + + /* read FDCTRL register. */ + fdctrl = base->FDCTRL; + + /* Enable FD operation and set bit rate switch. */ + if (brs) + { + fdctrl |= CAN_FDCTRL_FDRATE_MASK; + } + else + { + fdctrl &= ~CAN_FDCTRL_FDRATE_MASK; + } + + /* Before use "|=" operation for multi-bits field, CPU should clean previous Setting. */ + fdctrl = (fdctrl & ~CAN_FDCTRL_MBDSR0_MASK) | CAN_FDCTRL_MBDSR0(dataSize); +#if defined(CAN_FDCTRL_MBDSR1_MASK) + fdctrl = (fdctrl & ~CAN_FDCTRL_MBDSR1_MASK) | CAN_FDCTRL_MBDSR1(dataSize); +#endif +#if defined(CAN_FDCTRL_MBDSR2_MASK) + fdctrl = (fdctrl & ~CAN_FDCTRL_MBDSR2_MASK) | CAN_FDCTRL_MBDSR2(dataSize); +#endif +#if defined(CAN_FDCTRL_MBDSR3_MASK) + fdctrl = (fdctrl & ~CAN_FDCTRL_MBDSR3_MASK) | CAN_FDCTRL_MBDSR3(dataSize); +#endif + + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + /* Enable CAN FD operation. */ + base->MCR |= CAN_MCR_FDEN_MASK; + /* Clear SMP bit when CAN FD is enabled (CAN FD only can use one regular sample point plus one optional secondary + * sampling point). */ + base->CTRL1 &= ~CAN_CTRL1_SMP_MASK; + + if (brs && !(pConfig->enableLoopBack)) + { +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) + /* The TDC offset should be configured as shown in this equation : offset = DTSEG1 + 2 */ + if (((uint32_t)pConfig->timingConfig.fphaseSeg1 + pConfig->timingConfig.fpropSeg + 2U) * + (pConfig->timingConfig.fpreDivider + 1U) < + MAX_ETDCOFF) + { + base->ETDC = + CAN_ETDC_ETDCEN_MASK | CAN_ETDC_TDMDIS(!pConfig->enableTransceiverDelayMeasure) | + CAN_ETDC_ETDCOFF(((uint32_t)pConfig->timingConfig.fphaseSeg1 + pConfig->timingConfig.fpropSeg + 2U) * + (pConfig->timingConfig.fpreDivider + 1U)); + } + else + { + /* Enable the Transceiver Delay Compensation */ + base->ETDC = CAN_ETDC_ETDCEN_MASK | CAN_ETDC_TDMDIS(!pConfig->enableTransceiverDelayMeasure) | + CAN_ETDC_ETDCOFF(MAX_ETDCOFF); + } +#else + /* The TDC offset should be configured as shown in this equation : offset = PSEG1 + PROPSEG + 2 */ + if (((uint32_t)pConfig->timingConfig.fphaseSeg1 + pConfig->timingConfig.fpropSeg + 2U) * + (pConfig->timingConfig.fpreDivider + 1U) < + MAX_TDCOFF) + { + fdctrl = + (fdctrl & ~CAN_FDCTRL_TDCOFF_MASK) | + CAN_FDCTRL_TDCOFF(((uint32_t)pConfig->timingConfig.fphaseSeg1 + pConfig->timingConfig.fpropSeg + 2U) * + (pConfig->timingConfig.fpreDivider + 1U)); + } + else + { + fdctrl = (fdctrl & ~CAN_FDCTRL_TDCOFF_MASK) | CAN_FDCTRL_TDCOFF(MAX_TDCOFF); + } + /* Enable the Transceiver Delay Compensation */ + fdctrl = (fdctrl & ~CAN_FDCTRL_TDCEN_MASK) | CAN_FDCTRL_TDCEN_MASK; +#endif + } + + /* update the FDCTL register. */ + base->FDCTRL = fdctrl; + + /* Enable CAN FD ISO mode by default. */ + base->CTRL2 |= CAN_CTRL2_ISOCANFDEN_MASK; + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} +#endif + +/*! + * brief De-initializes a FlexCAN instance. + * + * This function disables the FlexCAN module clock and sets all register values + * to the reset value. + * + * param base FlexCAN peripheral base address. + */ +void FLEXCAN_Deinit(CAN_Type *base) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + uint32_t instance; +#endif + /* Reset all Register Contents. */ + FLEXCAN_Reset(base); + + /* Disable FlexCAN module. */ + FLEXCAN_Enable(base, false); + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + instance = FLEXCAN_GetInstance(base); +#if defined(FLEXCAN_PERIPH_CLOCKS) + /* Disable FlexCAN serial clock. */ + (void)CLOCK_DisableClock(s_flexcanPeriphClock[instance]); +#endif /* FLEXCAN_PERIPH_CLOCKS */ + /* Disable FlexCAN clock. */ + (void)CLOCK_DisableClock(s_flexcanClock[instance]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Gets the default configuration structure. + * + * This function initializes the FlexCAN configuration structure to default values. The default + * values are as follows. + * flexcanConfig->clkSrc = kFLEXCAN_ClkSrc0; + * flexcanConfig->bitRate = 1000000U; + * flexcanConfig->bitRateFD = 2000000U; + * flexcanConfig->maxMbNum = 16; + * flexcanConfig->enableLoopBack = false; + * flexcanConfig->enableSelfWakeup = false; + * flexcanConfig->enableIndividMask = false; + * flexcanConfig->disableSelfReception = false; + * flexcanConfig->enableListenOnlyMode = false; + * flexcanConfig->enableDoze = false; + * flexcanConfig->enablePretendedeNetworking = false; + * flexcanConfig->enableMemoryErrorControl = true; + * flexcanConfig->enableNonCorrectableErrorEnterFreeze = true; + * flexcanConfig->enableTransceiverDelayMeasure = true; + * flexcanConfig.timingConfig = timingConfig; + * + * param pConfig Pointer to the FlexCAN configuration structure. + */ +void FLEXCAN_GetDefaultConfig(flexcan_config_t *pConfig) +{ + /* Assertion. */ + assert(NULL != pConfig); + + /* Initializes the configure structure to zero. */ + (void)memset(pConfig, 0, sizeof(*pConfig)); + + /* Initialize FlexCAN Module config struct with default value. */ + pConfig->clkSrc = kFLEXCAN_ClkSrc0; + pConfig->bitRate = 1000000U; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + pConfig->bitRateFD = 2000000U; +#endif + pConfig->maxMbNum = 16; + pConfig->enableLoopBack = false; + pConfig->enableTimerSync = true; + pConfig->enableSelfWakeup = false; + pConfig->wakeupSrc = kFLEXCAN_WakeupSrcUnfiltered; + pConfig->enableIndividMask = false; + pConfig->disableSelfReception = false; + pConfig->enableListenOnlyMode = false; +#if !(defined(FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT) + pConfig->enableSupervisorMode = true; +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) + pConfig->enableDoze = false; +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) + pConfig->enablePretendedeNetworking = false; +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + pConfig->enableMemoryErrorControl = true; + pConfig->enableNonCorrectableErrorEnterFreeze = true; +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) + pConfig->enableTransceiverDelayMeasure = true; +#endif + + /* Default protocol timing configuration, nominal bit time quantum is 10 (80% SP), data bit time quantum is 5 + * (60%). Suggest use FLEXCAN_CalculateImprovedTimingValues/FLEXCAN_FDCalculateImprovedTimingValues to get the + * improved timing configuration.*/ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + pConfig->timingConfig.phaseSeg1 = 1; + pConfig->timingConfig.phaseSeg2 = 1; + pConfig->timingConfig.propSeg = 4; + pConfig->timingConfig.rJumpwidth = 1; + pConfig->timingConfig.fphaseSeg1 = 1; + pConfig->timingConfig.fphaseSeg2 = 1; + pConfig->timingConfig.fpropSeg = 0; + pConfig->timingConfig.frJumpwidth = 1; +#else + pConfig->timingConfig.phaseSeg1 = 1; + pConfig->timingConfig.phaseSeg2 = 1; + pConfig->timingConfig.propSeg = 4; + pConfig->timingConfig.rJumpwidth = 1; +#endif +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) +/*! + * brief Configures the FlexCAN Pretended Networking mode. + * + * This function configures the FlexCAN Pretended Networking mode with given configuration. + * + * param base FlexCAN peripheral base address. + * param pConfig Pointer to the FlexCAN Rx FIFO configuration structure. + */ +void FLEXCAN_SetPNConfig(CAN_Type *base, const flexcan_pn_config_t *pConfig) +{ + /* Assertion. */ + assert(NULL != pConfig); + assert(0U != pConfig->matchNum); + uint32_t pnctrl; + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + pnctrl = (pConfig->matchNum > 1U) ? CAN_CTRL1_PN_FCS(0x2U | (uint32_t)pConfig->matchSrc) : + CAN_CTRL1_PN_FCS(pConfig->matchSrc); + pnctrl |= (pConfig->enableMatch) ? (CAN_CTRL1_PN_WUMF_MSK_MASK) : 0U; + pnctrl |= (pConfig->enableTimeout) ? (CAN_CTRL1_PN_WTOF_MSK_MASK) : 0U; + pnctrl |= CAN_CTRL1_PN_NMATCH(pConfig->matchNum) | CAN_CTRL1_PN_IDFS(pConfig->idMatchMode) | + CAN_CTRL1_PN_PLFS(pConfig->dataMatchMode); + base->CTRL1_PN = pnctrl; + base->CTRL2_PN = CAN_CTRL2_PN_MATCHTO(pConfig->timeoutValue); + base->FLT_ID1 = pConfig->idLower; + base->FLT_ID2_IDMASK = pConfig->idUpper; + base->FLT_DLC = CAN_FLT_DLC_FLT_DLC_LO(pConfig->lengthLower) | CAN_FLT_DLC_FLT_DLC_HI(pConfig->lengthUpper); + base->PL1_LO = pConfig->lowerWord0; + base->PL1_HI = pConfig->lowerWord1; + base->PL2_PLMASK_LO = pConfig->upperWord0; + base->PL2_PLMASK_HI = pConfig->upperWord1; + + FLEXCAN_ClearStatusFlags(base, (uint64_t)kFLEXCAN_PNMatchIntFlag | (uint64_t)kFLEXCAN_PNTimeoutIntFlag); + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} + +/*! + * brief Reads a FlexCAN Message from Wake Up MB. + * + * This function reads a CAN message from the FlexCAN Wake up Message Buffers. There are four Wake up Message Buffers + * (WMBs) used to store incoming messages in Pretended Networking mode. The WMB index indicates the arrival order. The + * last message is stored in WMB3. + * + * param base FlexCAN peripheral base address. + * param pRxFrame Pointer to CAN message frame structure for reception. + * param mbIdx The FlexCAN Wake up Message Buffer index. Range in 0x0 ~ 0x3. + * retval kStatus_Success - Read Message from Wake up Message Buffer successfully. + * retval kStatus_Fail - Wake up Message Buffer has no valid content. + */ +status_t FLEXCAN_ReadPNWakeUpMB(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame) +{ + /* Assertion. */ + assert(NULL != pRxFrame); + assert(mbIdx <= 0x3U); + + uint32_t cs_temp; + status_t status; + + /* Check if Wake Up MB has valid content. */ + if (CAN_WU_MTC_MCOUNTER(mbIdx) < (base->WU_MTC & CAN_WU_MTC_MCOUNTER_MASK)) + { + /* Read CS field of wake up Message Buffer. */ + cs_temp = base->WMB[mbIdx].CS; + + /* Store Message ID. */ + pRxFrame->id = base->WMB[mbIdx].ID & (CAN_ID_EXT_MASK | CAN_ID_STD_MASK); + + /* Get the message ID and format. */ + pRxFrame->format = (cs_temp & CAN_CS_IDE_MASK) != 0U ? (uint8_t)kFLEXCAN_FrameFormatExtend : + (uint8_t)kFLEXCAN_FrameFormatStandard; + + /* Get the message type. */ + pRxFrame->type = + (cs_temp & CAN_CS_RTR_MASK) != 0U ? (uint8_t)kFLEXCAN_FrameTypeRemote : (uint8_t)kFLEXCAN_FrameTypeData; + + /* Get the message length. */ + pRxFrame->length = (uint8_t)((cs_temp & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT); + + /* Messages received during Pretended Networking mode don't have time stamps, and the respective field in the + WMB structure must be ignored. */ + pRxFrame->timestamp = 0x0; + + /* Store Message Payload. */ + pRxFrame->dataWord0 = base->WMB[mbIdx].D03; + pRxFrame->dataWord1 = base->WMB[mbIdx].D47; + + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + return status; +} +#endif + +/*! + * brief Sets the FlexCAN classical protocol timing characteristic. + * + * This function gives user settings to classical CAN or CAN FD nominal phase timing characteristic. + * The function is for an experienced user. For less experienced users, call the FLEXCAN_GetDefaultConfig() + * and get the default timing characteristicsthe, then call FLEXCAN_Init() and fill the + * bit rate field. + * + * note Calling FLEXCAN_SetTimingConfig() overrides the bit rate set + * in FLEXCAN_Init(). + * + * param base FlexCAN peripheral base address. + * param pConfig Pointer to the timing configuration structure. + */ +void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *pConfig) +{ + /* Assertion. */ + assert(NULL != pConfig); + + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base)) + { +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) + /* Enable extended Bit Timing register ENCBT. */ + base->CTRL2 |= CAN_CTRL2_BTE_MASK; + + /* Updating Timing Setting according to configuration structure. */ + base->EPRS = (base->EPRS & (~CAN_EPRS_ENPRESDIV_MASK)) | CAN_EPRS_ENPRESDIV(pConfig->preDivider); + base->ENCBT = CAN_ENCBT_NRJW(pConfig->rJumpwidth) | + CAN_ENCBT_NTSEG1((uint32_t)pConfig->phaseSeg1 + pConfig->propSeg + 1U) | + CAN_ENCBT_NTSEG2(pConfig->phaseSeg2); +#else + /* On RT106x devices, a single write may be ignored, so it is necessary to read back the register value to + * determine whether the value is written successfully. */ + + do + { + /* Enable Bit Timing register CBT, updating Timing Setting according to configuration structure. */ + base->CBT = CAN_CBT_BTF_MASK | CAN_CBT_EPRESDIV(pConfig->preDivider) | CAN_CBT_ERJW(pConfig->rJumpwidth) | + CAN_CBT_EPSEG1(pConfig->phaseSeg1) | CAN_CBT_EPSEG2(pConfig->phaseSeg2) | + CAN_CBT_EPROPSEG(pConfig->propSeg); + + } while ((CAN_CBT_EPRESDIV(pConfig->preDivider) | CAN_CBT_ERJW(pConfig->rJumpwidth) | + CAN_CBT_EPSEG1(pConfig->phaseSeg1) | CAN_CBT_EPSEG2(pConfig->phaseSeg2) | + CAN_CBT_EPROPSEG(pConfig->propSeg)) != + (base->CBT & (CAN_CBT_EPRESDIV_MASK | CAN_CBT_ERJW_MASK | CAN_CBT_EPSEG1_MASK | CAN_CBT_EPSEG2_MASK | + CAN_CBT_EPROPSEG_MASK))); +#endif + } + else + { + /* Cleaning previous Timing Setting. */ + base->CTRL1 &= ~(CAN_CTRL1_PRESDIV_MASK | CAN_CTRL1_RJW_MASK | CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PSEG2_MASK | + CAN_CTRL1_PROPSEG_MASK); + + /* Updating Timing Setting according to configuration structure. */ + base->CTRL1 |= (CAN_CTRL1_PRESDIV(pConfig->preDivider) | CAN_CTRL1_RJW(pConfig->rJumpwidth) | + CAN_CTRL1_PSEG1(pConfig->phaseSeg1) | CAN_CTRL1_PSEG2(pConfig->phaseSeg2) | + CAN_CTRL1_PROPSEG(pConfig->propSeg)); + } +#else + /* Cleaning previous Timing Setting. */ + base->CTRL1 &= ~(CAN_CTRL1_PRESDIV_MASK | CAN_CTRL1_RJW_MASK | CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PSEG2_MASK | + CAN_CTRL1_PROPSEG_MASK); + + /* Updating Timing Setting according to configuration structure. */ + base->CTRL1 |= (CAN_CTRL1_PRESDIV(pConfig->preDivider) | CAN_CTRL1_RJW(pConfig->rJumpwidth) | + CAN_CTRL1_PSEG1(pConfig->phaseSeg1) | CAN_CTRL1_PSEG2(pConfig->phaseSeg2) | + CAN_CTRL1_PROPSEG(pConfig->propSeg)); +#endif + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Sets the FlexCAN FD data phase timing characteristic. + * + * This function gives user settings to CAN FD data phase timing characteristic. + * The function is for an experienced user. For less experienced users, call the FLEXCAN_GetDefaultConfig() + * and get the default timing characteristicsthe, then call FLEXCAN_FDInit() and fill the + * data phase bit rate field. + * + * note Calling FLEXCAN_SetFDTimingConfig() overrides the bit rate set + * in FLEXCAN_FDInit(). + * + * param base FlexCAN peripheral base address. + * param pConfig Pointer to the timing configuration structure. + */ +void FLEXCAN_SetFDTimingConfig(CAN_Type *base, const flexcan_timing_config_t *pConfig) +{ + /* Assertion. */ + assert(NULL != pConfig); + + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) + /* Enable extended Bit Timing register EDCBT. */ + base->CTRL2 |= CAN_CTRL2_BTE_MASK; + + base->EPRS = (base->EPRS & (~CAN_EPRS_EDPRESDIV_MASK)) | CAN_EPRS_EDPRESDIV(pConfig->fpreDivider); + base->EDCBT = CAN_EDCBT_DRJW(pConfig->frJumpwidth) | CAN_EDCBT_DTSEG2(pConfig->fphaseSeg2) | + CAN_EDCBT_DTSEG1((uint32_t)pConfig->fphaseSeg1 + pConfig->fpropSeg); +#else + /* Enable Bit Timing register FDCBT,*/ + base->CBT |= CAN_CBT_BTF_MASK; + + /* On RT106x devices, a single write may be ignored, so it is necessary to read back the register value to determine + * whether the value is written successfully. */ + do + { + /* Updating Timing Setting according to configuration structure. */ + base->FDCBT = (CAN_FDCBT_FPRESDIV(pConfig->fpreDivider) | CAN_FDCBT_FRJW(pConfig->frJumpwidth) | + CAN_FDCBT_FPSEG1(pConfig->fphaseSeg1) | CAN_FDCBT_FPSEG2(pConfig->fphaseSeg2) | + CAN_FDCBT_FPROPSEG(pConfig->fpropSeg)); + } while ((CAN_FDCBT_FPRESDIV(pConfig->fpreDivider) | CAN_FDCBT_FRJW(pConfig->frJumpwidth) | + CAN_FDCBT_FPSEG1(pConfig->fphaseSeg1) | CAN_FDCBT_FPSEG2(pConfig->fphaseSeg2) | + CAN_FDCBT_FPROPSEG(pConfig->fpropSeg)) != + (base->FDCBT & (CAN_FDCBT_FPRESDIV_MASK | CAN_FDCBT_FRJW_MASK | CAN_FDCBT_FPSEG1_MASK | + CAN_FDCBT_FPSEG2_MASK | CAN_FDCBT_FPROPSEG_MASK))); +#endif + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} +#endif + +/*! + * brief Sets the FlexCAN receive message buffer global mask. + * + * This function sets the global mask for the FlexCAN message buffer in a matching process. + * The configuration is only effective when the Rx individual mask is disabled in the FLEXCAN_Init(). + * + * param base FlexCAN peripheral base address. + * param mask Rx Message Buffer Global Mask value. + */ +void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask) +{ + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + /* Setting Rx Message Buffer Global Mask value. */ + base->RXMGMASK = mask; + base->RX14MASK = mask; + base->RX15MASK = mask; + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} + +/*! + * brief Sets the FlexCAN receive FIFO global mask. + * + * This function sets the global mask for FlexCAN FIFO in a matching process. + * + * param base FlexCAN peripheral base address. + * param mask Rx Fifo Global Mask value. + */ +void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask) +{ + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + /* Setting Rx FIFO Global Mask value. */ + base->RXFGMASK = mask; + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} + +/*! + * brief Sets the FlexCAN receive individual mask. + * + * This function sets the individual mask for the FlexCAN matching process. + * The configuration is only effective when the Rx individual mask is enabled in the FLEXCAN_Init(). + * If the Rx FIFO is disabled, the individual mask is applied to the corresponding Message Buffer. + * If the Rx FIFO is enabled, the individual mask for Rx FIFO occupied Message Buffer is applied to + * the Rx Filter with the same index. Note that only the first 32 + * individual masks can be used as the Rx FIFO filter mask. + * + * param base FlexCAN peripheral base address. + * param maskIdx The Index of individual Mask. + * param mask Rx Individual Mask value. + */ +void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask) +{ + assert(maskIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + /* Setting Rx Individual Mask value. */ + base->RXIMR[maskIdx] = mask; + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} + +/*! + * brief Configures a FlexCAN transmit message buffer. + * + * This function aborts the previous transmission, cleans the Message Buffer, and + * configures it as a Transmit Message Buffer. + * + * param base FlexCAN peripheral base address. + * param mbIdx The Message Buffer index. + * param enable Enable/disable Tx Message Buffer. + * - true: Enable Tx Message Buffer. + * - false: Disable Tx Message Buffer. + */ +void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); +#endif + + /* Inactivate Message Buffer. */ + if (enable) + { + base->MB[mbIdx].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); + } + else + { + base->MB[mbIdx].CS = 0; + } + + /* Clean Message Buffer content. */ + base->MB[mbIdx].ID = 0x0; + base->MB[mbIdx].WORD0 = 0x0; + base->MB[mbIdx].WORD1 = 0x0; +} + +/*! + * brief Calculates the segment values for a single bit time for classical CAN. + * + * This function use to calculates the Classical CAN segment values which will be set in CTRL1/CBT/ENCBT register. + * + * param bitRate The classical CAN bit rate in bps. + * param base FlexCAN peripheral base address. + * param tqNum Number of time quantas per bit, range in 8 ~ 25 when use CTRL1, range in 8 ~ 129 when use CBT, range in + * 8 ~ 385 when use ENCBT. param pTimingConfig Pointer to the FlexCAN timing configuration structure. + */ +static void FLEXCAN_GetSegments(CAN_Type *base, + uint32_t bitRate, + uint32_t tqNum, + flexcan_timing_config_t *pTimingConfig) +{ + uint32_t ideal_sp; + uint32_t seg1Max, proSegMax; + uint32_t seg1Temp; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base)) + { +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) + /* Maximum value allowed in ENCBT register. */ + seg1Max = MAX_NTSEG2 + 1U; + proSegMax = MAX_NTSEG1 - MAX_NTSEG2; +#else + /* Maximum value allowed in CBT register. */ + seg1Max = MAX_EPSEG1 + 1U; + proSegMax = MAX_EPROPSEG + 1U; +#endif + } + else + { + /* Maximum value allowed in CTRL1 register. */ + seg1Max = MAX_PSEG1 + 1U; + proSegMax = MAX_PROPSEG + 1U; + } +#else + /* Maximum value allowed in CTRL1 register. */ + seg1Max = MAX_PSEG1 + 1U; + proSegMax = MAX_PROPSEG + 1U; +#endif + + /* Try to find the ideal sample point, according to CiA 301 doc.*/ + if (bitRate == 1000000U) + { + ideal_sp = IDEAL_SP_LOW; + } + else if (bitRate >= 800000U) + { + ideal_sp = IDEAL_SP_MID; + } + else + { + ideal_sp = IDEAL_SP_HIGH; + } + /* Calculates phaseSeg2. */ + pTimingConfig->phaseSeg2 = (uint8_t)(tqNum - (tqNum * ideal_sp) / (uint32_t)IDEAL_SP_FACTOR); + if (pTimingConfig->phaseSeg2 < MIN_TIME_SEGMENT2) + { + pTimingConfig->phaseSeg2 = MIN_TIME_SEGMENT2; + } + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base)) + { +#if !(defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) + if (pTimingConfig->phaseSeg2 > (uint8_t)(MAX_EPSEG2 + 1U)) + { + pTimingConfig->phaseSeg2 = (uint8_t)(MAX_EPSEG2 + 1U); + } +#endif + } +#endif + + /* Calculates phaseSeg1 and propSeg and try to make phaseSeg1 equal to phaseSeg2. */ + if ((tqNum - pTimingConfig->phaseSeg2 - 1U) > (seg1Max + proSegMax)) + { + seg1Temp = seg1Max + proSegMax; + pTimingConfig->phaseSeg2 = (uint8_t)(tqNum - 1U - seg1Temp); + } + else + { + seg1Temp = tqNum - pTimingConfig->phaseSeg2 - 1U; + } + if (seg1Temp > (pTimingConfig->phaseSeg2 + proSegMax)) + { + pTimingConfig->propSeg = (uint8_t)proSegMax; + pTimingConfig->phaseSeg1 = (uint8_t)(seg1Temp - proSegMax); + } + else + { + pTimingConfig->propSeg = (uint8_t)(seg1Temp - pTimingConfig->phaseSeg2); + pTimingConfig->phaseSeg1 = pTimingConfig->phaseSeg2; + } + + /* rJumpwidth (sjw) is the minimum value of phaseSeg1 and phaseSeg2. */ + pTimingConfig->rJumpwidth = + (pTimingConfig->phaseSeg1 > pTimingConfig->phaseSeg2) ? pTimingConfig->phaseSeg2 : pTimingConfig->phaseSeg1; +#if !(defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (pTimingConfig->rJumpwidth > (MAX_RJW + 1U)) + { + pTimingConfig->rJumpwidth = (uint8_t)(MAX_RJW + 1U); + } +#else + if (0 == FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base)) + { + if (pTimingConfig->rJumpwidth > (MAX_RJW + 1U)) + { + pTimingConfig->rJumpwidth = (uint8_t)(MAX_RJW + 1U); + } + } +#endif + + pTimingConfig->phaseSeg1 -= 1U; + pTimingConfig->phaseSeg2 -= 1U; + pTimingConfig->propSeg -= 1U; + pTimingConfig->rJumpwidth -= 1U; +} + +/*! + * brief Calculates the improved timing values by specific bit Rates for classical CAN. + * + * This function use to calculates the Classical CAN timing values according to the given bit rate. The Calculated + * timing values will be set in CTRL1/CBT/ENCBT register. The calculation is based on the recommendation of the CiA 301 + * v4.2.0 and previous version document. + * + * param base FlexCAN peripheral base address. + * param bitRate The classical CAN speed in bps defined by user, should be less than or equal to 1Mbps. + * param sourceClock_Hz The Source clock frequency in Hz. + * param pTimingConfig Pointer to the FlexCAN timing configuration structure. + * + * return TRUE if timing configuration found, FALSE if failed to find configuration. + */ +bool FLEXCAN_CalculateImprovedTimingValues(CAN_Type *base, + uint32_t bitRate, + uint32_t sourceClock_Hz, + flexcan_timing_config_t *pTimingConfig) +{ + /* Observe bit rate maximums. */ + assert(bitRate <= MAX_CAN_BITRATE); + + uint32_t clk; + uint32_t tqNum, tqMin, pdivMAX; + uint32_t spTemp = 1000U; + flexcan_timing_config_t configTemp = {0}; + bool fgRet = false; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base)) + { +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) + /* Auto Improved Protocal timing for ENCBT. */ + tqNum = ENCBT_MAX_TIME_QUANTA; + tqMin = ENCBT_MIN_TIME_QUANTA; + pdivMAX = MAX_ENPRESDIV; +#else + /* Auto Improved Protocal timing for CBT. */ + tqNum = CBT_MAX_TIME_QUANTA; + tqMin = CBT_MIN_TIME_QUANTA; + pdivMAX = MAX_PRESDIV; +#endif + } + else + { + /* Auto Improved Protocal timing for CTRL1. */ + tqNum = CTRL1_MAX_TIME_QUANTA; + tqMin = CTRL1_MIN_TIME_QUANTA; + pdivMAX = MAX_PRESDIV; + } +#else + /* Auto Improved Protocal timing for CTRL1. */ + tqNum = CTRL1_MAX_TIME_QUANTA; + tqMin = CTRL1_MIN_TIME_QUANTA; + pdivMAX = MAX_PRESDIV; +#endif + do + { + clk = bitRate * tqNum; + if (clk > sourceClock_Hz) + { + continue; /* tqNum too large, clk has been exceed sourceClock_Hz. */ + } + + if ((sourceClock_Hz / clk * clk) != sourceClock_Hz) + { + continue; /* Non-supporting: the frequency of clock source is not divisible by target bit rate, the user + should change a divisible bit rate. */ + } + + configTemp.preDivider = (uint16_t)(sourceClock_Hz / clk) - 1U; + if (configTemp.preDivider > pdivMAX) + { + break; /* The frequency of source clock is too large or the bit rate is too small, the pre-divider could + not handle it. */ + } + + /* Calculates the best timing configuration under current tqNum. */ + FLEXCAN_GetSegments(base, bitRate, tqNum, &configTemp); + /* Determine whether the calculated timing configuration can get the optimal sampling point. */ + if (((((uint32_t)configTemp.phaseSeg2 + 1U) * 1000U) / tqNum) < spTemp) + { + spTemp = (((uint32_t)configTemp.phaseSeg2 + 1U) * 1000U) / tqNum; + pTimingConfig->preDivider = configTemp.preDivider; + pTimingConfig->rJumpwidth = configTemp.rJumpwidth; + pTimingConfig->phaseSeg1 = configTemp.phaseSeg1; + pTimingConfig->phaseSeg2 = configTemp.phaseSeg2; + pTimingConfig->propSeg = configTemp.propSeg; + } + fgRet = true; + } while (--tqNum >= tqMin); + + return fgRet; +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Get Mailbox offset number by dword. + * + * This function gets the offset number of the specified mailbox. + * Mailbox is not consecutive between memory regions when payload is not 8 bytes + * so need to calculate the specified mailbox address. + * For example, in the first memory region, MB[0].CS address is 0x4002_4080. For 32 bytes + * payload frame, the second mailbox is ((1/12)*512 + 1%12*40)/4 = 10, meaning 10 dword + * after the 0x4002_4080, which is actually the address of mailbox MB[1].CS. + * + * param base FlexCAN peripheral base address. + * param mbIdx Mailbox index. + */ +static uint32_t FLEXCAN_GetFDMailboxOffset(CAN_Type *base, uint8_t mbIdx) +{ + uint32_t offset = 0; + uint32_t dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; + if (dataSize == (uint32_t)kFLEXCAN_8BperMB) + { + offset = (((uint32_t)mbIdx / 32U) * 512U + ((uint32_t)mbIdx % 32U) * 16U); + } + else if (dataSize == (uint32_t)kFLEXCAN_16BperMB) + { + offset = (((uint32_t)mbIdx / 21U) * 512U + ((uint32_t)mbIdx % 21U) * 24U); + } + else if (dataSize == (uint32_t)kFLEXCAN_32BperMB) + { + offset = (((uint32_t)mbIdx / 12U) * 512U + ((uint32_t)mbIdx % 12U) * 40U); + } + else + { + offset = (((uint32_t)mbIdx / 7U) * 512U + ((uint32_t)mbIdx % 7U) * 72U); + } + + /* To get the dword aligned offset, need to divide by 4. */ + offset = offset / 4U; + return offset; +} + +/*! + * brief Calculates the segment values for a single bit time for CAN FD data phase. + * + * This function use to calculates the CAN FD data phase segment values which will be set in CFDCBT/EDCBT + * register. + * + * param bitRateFD CAN FD data phase bit rate. + * param tqNum Number of time quanta per bit + * param pTimingConfig Pointer to the FlexCAN timing configuration structure. + */ +static void FLEXCAN_FDGetSegments(uint32_t bitRateFD, uint32_t tqNum, flexcan_timing_config_t *pTimingConfig) +{ + uint32_t ideal_sp; + uint32_t seg1Max, proSegMax, seg2Max; + uint32_t seg1Temp; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) + /* Maximum value allowed in EDCBT register. */ + seg1Max = MAX_DTSEG2 + 1U; + proSegMax = MAX_DTSEG1 - MAX_DTSEG2; + seg2Max = MAX_DTSEG2 + 1U; +#else + /* Maximum value allowed in FDCBT register. */ + seg1Max = MAX_FPSEG1 + 1U; + proSegMax = MAX_FPROPSEG; + seg2Max = MAX_FPSEG2 + 1U; +#endif + + /* According to CiA doc 1301 v1.0.0, which specified data phase sample point postion for CAN FD at 80 MHz. */ + if (bitRateFD <= 1000000U) + { + ideal_sp = IDEAL_DATA_SP_1; + } + else if (bitRateFD <= 2000000U) + { + ideal_sp = IDEAL_DATA_SP_2; + } + else if (bitRateFD <= 4000000U) + { + ideal_sp = IDEAL_DATA_SP_3; + } + else + { + ideal_sp = IDEAL_DATA_SP_4; + } + + /* Calculates fphaseSeg2. */ + pTimingConfig->fphaseSeg2 = (uint8_t)(tqNum - (tqNum * ideal_sp) / (uint32_t)IDEAL_SP_FACTOR); + if (pTimingConfig->fphaseSeg2 < MIN_TIME_SEGMENT2) + { + pTimingConfig->fphaseSeg2 = MIN_TIME_SEGMENT2; + } + else if (pTimingConfig->fphaseSeg2 > seg2Max) + { + pTimingConfig->fphaseSeg2 = (uint8_t)seg2Max; + } + else + { + ; /* Intentional empty */ + } + + /* Calculates fphaseSeg1 and fpropSeg and try to make phaseSeg1 equal to phaseSeg2 */ + if ((tqNum - pTimingConfig->fphaseSeg2 - 1U) > (seg1Max + proSegMax)) + { + seg1Temp = seg1Max + proSegMax; + pTimingConfig->fphaseSeg2 = (uint8_t)(tqNum - 1U - seg1Temp); + } + else + { + seg1Temp = tqNum - pTimingConfig->fphaseSeg2 - 1U; + } + if (seg1Temp > (pTimingConfig->fphaseSeg2 + proSegMax)) + { + pTimingConfig->fpropSeg = (uint8_t)proSegMax; + pTimingConfig->fphaseSeg1 = (uint8_t)(seg1Temp - proSegMax); + } + else if (seg1Temp > pTimingConfig->fphaseSeg2) + { + pTimingConfig->fpropSeg = (uint8_t)(seg1Temp - pTimingConfig->fphaseSeg2); + pTimingConfig->fphaseSeg1 = pTimingConfig->fphaseSeg2; + } + else + { + pTimingConfig->fpropSeg = 0U; + pTimingConfig->fphaseSeg1 = (uint8_t)seg1Temp; + } + + /* rJumpwidth (sjw) is the minimum value of phaseSeg1 and phaseSeg2. */ + pTimingConfig->frJumpwidth = + (pTimingConfig->fphaseSeg1 > pTimingConfig->fphaseSeg2) ? pTimingConfig->fphaseSeg2 : pTimingConfig->fphaseSeg1; + + pTimingConfig->fphaseSeg1 -= 1U; + pTimingConfig->fphaseSeg2 -= 1U; + pTimingConfig->frJumpwidth -= 1U; +} + +/*! + * brief Calculates the improved timing values by specific bit rate for CAN FD nominal phase. + * + * This function use to calculates the CAN FD nominal phase timing values according to the given nominal phase bit rate. + * The Calculated timing values will be set in CBT/ENCBT registers. The calculation is based on the recommendation of + * the CiA 1301 v1.0.0 document. + * + * param bitRate The CAN FD nominal phase speed in bps defined by user, should be less than or equal to 1Mbps. + * param sourceClock_Hz The Source clock frequency in Hz. + * param pTimingConfig Pointer to the FlexCAN timing configuration structure. + * + * return TRUE if timing configuration found, FALSE if failed to find configuration. + */ +static bool FLEXCAN_CalculateImprovedNominalTimingValues(uint32_t bitRate, + uint32_t sourceClock_Hz, + flexcan_timing_config_t *pTimingConfig) +{ + /* Observe bit rate maximums. */ + assert(bitRate <= MAX_CAN_BITRATE); + + uint32_t clk; + uint32_t tqNum, tqMin, pdivMAX, seg1Max, proSegMax, seg1Temp; + uint32_t spTemp = 1000U; + flexcan_timing_config_t configTemp = {0}; + bool fgRet = false; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) + /* Auto Improved Protocal timing for ENCBT. */ + tqNum = ENCBT_MAX_TIME_QUANTA; + tqMin = ENCBT_MIN_TIME_QUANTA; + pdivMAX = MAX_ENPRESDIV; + seg1Max = MAX_NTSEG2 + 1U; + proSegMax = MAX_NTSEG1 - MAX_NTSEG2; +#else + /* Auto Improved Protocal timing for CBT. */ + tqNum = CBT_MAX_TIME_QUANTA; + tqMin = CBT_MIN_TIME_QUANTA; + pdivMAX = MAX_PRESDIV; + seg1Max = MAX_EPSEG1 + 1U; + proSegMax = MAX_EPROPSEG + 1U; +#endif + + do + { + clk = bitRate * tqNum; + if (clk > sourceClock_Hz) + { + continue; /* tqNum too large, clk has been exceed sourceClock_Hz. */ + } + + if ((sourceClock_Hz / clk * clk) != sourceClock_Hz) + { + continue; /* Non-supporting: the frequency of clock source is not divisible by target bit rate, the user + should change a divisible bit rate. */ + } + + configTemp.preDivider = (uint16_t)(sourceClock_Hz / clk) - 1U; + if (configTemp.preDivider > pdivMAX) + { + break; /* The frequency of source clock is too large or the bit rate is too small, the pre-divider could + not handle it. */ + } + + /* Calculates the best timing configuration under current tqNum. */ + configTemp.phaseSeg2 = (uint8_t)(tqNum - (tqNum * IDEAL_NOMINAL_SP) / (uint32_t)IDEAL_SP_FACTOR); + + /* Calculates phaseSeg1 and propSeg and try to make phaseSeg1 equal to phaseSeg2. */ + if ((tqNum - configTemp.phaseSeg2 - 1U) > (seg1Max + proSegMax)) + { + seg1Temp = seg1Max + proSegMax; + configTemp.phaseSeg2 = (uint8_t)(tqNum - 1U - seg1Temp); + } + else + { + seg1Temp = tqNum - configTemp.phaseSeg2 - 1U; + } + if (seg1Temp > (configTemp.phaseSeg2 + proSegMax)) + { + configTemp.propSeg = (uint8_t)proSegMax; + configTemp.phaseSeg1 = (uint8_t)(seg1Temp - proSegMax); + } + else + { + configTemp.propSeg = (uint8_t)(seg1Temp - configTemp.phaseSeg2); + configTemp.phaseSeg1 = configTemp.phaseSeg2; + } + + /* rJumpwidth (sjw) is the minimum value of phaseSeg1 and phaseSeg2. */ + configTemp.rJumpwidth = + (configTemp.phaseSeg1 > configTemp.phaseSeg2) ? configTemp.phaseSeg2 : configTemp.phaseSeg1; + configTemp.phaseSeg1 -= 1U; + configTemp.phaseSeg2 -= 1U; + configTemp.propSeg -= 1U; + configTemp.rJumpwidth -= 1U; + + if (((((uint32_t)configTemp.phaseSeg2 + 1U) * 1000U) / tqNum) < spTemp) + { + spTemp = (((uint32_t)configTemp.phaseSeg2 + 1U) * 1000U) / tqNum; + pTimingConfig->preDivider = configTemp.preDivider; + pTimingConfig->rJumpwidth = configTemp.rJumpwidth; + pTimingConfig->phaseSeg1 = configTemp.phaseSeg1; + pTimingConfig->phaseSeg2 = configTemp.phaseSeg2; + pTimingConfig->propSeg = configTemp.propSeg; + } + fgRet = true; + } while (--tqNum >= tqMin); + + return fgRet; +} + +/*! + * brief Calculates the improved timing values by specific bit rates for CAN FD. + * + * This function use to calculates the CAN FD timing values according to the given nominal phase bit rate and data phase + * bit rate. The Calculated timing values will be set in CBT/ENCBT and FDCBT/EDCBT registers. The calculation is based + * on the recommendation of the CiA 1301 v1.0.0 document. + * + * param bitRate The CAN FD nominal phase speed in bps defined by user. + * param bitRateFD The CAN FD data phase speed in bps defined by user. Equal to bitRate means disable bit rate + * switching. param sourceClock_Hz The Source clock frequency in Hz. param pTimingConfig Pointer to the FlexCAN timing + * configuration structure. + * + * return TRUE if timing configuration found, FALSE if failed to find configuration + */ +bool FLEXCAN_FDCalculateImprovedTimingValues(CAN_Type *base, + uint32_t bitRate, + uint32_t bitRateFD, + uint32_t sourceClock_Hz, + flexcan_timing_config_t *pTimingConfig) +{ + /* Observe bit rate maximums */ + assert(bitRate <= MAX_CANFD_BITRATE); + assert(bitRateFD <= MAX_CANFD_BITRATE); + /* Data phase bit rate need greater or equal to nominal phase bit rate. */ + assert(bitRate <= bitRateFD); + + uint32_t clk; + uint32_t tqMin, pdivMAX, tqTemp; + bool fgRet = false; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) + /* Auto Improved Protocal timing for EDCBT. */ + tqTemp = EDCBT_MAX_TIME_QUANTA; + tqMin = EDCBT_MIN_TIME_QUANTA; + pdivMAX = MAX_EDPRESDIV; +#else + /* Auto Improved Protocal timing for FDCBT. */ + tqTemp = FDCBT_MAX_TIME_QUANTA; + tqMin = FDCBT_MIN_TIME_QUANTA; + pdivMAX = MAX_FPRESDIV; +#endif + + if (bitRate != bitRateFD) + { + /* To minimize errors when processing FD frames, try to get the same bit rate prescaler value for nominal phase + and data phase. */ + do + { + clk = bitRateFD * tqTemp; + if (clk > sourceClock_Hz) + { + continue; /* tqTemp too large, clk x tqTemp has been exceed sourceClock_Hz. */ + } + + if ((sourceClock_Hz / clk * clk) != sourceClock_Hz) + { + continue; /* the frequency of clock source is not divisible by target bit rate. */ + } + + pTimingConfig->fpreDivider = (uint16_t)(sourceClock_Hz / clk) - 1U; + + if (pTimingConfig->fpreDivider > pdivMAX) + { + break; /* The frequency of source clock is too large or the bit rate is too small, the pre-divider + could not handle it. */ + } + + /* Calculates the best data phase timing configuration. */ + FLEXCAN_FDGetSegments(bitRateFD, tqTemp, pTimingConfig); + + if (FLEXCAN_CalculateImprovedNominalTimingValues( + bitRate, sourceClock_Hz / ((uint32_t)pTimingConfig->fpreDivider + 1U), pTimingConfig)) + { + fgRet = true; + if (pTimingConfig->preDivider == 0U) + { + pTimingConfig->preDivider = pTimingConfig->fpreDivider; + break; + } + else + { + pTimingConfig->preDivider = + (pTimingConfig->preDivider + 1U) * (pTimingConfig->fpreDivider + 1U) - 1U; + continue; + } + } + } while (--tqTemp >= tqMin); + } + else + { + if (FLEXCAN_CalculateImprovedNominalTimingValues(bitRate, sourceClock_Hz, pTimingConfig)) + { + /* No need data phase timing configuration, data phase rate equal to nominal phase rate, user don't use Brs + feature. */ + pTimingConfig->fpreDivider = 0U; + pTimingConfig->frJumpwidth = 0U; + pTimingConfig->fphaseSeg1 = 0U; + pTimingConfig->fphaseSeg2 = 0U; + pTimingConfig->fpropSeg = 0U; + fgRet = true; + } + } + return fgRet; +} + +/*! + * brief Configures a FlexCAN transmit message buffer. + * + * This function aborts the previous transmission, cleans the Message Buffer, and + * configures it as a Transmit Message Buffer. + * + * param base FlexCAN peripheral base address. + * param mbIdx The Message Buffer index. + * param enable Enable/disable Tx Message Buffer. + * - true: Enable Tx Message Buffer. + * - false: Disable Tx Message Buffer. + */ +void FLEXCAN_SetFDTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); +#endif + + uint8_t cnt = 0; + uint8_t payload_dword = 1; + uint32_t dataSize; + dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; + volatile uint32_t *mbAddr = &(base->MB[0].CS); + uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) + uint32_t availoffset = FLEXCAN_GetFDMailboxOffset(base, FLEXCAN_GetFirstValidMb(base)); +#endif + + /* Inactivate Message Buffer. */ + if (enable) + { + /* Inactivate by writing CS. */ + mbAddr[offset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive); + } + else + { + mbAddr[offset] = 0x0; + } + + /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64 + Bytes payload. */ + for (cnt = 0; cnt < (dataSize + 1U); cnt++) + { + payload_dword *= 2U; + } + + /* Clean ID. */ + mbAddr[offset + 1U] = 0x0U; + /* Clean Message Buffer content, DWORD by DWORD. */ + for (cnt = 0; cnt < payload_dword; cnt++) + { + mbAddr[offset + 2U + cnt] = 0x0U; + } + +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) + mbAddr[availoffset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive); +#endif +} +#endif /* FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE */ + +/*! + * brief Configures a FlexCAN Receive Message Buffer. + * + * This function cleans a FlexCAN build-in Message Buffer and configures it + * as a Receive Message Buffer. + * + * param base FlexCAN peripheral base address. + * param mbIdx The Message Buffer index. + * param pRxMbConfig Pointer to the FlexCAN Message Buffer configuration structure. + * param enable Enable/disable Rx Message Buffer. + * - true: Enable Rx Message Buffer. + * - false: Disable Rx Message Buffer. + */ +void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *pRxMbConfig, bool enable) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(((NULL != pRxMbConfig) || (false == enable))); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); +#endif + + uint32_t cs_temp = 0; + + /* Inactivate Message Buffer. */ + base->MB[mbIdx].CS = 0; + + /* Clean Message Buffer content. */ + base->MB[mbIdx].ID = 0x0; + base->MB[mbIdx].WORD0 = 0x0; + base->MB[mbIdx].WORD1 = 0x0; + + if (enable) + { + /* Setup Message Buffer ID. */ + base->MB[mbIdx].ID = pRxMbConfig->id; + + /* Setup Message Buffer format. */ + if (kFLEXCAN_FrameFormatExtend == pRxMbConfig->format) + { + cs_temp |= CAN_CS_IDE_MASK; + } + + /* Setup Message Buffer type. */ + if (kFLEXCAN_FrameTypeRemote == pRxMbConfig->type) + { + cs_temp |= CAN_CS_RTR_MASK; + } + + /* Activate Rx Message Buffer. */ + cs_temp |= CAN_CS_CODE(kFLEXCAN_RxMbEmpty); + base->MB[mbIdx].CS = cs_temp; + } +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Configures a FlexCAN Receive Message Buffer. + * + * This function cleans a FlexCAN build-in Message Buffer and configures it + * as a Receive Message Buffer. + * + * param base FlexCAN peripheral base address. + * param mbIdx The Message Buffer index. + * param pRxMbConfig Pointer to the FlexCAN Message Buffer configuration structure. + * param enable Enable/disable Rx Message Buffer. + * - true: Enable Rx Message Buffer. + * - false: Disable Rx Message Buffer. + */ +void FLEXCAN_SetFDRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *pRxMbConfig, bool enable) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(((NULL != pRxMbConfig) || (false == enable))); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); +#endif + + uint32_t cs_temp = 0; + uint8_t cnt = 0; + volatile uint32_t *mbAddr = &(base->MB[0].CS); + uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); + uint8_t payload_dword; + uint32_t dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; + + /* Inactivate Message Buffer. */ + mbAddr[offset] = 0U; + + /* Clean Message Buffer content. */ + mbAddr[offset + 1U] = 0U; + /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64 + Bytes payload. */ + payload_dword = (2U << dataSize); + for (cnt = 0; cnt < payload_dword; cnt++) + { + mbAddr[offset + 2U + cnt] = 0x0; + } + + if (enable) + { + /* Setup Message Buffer ID. */ + mbAddr[offset + 1U] = pRxMbConfig->id; + + /* Setup Message Buffer format. */ + if (kFLEXCAN_FrameFormatExtend == pRxMbConfig->format) + { + cs_temp |= CAN_CS_IDE_MASK; + } + + /* Setup Message Buffer type. */ + if (kFLEXCAN_FrameTypeRemote == pRxMbConfig->type) + { + cs_temp |= CAN_CS_RTR_MASK; + } + + /* Activate Rx Message Buffer. */ + cs_temp |= CAN_CS_CODE(kFLEXCAN_RxMbEmpty); + mbAddr[offset] = cs_temp; + } +} +#endif + +/*! + * brief Configures the FlexCAN Legacy Rx FIFO. + * + * This function configures the FlexCAN Rx FIFO with given configuration. + * note Legacy Rx FIFO only can receive classic CAN message. + * + * param base FlexCAN peripheral base address. + * param pRxFifoConfig Pointer to the FlexCAN Legacy Rx FIFO configuration structure. Can be NULL when enable parameter + * is false. + * param enable Enable/disable Legacy Rx FIFO. + * - true: Enable Legacy Rx FIFO. + * - false: Disable Legacy Rx FIFO. + */ +void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *pRxFifoConfig, bool enable) +{ + /* Assertion. */ + assert((NULL != pRxFifoConfig) || (false == enable)); + + volatile uint32_t *mbAddr; + uint8_t i, j, k, rffn = 0, numMbOccupy; + uint32_t setup_mb = 0; + + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + if (enable) + { + assert(pRxFifoConfig->idFilterNum <= 128U); +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + /* Legacy Rx FIFO and Enhanced Rx FIFO cannot be enabled at the same time. */ + assert((base->ERFCR & CAN_ERFCR_ERFEN_MASK) == 0U); +#endif + + /* Get the setup_mb value. */ + setup_mb = (uint8_t)((base->MCR & CAN_MCR_MAXMB_MASK) >> CAN_MCR_MAXMB_SHIFT); + setup_mb = (setup_mb < (uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base)) ? + setup_mb : + (uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); + + /* Determine RFFN value. */ + for (i = 0; i <= 0xFU; i++) + { + if ((8U * (i + 1U)) >= pRxFifoConfig->idFilterNum) + { + rffn = i; + assert(((setup_mb - 8U) - (2U * rffn)) > 0U); + + base->CTRL2 = (base->CTRL2 & ~CAN_CTRL2_RFFN_MASK) | CAN_CTRL2_RFFN(rffn); + break; + } + } + + /* caculate the Number of Mailboxes occupied by RX Legacy FIFO and the filter. */ + numMbOccupy = 6U + (rffn + 1U) * 2U; + + /* Copy ID filter table to Message Buffer Region (Fix MISRA_C-2012 Rule 18.1). */ + j = 0U; + for (i = 6U; i < numMbOccupy; i++) + { + /* Get address for current mail box. */ + mbAddr = &(base->MB[i].CS); + + /* One Mail box contain 4U DWORD registers. */ + for (k = 0; k < 4U; k++) + { + /* Fill all valid filter in the mail box occupied by filter. + * Disable unused Rx FIFO Filter, the other rest of register in the last Mail box occupied by fiter set + * as 0xffffffff. + */ + mbAddr[k] = (j < pRxFifoConfig->idFilterNum) ? (pRxFifoConfig->idFilterTable[j]) : 0xFFFFFFFFU; + + /* Try to fill next filter in current Mail Box. */ + j++; + } + } + + /* Setup ID Fitlter Type. */ + switch (pRxFifoConfig->idFilterType) + { + case kFLEXCAN_RxFifoFilterTypeA: + base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x0); + break; + case kFLEXCAN_RxFifoFilterTypeB: + base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x1); + break; + case kFLEXCAN_RxFifoFilterTypeC: + base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x2); + break; + case kFLEXCAN_RxFifoFilterTypeD: + /* All frames rejected. */ + base->MCR = (base->MCR & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0x3); + break; + default: + /* All the cases have been listed above, the default clause should not be reached. */ + assert(false); + break; + } + + /* Setting Message Reception Priority. */ + base->CTRL2 = (pRxFifoConfig->priority == kFLEXCAN_RxFifoPrioHigh) ? (base->CTRL2 & ~CAN_CTRL2_MRP_MASK) : + (base->CTRL2 | CAN_CTRL2_MRP_MASK); + + /* Enable Rx Message FIFO. */ + base->MCR |= CAN_MCR_RFEN_MASK; + } + else + { + rffn = (uint8_t)((base->CTRL2 & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT); + /* caculate the Number of Mailboxes occupied by RX Legacy FIFO and the filter. */ + numMbOccupy = 6U + (rffn + 1U) * 2U; + + /* Disable Rx Message FIFO. */ + base->MCR &= ~CAN_MCR_RFEN_MASK; + + /* Clean MB0 ~ MB5 and all MB occupied by ID filters (Fix MISRA_C-2012 Rule 18.1). */ + + for (i = 0; i < numMbOccupy; i++) + { + FLEXCAN_SetRxMbConfig(base, i, NULL, false); + } + } + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * brief Configures the FlexCAN Enhanced Rx FIFO. + * + * This function configures the Enhanced Rx FIFO with given configuration. + * note Enhanced Rx FIFO support receive classic CAN or CAN FD messages, Legacy Rx FIFO and Enhanced Rx FIFO + * cannot be enabled at the same time. + * + * param base FlexCAN peripheral base address. + * param pConfig Pointer to the FlexCAN Enhanced Rx FIFO configuration structure. Can be NULL when enable parameter + * is false. + * param enable Enable/disable Enhanced Rx FIFO. + * - true: Enable Enhanced Rx FIFO. + * - false: Disable Enhanced Rx FIFO. + */ +void FLEXCAN_SetEnhancedRxFifoConfig(CAN_Type *base, const flexcan_enhanced_rx_fifo_config_t *pConfig, bool enable) +{ + /* Assertion. */ + assert((NULL != pConfig) || (false == enable)); + uint32_t i; + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + if (enable) + { + /* Each pair of filter elements occupies 2 words and can consist of one extended ID filter element or two + * standard ID filter elements. */ + assert((((uint32_t)pConfig->idFilterPairNum * 2UL) < + (uint32_t)FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER) && + (pConfig->extendIdFilterNum <= pConfig->idFilterPairNum) && (0UL != pConfig->idFilterPairNum)); + + /* The Enhanced Rx FIFO Watermark cannot be greater than the enhanced Rx FIFO size. */ + assert(pConfig->fifoWatermark < (uint32_t)FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_SIZE); + + /* Legacy Rx FIFO and Enhanced Rx FIFO cannot be enabled at the same time. */ + assert((base->MCR & CAN_MCR_RFEN_MASK) == 0U); + + /* Reset Enhanced Rx FIFO engine and clear flags. */ + base->ERFSR |= CAN_ERFSR_ERFCLR_MASK | CAN_ERFSR_ERFUFW_MASK | CAN_ERFSR_ERFOVF_MASK | CAN_ERFSR_ERFWMI_MASK | + CAN_ERFSR_ERFDA_MASK; + /* Setting Enhanced Rx FIFO. */ + base->ERFCR = CAN_ERFCR_DMALW(pConfig->dmaPerReadLength) | CAN_ERFCR_NEXIF(pConfig->extendIdFilterNum) | + CAN_ERFCR_NFE((uint32_t)pConfig->idFilterPairNum - 1UL) | CAN_ERFCR_ERFWM(pConfig->fifoWatermark); + /* Copy ID filter table to Enhanced Rx FIFO Filter Element registers. */ + for (i = 0; i < (uint32_t)FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER; i++) + { + base->ERFFEL[i] = (i < ((uint32_t)pConfig->idFilterPairNum * 2U)) ? pConfig->idFilterTable[i] : 0xFFFFFFFFU; + } + + /* Setting Message Reception Priority. */ + base->CTRL2 = (pConfig->priority == kFLEXCAN_RxFifoPrioHigh) ? (base->CTRL2 & ~CAN_CTRL2_MRP_MASK) : + (base->CTRL2 | CAN_CTRL2_MRP_MASK); + /* Enable Enhanced Rx FIFO. */ + base->ERFCR |= CAN_ERFCR_ERFEN_MASK; + } + else + { + /* Disable Enhanced Rx FIFO. */ + base->ERFCR = 0U; + /* Reset Enhanced Rx FIFO engine and clear flags. */ + base->ERFSR |= CAN_ERFSR_ERFCLR_MASK | CAN_ERFSR_ERFUFW_MASK | CAN_ERFSR_ERFOVF_MASK | CAN_ERFSR_ERFWMI_MASK | + CAN_ERFSR_ERFDA_MASK; + /* Clean all Enhanced Rx FIFO Filter Element registers. */ + for (i = 0; i < (uint32_t)FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER; i++) + { + base->ERFFEL[i] = 0xFFFFFFFFU; + } + } + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); +} +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) && FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) +/*! + * brief Enables or disables the FlexCAN Legacy/Enhanced Rx FIFO DMA request. + * + * This function enables or disables the DMA feature of FlexCAN build-in Rx FIFO. + * + * param base FlexCAN peripheral base address. + * param enable true to enable, false to disable. + */ +void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable) +{ + if (enable) + { + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + /* Enable FlexCAN DMA. */ + base->MCR |= CAN_MCR_DMA_MASK; + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); + } + else + { + /* Enter Freeze Mode. */ + FLEXCAN_EnterFreezeMode(base); + + /* Disable FlexCAN DMA. */ + base->MCR &= ~CAN_MCR_DMA_MASK; + + /* Exit Freeze Mode. */ + FLEXCAN_ExitFreezeMode(base); + } +} +#endif /* FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA */ + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) +/*! + * brief Gets the FlexCAN Memory Error Report registers status. + * + * This function gets the FlexCAN Memory Error Report registers status. + * + * param base FlexCAN peripheral base address. + * param errorStatus Pointer to FlexCAN Memory Error Report registers status structure. + */ +void FLEXCAN_GetMemoryErrorReportStatus(CAN_Type *base, flexcan_memory_error_report_status_t *errorStatus) +{ + uint32_t temp; + /* Disable updates of the error report registers. */ + base->MECR |= CAN_MECR_RERRDIS_MASK; + + errorStatus->accessAddress = (uint16_t)(base->RERRAR & CAN_RERRAR_ERRADDR_MASK); + errorStatus->errorData = base->RERRDR; + errorStatus->errorType = + (base->RERRAR & CAN_RERRAR_NCE_MASK) == 0U ? kFLEXCAN_CorrectableError : kFLEXCAN_NonCorrectableError; + + temp = (base->RERRAR & CAN_RERRAR_SAID_MASK) >> CAN_RERRAR_SAID_SHIFT; + switch (temp) + { + case (uint32_t)kFLEXCAN_MoveOutFlexCanAccess: + case (uint32_t)kFLEXCAN_MoveInAccess: + case (uint32_t)kFLEXCAN_TxArbitrationAccess: + case (uint32_t)kFLEXCAN_RxMatchingAccess: + case (uint32_t)kFLEXCAN_MoveOutHostAccess: + errorStatus->accessType = (flexcan_memory_access_type_t)temp; + break; + default: + assert(false); + break; + } + + for (uint32_t i = 0; i < 4U; i++) + { + temp = (base->RERRSYNR & ((uint32_t)CAN_RERRSYNR_SYND0_MASK << (i * 8U))) >> (i * 8U); + errorStatus->byteStatus[i].byteIsRead = (base->RERRSYNR & ((uint32_t)CAN_RERRSYNR_BE0_MASK << (i * 8U))) != 0U; + switch (temp) + { + case CAN_RERRSYNR_SYND0(kFLEXCAN_NoError): + case CAN_RERRSYNR_SYND0(kFLEXCAN_ParityBits0Error): + case CAN_RERRSYNR_SYND0(kFLEXCAN_ParityBits1Error): + case CAN_RERRSYNR_SYND0(kFLEXCAN_ParityBits2Error): + case CAN_RERRSYNR_SYND0(kFLEXCAN_ParityBits3Error): + case CAN_RERRSYNR_SYND0(kFLEXCAN_ParityBits4Error): + case CAN_RERRSYNR_SYND0(kFLEXCAN_DataBits0Error): + case CAN_RERRSYNR_SYND0(kFLEXCAN_DataBits1Error): + case CAN_RERRSYNR_SYND0(kFLEXCAN_DataBits2Error): + case CAN_RERRSYNR_SYND0(kFLEXCAN_DataBits3Error): + case CAN_RERRSYNR_SYND0(kFLEXCAN_DataBits4Error): + case CAN_RERRSYNR_SYND0(kFLEXCAN_DataBits5Error): + case CAN_RERRSYNR_SYND0(kFLEXCAN_DataBits6Error): + case CAN_RERRSYNR_SYND0(kFLEXCAN_DataBits7Error): + case CAN_RERRSYNR_SYND0(kFLEXCAN_AllZeroError): + case CAN_RERRSYNR_SYND0(kFLEXCAN_AllOneError): + errorStatus->byteStatus[i].bitAffected = (flexcan_byte_error_syndrome_t)temp; + break; + default: + errorStatus->byteStatus[i].bitAffected = kFLEXCAN_NonCorrectableErrors; + break; + } + } + + /* Re-enable updates of the error report registers. */ + base->MECR &= CAN_MECR_RERRDIS_MASK; +} +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) +/*! + * FlexCAN: A frame with wrong ID or payload is transmitted into + * the CAN bus when the Message Buffer under transmission is + * either aborted or deactivated while the CAN bus is in the Bus Idle state + * + * This function to do workaround for ERR006032 + * + * param base FlexCAN peripheral base address. + * param mbIdx The FlexCAN Message Buffer index. + */ +static void FLEXCAN_ERRATA_6032(CAN_Type *base, volatile uint32_t *mbCSAddr) +{ + uint32_t dbg_temp = 0U; + uint32_t u32TempCS = 0U; + uint32_t u32Timeout = DELAY_BUSIDLE; + /*disable ALL interrupts to prevent any context switching*/ + uint32_t irqMask = DisableGlobalIRQ(); + dbg_temp = (uint32_t)(base->DBG1); + switch (dbg_temp & CAN_DBG1_CFSM_MASK) + { + case RXINTERMISSION: + if (CBN_VALUE3 == (dbg_temp & CAN_DBG1_CBN_MASK)) + { + /*wait until CFSM is different from RXINTERMISSION */ + while (RXINTERMISSION == (base->DBG1 & CAN_DBG1_CFSM_MASK)) + { + __NOP(); + } + } + break; + case TXINTERMISSION: + if (CBN_VALUE3 == (dbg_temp & CAN_DBG1_CBN_MASK)) + { + /*wait until CFSM is different from TXINTERMISSION*/ + while (TXINTERMISSION == (base->DBG1 & CAN_DBG1_CFSM_MASK)) + { + __NOP(); + } + } + break; + default: + /* To avoid MISRA-C 2012 rule 16.4 issue. */ + break; + } + /*Anyway, BUSIDLE need to delay*/ + if (BUSIDLE == (base->DBG1 & CAN_DBG1_CFSM_MASK)) + { + while (u32Timeout-- > 0U) + { + __NOP(); + } + + /*Write 0x0 into Code field of CS word.*/ + u32TempCS = (uint32_t)(*mbCSAddr); + u32TempCS &= ~CAN_CS_CODE_MASK; + *mbCSAddr = u32TempCS; + } + /*restore interruption*/ + EnableGlobalIRQ(irqMask); +} +#endif + +/*! + * brief Writes a FlexCAN Message to the Transmit Message Buffer. + * + * This function writes a CAN Message to the specified Transmit Message Buffer + * and changes the Message Buffer state to start CAN Message transmit. After + * that the function returns immediately. + * + * param base FlexCAN peripheral base address. + * param mbIdx The FlexCAN Message Buffer index. + * param pTxFrame Pointer to CAN message frame to be sent. + * retval kStatus_Success - Write Tx Message Buffer Successfully. + * retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t *pTxFrame) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(NULL != pTxFrame); + assert(pTxFrame->length <= 8U); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); +#endif + + uint32_t cs_temp = 0; + status_t status; + + /* Check if Message Buffer is available. */ + if (CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) != (base->MB[mbIdx].CS & CAN_CS_CODE_MASK)) + { +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) + FLEXCAN_ERRATA_6032(base, &(base->MB[mbIdx].CS)); +#endif + /* Inactive Tx Message Buffer. */ + base->MB[mbIdx].CS = (base->MB[mbIdx].CS & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive); + + /* Fill Message ID field. */ + base->MB[mbIdx].ID = pTxFrame->id; + + /* Fill Message Format field. */ + if ((uint32_t)kFLEXCAN_FrameFormatExtend == pTxFrame->format) + { + cs_temp |= CAN_CS_SRR_MASK | CAN_CS_IDE_MASK; + } + + /* Fill Message Type field. */ + if ((uint32_t)kFLEXCAN_FrameTypeRemote == pTxFrame->type) + { + cs_temp |= CAN_CS_RTR_MASK; + } + + cs_temp |= CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) | CAN_CS_DLC(pTxFrame->length); + + /* Load Message Payload. */ + base->MB[mbIdx].WORD0 = pTxFrame->dataWord0; + base->MB[mbIdx].WORD1 = pTxFrame->dataWord1; + + /* Activate Tx Message Buffer. */ + base->MB[mbIdx].CS = cs_temp; + +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) + base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); + base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive); +#endif + + status = kStatus_Success; + } + else + { + /* Tx Message Buffer is activated, return immediately. */ + status = kStatus_Fail; + } + + return status; +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Writes a FlexCAN FD Message to the Transmit Message Buffer. + * + * This function writes a CAN FD Message to the specified Transmit Message Buffer + * and changes the Message Buffer state to start CAN FD Message transmit. After + * that the function returns immediately. + * + * param base FlexCAN peripheral base address. + * param mbIdx The FlexCAN FD Message Buffer index. + * param pTxFrame Pointer to CAN FD message frame to be sent. + * retval kStatus_Success - Write Tx Message Buffer Successfully. + * retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_frame_t *pTxFrame) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(NULL != pTxFrame); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); +#endif + + status_t status; + uint32_t cs_temp = 0; + uint8_t cnt = 0; + uint32_t can_cs = 0; + uint8_t payload_dword = 1; + uint32_t dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) + uint32_t availoffset = FLEXCAN_GetFDMailboxOffset(base, FLEXCAN_GetFirstValidMb(base)); +#endif + volatile uint32_t *mbAddr = &(base->MB[0].CS); + uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); + + can_cs = mbAddr[offset]; + /* Check if Message Buffer is available. */ + if (CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) != (can_cs & CAN_CS_CODE_MASK)) + { +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032) + FLEXCAN_ERRATA_6032(base, &(mbAddr[offset])); +#endif + /* Inactive Tx Message Buffer and Fill Message ID field. */ + mbAddr[offset] = (can_cs & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive); + mbAddr[offset + 1U] = pTxFrame->id; + + /* Fill Message Format field. */ + if ((uint32_t)kFLEXCAN_FrameFormatExtend == pTxFrame->format) + { + cs_temp |= CAN_CS_SRR_MASK | CAN_CS_IDE_MASK; + } + + /* Fill Message Type field. */ + if ((uint32_t)kFLEXCAN_FrameTypeRemote == pTxFrame->type) + { + cs_temp |= CAN_CS_RTR_MASK; + } + + cs_temp |= CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) | CAN_CS_DLC(pTxFrame->length) | CAN_CS_EDL(1) | + CAN_CS_BRS(pTxFrame->brs); + + /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64 + Bytes payload. */ + for (cnt = 0; cnt < (dataSize + 1U); cnt++) + { + payload_dword *= 2U; + } + + /* Load Message Payload and Activate Tx Message Buffer. */ + for (cnt = 0; cnt < payload_dword; cnt++) + { + mbAddr[offset + 2U + cnt] = pTxFrame->dataWord[cnt]; + } + mbAddr[offset] = cs_temp; + +#if ((defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829)) + mbAddr[availoffset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive); + mbAddr[availoffset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive); +#endif + + status = kStatus_Success; + } + else + { + /* Tx Message Buffer is activated, return immediately. */ + status = kStatus_Fail; + } + + return status; +} +#endif + +/*! + * brief Reads a FlexCAN Message from Receive Message Buffer. + * + * This function reads a CAN message from a specified Receive Message Buffer. + * The function fills a receive CAN message frame structure with + * just received data and activates the Message Buffer again. + * The function returns immediately. + * + * param base FlexCAN peripheral base address. + * param mbIdx The FlexCAN Message Buffer index. + * param pRxFrame Pointer to CAN message frame structure for reception. + * retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * retval kStatus_Fail - Rx Message Buffer is empty. + */ +status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(NULL != pRxFrame); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); +#endif + + uint32_t cs_temp; + uint32_t rx_code; + status_t status; + + /* Read CS field of Rx Message Buffer to lock Message Buffer. */ + cs_temp = base->MB[mbIdx].CS; + /* Get Rx Message Buffer Code field. */ + rx_code = (cs_temp & CAN_CS_CODE_MASK) >> CAN_CS_CODE_SHIFT; + + /* Check to see if Rx Message Buffer is full. */ + if (((uint32_t)kFLEXCAN_RxMbFull == rx_code) || ((uint32_t)kFLEXCAN_RxMbOverrun == rx_code)) + { + /* Store Message ID. */ + pRxFrame->id = base->MB[mbIdx].ID & (CAN_ID_EXT_MASK | CAN_ID_STD_MASK); + + /* Get the message ID and format. */ + pRxFrame->format = (cs_temp & CAN_CS_IDE_MASK) != 0U ? (uint8_t)kFLEXCAN_FrameFormatExtend : + (uint8_t)kFLEXCAN_FrameFormatStandard; + + /* Get the message type. */ + pRxFrame->type = + (cs_temp & CAN_CS_RTR_MASK) != 0U ? (uint8_t)kFLEXCAN_FrameTypeRemote : (uint8_t)kFLEXCAN_FrameTypeData; + + /* Get the message length. */ + pRxFrame->length = (uint8_t)((cs_temp & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT); + + /* Get the time stamp. */ + pRxFrame->timestamp = (uint16_t)((cs_temp & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT); + + /* Store Message Payload. */ + pRxFrame->dataWord0 = base->MB[mbIdx].WORD0; + pRxFrame->dataWord1 = base->MB[mbIdx].WORD1; + + /* Read free-running timer to unlock Rx Message Buffer. */ + (void)base->TIMER; + + if ((uint32_t)kFLEXCAN_RxMbFull == rx_code) + { + status = kStatus_Success; + } + else + { + status = kStatus_FLEXCAN_RxOverflow; + } + } + else + { + /* Read free-running timer to unlock Rx Message Buffer. */ + (void)base->TIMER; + + status = kStatus_Fail; + } + + return status; +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Reads a FlexCAN FD Message from Receive Message Buffer. + * + * This function reads a CAN FD message from a specified Receive Message Buffer. + * The function fills a receive CAN FD message frame structure with + * just received data and activates the Message Buffer again. + * The function returns immediately. + * + * param base FlexCAN peripheral base address. + * param mbIdx The FlexCAN FD Message Buffer index. + * param pRxFrame Pointer to CAN FD message frame structure for reception. + * retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * retval kStatus_Fail - Rx Message Buffer is empty. + */ +status_t FLEXCAN_ReadFDRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pRxFrame) +{ + /* Assertion. */ + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); + assert(NULL != pRxFrame); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); +#endif + + status_t status; + uint32_t cs_temp; + uint8_t rx_code; + uint8_t cnt = 0; + uint32_t can_id = 0; + uint32_t dataSize; + dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT; + uint8_t payload_dword = 1; + volatile uint32_t *mbAddr = &(base->MB[0].CS); + uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); + + /* Read CS field of Rx Message Buffer to lock Message Buffer. */ + cs_temp = mbAddr[offset]; + can_id = mbAddr[offset + 1U]; + + /* Get Rx Message Buffer Code field. */ + rx_code = (uint8_t)((cs_temp & CAN_CS_CODE_MASK) >> CAN_CS_CODE_SHIFT); + + /* Check to see if Rx Message Buffer is full. */ + if (((uint8_t)kFLEXCAN_RxMbFull == rx_code) || ((uint8_t)kFLEXCAN_RxMbOverrun == rx_code)) + { + /* Store Message ID. */ + pRxFrame->id = can_id & (CAN_ID_EXT_MASK | CAN_ID_STD_MASK); + + /* Get the message ID and format. */ + pRxFrame->format = (cs_temp & CAN_CS_IDE_MASK) != 0U ? (uint8_t)kFLEXCAN_FrameFormatExtend : + (uint8_t)kFLEXCAN_FrameFormatStandard; + + /* Get the message type. */ + pRxFrame->type = + (cs_temp & CAN_CS_RTR_MASK) != 0U ? (uint8_t)kFLEXCAN_FrameTypeRemote : (uint8_t)kFLEXCAN_FrameTypeData; + + /* Get the message length. */ + pRxFrame->length = (uint8_t)((cs_temp & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT); + + /* Get the time stamp. */ + pRxFrame->timestamp = (uint16_t)((cs_temp & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT); + + /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64 + Bytes payload. */ + for (cnt = 0; cnt < (dataSize + 1U); cnt++) + { + payload_dword *= 2U; + } + + /* Store Message Payload. */ + for (cnt = 0; cnt < payload_dword; cnt++) + { + pRxFrame->dataWord[cnt] = mbAddr[offset + 2U + cnt]; + } + + /* Read free-running timer to unlock Rx Message Buffer. */ + (void)base->TIMER; + + if ((uint32_t)kFLEXCAN_RxMbFull == rx_code) + { + status = kStatus_Success; + } + else + { + status = kStatus_FLEXCAN_RxOverflow; + } + } + else + { + /* Read free-running timer to unlock Rx Message Buffer. */ + (void)base->TIMER; + + status = kStatus_Fail; + } + + return status; +} +#endif + +/*! + * brief Reads a FlexCAN Message from Legacy Rx FIFO. + * + * This function reads a CAN message from the FlexCAN Legacy Rx FIFO. + * + * param base FlexCAN peripheral base address. + * param pRxFrame Pointer to CAN message frame structure for reception. + * retval kStatus_Success - Read Message from Rx FIFO successfully. + * retval kStatus_Fail - Rx FIFO is not enabled. + */ +status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *pRxFrame) +{ + /* Assertion. */ + assert(NULL != pRxFrame); + + uint32_t cs_temp; + status_t status; + + /* Check if Legacy Rx FIFO is Enabled. */ + if (0U != (base->MCR & CAN_MCR_RFEN_MASK)) + { + /* Read CS field of Rx Message Buffer to lock Message Buffer. */ + cs_temp = base->MB[0].CS; + + /* Read data from Rx FIFO output port. */ + /* Store Message ID. */ + pRxFrame->id = base->MB[0].ID & (CAN_ID_EXT_MASK | CAN_ID_STD_MASK); + + /* Get the message ID and format. */ + pRxFrame->format = (cs_temp & CAN_CS_IDE_MASK) != 0U ? (uint8_t)kFLEXCAN_FrameFormatExtend : + (uint8_t)kFLEXCAN_FrameFormatStandard; + + /* Get the message type. */ + pRxFrame->type = + (cs_temp & CAN_CS_RTR_MASK) != 0U ? (uint8_t)kFLEXCAN_FrameTypeRemote : (uint8_t)kFLEXCAN_FrameTypeData; + + /* Get the message length. */ + pRxFrame->length = (uint8_t)((cs_temp & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT); + + /* Get the time stamp. */ + pRxFrame->timestamp = (uint16_t)((cs_temp & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT); + + /* Store Message Payload. */ + pRxFrame->dataWord0 = base->MB[0].WORD0; + pRxFrame->dataWord1 = base->MB[0].WORD1; + + /* Store ID Filter Hit Index. */ + pRxFrame->idhit = (uint16_t)(base->RXFIR & CAN_RXFIR_IDHIT_MASK); + + /* Read free-running timer to unlock Rx Message Buffer. */ + (void)base->TIMER; + + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + return status; +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * brief Reads a FlexCAN Message from Enhanced Rx FIFO. + * + * This function reads a CAN or CAN FD message from the FlexCAN Enhanced Rx FIFO. + * + * param base FlexCAN peripheral base address. + * param pRxFrame Pointer to CAN FD message frame structure for reception. + * retval kStatus_Success - Read Message from Rx FIFO successfully. + * retval kStatus_Fail - Rx FIFO is not enabled. + */ +status_t FLEXCAN_ReadEnhancedRxFifo(CAN_Type *base, flexcan_fd_frame_t *pRxFrame) +{ + /* Assertion. */ + assert(NULL != pRxFrame); + + status_t status; + uint32_t idHitOff; + + /* Check if Enhanced Rx FIFO is Enabled. */ + if (0U != (base->ERFCR & CAN_ERFCR_ERFEN_MASK)) + { + /* Enhanced Rx FIFO ID HIT offset is changed dynamically according to data length code (DLC) . */ + idHitOff = (DLC_LENGTH_DECODE(((flexcan_fd_frame_t *)E_RX_FIFO(base))->length) + 3U) / 4U + 3U; + /* Copy CAN FD Message from Enhanced Rx FIFO, should use the DLC value to identify the bytes that belong to the + * message which is being read. */ + (void)memcpy((void *)pRxFrame, (void *)(uint32_t *)E_RX_FIFO(base), sizeof(uint32_t) * idHitOff); + pRxFrame->idhit = pRxFrame->dataWord[idHitOff - 3U]; + /* Clear the unused frame data. */ + for (uint32_t i = (idHitOff - 3U); i < 16U; i++) + { + pRxFrame->dataWord[i] = 0x0; + } + + /* Clear data available flag to let FlexCAN know one frame has been read from the Enhanced Rx FIFO. */ + base->ERFSR = CAN_ERFSR_ERFDA_MASK; + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + return status; +} +#endif + +/*! + * brief Performs a polling send transaction on the CAN bus. + * + * note A transfer handle does not need to be created before calling this API. + * + * param base FlexCAN peripheral base pointer. + * param mbIdx The FlexCAN Message Buffer index. + * param pTxFrame Pointer to CAN message frame to be sent. + * retval kStatus_Success - Write Tx Message Buffer Successfully. + * retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pTxFrame) +{ + status_t status; + + /* Write Tx Message Buffer to initiate a data sending. */ + if (kStatus_Success == FLEXCAN_WriteTxMb(base, mbIdx, (const flexcan_frame_t *)(uintptr_t)pTxFrame)) + { +/* Wait until CAN Message send out. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint64_t u64flag = 1; + while (0U == FLEXCAN_GetMbStatusFlags(base, u64flag << mbIdx)) +#else + uint32_t u32flag = 1; + while (0U == FLEXCAN_GetMbStatusFlags(base, u32flag << mbIdx)) +#endif + { + } + +/* Clean Tx Message Buffer Flag. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_ClearMbStatusFlags(base, u64flag << mbIdx); +#else + FLEXCAN_ClearMbStatusFlags(base, u32flag << mbIdx); +#endif + /*After TX MB tranfered success, update the Timestamp from MB[mbIdx].CS register*/ + pTxFrame->timestamp = (uint16_t)((base->MB[mbIdx].CS & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT); + + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + return status; +} + +/*! + * brief Performs a polling receive transaction on the CAN bus. + * + * note A transfer handle does not need to be created before calling this API. + * + * param base FlexCAN peripheral base pointer. + * param mbIdx The FlexCAN Message Buffer index. + * param pRxFrame Pointer to CAN message frame structure for reception. + * retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * retval kStatus_Fail - Rx Message Buffer is empty. + */ +status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame) +{ +/* Wait until Rx Message Buffer non-empty. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint64_t u64flag = 1; + while (0U == FLEXCAN_GetMbStatusFlags(base, u64flag << mbIdx)) +#else + uint32_t u32flag = 1; + while (0U == FLEXCAN_GetMbStatusFlags(base, u32flag << mbIdx)) +#endif + { + } + +/* Clean Rx Message Buffer Flag. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_ClearMbStatusFlags(base, u64flag << mbIdx); +#else + FLEXCAN_ClearMbStatusFlags(base, u32flag << mbIdx); +#endif + + /* Read Received CAN Message. */ + return FLEXCAN_ReadRxMb(base, mbIdx, pRxFrame); +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Performs a polling send transaction on the CAN bus. + * + * note A transfer handle does not need to be created before calling this API. + * + * param base FlexCAN peripheral base pointer. + * param mbIdx The FlexCAN FD Message Buffer index. + * param pTxFrame Pointer to CAN FD message frame to be sent. + * retval kStatus_Success - Write Tx Message Buffer Successfully. + * retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t FLEXCAN_TransferFDSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pTxFrame) +{ + status_t status; + + /* Write Tx Message Buffer to initiate a data sending. */ + if (kStatus_Success == FLEXCAN_WriteFDTxMb(base, mbIdx, (const flexcan_fd_frame_t *)(uintptr_t)pTxFrame)) + { +/* Wait until CAN Message send out. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint64_t u64flag = 1; + while (0U == FLEXCAN_GetMbStatusFlags(base, u64flag << mbIdx)) +#else + uint32_t u32flag = 1; + while (0U == FLEXCAN_GetMbStatusFlags(base, u32flag << mbIdx)) +#endif + { + } + +/* Clean Tx Message Buffer Flag. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_ClearMbStatusFlags(base, u64flag << mbIdx); +#else + FLEXCAN_ClearMbStatusFlags(base, u32flag << mbIdx); +#endif + /*After TX MB tranfered success, update the Timestamp from base->MB[offset for CAN FD].CS register*/ + volatile uint32_t *mbAddr = &(base->MB[0].CS); + uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); + pTxFrame->timestamp = (uint16_t)((mbAddr[offset] & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT); + + status = kStatus_Success; + } + else + { + status = kStatus_Fail; + } + + return status; +} + +/*! + * brief Performs a polling receive transaction on the CAN bus. + * + * note A transfer handle does not need to be created before calling this API. + * + * param base FlexCAN peripheral base pointer. + * param mbIdx The FlexCAN FD Message Buffer index. + * param pRxFrame Pointer to CAN FD message frame structure for reception. + * retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * retval kStatus_Fail - Rx Message Buffer is empty. + */ +status_t FLEXCAN_TransferFDReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pRxFrame) +{ +/* Wait until Rx Message Buffer non-empty. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint64_t u64flag = 1; + while (0U == FLEXCAN_GetMbStatusFlags(base, u64flag << mbIdx)) +#else + uint32_t u32flag = 1; + while (0U == FLEXCAN_GetMbStatusFlags(base, u32flag << mbIdx)) +#endif + { + } + +/* Clean Rx Message Buffer Flag. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + FLEXCAN_ClearMbStatusFlags(base, u64flag << mbIdx); +#else + FLEXCAN_ClearMbStatusFlags(base, u32flag << mbIdx); +#endif + + /* Read Received CAN Message. */ + return FLEXCAN_ReadFDRxMb(base, mbIdx, pRxFrame); +} +#endif + +/*! + * brief Performs a polling receive transaction from Legacy Rx FIFO on the CAN bus. + * + * note A transfer handle does not need to be created before calling this API. + * + * param base FlexCAN peripheral base pointer. + * param pRxFrame Pointer to CAN message frame structure for reception. + * retval kStatus_Success - Read Message from Rx FIFO successfully. + * retval kStatus_Fail - Rx FIFO is not enabled. + */ +status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *pRxFrame) +{ + status_t rxFifoStatus; + + /* Wait until Legacy Rx FIFO non-empty. */ + while (0U == FLEXCAN_GetMbStatusFlags(base, (uint32_t)kFLEXCAN_RxFifoFrameAvlFlag)) + { + } + + /* Read data from Legacy Rx FIFO. */ + rxFifoStatus = FLEXCAN_ReadRxFifo(base, pRxFrame); + + /* Clean Rx Fifo available flag. */ + FLEXCAN_ClearMbStatusFlags(base, (uint32_t)kFLEXCAN_RxFifoFrameAvlFlag); + + return rxFifoStatus; +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * brief Performs a polling receive transaction from Enhanced Rx FIFO on the CAN bus. + * + * note A transfer handle does not need to be created before calling this API. + * + * param base FlexCAN peripheral base pointer. + * param pRxFrame Pointer to CAN FD message frame structure for reception. + * retval kStatus_Success - Read Message from Rx FIFO successfully. + * retval kStatus_Fail - Rx FIFO is not enabled. + */ +status_t FLEXCAN_TransferReceiveEnhancedFifoBlocking(CAN_Type *base, flexcan_fd_frame_t *pRxFrame) +{ + status_t rxFifoStatus; + + /* Wait until Enhanced Rx FIFO non-empty. */ + while (0U == (FLEXCAN_GetStatusFlags(base) & (uint64_t)kFLEXCAN_ERxFifoDataAvlIntFlag)) + { + } + + /* Read data from Enhanced Rx FIFO */ + rxFifoStatus = FLEXCAN_ReadEnhancedRxFifo(base, pRxFrame); + + return rxFifoStatus; +} +#endif + +/*! + * brief Initializes the FlexCAN handle. + * + * This function initializes the FlexCAN handle, which can be used for other FlexCAN + * transactional APIs. Usually, for a specified FlexCAN instance, + * call this API once to get the initialized handle. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param callback The callback function. + * param userData The parameter of the callback function. + */ +void FLEXCAN_TransferCreateHandle(CAN_Type *base, + flexcan_handle_t *handle, + flexcan_transfer_callback_t callback, + void *userData) +{ + assert(NULL != handle); + + uint8_t instance; + + /* Clean FlexCAN transfer handle. */ + (void)memset(handle, 0, sizeof(*handle)); + + /* Get instance from peripheral base address. */ + instance = (uint8_t)FLEXCAN_GetInstance(base); + + /* Save the context in global variables to support the double weak mechanism. */ + s_flexcanHandle[instance] = handle; + + /* Register Callback function. */ + handle->callback = callback; + handle->userData = userData; + + s_flexcanIsr = FLEXCAN_TransferHandleIRQ; + + /* We Enable Error & Status interrupt here, because this interrupt just + * report current status of FlexCAN module through Callback function. + * It is insignificance without a available callback function. + */ + if (handle->callback != NULL) + { + FLEXCAN_EnableInterrupts( + base, (uint32_t)kFLEXCAN_BusOffInterruptEnable | (uint32_t)kFLEXCAN_ErrorInterruptEnable | + (uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable | + (uint32_t)kFLEXCAN_WakeUpInterruptEnable +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) + | (uint64_t)kFLEXCAN_PNMatchWakeUpInterruptEnable | + (uint64_t)kFLEXCAN_PNTimeoutWakeUpInterruptEnable +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + | (uint64_t)kFLEXCAN_HostAccessNCErrorInterruptEnable | + (uint64_t)kFLEXCAN_FlexCanAccessNCErrorInterruptEnable | + (uint64_t)kFLEXCAN_HostOrFlexCanCErrorInterruptEnable +#endif + ); + } + else + { + FLEXCAN_DisableInterrupts( + base, (uint32_t)kFLEXCAN_BusOffInterruptEnable | (uint32_t)kFLEXCAN_ErrorInterruptEnable | + (uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable | + (uint32_t)kFLEXCAN_WakeUpInterruptEnable +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) + | (uint64_t)kFLEXCAN_PNMatchWakeUpInterruptEnable | + (uint64_t)kFLEXCAN_PNTimeoutWakeUpInterruptEnable +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + | (uint64_t)kFLEXCAN_HostAccessNCErrorInterruptEnable | + (uint64_t)kFLEXCAN_FlexCanAccessNCErrorInterruptEnable | + (uint64_t)kFLEXCAN_HostOrFlexCanCErrorInterruptEnable +#endif + ); + } + + /* Enable interrupts in NVIC. */ + (void)EnableIRQ((IRQn_Type)(s_flexcanRxWarningIRQ[instance])); + (void)EnableIRQ((IRQn_Type)(s_flexcanTxWarningIRQ[instance])); + (void)EnableIRQ((IRQn_Type)(s_flexcanWakeUpIRQ[instance])); + (void)EnableIRQ((IRQn_Type)(s_flexcanErrorIRQ[instance])); + (void)EnableIRQ((IRQn_Type)(s_flexcanBusOffIRQ[instance])); + (void)EnableIRQ((IRQn_Type)(s_flexcanMbIRQ[instance])); +} + +/*! + * brief Sends a message using IRQ. + * + * This function sends a message using IRQ. This is a non-blocking function, which returns + * right away. When messages have been sent out, the send callback function is called. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param pMbXfer FlexCAN Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * retval kStatus_Success Start Tx Message Buffer sending process successfully. + * retval kStatus_Fail Write Tx Message Buffer failed. + * retval kStatus_FLEXCAN_TxBusy Tx Message Buffer is in use. + */ +status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer) +{ + /* Assertion. */ + assert(NULL != handle); + assert(NULL != pMbXfer); + assert(pMbXfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, pMbXfer->mbIdx)); +#endif + + status_t status; + + /* Check if Message Buffer is idle. */ + if ((uint8_t)kFLEXCAN_StateIdle == handle->mbState[pMbXfer->mbIdx]) + { + /* Distinguish transmit type. */ + if ((uint32_t)kFLEXCAN_FrameTypeRemote == pMbXfer->frame->type) + { + handle->mbState[pMbXfer->mbIdx] = (uint8_t)kFLEXCAN_StateTxRemote; + } + else + { + handle->mbState[pMbXfer->mbIdx] = (uint8_t)kFLEXCAN_StateTxData; + } + + if (kStatus_Success == + FLEXCAN_WriteTxMb(base, pMbXfer->mbIdx, (const flexcan_frame_t *)(uintptr_t)pMbXfer->frame)) + { +/* Enable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint64_t u64mask = 1; + FLEXCAN_EnableMbInterrupts(base, u64mask << pMbXfer->mbIdx); +#else + uint32_t u32mask = 1; + FLEXCAN_EnableMbInterrupts(base, u32mask << pMbXfer->mbIdx); +#endif + status = kStatus_Success; + } + else + { + handle->mbState[pMbXfer->mbIdx] = (uint8_t)kFLEXCAN_StateIdle; + status = kStatus_Fail; + } + } + else + { + status = kStatus_FLEXCAN_TxBusy; + } + + return status; +} + +/*! + * brief Receives a message using IRQ. + * + * This function receives a message using IRQ. This is non-blocking function, which returns + * right away. When the message has been received, the receive callback function is called. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param pMbXfer FlexCAN Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * retval kStatus_Success - Start Rx Message Buffer receiving process successfully. + * retval kStatus_FLEXCAN_RxBusy - Rx Message Buffer is in use. + */ +status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer) +{ + status_t status; + + /* Assertion. */ + assert(NULL != handle); + assert(NULL != pMbXfer); + assert(pMbXfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, pMbXfer->mbIdx)); +#endif + + /* Check if Message Buffer is idle. */ + if ((uint8_t)kFLEXCAN_StateIdle == handle->mbState[pMbXfer->mbIdx]) + { + handle->mbState[pMbXfer->mbIdx] = (uint8_t)kFLEXCAN_StateRxData; + + /* Register Message Buffer. */ + handle->mbFrameBuf[pMbXfer->mbIdx] = pMbXfer->frame; + +/* Enable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint64_t u64mask = 1; + FLEXCAN_EnableMbInterrupts(base, u64mask << pMbXfer->mbIdx); +#else + uint32_t u32mask = 1; + FLEXCAN_EnableMbInterrupts(base, u32mask << pMbXfer->mbIdx); +#endif + + status = kStatus_Success; + } + else + { + status = kStatus_FLEXCAN_RxBusy; + } + + return status; +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Sends a message using IRQ. + * + * This function sends a message using IRQ. This is a non-blocking function, which returns + * right away. When messages have been sent out, the send callback function is called. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param pMbXfer FlexCAN FD Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * retval kStatus_Success Start Tx Message Buffer sending process successfully. + * retval kStatus_Fail Write Tx Message Buffer failed. + * retval kStatus_FLEXCAN_TxBusy Tx Message Buffer is in use. + */ +status_t FLEXCAN_TransferFDSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer) +{ + /* Assertion. */ + assert(NULL != handle); + assert(NULL != pMbXfer); + assert(pMbXfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, pMbXfer->mbIdx)); +#endif + + status_t status; + + /* Check if Message Buffer is idle. */ + if ((uint8_t)kFLEXCAN_StateIdle == handle->mbState[pMbXfer->mbIdx]) + { + /* Distinguish transmit type. */ + if ((uint32_t)kFLEXCAN_FrameTypeRemote == pMbXfer->framefd->type) + { + handle->mbState[pMbXfer->mbIdx] = (uint8_t)kFLEXCAN_StateTxRemote; + } + else + { + handle->mbState[pMbXfer->mbIdx] = (uint8_t)kFLEXCAN_StateTxData; + } + + if (kStatus_Success == + FLEXCAN_WriteFDTxMb(base, pMbXfer->mbIdx, (const flexcan_fd_frame_t *)(uintptr_t)pMbXfer->framefd)) + { +/* Enable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint64_t u64mask = 1; + FLEXCAN_EnableMbInterrupts(base, u64mask << pMbXfer->mbIdx); +#else + uint32_t u32mask = 1; + FLEXCAN_EnableMbInterrupts(base, u32mask << pMbXfer->mbIdx); +#endif + + status = kStatus_Success; + } + else + { + handle->mbState[pMbXfer->mbIdx] = (uint8_t)kFLEXCAN_StateIdle; + status = kStatus_Fail; + } + } + else + { + status = kStatus_FLEXCAN_TxBusy; + } + + return status; +} + +/*! + * brief Receives a message using IRQ. + * + * This function receives a message using IRQ. This is non-blocking function, which returns + * right away. When the message has been received, the receive callback function is called. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param pMbXfer FlexCAN FD Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * retval kStatus_Success - Start Rx Message Buffer receiving process successfully. + * retval kStatus_FLEXCAN_RxBusy - Rx Message Buffer is in use. + */ +status_t FLEXCAN_TransferFDReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer) +{ + /* Assertion. */ + assert(NULL != handle); + assert(NULL != pMbXfer); + assert(pMbXfer->mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, pMbXfer->mbIdx)); +#endif + + status_t status; + + /* Check if Message Buffer is idle. */ + if ((uint8_t)kFLEXCAN_StateIdle == handle->mbState[pMbXfer->mbIdx]) + { + handle->mbState[pMbXfer->mbIdx] = (uint8_t)kFLEXCAN_StateRxData; + + /* Register Message Buffer. */ + handle->mbFDFrameBuf[pMbXfer->mbIdx] = pMbXfer->framefd; + +/* Enable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint64_t u64mask = 1; + FLEXCAN_EnableMbInterrupts(base, u64mask << pMbXfer->mbIdx); +#else + uint32_t u32mask = 1; + FLEXCAN_EnableMbInterrupts(base, u32mask << pMbXfer->mbIdx); +#endif + + status = kStatus_Success; + } + else + { + status = kStatus_FLEXCAN_RxBusy; + } + + return status; +} +#endif + +/*! + * brief Receives a message from Legacy Rx FIFO using IRQ. + * + * This function receives a message using IRQ. This is a non-blocking function, which returns + * right away. When all messages have been received, the receive callback function is called. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param pFifoXfer FlexCAN Rx FIFO transfer structure. See the ref flexcan_fifo_transfer_t. + * retval kStatus_Success - Start Rx FIFO receiving process successfully. + * retval kStatus_FLEXCAN_RxFifoBusy - Rx FIFO is currently in use. + */ +status_t FLEXCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, + flexcan_handle_t *handle, + flexcan_fifo_transfer_t *pFifoXfer) +{ + /* Assertion. */ + assert(NULL != handle); + assert(NULL != pFifoXfer); + + status_t status; + uint32_t irqMask = (uint32_t)kFLEXCAN_RxFifoOverflowFlag | (uint32_t)kFLEXCAN_RxFifoWarningFlag; + + /* Check if Message Buffer is idle. */ + if ((uint8_t)kFLEXCAN_StateIdle == handle->rxFifoState) + { + handle->rxFifoState = (uint8_t)kFLEXCAN_StateRxFifo; + + /* Register Message Buffer. */ + handle->rxFifoFrameBuf = pFifoXfer->frame; + handle->rxFifoFrameNum = pFifoXfer->frameNum; + handle->rxFifoTransferTotalNum = pFifoXfer->frameNum; + + if (handle->rxFifoTransferTotalNum < 5U) + { + /* Enable data available interrupt. */ + irqMask |= (uint32_t)kFLEXCAN_RxFifoFrameAvlFlag; + } + + /* Enable Message Buffer Interrupt. */ + FLEXCAN_EnableMbInterrupts(base, irqMask); + + status = kStatus_Success; + } + else + { + status = kStatus_FLEXCAN_RxFifoBusy; + } + + return status; +} + +/*! + * brief Gets the Legacy Rx Fifo transfer status during a interrupt non-blocking receive. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param count Number of CAN messages receive so far by the non-blocking transaction. + * retval kStatus_InvalidArgument count is Invalid. + * retval kStatus_Success Successfully return the count. + */ + +status_t FLEXCAN_TransferGetReceiveFifoCount(CAN_Type *base, flexcan_handle_t *handle, size_t *count) +{ + assert(NULL != handle); + + status_t result = kStatus_Success; + + if (handle->rxFifoState == (uint32_t)kFLEXCAN_StateIdle) + { + result = kStatus_NoTransferInProgress; + } + else + { + *count = handle->rxFifoTransferTotalNum - handle->rxFifoFrameNum; + } + + return result; +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * brief Receives a message from Enhanced Rx FIFO using IRQ. + * + * This function receives a message using IRQ. This is a non-blocking function, which returns + * right away. When all messages have been received, the receive callback function is called. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param pFifoXfer FlexCAN Rx FIFO transfer structure. See the ref flexcan_fifo_transfer_t. + * retval kStatus_Success - Start Rx FIFO receiving process successfully. + * retval kStatus_FLEXCAN_RxFifoBusy - Rx FIFO is currently in use. + */ +status_t FLEXCAN_TransferReceiveEnhancedFifoNonBlocking(CAN_Type *base, + flexcan_handle_t *handle, + flexcan_fifo_transfer_t *pFifoXfer) +{ + /* Assertion. */ + assert(NULL != handle); + assert(NULL != pFifoXfer); + + status_t status; + uint32_t watermark = ((base->ERFCR & CAN_ERFCR_ERFWM_MASK) >> CAN_ERFCR_ERFWM_SHIFT) + 1U; + uint64_t irqMask = + (uint64_t)kFLEXCAN_ERxFifoUnderflowInterruptEnable | (uint64_t)kFLEXCAN_ERxFifoOverflowInterruptEnable; + + /* Check if Enhanced Rx FIFO is idle. */ + if ((uint8_t)kFLEXCAN_StateIdle == handle->rxFifoState) + { + handle->rxFifoState = (uint8_t)kFLEXCAN_StateRxFifo; + + /* Register Message Buffer. */ + handle->rxFifoFDFrameBuf = pFifoXfer->framefd; + handle->rxFifoFrameNum = pFifoXfer->frameNum; + handle->rxFifoTransferTotalNum = pFifoXfer->frameNum; + + if (handle->rxFifoTransferTotalNum >= watermark) + { + /* Enable watermark interrupt. */ + irqMask |= (uint64_t)kFLEXCAN_ERxFifoWatermarkInterruptEnable; + } + else + { + /* Enable data available interrupt. */ + irqMask |= (uint64_t)kFLEXCAN_ERxFifoDataAvlInterruptEnable; + } + /* Enable Enhanced Rx FIFO Interrupt. */ + FLEXCAN_EnableInterrupts(base, irqMask); + + status = kStatus_Success; + } + else + { + status = kStatus_FLEXCAN_RxFifoBusy; + } + + return status; +} +#endif + +/*! + * brief Aborts the interrupt driven message send process. + * + * This function aborts the interrupt driven message send process. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param mbIdx The FlexCAN Message Buffer index. + */ +void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) +{ + uint16_t timestamp; + + /* Assertion. */ + assert(NULL != handle); + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); +#endif + +/* Disable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint64_t u64mask = 1; + FLEXCAN_DisableMbInterrupts(base, u64mask << mbIdx); +#else + uint32_t u32mask = 1; + FLEXCAN_DisableMbInterrupts(base, u32mask << mbIdx); +#endif + + /* Update the TX frame 's time stamp by MB[mbIdx].cs. */ + timestamp = (uint16_t)((base->MB[mbIdx].CS & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT); + handle->timestamp[mbIdx] = timestamp; + + /* Clean Message Buffer. */ + FLEXCAN_SetTxMbConfig(base, mbIdx, true); + + handle->mbState[mbIdx] = (uint8_t)kFLEXCAN_StateIdle; +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * brief Aborts the interrupt driven message send process. + * + * This function aborts the interrupt driven message send process. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param mbIdx The FlexCAN FD Message Buffer index. + */ +void FLEXCAN_TransferFDAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) +{ + volatile uint32_t *mbAddr; + uint32_t offset; + uint16_t timestamp; + + /* Assertion. */ + assert(NULL != handle); + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); +#endif + +/* Disable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint64_t u64mask = 1; + FLEXCAN_DisableMbInterrupts(base, u64mask << mbIdx); +#else + uint32_t u32mask = 1; + FLEXCAN_DisableMbInterrupts(base, u32mask << mbIdx); +#endif + + /* Update the TX frame 's time stamp by base->MB[offset for CAN FD].CS. */ + mbAddr = &(base->MB[0].CS); + offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx); + timestamp = (uint16_t)((mbAddr[offset] & CAN_CS_TIME_STAMP_MASK) >> CAN_CS_TIME_STAMP_SHIFT); + handle->timestamp[mbIdx] = timestamp; + + /* Clean Message Buffer. */ + FLEXCAN_SetFDTxMbConfig(base, mbIdx, true); + + handle->mbState[mbIdx] = (uint8_t)kFLEXCAN_StateIdle; +} + +/*! + * brief Aborts the interrupt driven message receive process. + * + * This function aborts the interrupt driven message receive process. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param mbIdx The FlexCAN FD Message Buffer index. + */ +void FLEXCAN_TransferFDAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) +{ + /* Assertion. */ + assert(NULL != handle); + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); +#endif + +/* Disable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint64_t u64mask = 1; + FLEXCAN_DisableMbInterrupts(base, u64mask << mbIdx); +#else + uint32_t u32mask = 1; + FLEXCAN_DisableMbInterrupts(base, u32mask << mbIdx); +#endif + + /* Un-register handle. */ + handle->mbFDFrameBuf[mbIdx] = NULL; + handle->mbState[mbIdx] = (uint8_t)kFLEXCAN_StateIdle; +} +#endif + +/*! + * brief Aborts the interrupt driven message receive process. + * + * This function aborts the interrupt driven message receive process. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param mbIdx The FlexCAN Message Buffer index. + */ +void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx) +{ + /* Assertion. */ + assert(NULL != handle); + assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK)); +#if !defined(NDEBUG) + assert(!FLEXCAN_IsMbOccupied(base, mbIdx)); +#endif + +/* Disable Message Buffer Interrupt. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint64_t u64mask = 1; + FLEXCAN_DisableMbInterrupts(base, (u64mask << mbIdx)); +#else + uint32_t u32mask = 1; + FLEXCAN_DisableMbInterrupts(base, (u32mask << mbIdx)); +#endif + + /* Un-register handle. */ + handle->mbFrameBuf[mbIdx] = NULL; + handle->mbState[mbIdx] = (uint8_t)kFLEXCAN_StateIdle; +} + +/*! + * brief Aborts the interrupt driven message receive from Legacy Rx FIFO process. + * + * This function aborts the interrupt driven message receive from Legacy Rx FIFO process. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + */ +void FLEXCAN_TransferAbortReceiveFifo(CAN_Type *base, flexcan_handle_t *handle) +{ + /* Assertion. */ + assert(NULL != handle); + + /* Check if Rx FIFO is enabled. */ + if (0U != (base->MCR & CAN_MCR_RFEN_MASK)) + { + /* Disable Rx Message FIFO Interrupts. */ + FLEXCAN_DisableMbInterrupts(base, (uint32_t)kFLEXCAN_RxFifoOverflowFlag | (uint32_t)kFLEXCAN_RxFifoWarningFlag | + (uint32_t)kFLEXCAN_RxFifoFrameAvlFlag); + + /* Un-register handle. */ + handle->rxFifoFrameBuf = NULL; + /* Clear transfer count. */ + handle->rxFifoFrameNum = 0U; + handle->rxFifoTransferTotalNum = 0U; + } + + handle->rxFifoState = (uint8_t)kFLEXCAN_StateIdle; +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * brief Aborts the interrupt driven message receive from Enhanced Rx FIFO process. + * + * This function aborts the interrupt driven message receive from Rx FIFO process. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + */ +void FLEXCAN_TransferAbortReceiveEnhancedFifo(CAN_Type *base, flexcan_handle_t *handle) +{ + /* Assertion. */ + assert(NULL != handle); + + /* Check if Enhanced Rx FIFO is enabled. */ + if (0U != (base->ERFCR & CAN_ERFCR_ERFEN_MASK)) + { + /* Disable all Rx Message FIFO interrupts. */ + FLEXCAN_DisableInterrupts(base, (uint64_t)kFLEXCAN_ERxFifoUnderflowInterruptEnable | + (uint64_t)kFLEXCAN_ERxFifoOverflowInterruptEnable | + (uint64_t)kFLEXCAN_ERxFifoWatermarkInterruptEnable | + (uint64_t)kFLEXCAN_ERxFifoDataAvlInterruptEnable); + + /* Un-register handle. */ + handle->rxFifoFDFrameBuf = NULL; + /* Clear transfer count. */ + handle->rxFifoFrameNum = 0U; + handle->rxFifoTransferTotalNum = 0U; + } + + handle->rxFifoState = (uint8_t)kFLEXCAN_StateIdle; +} +#endif + +/*! + * brief Gets the detail index of Mailbox's Timestamp by handle. + * + * Then function can only be used when calling non-blocking Data transfer (TX/RX) API, + * After TX/RX data transfer done (User can get the status by handler's callback function), + * we can get the detail index of Mailbox's timestamp by handle, + * Detail non-blocking data transfer API (TX/RX) contain. + * -FLEXCAN_TransferSendNonBlocking + * -FLEXCAN_TransferFDSendNonBlocking + * -FLEXCAN_TransferReceiveNonBlocking + * -FLEXCAN_TransferFDReceiveNonBlocking + * -FLEXCAN_TransferReceiveFifoNonBlocking + * + * param handle FlexCAN handle pointer. + * param mbIdx The FlexCAN FD Message Buffer index. + * return the index of mailbox 's timestamp stored in the handle. + * + */ +uint32_t FLEXCAN_GetTimeStamp(flexcan_handle_t *handle, uint8_t mbIdx) +{ + /* Assertion. */ + assert(NULL != handle); + + return (uint32_t)(handle->timestamp[mbIdx]); +} + +/*! + * brief Check unhandle interrupt events + * + * param base FlexCAN peripheral base address. + * return TRUE if unhandled interrupt action exist, FALSE if no unhandlered interrupt action exist. + */ +static bool FLEXCAN_CheckUnhandleInterruptEvents(CAN_Type *base) +{ + uint64_t tempmask; + uint64_t tempflag; + bool fgRet = false; + + if (0U == (FLEXCAN_GetStatusFlags(base) & + (FLEXCAN_ERROR_AND_STATUS_INIT_FLAG | FLEXCAN_WAKE_UP_FLAG | FLEXCAN_MEMORY_ENHANCED_RX_FIFO_INIT_FLAG))) + { + /* If no error, wake_up or enhanced RX FIFO status, Checking whether exist MB interrupt status and legacy RX + * FIFO interrupt status */ + tempmask = (uint64_t)base->IMASK1; + tempflag = (uint64_t)base->IFLAG1; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + tempmask |= ((uint64_t)base->IMASK2) << 32; + tempflag |= ((uint64_t)base->IFLAG2) << 32; +#endif + fgRet = (0U != (tempmask & tempflag)); + } +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + else if (0U != (FLEXCAN_GetStatusFlags(base) & FLEXCAN_MEMORY_ENHANCED_RX_FIFO_INIT_FLAG)) + { + /* Checking whether exist enhanced RX FIFO interrupt status. */ + tempmask = (uint64_t)base->ERFIER; + tempflag = (uint64_t)base->ERFSR; + fgRet = (0U != (tempmask & tempflag)); + } +#endif + else + { + /* Exist error or wake up flag. */ + fgRet = true; + } + + return fgRet; +} + +/*! + * brief Sub Handler Data Trasfered Events + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param pResult Pointer to the Handle result. + * + * return the status after handle each data transfered event. + */ +static status_t FLEXCAN_SubHandlerForDataTransfered(CAN_Type *base, flexcan_handle_t *handle, uint32_t *pResult) +{ + status_t status = kStatus_FLEXCAN_UnHandled; + uint32_t result = 0xFFU; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint64_t intflag = (((uint64_t)base->IMASK2 & base->IFLAG2) << 32UL) | (base->IMASK1 & base->IFLAG1); +#else + uint32_t intflag = base->IMASK1 & base->IFLAG1; +#endif + /* For this implementation, we solve the Message with lowest MB index first. */ + for (result = 0U; result < (uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); result++) + { + /* Find the lowest unhandled Message Buffer */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + if (0UL != (intflag & ((uint64_t)1UL << result))) +#else + if (0UL != (intflag & ((uint32_t)1UL << result))) +#endif + { + break; + } + } + + /* find Message to deal with. */ + if (result < (uint32_t)FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base)) + { + /* Solve Legacy Rx FIFO interrupt. */ + if (((uint8_t)kFLEXCAN_StateIdle != handle->rxFifoState) && (result <= (uint32_t)CAN_IFLAG1_BUF7I_SHIFT) && + ((base->MCR & CAN_MCR_RFEN_MASK) != 0U)) + { + uint32_t u32mask = 1; + switch (u32mask << result) + { + case kFLEXCAN_RxFifoOverflowFlag: + status = kStatus_FLEXCAN_RxFifoOverflow; + break; + + case kFLEXCAN_RxFifoWarningFlag: + if ((handle->rxFifoFrameNum > 5U) && (0U != (base->IFLAG1 & (uint32_t)kFLEXCAN_RxFifoFrameAvlFlag))) + { + for (uint32_t i = 0; i < 5UL; i++) + { + status = FLEXCAN_ReadRxFifo(base, handle->rxFifoFrameBuf); + + if (kStatus_Success == status) + { + /* Align the current rxfifo timestamp to the timestamp array by handle. */ + handle->timestamp[i] = handle->rxFifoFrameBuf->timestamp; + handle->rxFifoFrameBuf++; + handle->rxFifoFrameNum--; + /* Clean Rx Fifo available flag to discard the frame that has been read. */ + FLEXCAN_ClearMbStatusFlags(base, (uint32_t)kFLEXCAN_RxFifoFrameAvlFlag); + } + else + { + return kStatus_FLEXCAN_RxFifoDisabled; + } + } + if (handle->rxFifoFrameNum < 5UL) + { + /* Enable data avaliable interrupt. */ + FLEXCAN_EnableMbInterrupts(base, (uint32_t)kFLEXCAN_RxFifoFrameAvlFlag); + } + status = kStatus_FLEXCAN_RxFifoBusy; + } + else + { + /* Should enter case kFLEXCAN_RxFifoFrameAvlFlag but not, means previous transfer may have + * overflow*/ + status = kStatus_FLEXCAN_RxFifoWarning; + } + break; + + case kFLEXCAN_RxFifoFrameAvlFlag: + /* Whether still has CAN messages remaining to be received. */ + if (handle->rxFifoFrameNum > 0U) + { + status = FLEXCAN_ReadRxFifo(base, handle->rxFifoFrameBuf); + if (kStatus_Success == status) + { + /* Align the current (index 0) rxfifo timestamp to the timestamp array by handle. */ + handle->timestamp[0] = handle->rxFifoFrameBuf->timestamp; + handle->rxFifoFrameBuf++; + handle->rxFifoFrameNum--; + } + else + { + return kStatus_FLEXCAN_RxFifoDisabled; + } + } + if (handle->rxFifoFrameNum == 0U) + { + /* Stop receiving Ehanced Rx FIFO when the transmission is over. */ + FLEXCAN_TransferAbortReceiveFifo(base, handle); + status = kStatus_FLEXCAN_RxFifoIdle; + } + else + { + /* Continue use data avaliable interrupt. */ + status = kStatus_FLEXCAN_RxFifoBusy; + } + break; + + default: + status = kStatus_FLEXCAN_UnHandled; + break; + } + } + else + { + /* Get current State of Message Buffer. */ + switch (handle->mbState[result]) + { + /* Solve Rx Data Frame. */ + case (uint8_t)kFLEXCAN_StateRxData: +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (0U != (base->MCR & CAN_MCR_FDEN_MASK)) + { + status = FLEXCAN_ReadFDRxMb(base, (uint8_t)result, handle->mbFDFrameBuf[result]); + if (kStatus_Success == status) + { + /* Align the current index of RX MB timestamp to the timestamp array by handle. */ + handle->timestamp[result] = handle->mbFDFrameBuf[result]->timestamp; + status = kStatus_FLEXCAN_RxIdle; + } + } + else +#endif + { + status = FLEXCAN_ReadRxMb(base, (uint8_t)result, handle->mbFrameBuf[result]); + if (kStatus_Success == status) + { + /* Align the current index of RX MB timestamp to the timestamp array by handle. */ + handle->timestamp[result] = handle->mbFrameBuf[result]->timestamp; + status = kStatus_FLEXCAN_RxIdle; + } + } +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (0U != (base->MCR & CAN_MCR_FDEN_MASK)) + { + FLEXCAN_TransferFDAbortReceive(base, handle, (uint8_t)result); + } + else +#endif + { + FLEXCAN_TransferAbortReceive(base, handle, (uint8_t)result); + } + break; + + /* Sove Rx Remote Frame. User need to Read the frame in Mail box in time by Read from MB API. */ + case (uint8_t)kFLEXCAN_StateRxRemote: + status = kStatus_FLEXCAN_RxRemote; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (0U != (base->MCR & CAN_MCR_FDEN_MASK)) + { + FLEXCAN_TransferFDAbortReceive(base, handle, (uint8_t)result); + } + else +#endif + { + FLEXCAN_TransferAbortReceive(base, handle, (uint8_t)result); + } + break; + + /* Solve Tx Data Frame. */ + case (uint8_t)kFLEXCAN_StateTxData: + status = kStatus_FLEXCAN_TxIdle; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (0U != (base->MCR & CAN_MCR_FDEN_MASK)) + { + FLEXCAN_TransferFDAbortSend(base, handle, (uint8_t)result); + } + else +#endif + { + FLEXCAN_TransferAbortSend(base, handle, (uint8_t)result); + } + break; + + /* Solve Tx Remote Frame. */ + case (uint8_t)kFLEXCAN_StateTxRemote: + handle->mbState[result] = (uint8_t)kFLEXCAN_StateRxRemote; + status = kStatus_FLEXCAN_TxSwitchToRx; + break; + + default: + status = kStatus_FLEXCAN_UnHandled; + break; + } + } + + /* Clear resolved Message Buffer IRQ. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint64_t u64flag = 1; + FLEXCAN_ClearMbStatusFlags(base, u64flag << result); +#else + uint32_t u32flag = 1; + FLEXCAN_ClearMbStatusFlags(base, u32flag << result); +#endif + } + + *pResult = result; + + return status; +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * brief Sub Handler Ehanced Rx FIFO event + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + * param flags FlexCAN interrupt flags. + * + * return the status after handle Ehanced Rx FIFO event. + */ +static status_t FLEXCAN_SubHandlerForEhancedRxFifo(CAN_Type *base, flexcan_handle_t *handle, uint64_t flags) +{ + uint32_t watermark = ((base->ERFCR & CAN_ERFCR_ERFWM_MASK) >> CAN_ERFCR_ERFWM_SHIFT) + 1U; + uint32_t transferFrames; + + status_t status; + /* Solve Ehanced Rx FIFO interrupt. */ + if ((0u != (flags & (uint64_t)kFLEXCAN_ERxFifoUnderflowIntFlag)) && + (0u != (base->ERFIER & CAN_ERFIER_ERFUFWIE_MASK))) + { + status = kStatus_FLEXCAN_RxFifoUnderflow; + FLEXCAN_ClearStatusFlags(base, (uint64_t)kFLEXCAN_ERxFifoUnderflowIntFlag); + } + else if ((0u != (flags & (uint64_t)kFLEXCAN_ERxFifoOverflowIntFlag)) && + (0u != (base->ERFIER & CAN_ERFIER_ERFOVFIE_MASK))) + { + status = kStatus_FLEXCAN_RxFifoOverflow; + FLEXCAN_ClearStatusFlags(base, (uint64_t)kFLEXCAN_ERxFifoOverflowIntFlag); + } + else if ((0u != (flags & (uint64_t)kFLEXCAN_ERxFifoWatermarkIntFlag)) && + (0u != (base->ERFIER & CAN_ERFIER_ERFWMIIE_MASK))) + { + /* Whether the number of CAN messages remaining to be received is greater than the watermark. */ + transferFrames = (handle->rxFifoFrameNum > watermark) ? watermark : handle->rxFifoFrameNum; + + for (uint32_t i = 0; i < transferFrames; i++) + { + status = FLEXCAN_ReadEnhancedRxFifo(base, handle->rxFifoFDFrameBuf); + + if (kStatus_Success == status) + { + handle->rxFifoFDFrameBuf++; + handle->rxFifoFrameNum--; + /* Clear data Watermark flag due to has read back one frame. */ + base->ERFSR = CAN_ERFSR_ERFWMI_MASK; + } + else + { + return kStatus_FLEXCAN_RxFifoDisabled; + } + } + if (handle->rxFifoFrameNum == 0U) + { + /* Stop receiving Ehanced Rx FIFO when the transmission is over. */ + FLEXCAN_TransferAbortReceiveEnhancedFifo(base, handle); + status = kStatus_FLEXCAN_RxFifoIdle; + } + else if (handle->rxFifoFrameNum < watermark) + { + /* Disable watermark interrupt and enable data avaliable interrupt. */ + FLEXCAN_DisableInterrupts(base, (uint64_t)kFLEXCAN_ERxFifoWatermarkInterruptEnable); + FLEXCAN_EnableInterrupts(base, (uint64_t)kFLEXCAN_ERxFifoDataAvlInterruptEnable); + status = kStatus_FLEXCAN_RxFifoBusy; + } + else + { + /* Continue use watermark interrupt. */ + status = kStatus_FLEXCAN_RxFifoBusy; + } + } + else + { + /* Data available status, check Whether still has CAN messages remaining to be received. */ + if (handle->rxFifoFrameNum > 0U) + { + status = FLEXCAN_ReadEnhancedRxFifo(base, handle->rxFifoFDFrameBuf); + + if (kStatus_Success == status) + { + handle->rxFifoFDFrameBuf++; + handle->rxFifoFrameNum--; + } + else + { + return kStatus_FLEXCAN_RxFifoDisabled; + } + } + if (handle->rxFifoFrameNum == 0U) + { + /* Stop receiving Ehanced Rx FIFO when the transmission is over. */ + FLEXCAN_TransferAbortReceiveEnhancedFifo(base, handle); + status = kStatus_FLEXCAN_RxFifoIdle; + } + else + { + /* Continue use data avaliable interrupt. */ + status = kStatus_FLEXCAN_RxFifoBusy; + } + } + return status; +} +#endif + +/*! + * brief FlexCAN IRQ handle function. + * + * This function handles the FlexCAN Error, the Message Buffer, and the Rx FIFO IRQ request. + * + * param base FlexCAN peripheral base address. + * param handle FlexCAN handle pointer. + */ +void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle) +{ + /* Assertion. */ + assert(NULL != handle); + + status_t status; + uint32_t mbNum = 0xFFU; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + uint64_t result = 0U; +#else + uint32_t result = 0U; +#endif + do + { + /* Get Current FlexCAN Module Error and Status. */ + result = FLEXCAN_GetStatusFlags(base); + + /* To handle FlexCAN Error and Status Interrupt first. */ + if (0U != (result & FLEXCAN_ERROR_AND_STATUS_INIT_FLAG)) + { + status = kStatus_FLEXCAN_ErrorStatus; + /* Clear FlexCAN Error and Status Interrupt. */ + FLEXCAN_ClearStatusFlags(base, FLEXCAN_ERROR_AND_STATUS_INIT_FLAG); + } + else if (0U != (result & FLEXCAN_WAKE_UP_FLAG)) + { + status = kStatus_FLEXCAN_WakeUp; + FLEXCAN_ClearStatusFlags(base, FLEXCAN_WAKE_UP_FLAG); + } +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + else if (0U != (FLEXCAN_EFIFO_STATUS_UNMASK(result & FLEXCAN_MEMORY_ENHANCED_RX_FIFO_INIT_FLAG) & base->ERFIER)) + { + status = FLEXCAN_SubHandlerForEhancedRxFifo(base, handle, result); + } +#endif + else + { + /* To handle Message Buffer or Legacy Rx FIFO transfer. */ + status = FLEXCAN_SubHandlerForDataTransfered(base, handle, &mbNum); + result = mbNum; + } + + /* Calling Callback Function if has one. */ + if (handle->callback != NULL) + { + handle->callback(base, handle, status, result, handle->userData); + } + } while (FLEXCAN_CheckUnhandleInterruptEvents(base)); +} + +#if defined(CAN0) +void CAN0_DriverIRQHandler(void); +void CAN0_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[0]); + + s_flexcanIsr(CAN0, s_flexcanHandle[0]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CAN1) +void CAN1_DriverIRQHandler(void); +void CAN1_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[1]); + + s_flexcanIsr(CAN1, s_flexcanHandle[1]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CAN2) +void CAN2_DriverIRQHandler(void); +void CAN2_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[2]); + + s_flexcanIsr(CAN2, s_flexcanHandle[2]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CAN3) +void CAN3_DriverIRQHandler(void); +void CAN3_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[3]); + + s_flexcanIsr(CAN3, s_flexcanHandle[3]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(CAN4) +void CAN4_DriverIRQHandler(void); +void CAN4_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[4]); + + s_flexcanIsr(CAN4, s_flexcanHandle[4]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(DMA__CAN0) +void DMA_FLEXCAN0_INT_DriverIRQHandler(void); +void DMA_FLEXCAN0_INT_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN0)]); + + s_flexcanIsr(DMA__CAN0, s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN0)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(DMA__CAN1) +void DMA_FLEXCAN1_INT_DriverIRQHandler(void); +void DMA_FLEXCAN1_INT_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN1)]); + + s_flexcanIsr(DMA__CAN1, s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN1)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(DMA__CAN2) +void DMA_FLEXCAN2_INT_DriverIRQHandler(void); +void DMA_FLEXCAN2_INT_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN2)]); + + s_flexcanIsr(DMA__CAN2, s_flexcanHandle[FLEXCAN_GetInstance(DMA__CAN2)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(ADMA__CAN0) +void ADMA_FLEXCAN0_INT_DriverIRQHandler(void); +void ADMA_FLEXCAN0_INT_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN0)]); + + s_flexcanIsr(ADMA__CAN0, s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN0)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(ADMA__CAN1) +void ADMA_FLEXCAN1_INT_DriverIRQHandler(void); +void ADMA_FLEXCAN1_INT_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN1)]); + + s_flexcanIsr(ADMA__CAN1, s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN1)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(ADMA__CAN2) +void ADMA_FLEXCAN2_INT_DriverIRQHandler(void); +void ADMA_FLEXCAN2_INT_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN2)]); + + s_flexcanIsr(ADMA__CAN2, s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN2)]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCAN1) +void CAN_FD1_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[1]); + + s_flexcanIsr(FLEXCAN1, s_flexcanHandle[1]); + SDK_ISR_EXIT_BARRIER; +} +#endif + +#if defined(FLEXCAN2) +void CAN_FD2_DriverIRQHandler(void) +{ + assert(NULL != s_flexcanHandle[2]); + + s_flexcanIsr(FLEXCAN2, s_flexcanHandle[2]); + SDK_ISR_EXIT_BARRIER; +} +#endif diff --git a/bsps/arm/imxrt/mcux-sdk/drivers/flexcan/fsl_flexcan.h b/bsps/arm/imxrt/mcux-sdk/drivers/flexcan/fsl_flexcan.h new file mode 100644 index 0000000000..b3d1c46a33 --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/drivers/flexcan/fsl_flexcan.h @@ -0,0 +1,2241 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_FLEXCAN_H_ +#define _FSL_FLEXCAN_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup flexcan_driver + * @{ + */ + +/****************************************************************************** + * Definitions + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexCAN driver version. */ +#define FSL_FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 9, 2)) +/*@}*/ + +#if !(defined(FLEXCAN_WAIT_TIMEOUT) && FLEXCAN_WAIT_TIMEOUT) +/* Define to 1000 means keep waiting 1000 times until the flag is assert/deassert. */ +#define FLEXCAN_WAIT_TIMEOUT (1000U) +#endif + +/*! @brief FlexCAN frame length helper macro. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +#define DLC_LENGTH_DECODE(dlc) (((dlc) <= 8U) ? (dlc) : (((dlc) <= 12U) ? (((dlc)-6U) * 4U) : (((dlc)-11U) * 16U))) +#endif + +/*! @brief FlexCAN Frame ID helper macro. */ +#define FLEXCAN_ID_STD(id) \ + (((uint32_t)(((uint32_t)(id)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) /*!< Standard Frame ID helper macro. */ +#define FLEXCAN_ID_EXT(id) \ + (((uint32_t)(((uint32_t)(id)) << CAN_ID_EXT_SHIFT)) & \ + (CAN_ID_EXT_MASK | CAN_ID_STD_MASK)) /*!< Extend Frame ID helper macro. */ + +/*! @brief FlexCAN Rx Message Buffer Mask helper macro. */ +#define FLEXCAN_RX_MB_STD_MASK(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + FLEXCAN_ID_STD(id)) /*!< Standard Rx Message Buffer Mask helper macro. */ +#define FLEXCAN_RX_MB_EXT_MASK(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + FLEXCAN_ID_EXT(id)) /*!< Extend Rx Message Buffer Mask helper macro. */ + +/*! @brief FlexCAN Legacy Rx FIFO Mask helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_A(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + (FLEXCAN_ID_STD(id) << 1)) /*!< Standard Rx FIFO Mask helper macro Type A helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_HIGH(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + (((uint32_t)(id)&0x7FF) << 19)) /*!< Standard Rx FIFO Mask helper macro Type B upper part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_LOW(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \ + (((uint32_t)(id)&0x7FF) << 3)) /*!< Standard Rx FIFO Mask helper macro Type B lower part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_HIGH(id) \ + (((uint32_t)(id)&0x7F8) << 21) /*!< Standard Rx FIFO Mask helper macro Type C upper part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_HIGH(id) \ + (((uint32_t)(id)&0x7F8) << 13) /*!< Standard Rx FIFO Mask helper macro Type C mid-upper part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW(id) \ + (((uint32_t)(id)&0x7F8) << 5) /*!< Standard Rx FIFO Mask helper macro Type C mid-lower part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW(id) \ + (((uint32_t)(id)&0x7F8) >> 3) /*!< Standard Rx FIFO Mask helper macro Type C lower part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + (FLEXCAN_ID_EXT(id) << 1)) /*!< Extend Rx FIFO Mask helper macro Type A helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH(id, rtr, ide) \ + ( \ + ((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \ + ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) \ + << 1)) /*!< Extend Rx FIFO Mask helper macro Type B upper part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW(id, rtr, ide) \ + (((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \ + ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) >> \ + 15)) /*!< Extend Rx FIFO Mask helper macro Type B lower part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH(id) \ + ((FLEXCAN_ID_EXT(id) & 0x1FE00000) << 3) /*!< Extend Rx FIFO Mask helper macro Type C upper part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_HIGH(id) \ + ((FLEXCAN_ID_EXT(id) & 0x1FE00000) >> \ + 5) /*!< Extend Rx FIFO Mask helper macro Type C mid-upper part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_LOW(id) \ + ((FLEXCAN_ID_EXT(id) & 0x1FE00000) >> \ + 13) /*!< Extend Rx FIFO Mask helper macro Type C mid-lower part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_LOW(id) \ + ((FLEXCAN_ID_EXT(id) & 0x1FE00000) >> 21) /*!< Extend Rx FIFO Mask helper macro Type C lower part helper macro. */ + +/*! @brief FlexCAN Rx FIFO Filter helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_A(id, rtr, ide) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_A(id, rtr, ide) /*!< Standard Rx FIFO Filter helper macro Type A helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_B_HIGH(id, rtr, ide) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_HIGH( \ + id, rtr, ide) /*!< Standard Rx FIFO Filter helper macro Type B upper part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_B_LOW(id, rtr, ide) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_LOW( \ + id, rtr, ide) /*!< Standard Rx FIFO Filter helper macro Type B lower part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_HIGH(id) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_HIGH( \ + id) /*!< Standard Rx FIFO Filter helper macro Type C upper part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_HIGH(id) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_HIGH( \ + id) /*!< Standard Rx FIFO Filter helper macro Type C mid-upper part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_LOW(id) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW( \ + id) /*!< Standard Rx FIFO Filter helper macro Type C mid-lower part helper macro. */ +#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_LOW(id) \ + FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW( \ + id) /*!< Standard Rx FIFO Filter helper macro Type C lower part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_A(id, rtr, ide) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type A helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_HIGH(id, rtr, ide) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH( \ + id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type B upper part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_LOW(id, rtr, ide) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW( \ + id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type B lower part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_HIGH(id) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH( \ + id) /*!< Extend Rx FIFO Filter helper macro Type C upper part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_HIGH(id) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_HIGH( \ + id) /*!< Extend Rx FIFO Filter helper macro Type C mid-upper part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_LOW(id) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_LOW( \ + id) /*!< Extend Rx FIFO Filter helper macro Type C mid-lower part helper macro. */ +#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_LOW(id) \ + FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_LOW(id) /*!< Extend Rx FIFO Filter helper macro Type C lower part helper macro. */ + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! @brief FlexCAN Enhanced Rx FIFO Filter and Mask helper macro. */ +#define ENHANCED_RX_FIFO_FSCH(x) (((uint32_t)(((uint32_t)(x)) << 30)) & 0xC0000000U) +#define RTR_STD_HIGH(x) (((uint32_t)(((uint32_t)(x)) << 27)) & 0x08000000U) +#define RTR_STD_LOW(x) (((uint32_t)(((uint32_t)(x)) << 11)) & 0x00000800U) +#define RTR_EXT(x) (((uint32_t)(((uint32_t)(x)) << 29)) & 0x40000000U) +#define ID_STD_LOW(id) (((uint32_t)id) & 0x7FFU) +#define ID_STD_HIGH(id) (((uint32_t)(((uint32_t)(id)) << 16)) & 0x07FF0000U) +#define ID_EXT(id) (((uint32_t)id) & 0x1FFFFFFFU) + +/*! Standard ID filter element with filter + mask scheme. */ +#define FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(id, rtr, id_mask, rtr_mask) \ + (ENHANCED_RX_FIFO_FSCH(0x0) | RTR_STD_HIGH(rtr) | ID_STD_HIGH(id) | RTR_STD_LOW(rtr_mask) | ID_STD_LOW(id_mask)) +/*! Standard ID filter element with filter range. */ +#define FLEXCAN_ENHANCED_RX_FIFO_STD_FILTER_WITH_RANGE(id_upper, rtr, id_lower, rtr_mask) \ + (ENHANCED_RX_FIFO_FSCH(0x1) | RTR_STD_HIGH(rtr) | ID_STD_HIGH(id_upper) | RTR_STD_LOW(rtr_mask) | \ + ID_STD_LOW(id_lower)) +/*! Standard ID filter element with two filters without masks. */ +#define FLEXCAN_ENHANCED_RX_FIFO_STD_TWO_FILTERS(id1, rtr1, id2, rtr2) \ + (ENHANCED_RX_FIFO_FSCH(0x2) | RTR_STD_HIGH(rtr1) | ID_STD_HIGH(id1) | RTR_STD_LOW(rtr2) | ID_STD_LOW(id2)) +/*! Extended ID filter element with filter + mask scheme low word. */ +#define FLEXCAN_ENHANCED_RX_FIFO_EXT_MASK_AND_FILTER_LOW(id, rtr) \ + (ENHANCED_RX_FIFO_FSCH(0x0) | RTR_EXT(rtr) | ID_EXT(id)) +/*! Extended ID filter element with filter + mask scheme high word. */ +#define FLEXCAN_ENHANCED_RX_FIFO_EXT_MASK_AND_FILTER_HIGH(id_mask, rtr_mask) \ + (ENHANCED_RX_FIFO_FSCH(0x0) | RTR_EXT(rtr_mask) | ID_EXT(id_mask)) +/*! Extended ID filter element with range scheme low word. */ +#define FLEXCAN_ENHANCED_RX_FIFO_EXT_FILTER_WITH_RANGE_LOW(id_upper, rtr) \ + (ENHANCED_RX_FIFO_FSCH(0x1) | RTR_EXT(rtr) | ID_EXT(id_upper)) +/*! Extended ID filter element with range scheme high word. */ +#define FLEXCAN_ENHANCED_RX_FIFO_EXT_FILTER_WITH_RANGE_HIGH(id_lower, rtr_mask) \ + (ENHANCED_RX_FIFO_FSCH(0x1) | RTR_EXT(rtr_mask) | ID_EXT(id_lower)) +/*! Extended ID filter element with two filters without masks low word. */ +#define FLEXCAN_ENHANCED_RX_FIFO_EXT_TWO_FILTERS_LOW(id2, rtr2) \ + (ENHANCED_RX_FIFO_FSCH(0x2) | RTR_EXT(rtr2) | ID_EXT(id2)) +/*! Extended ID filter element with two filters without masks high word. */ +#define FLEXCAN_ENHANCED_RX_FIFO_EXT_TWO_FILTERS_HIGH(id1, rtr1) \ + (ENHANCED_RX_FIFO_FSCH(0x2) | RTR_EXT(rtr1) | ID_EXT(id1)) +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) +/*! @brief FlexCAN Pretended Networking ID Mask helper macro. */ +#define FLEXCAN_PN_STD_MASK(id, rtr) \ + ((uint32_t)((uint32_t)(rtr) << CAN_FLT_ID1_FLT_RTR_SHIFT) | \ + FLEXCAN_ID_STD(id)) /*!< Standard Rx Message Buffer Mask helper macro. */ +#define FLEXCAN_PN_EXT_MASK(id, rtr) \ + ((uint32_t)CAN_FLT_ID1_FLT_IDE_MASK | (uint32_t)((uint32_t)(rtr) << CAN_FLT_ID1_FLT_RTR_SHIFT) | \ + FLEXCAN_ID_EXT(id)) /*!< Extend Rx Message Buffer Mask helper macro. */ +#endif + +/*! @brief FlexCAN interrupt/status flag helper macro. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) +#define FLEXCAN_PN_INT_MASK(x) (((uint64_t)(((uint64_t)(x)) << 32)) & 0x3000000000000U) +#define FLEXCAN_PN_INT_UNMASK(x) (((uint32_t)(((uint64_t)(x)) >> 32)) & 0x00030000U) +#define FLEXCAN_PN_STATUS_MASK(x) (((uint64_t)(((uint64_t)(x)) << 16)) & 0x300000000U) +#define FLEXCAN_PN_STATUS_UNMASK(x) (((uint32_t)(((uint64_t)(x)) >> 16)) & 0x00030000U) +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +#define FLEXCAN_EFIFO_INT_MASK(x) (((uint64_t)(((uint64_t)(x)) << 32)) & 0xF000000000000000U) +#define FLEXCAN_EFIFO_INT_UNMASK(x) (((uint32_t)(((uint64_t)(x)) >> 32)) & 0xF0000000U) +#define FLEXCAN_EFIFO_STATUS_MASK(x) (((uint64_t)(((uint64_t)(x)) << 32)) & 0xF003000000000000U) +#define FLEXCAN_EFIFO_STATUS_UNMASK(x) (((uint32_t)(((uint64_t)(x)) >> 32)) & 0xF0030000U) +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) +#define FLEXCAN_MECR_INT_MASK(x) (((uint64_t)(((uint64_t)(x)) << 16)) & 0xD00000000U) +#define FLEXCAN_MECR_INT_UNMASK(x) (((uint32_t)(((uint64_t)(x)) >> 16)) & 0x000D0000U) +#define FLEXCAN_MECR_STATUS_MASK(x) (((uint64_t)(((uint64_t)(x)) << 34)) & 0x34003400000000U) +#define FLEXCAN_MECR_STATUS_UNMASK(x) (((uint32_t)(((uint64_t)(x)) >> 34)) & 0x000D000DU) +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +#define FLEXCAN_ERROR_AND_STATUS_INIT_FLAG \ + ((uint32_t)kFLEXCAN_ErrorOverrunFlag | (uint32_t)kFLEXCAN_FDErrorIntFlag | (uint32_t)kFLEXCAN_BusoffDoneIntFlag | \ + (uint32_t)kFLEXCAN_TxWarningIntFlag | (uint32_t)kFLEXCAN_RxWarningIntFlag | (uint32_t)kFLEXCAN_BusOffIntFlag | \ + (uint32_t)kFLEXCAN_ErrorIntFlag | FLEXCAN_MEMORY_ERROR_INIT_FLAG) +#else +#define FLEXCAN_ERROR_AND_STATUS_INIT_FLAG \ + ((uint32_t)kFLEXCAN_TxWarningIntFlag | (uint32_t)kFLEXCAN_RxWarningIntFlag | (uint32_t)kFLEXCAN_BusOffIntFlag | \ + (uint32_t)kFLEXCAN_ErrorIntFlag | FLEXCAN_MEMORY_ERROR_INIT_FLAG) +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) +#define FLEXCAN_WAKE_UP_FLAG \ + ((uint32_t)kFLEXCAN_WakeUpIntFlag | (uint64_t)kFLEXCAN_PNMatchIntFlag | (uint64_t)kFLEXCAN_PNTimeoutIntFlag) +#else +#define FLEXCAN_WAKE_UP_FLAG ((uint32_t)kFLEXCAN_WakeUpIntFlag) +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) +#define FLEXCAN_MEMORY_ERROR_INIT_FLAG ((uint64_t)kFLEXCAN_AllMemoryErrorFlag) +#else +#define FLEXCAN_MEMORY_ERROR_INIT_FLAG (0U) +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +#define FLEXCAN_MEMORY_ENHANCED_RX_FIFO_INIT_FLAG \ + ((uint64_t)kFLEXCAN_ERxFifoUnderflowIntFlag | (uint64_t)kFLEXCAN_ERxFifoOverflowIntFlag | \ + (uint64_t)kFLEXCAN_ERxFifoWatermarkIntFlag | (uint64_t)kFLEXCAN_ERxFifoDataAvlIntFlag) +#endif +/*! @brief FlexCAN Enhanced Rx FIFO base address helper macro. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +#define E_RX_FIFO(base) ((uint32_t)(base) + 0x2000U) +#else +#define FLEXCAN_MEMORY_ENHANCED_RX_FIFO_INIT_FLAG (0U) +#endif +/*! @brief FlexCAN transfer status. */ +enum +{ + kStatus_FLEXCAN_TxBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 0), /*!< Tx Message Buffer is Busy. */ + kStatus_FLEXCAN_TxIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 1), /*!< Tx Message Buffer is Idle. */ + kStatus_FLEXCAN_TxSwitchToRx = MAKE_STATUS( + kStatusGroup_FLEXCAN, 2), /*!< Remote Message is send out and Message buffer changed to Receive one. */ + kStatus_FLEXCAN_RxBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 3), /*!< Rx Message Buffer is Busy. */ + kStatus_FLEXCAN_RxIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 4), /*!< Rx Message Buffer is Idle. */ + kStatus_FLEXCAN_RxOverflow = MAKE_STATUS(kStatusGroup_FLEXCAN, 5), /*!< Rx Message Buffer is Overflowed. */ + kStatus_FLEXCAN_RxFifoBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 6), /*!< Rx Message FIFO is Busy. */ + kStatus_FLEXCAN_RxFifoIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 7), /*!< Rx Message FIFO is Idle. */ + kStatus_FLEXCAN_RxFifoOverflow = MAKE_STATUS(kStatusGroup_FLEXCAN, 8), /*!< Rx Message FIFO is overflowed. */ + kStatus_FLEXCAN_RxFifoWarning = MAKE_STATUS(kStatusGroup_FLEXCAN, 9), /*!< Rx Message FIFO is almost overflowed. */ + kStatus_FLEXCAN_RxFifoDisabled = + MAKE_STATUS(kStatusGroup_FLEXCAN, 10), /*!< Rx Message FIFO is disabled during reading. */ + kStatus_FLEXCAN_ErrorStatus = MAKE_STATUS(kStatusGroup_FLEXCAN, 11), /*!< FlexCAN Module Error and Status. */ + kStatus_FLEXCAN_WakeUp = MAKE_STATUS(kStatusGroup_FLEXCAN, 12), /*!< FlexCAN is waken up from STOP mode. */ + kStatus_FLEXCAN_UnHandled = MAKE_STATUS(kStatusGroup_FLEXCAN, 13), /*!< UnHadled Interrupt asserted. */ + kStatus_FLEXCAN_RxRemote = MAKE_STATUS(kStatusGroup_FLEXCAN, 14), /*!< Rx Remote Message Received in Mail box. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + kStatus_FLEXCAN_RxFifoUnderflow = + MAKE_STATUS(kStatusGroup_FLEXCAN, 15), /*!< Enhanced Rx Message FIFO is underflow. */ +#endif +}; + +/*! @brief FlexCAN frame format. */ +typedef enum _flexcan_frame_format +{ + kFLEXCAN_FrameFormatStandard = 0x0U, /*!< Standard frame format attribute. */ + kFLEXCAN_FrameFormatExtend = 0x1U, /*!< Extend frame format attribute. */ +} flexcan_frame_format_t; + +/*! @brief FlexCAN frame type. */ +typedef enum _flexcan_frame_type +{ + kFLEXCAN_FrameTypeData = 0x0U, /*!< Data frame type attribute. */ + kFLEXCAN_FrameTypeRemote = 0x1U, /*!< Remote frame type attribute. */ +} flexcan_frame_type_t; + +/*! @brief FlexCAN clock source. + * @deprecated Do not use the kFLEXCAN_ClkSrcOs. It has been superceded kFLEXCAN_ClkSrc0 + * @deprecated Do not use the kFLEXCAN_ClkSrcPeri. It has been superceded kFLEXCAN_ClkSrc1 + */ +typedef enum _flexcan_clock_source +{ + kFLEXCAN_ClkSrcOsc = 0x0U, /*!< FlexCAN Protocol Engine clock from Oscillator. */ + kFLEXCAN_ClkSrcPeri = 0x1U, /*!< FlexCAN Protocol Engine clock from Peripheral Clock. */ + kFLEXCAN_ClkSrc0 = 0x0U, /*!< FlexCAN Protocol Engine clock selected by user as SRC == 0. */ + kFLEXCAN_ClkSrc1 = 0x1U, /*!< FlexCAN Protocol Engine clock selected by user as SRC == 1. */ +} flexcan_clock_source_t; + +/*! @brief FlexCAN wake up source. */ +typedef enum _flexcan_wake_up_source +{ + kFLEXCAN_WakeupSrcUnfiltered = 0x0U, /*!< FlexCAN uses unfiltered Rx input to detect edge. */ + kFLEXCAN_WakeupSrcFiltered = 0x1U, /*!< FlexCAN uses filtered Rx input to detect edge. */ +} flexcan_wake_up_source_t; + +/*! @brief FlexCAN Rx Fifo Filter type. */ +typedef enum _flexcan_rx_fifo_filter_type +{ + kFLEXCAN_RxFifoFilterTypeA = 0x0U, /*!< One full ID (standard and extended) per ID Filter element. */ + kFLEXCAN_RxFifoFilterTypeB = + 0x1U, /*!< Two full standard IDs or two partial 14-bit ID slices per ID Filter Table element. */ + kFLEXCAN_RxFifoFilterTypeC = + 0x2U, /*!< Four partial 8-bit Standard or extended ID slices per ID Filter Table element. */ + kFLEXCAN_RxFifoFilterTypeD = 0x3U, /*!< All frames rejected. */ +} flexcan_rx_fifo_filter_type_t; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief FlexCAN Message Buffer Payload size. + */ +typedef enum _flexcan_mb_size +{ + kFLEXCAN_8BperMB = 0x0U, /*!< Selects 8 bytes per Message Buffer. */ + kFLEXCAN_16BperMB = 0x1U, /*!< Selects 16 bytes per Message Buffer. */ + kFLEXCAN_32BperMB = 0x2U, /*!< Selects 32 bytes per Message Buffer. */ + kFLEXCAN_64BperMB = 0x3U, /*!< Selects 64 bytes per Message Buffer. */ +} flexcan_mb_size_t; + +/*! + * @brief FlexCAN CAN FD frame supporting data length (available DLC values). + * + * For Tx, when the Data size corresponding to DLC value stored in the MB selected for transmission is larger than the + * MB Payload size, FlexCAN adds the necessary number of bytes with constant 0xCC pattern to complete the expected DLC. + * For Rx, when the Data size corresponding to DLC value received from the CAN bus is larger than the MB Payload size, + * the high order bytes that do not fit the Payload size will lose. + */ +enum _flexcan_fd_frame_length +{ + kFLEXCAN_0BperFrame = 0x0U, /*!< Frame contains 0 valid data bytes. */ + kFLEXCAN_1BperFrame, /*!< Frame contains 1 valid data bytes. */ + kFLEXCAN_2BperFrame, /*!< Frame contains 2 valid data bytes. */ + kFLEXCAN_3BperFrame, /*!< Frame contains 3 valid data bytes. */ + kFLEXCAN_4BperFrame, /*!< Frame contains 4 valid data bytes. */ + kFLEXCAN_5BperFrame, /*!< Frame contains 5 valid data bytes. */ + kFLEXCAN_6BperFrame, /*!< Frame contains 6 valid data bytes. */ + kFLEXCAN_7BperFrame, /*!< Frame contains 7 valid data bytes. */ + kFLEXCAN_8BperFrame, /*!< Frame contains 8 valid data bytes. */ + kFLEXCAN_12BperFrame, /*!< Frame contains 12 valid data bytes. */ + kFLEXCAN_16BperFrame, /*!< Frame contains 16 valid data bytes. */ + kFLEXCAN_20BperFrame, /*!< Frame contains 20 valid data bytes. */ + kFLEXCAN_24Bperrame, /*!< Frame contains 24 valid data bytes. */ + kFLEXCAN_32BperFrame, /*!< Frame contains 32 valid data bytes. */ + kFLEXCAN_48BperFrame, /*!< Frame contains 48 valid data bytes. */ + kFLEXCAN_64BperFrame, /*!< Frame contains 64 valid data bytes. */ +}; +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! @brief FlexCAN Enhanced Rx Fifo DMA transfer per read length enumerations. */ +typedef enum _flexcan_efifo_dma_per_read_length +{ + kFLEXCAN_1WordPerRead = 0x0U, /*!< Transfer 1 32-bit words (CS).*/ + kFLEXCAN_2WordPerRead, /*!< Transfer 2 32-bit words (CS + ID).*/ + kFLEXCAN_3WordPerRead, /*!< Transfer 3 32-bit words (CS + ID + 1~4 bytes data).*/ + kFLEXCAN_4WordPerRead, /*!< Transfer 4 32-bit words (CS + ID + 5~8 bytes data).*/ + kFLEXCAN_5WordPerRead, /*!< Transfer 5 32-bit words (CS + ID + 9~12 bytes data).*/ + kFLEXCAN_6WordPerRead, /*!< Transfer 6 32-bit words (CS + ID + 13~16 bytes data).*/ + kFLEXCAN_7WordPerRead, /*!< Transfer 7 32-bit words (CS + ID + 17~20 bytes data).*/ + kFLEXCAN_8WordPerRead, /*!< Transfer 8 32-bit words (CS + ID + 21~24 bytes data).*/ + kFLEXCAN_9WordPerRead, /*!< Transfer 9 32-bit words (CS + ID + 25~28 bytes data).*/ + kFLEXCAN_10WordPerRead, /*!< Transfer 10 32-bit words (CS + ID + 29~32 bytes data).*/ + kFLEXCAN_11WordPerRead, /*!< Transfer 11 32-bit words (CS + ID + 33~36 bytes data).*/ + kFLEXCAN_12WordPerRead, /*!< Transfer 12 32-bit words (CS + ID + 37~40 bytes data).*/ + kFLEXCAN_13WordPerRead, /*!< Transfer 13 32-bit words (CS + ID + 41~44 bytes data).*/ + kFLEXCAN_14WordPerRead, /*!< Transfer 14 32-bit words (CS + ID + 45~48 bytes data).*/ + kFLEXCAN_15WordPerRead, /*!< Transfer 15 32-bit words (CS + ID + 49~52 bytes data).*/ + kFLEXCAN_16WordPerRead, /*!< Transfer 16 32-bit words (CS + ID + 53~56 bytes data).*/ + kFLEXCAN_17WordPerRead, /*!< Transfer 17 32-bit words (CS + ID + 57~60 bytes data).*/ + kFLEXCAN_18WordPerRead, /*!< Transfer 18 32-bit words (CS + ID + 61~64 bytes data).*/ + kFLEXCAN_19WordPerRead /*!< Transfer 19 32-bit words (CS + ID + 64 bytes data + ID HIT).*/ +} flexcan_efifo_dma_per_read_length_t; +#endif + +/*! + * @brief FlexCAN Enhanced/Legacy Rx FIFO priority. + * + * The matching process starts from the Rx MB(or Enhanced/Legacy Rx FIFO) with higher priority. + * If no MB(or Enhanced/Legacy Rx FIFO filter) is satisfied, the matching process goes on with + * the Enhanced/Legacy Rx FIFO(or Rx MB) with lower priority. + */ +typedef enum _flexcan_rx_fifo_priority +{ + kFLEXCAN_RxFifoPrioLow = 0x0U, /*!< Matching process start from Rx Message Buffer first. */ + kFLEXCAN_RxFifoPrioHigh = 0x1U, /*!< Matching process start from Enhanced/Legacy Rx FIFO first. */ +} flexcan_rx_fifo_priority_t; + +/*! + * @brief FlexCAN interrupt enable enumerations. + * + * This provides constants for the FlexCAN interrupt enable enumerations for use in the FlexCAN functions. + * @note FlexCAN Message Buffers and Legacy Rx FIFO interrupts not included in. + */ +enum _flexcan_interrupt_enable +{ + kFLEXCAN_BusOffInterruptEnable = CAN_CTRL1_BOFFMSK_MASK, /*!< Bus Off interrupt, use bit 15. */ + kFLEXCAN_ErrorInterruptEnable = CAN_CTRL1_ERRMSK_MASK, /*!< CAN Error interrupt, use bit 14. */ + kFLEXCAN_TxWarningInterruptEnable = CAN_CTRL1_TWRNMSK_MASK, /*!< Tx Warning interrupt, use bit 11. */ + kFLEXCAN_RxWarningInterruptEnable = CAN_CTRL1_RWRNMSK_MASK, /*!< Rx Warning interrupt, use bit 10. */ + kFLEXCAN_WakeUpInterruptEnable = CAN_MCR_WAKMSK_MASK, /*!< Self Wake Up interrupt, use bit 26. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + kFLEXCAN_FDErrorInterruptEnable = CAN_CTRL2_ERRMSK_FAST_MASK, /*!< CAN FD Error interrupt, use bit 31. */ +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) + /*! PN Match Wake Up interrupt, use high word bit 17. */ + kFLEXCAN_PNMatchWakeUpInterruptEnable = FLEXCAN_PN_INT_MASK(CAN_CTRL1_PN_WTOF_MSK_MASK), + /*! PN Timeout Wake Up interrupt, use high word bit 16. */ + kFLEXCAN_PNTimeoutWakeUpInterruptEnable = FLEXCAN_PN_INT_MASK(CAN_CTRL1_PN_WUMF_MSK_MASK), +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + /*!< Enhanced Rx FIFO Underflow interrupt, use high word bit 31. */ + kFLEXCAN_ERxFifoUnderflowInterruptEnable = FLEXCAN_EFIFO_INT_MASK(CAN_ERFIER_ERFUFWIE_MASK), + /*!< Enhanced Rx FIFO Overflow interrupt, use high word bit 30. */ + kFLEXCAN_ERxFifoOverflowInterruptEnable = FLEXCAN_EFIFO_INT_MASK(CAN_ERFIER_ERFOVFIE_MASK), + /*!< Enhanced Rx FIFO Watermark interrupt, use high word bit 29. */ + kFLEXCAN_ERxFifoWatermarkInterruptEnable = FLEXCAN_EFIFO_INT_MASK(CAN_ERFIER_ERFWMIIE_MASK), + /*!< Enhanced Rx FIFO Data Avilable interrupt, use high word bit 28. */ + kFLEXCAN_ERxFifoDataAvlInterruptEnable = FLEXCAN_EFIFO_INT_MASK(CAN_ERFIER_ERFDAIE_MASK), +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + /*! Host Access With Non-Correctable Errors interrupt, use high word bit 0. */ + kFLEXCAN_HostAccessNCErrorInterruptEnable = FLEXCAN_MECR_INT_MASK(CAN_MECR_HANCEI_MSK_MASK), + /*! FlexCAN Access With Non-Correctable Errors interrupt, use high word bit 2. */ + kFLEXCAN_FlexCanAccessNCErrorInterruptEnable = FLEXCAN_MECR_INT_MASK(CAN_MECR_FANCEI_MSK_MASK), + /*! Host or FlexCAN Access With Correctable Errors interrupt, use high word bit 3. */ + kFLEXCAN_HostOrFlexCanCErrorInterruptEnable = FLEXCAN_MECR_INT_MASK(CAN_MECR_CEI_MSK_MASK), +#endif +}; + +/*! + * @brief FlexCAN status flags. + * + * This provides constants for the FlexCAN status flags for use in the FlexCAN functions. + * @note The CPU read action clears the bits corresponding to the FlEXCAN_ErrorFlag macro, therefore user need to + * read status flags and distinguish which error is occur using @ref _flexcan_error_flags enumerations. + */ +enum _flexcan_flags +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + kFLEXCAN_ErrorOverrunFlag = CAN_ESR1_ERROVR_MASK, /*!< Error Overrun Status. */ + kFLEXCAN_FDErrorIntFlag = CAN_ESR1_ERRINT_FAST_MASK, /*!< CAN FD Error Interrupt Flag. */ + kFLEXCAN_BusoffDoneIntFlag = CAN_ESR1_BOFFDONEINT_MASK, /*!< Bus Off process completed Interrupt Flag. */ +#endif + kFLEXCAN_SynchFlag = CAN_ESR1_SYNCH_MASK, /*!< CAN Synchronization Status. */ + kFLEXCAN_TxWarningIntFlag = CAN_ESR1_TWRNINT_MASK, /*!< Tx Warning Interrupt Flag. */ + kFLEXCAN_RxWarningIntFlag = CAN_ESR1_RWRNINT_MASK, /*!< Rx Warning Interrupt Flag. */ + kFLEXCAN_IdleFlag = CAN_ESR1_IDLE_MASK, /*!< FlexCAN In IDLE Status. */ + kFLEXCAN_FaultConfinementFlag = CAN_ESR1_FLTCONF_MASK, /*!< FlexCAN Fault Confinement State. */ + kFLEXCAN_TransmittingFlag = CAN_ESR1_TX_MASK, /*!< FlexCAN In Transmission Status. */ + kFLEXCAN_ReceivingFlag = CAN_ESR1_RX_MASK, /*!< FlexCAN In Reception Status. */ + kFLEXCAN_BusOffIntFlag = CAN_ESR1_BOFFINT_MASK, /*!< Bus Off Interrupt Flag. */ + kFLEXCAN_ErrorIntFlag = CAN_ESR1_ERRINT_MASK, /*!< CAN Error Interrupt Flag. */ + kFLEXCAN_WakeUpIntFlag = CAN_ESR1_WAKINT_MASK, /*!< Self Wake-Up Interrupt Flag. */ + kFLEXCAN_ErrorFlag = + (uint32_t)(/*!< All FlexCAN Read Clear Error Status. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + CAN_ESR1_STFERR_FAST_MASK | CAN_ESR1_FRMERR_FAST_MASK | CAN_ESR1_CRCERR_FAST_MASK | + CAN_ESR1_BIT0ERR_FAST_MASK | CAN_ESR1_BIT1ERR_FAST_MASK | CAN_ESR1_ERROVR_MASK | +#endif + CAN_ESR1_TXWRN_MASK | CAN_ESR1_RXWRN_MASK | CAN_ESR1_BIT1ERR_MASK | CAN_ESR1_BIT0ERR_MASK | + CAN_ESR1_ACKERR_MASK | CAN_ESR1_CRCERR_MASK | CAN_ESR1_FRMERR_MASK | CAN_ESR1_STFERR_MASK), +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) + kFLEXCAN_PNMatchIntFlag = FLEXCAN_PN_STATUS_MASK(CAN_WU_MTC_WUMF_MASK), /*!< PN Matching Event Interrupt Flag. */ + kFLEXCAN_PNTimeoutIntFlag = FLEXCAN_PN_STATUS_MASK(CAN_WU_MTC_WTOF_MASK), /*!< PN Timeout Event Interrupt Flag. */ +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + kFLEXCAN_ERxFifoUnderflowIntFlag = + FLEXCAN_EFIFO_STATUS_MASK(CAN_ERFSR_ERFUFW_MASK), /*!< Enhanced Rx FIFO underflow Interrupt Flag. */ + kFLEXCAN_ERxFifoOverflowIntFlag = + FLEXCAN_EFIFO_STATUS_MASK(CAN_ERFSR_ERFOVF_MASK), /*!< Enhanced Rx FIFO overflow Interrupt Flag. */ + kFLEXCAN_ERxFifoWatermarkIntFlag = + FLEXCAN_EFIFO_STATUS_MASK(CAN_ERFSR_ERFWMI_MASK), /*!< Enhanced Rx FIFO watermark Interrupt Flag. */ + kFLEXCAN_ERxFifoDataAvlIntFlag = + FLEXCAN_EFIFO_STATUS_MASK(CAN_ERFSR_ERFDA_MASK), /*!< Enhanced Rx FIFO data available Interrupt Flag. */ + kFLEXCAN_ERxFifoEmptyFlag = FLEXCAN_EFIFO_STATUS_MASK(CAN_ERFSR_ERFE_MASK), /*!< Enhanced Rx FIFO empty status. */ + kFLEXCAN_ERxFifoFullFlag = FLEXCAN_EFIFO_STATUS_MASK(CAN_ERFSR_ERFF_MASK), /*!< Enhanced Rx FIFO full status. */ +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + /*! Host Access With Non-Correctable Error Interrupt Flag. */ + kFLEXCAN_HostAccessNonCorrectableErrorIntFlag = FLEXCAN_MECR_INT_MASK(CAN_ERRSR_HANCEIF_MASK), + /*! FlexCAN Access With Non-Correctable Error Interrupt Flag. */ + kFLEXCAN_FlexCanAccessNonCorrectableErrorIntFlag = FLEXCAN_MECR_INT_MASK(CAN_ERRSR_FANCEIF_MASK), + /*! Correctable Error Interrupt Flag. */ + kFLEXCAN_CorrectableErrorIntFlag = FLEXCAN_MECR_INT_MASK(CAN_ERRSR_CEIF_MASK), + /*! Host Access With Non-Correctable Error Interrupt Overrun Flag. */ + kFLEXCAN_HostAccessNonCorrectableErrorOverrunFlag = FLEXCAN_MECR_INT_MASK(CAN_ERRSR_HANCEIOF_MASK), + /*! FlexCAN Access With Non-Correctable Error Interrupt Overrun Flag. */ + kFLEXCAN_FlexCanAccessNonCorrectableErrorOverrunFlag = FLEXCAN_MECR_INT_MASK(CAN_ERRSR_FANCEIOF_MASK), + /*! Correctable Error Interrupt Overrun Flag. */ + kFLEXCAN_CorrectableErrorOverrunFlag = FLEXCAN_MECR_INT_MASK(CAN_ERRSR_CEIOF_MASK), + /*! All Memory Error Flags. */ + kFLEXCAN_AllMemoryErrorFlag = + (kFLEXCAN_HostAccessNonCorrectableErrorIntFlag | kFLEXCAN_FlexCanAccessNonCorrectableErrorIntFlag | + kFLEXCAN_CorrectableErrorIntFlag | kFLEXCAN_HostAccessNonCorrectableErrorOverrunFlag | + kFLEXCAN_FlexCanAccessNonCorrectableErrorOverrunFlag | kFLEXCAN_CorrectableErrorOverrunFlag) +#endif +}; + +/*! + * @brief FlexCAN error status flags. + * + * The FlexCAN Error Status enumerations is used to report current error of the FlexCAN bus. + * This enumerations should be used with KFLEXCAN_ErrorFlag in @ref _flexcan_flags enumerations + * to ditermine which error is generated. + */ +enum _flexcan_error_flags +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + kFLEXCAN_FDStuffingError = CAN_ESR1_STFERR_FAST_MASK, /*!< Stuffing Error. */ + kFLEXCAN_FDFormError = CAN_ESR1_FRMERR_FAST_MASK, /*!< Form Error. */ + kFLEXCAN_FDCrcError = CAN_ESR1_CRCERR_FAST_MASK, /*!< Cyclic Redundancy Check Error. */ + kFLEXCAN_FDBit0Error = CAN_ESR1_BIT0ERR_FAST_MASK, /*!< Unable to send dominant bit. */ + kFLEXCAN_FDBit1Error = (int)CAN_ESR1_BIT1ERR_FAST_MASK, /*!< Unable to send recessive bit. */ +#endif + kFLEXCAN_TxErrorWarningFlag = CAN_ESR1_TXWRN_MASK, /*!< Tx Error Warning Status. */ + kFLEXCAN_RxErrorWarningFlag = CAN_ESR1_RXWRN_MASK, /*!< Rx Error Warning Status. */ + kFLEXCAN_StuffingError = CAN_ESR1_STFERR_MASK, /*!< Stuffing Error. */ + kFLEXCAN_FormError = CAN_ESR1_FRMERR_MASK, /*!< Form Error. */ + kFLEXCAN_CrcError = CAN_ESR1_CRCERR_MASK, /*!< Cyclic Redundancy Check Error. */ + kFLEXCAN_AckError = CAN_ESR1_ACKERR_MASK, /*!< Received no ACK on transmission. */ + kFLEXCAN_Bit0Error = CAN_ESR1_BIT0ERR_MASK, /*!< Unable to send dominant bit. */ + kFLEXCAN_Bit1Error = CAN_ESR1_BIT1ERR_MASK, /*!< Unable to send recessive bit. */ +}; + +/*! + * @brief FlexCAN Legacy Rx FIFO status flags. + * + * The FlexCAN Legacy Rx FIFO Status enumerations are used to determine the status of the + * Rx FIFO. Because Rx FIFO occupy the MB0 ~ MB7 (Rx Fifo filter also occupies + * more Message Buffer space), Rx FIFO status flags are mapped to the corresponding + * Message Buffer status flags. + */ +enum +{ + kFLEXCAN_RxFifoOverflowFlag = CAN_IFLAG1_BUF7I_MASK, /*!< Rx FIFO overflow flag. */ + kFLEXCAN_RxFifoWarningFlag = CAN_IFLAG1_BUF6I_MASK, /*!< Rx FIFO almost full flag. */ + kFLEXCAN_RxFifoFrameAvlFlag = CAN_IFLAG1_BUF5I_MASK, /*!< Frames available in Rx FIFO flag. */ +}; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) +/*! + * @brief FlexCAN Memory Error Type. + */ +typedef enum _flexcan_memory_error_type +{ + kFLEXCAN_CorrectableError = 0U, /*!< The memory error is correctable which means on bit error. */ + kFLEXCAN_NonCorrectableError /*!< The memory error is non-correctable which means two bit errors. */ +} flexcan_memory_error_type_t; + +/*! + * @brief FlexCAN Memory Access Type. + */ +typedef enum _flexcan_memory_access_type +{ + kFLEXCAN_MoveOutFlexCanAccess = 0U, /*!< The memory error was detected during move-out FlexCAN access. */ + kFLEXCAN_MoveInAccess, /*!< The memory error was detected during move-in FlexCAN access. */ + kFLEXCAN_TxArbitrationAccess, /*!< The memory error was detected during Tx Arbitration FlexCAN access. */ + kFLEXCAN_RxMatchingAccess, /*!< The memory error was detected during Rx Matching FlexCAN access. */ + kFLEXCAN_MoveOutHostAccess /*!< The memory error was detected during Rx Matching Host (CPU) access. */ +} flexcan_memory_access_type_t; + +/*! + * @brief FlexCAN Memory Error Byte Syndrome. + */ +typedef enum _flexcan_byte_error_syndrome +{ + kFLEXCAN_NoError = 0U, /*!< No bit error in this byte. */ + kFLEXCAN_ParityBits0Error = 1U, /*!< Parity bit 0 error in this byte. */ + kFLEXCAN_ParityBits1Error = 2U, /*!< Parity bit 1 error in this byte. */ + kFLEXCAN_ParityBits2Error = 4U, /*!< Parity bit 2 error in this byte. */ + kFLEXCAN_ParityBits3Error = 8U, /*!< Parity bit 3 error in this byte. */ + kFLEXCAN_ParityBits4Error = 16U, /*!< Parity bit 4 error in this byte. */ + kFLEXCAN_DataBits0Error = 28U, /*!< Data bit 0 error in this byte. */ + kFLEXCAN_DataBits1Error = 22U, /*!< Data bit 1 error in this byte. */ + kFLEXCAN_DataBits2Error = 19U, /*!< Data bit 2 error in this byte. */ + kFLEXCAN_DataBits3Error = 25U, /*!< Data bit 3 error in this byte. */ + kFLEXCAN_DataBits4Error = 26U, /*!< Data bit 4 error in this byte. */ + kFLEXCAN_DataBits5Error = 7U, /*!< Data bit 5 error in this byte. */ + kFLEXCAN_DataBits6Error = 21U, /*!< Data bit 6 error in this byte. */ + kFLEXCAN_DataBits7Error = 14U, /*!< Data bit 7 error in this byte. */ + kFLEXCAN_AllZeroError = 6U, /*!< All-zeros non-correctable error in this byte. */ + kFLEXCAN_AllOneError = 31U, /*!< All-ones non-correctable error in this byte. */ + kFLEXCAN_NonCorrectableErrors /*!< Non-correctable error in this byte. */ +} flexcan_byte_error_syndrome_t; + +/*! + * @brief FlexCAN memory error register status structure + * + * This structure contains the memory access properties that caused a memory error access. + * It is used as the parameter of FLEXCAN_GetMemoryErrorReportStatus() function. And user can + * use FLEXCAN_GetMemoryErrorReportStatus to get the status of the last memory error access. + */ +typedef struct _flexcan_memory_error_report_status +{ + flexcan_memory_error_type_t errorType; /*!< The type of memory error that giving rise to the report. */ + flexcan_memory_access_type_t accessType; /*!< The type of memory access that giving rise to the memory error. */ + uint16_t accessAddress; /*!< The address where memory error detected. */ + uint32_t errorData; /*!< The raw data word read from memory with error. */ + struct + { + bool byteIsRead; /*!< The byte n (0~3) was read or not. */ + /*!< The type of error and which bit in byte (n) is affected by the error. */ + flexcan_byte_error_syndrome_t bitAffected; + } byteStatus[4]; +} flexcan_memory_error_report_status_t; +#endif + +#if defined(__CC_ARM) +#pragma anon_unions +#endif +/*! @brief FlexCAN message frame structure. */ +typedef struct _flexcan_frame +{ + struct + { + uint32_t timestamp : 16; /*!< FlexCAN internal Free-Running Counter Time Stamp. */ + uint32_t length : 4; /*!< CAN frame data length in bytes (Range: 0~8). */ + uint32_t type : 1; /*!< CAN Frame Type(DATA or REMOTE). */ + uint32_t format : 1; /*!< CAN Frame Identifier(STD or EXT format). */ + uint32_t : 1; /*!< Reserved. */ + uint32_t idhit : 9; /*!< CAN Rx FIFO filter hit id(This value is only used in Rx FIFO receive mode). */ + }; + struct + { + uint32_t id : 29; /*!< CAN Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro. */ + uint32_t : 3; /*!< Reserved. */ + }; + union + { + struct + { + uint32_t dataWord0; /*!< CAN Frame payload word0. */ + uint32_t dataWord1; /*!< CAN Frame payload word1. */ + }; + struct + { + uint8_t dataByte3; /*!< CAN Frame payload byte3. */ + uint8_t dataByte2; /*!< CAN Frame payload byte2. */ + uint8_t dataByte1; /*!< CAN Frame payload byte1. */ + uint8_t dataByte0; /*!< CAN Frame payload byte0. */ + uint8_t dataByte7; /*!< CAN Frame payload byte7. */ + uint8_t dataByte6; /*!< CAN Frame payload byte6. */ + uint8_t dataByte5; /*!< CAN Frame payload byte5. */ + uint8_t dataByte4; /*!< CAN Frame payload byte4. */ + }; + }; +} flexcan_frame_t; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! @brief CAN FD message frame structure. + * + * The CAN FD message supporting up to sixty four bytes can be used for a data frame, depending on the length + * selected for the message buffers. The length should be a enumeration member, see @ref _flexcan_fd_frame_length. + */ +typedef struct _flexcan_fd_frame +{ + struct + { + uint32_t timestamp : 16; /*!< FlexCAN internal Free-Running Counter Time Stamp. */ + uint32_t length : 4; /*!< CAN FD frame data length code (DLC), range see @ref _flexcan_fd_frame_length, When the + length <= 8, it equal to the data length, otherwise the number of valid frame data is + not equal to the length value. user can + use DLC_LENGTH_DECODE(length) macro to get the number of valid data bytes. */ + uint32_t type : 1; /*!< CAN Frame Type(DATA or REMOTE). */ + uint32_t format : 1; /*!< CAN Frame Identifier(STD or EXT format). */ + uint32_t srr : 1; /*!< Substitute Remote request. */ + uint32_t : 6; + uint32_t esi : 1; /*!< Error State Indicator. */ + uint32_t brs : 1; /*!< Bit Rate Switch. */ + uint32_t edl : 1; /*!< Extended Data Length. */ + }; + struct + { + uint32_t id : 29; /*!< CAN Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro. */ + uint32_t : 3; /*!< Reserved. */ + }; + union + { + struct + { + uint32_t dataWord[16]; /*!< CAN FD Frame payload, 16 double word maximum. */ + }; + /* Note: the maximum databyte* below is actually 64, user can add them if needed, + or just use dataWord[*] instead. */ + struct + { + uint8_t dataByte3; /*!< CAN Frame payload byte3. */ + uint8_t dataByte2; /*!< CAN Frame payload byte2. */ + uint8_t dataByte1; /*!< CAN Frame payload byte1. */ + uint8_t dataByte0; /*!< CAN Frame payload byte0. */ + uint8_t dataByte7; /*!< CAN Frame payload byte7. */ + uint8_t dataByte6; /*!< CAN Frame payload byte6. */ + uint8_t dataByte5; /*!< CAN Frame payload byte5. */ + uint8_t dataByte4; /*!< CAN Frame payload byte4. */ + }; + }; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + /*! @note ID HIT offset is changed dynamically according to data length code (DLC), when DLC is 15, they will be + * located below. Using FLEXCAN_FixEnhancedRxFifoFrameIdHit API is recommended to ensure this idhit value is + * correct.*/ + uint32_t idhit; /*!< CAN Enhanced Rx FIFO filter hit id (This value is only used in Enhanced Rx FIFO receive + mode). */ +#endif +} flexcan_fd_frame_t; +#endif + +/*! @brief FlexCAN protocol timing characteristic configuration structure. */ +typedef struct _flexcan_timing_config +{ + uint16_t preDivider; /*!< Classic CAN or CAN FD nominal phase bit rate prescaler. */ + uint8_t rJumpwidth; /*!< Classic CAN or CAN FD nominal phase Re-sync Jump Width. */ + uint8_t phaseSeg1; /*!< Classic CAN or CAN FD nominal phase Segment 1. */ + uint8_t phaseSeg2; /*!< Classic CAN or CAN FD nominal phase Segment 2. */ + uint8_t propSeg; /*!< Classic CAN or CAN FD nominal phase Propagation Segment. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + uint16_t fpreDivider; /*!< CAN FD data phase bit rate prescaler. */ + uint8_t frJumpwidth; /*!< CAN FD data phase Re-sync Jump Width. */ + uint8_t fphaseSeg1; /*!< CAN FD data phase Phase Segment 1. */ + uint8_t fphaseSeg2; /*!< CAN FD data phase Phase Segment 2. */ + uint8_t fpropSeg; /*!< CAN FD data phase Propagation Segment. */ +#endif +} flexcan_timing_config_t; + +/*! @brief FlexCAN module configuration structure. + * @deprecated Do not use the baudRate. It has been superceded bitRate + * @deprecated Do not use the baudRateFD. It has been superceded bitRateFD + */ +typedef struct _flexcan_config +{ + union + { + struct + { + uint32_t baudRate; /*!< FlexCAN bit rate in bps, for classical CAN or CANFD nominal phase. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + uint32_t baudRateFD; /*!< FlexCAN FD bit rate in bps, for CANFD data phase. */ +#endif + }; + struct + { + uint32_t bitRate; /*!< FlexCAN bit rate in bps, for classical CAN or CANFD nominal phase. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + uint32_t bitRateFD; /*!< FlexCAN FD bit rate in bps, for CANFD data phase. */ +#endif + }; + }; + flexcan_clock_source_t clkSrc; /*!< Clock source for FlexCAN Protocol Engine. */ + flexcan_wake_up_source_t wakeupSrc; /*!< Wake up source selection. */ + uint8_t maxMbNum; /*!< The maximum number of Message Buffers used by user. */ + bool enableLoopBack; /*!< Enable or Disable Loop Back Self Test Mode. */ + bool enableTimerSync; /*!< Enable or Disable Timer Synchronization. */ + bool enableSelfWakeup; /*!< Enable or Disable Self Wakeup Mode. */ + bool enableIndividMask; /*!< Enable or Disable Rx Individual Mask and Queue feature. */ + bool disableSelfReception; /*!< Enable or Disable Self Reflection. */ + bool enableListenOnlyMode; /*!< Enable or Disable Listen Only Mode. */ +#if !(defined(FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT) + bool enableSupervisorMode; /*!< Enable or Disable Supervisor Mode, enable this mode will make registers allow only + Supervisor access. */ +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) + bool enableDoze; /*!< Enable or Disable Doze Mode. */ +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) + bool enablePretendedeNetworking; /*!< Enable or Disable the Pretended Networking mode. */ +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + bool enableMemoryErrorControl; /*!< Enable or Disable the memory errors detection and correction mechanism. */ + bool enableNonCorrectableErrorEnterFreeze; /*!< Enable or Disable Non-Correctable Errors In FlexCAN Access Put + Device In Freeze Mode. */ +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) + bool enableTransceiverDelayMeasure; /*!< Enable or Disable the transceiver delay measurement, when it is enabled, + then the secondary sample point position is determined by the sum of the + transceiver delay measurement plus the enhanced TDC offset. */ +#endif + flexcan_timing_config_t timingConfig; /* Protocol timing . */ +} flexcan_config_t; + +/*! + * @brief FlexCAN Receive Message Buffer configuration structure + * + * This structure is used as the parameter of FLEXCAN_SetRxMbConfig() function. + * The FLEXCAN_SetRxMbConfig() function is used to configure FlexCAN Receive + * Message Buffer. The function abort previous receiving process, clean the + * Message Buffer and activate the Rx Message Buffer using given Message Buffer + * setting. + */ +typedef struct _flexcan_rx_mb_config +{ + uint32_t id; /*!< CAN Message Buffer Frame Identifier, should be set using + FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro. */ + flexcan_frame_format_t format; /*!< CAN Frame Identifier format(Standard of Extend). */ + flexcan_frame_type_t type; /*!< CAN Frame Type(Data or Remote). */ +} flexcan_rx_mb_config_t; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) +/*! @brief FlexCAN Pretended Networking match source selection. */ +typedef enum _flexcan_pn_match_source +{ + kFLEXCAN_PNMatSrcID = 0U, /*!< Message match with ID filtering. */ + kFLEXCAN_PNMatSrcIDAndData, /*!< Message match with ID filtering and payload filtering. */ +} flexcan_pn_match_source_t; + +/*! @brief FlexCAN Pretended Networking mode match type. */ +typedef enum _flexcan_pn_match_mode +{ + kFLEXCAN_PNMatModeEqual = 0x0U, /*!< Match upon ID/Payload contents against an exact target value. */ + kFLEXCAN_PNMatModeGreater, /*!< Match upon an ID/Payload value greater than or equal to a specified target value. + */ + kFLEXCAN_PNMatModeSmaller, /*!< Match upon an ID/Payload value smaller than or equal to a specified target value. + */ + kFLEXCAN_PNMatModeRange, /*!< Match upon an ID/Payload value inside a range, greater than or equal to a specified + lower limit, and smaller than or equal to a specified upper limit */ +} flexcan_pn_match_mode_t; + +/*! + * @brief FlexCAN Pretended Networking configuration structure + * + * This structure is used as the parameter of FLEXCAN_SetPNConfig() function. + * The FLEXCAN_SetPNConfig() function is used to configure FlexCAN Networking work mode. + */ +typedef struct _flexcan_pn_config +{ + bool enableTimeout; /*!< Enable or Disable timeout event trigger wakeup.*/ + uint16_t timeoutValue; /*!< The timeout value that generates a wakeup event, the counter timer is incremented based + on 64 times the CAN Bit Time unit. */ + bool enableMatch; /*!< Enable or Disable match event trigger wakeup.*/ + flexcan_pn_match_source_t matchSrc; /*!< Selects the match source (ID and/or data match) to trigger wakeup. */ + uint8_t matchNum; /*!< The number of times a given message must match the predefined ID and/or data before + generating a wakeup event, range in 0x1 ~ 0xFF. */ + flexcan_pn_match_mode_t idMatchMode; /*!< The ID match type. */ + flexcan_pn_match_mode_t dataMatchMode; /*!< The data match type. */ + uint32_t idLower; /*!< The ID target values 1 which used either for ID match "equal to", "smaller than", + "greater than" comparisons, or as the lower limit value in ID match "range detection". */ + uint32_t idUpper; /*!< The ID target values 2 which used only as the upper limit value in ID match "range + detection" or used to store the ID mask in "equal to". */ + uint8_t lengthLower; /*!< The lower limit for length of data bytes which used only in data match "range + detection". Range in 0x0 ~ 0x8.*/ + uint8_t lengthUpper; /*!< The upper limit for length of data bytes which used only in data match "range + detection". Range in 0x0 ~ 0x8.*/ + union + { + /*!< The data target values 1 which used either for data match "equal to", "smaller than", + "greater than" comparisons, or as the lower limit value in data match "range + detection". */ + struct + { + uint32_t lowerWord0; /*!< CAN Frame payload word0. */ + uint32_t lowerWord1; /*!< CAN Frame payload word1. */ + }; + struct + { + uint8_t lowerByte3; /*!< CAN Frame payload byte3. */ + uint8_t lowerByte2; /*!< CAN Frame payload byte2. */ + uint8_t lowerByte1; /*!< CAN Frame payload byte1. */ + uint8_t lowerByte0; /*!< CAN Frame payload byte0. */ + uint8_t lowerByte7; /*!< CAN Frame payload byte7. */ + uint8_t lowerByte6; /*!< CAN Frame payload byte6. */ + uint8_t lowerByte5; /*!< CAN Frame payload byte5. */ + uint8_t lowerByte4; /*!< CAN Frame payload byte4. */ + }; + }; + union + { + /*!< The data target values 2 which used only as the upper limit value in data match "range + detection" or used to store the data mask in "equal to". */ + struct + { + uint32_t upperWord0; /*!< CAN Frame payload word0. */ + uint32_t upperWord1; /*!< CAN Frame payload word1. */ + }; + struct + { + uint8_t upperByte3; /*!< CAN Frame payload byte3. */ + uint8_t upperByte2; /*!< CAN Frame payload byte2. */ + uint8_t upperByte1; /*!< CAN Frame payload byte1. */ + uint8_t upperByte0; /*!< CAN Frame payload byte0. */ + uint8_t upperByte7; /*!< CAN Frame payload byte7. */ + uint8_t upperByte6; /*!< CAN Frame payload byte6. */ + uint8_t upperByte5; /*!< CAN Frame payload byte5. */ + uint8_t upperByte4; /*!< CAN Frame payload byte4. */ + }; + }; +} flexcan_pn_config_t; +#endif + +/*! @brief FlexCAN Legacy Rx FIFO configuration structure. */ +typedef struct _flexcan_rx_fifo_config +{ + uint32_t *idFilterTable; /*!< Pointer to the FlexCAN Legacy Rx FIFO identifier filter table. */ + uint8_t idFilterNum; /*!< The FlexCAN Legacy Rx FIFO Filter elements quantity. */ + flexcan_rx_fifo_filter_type_t idFilterType; /*!< The FlexCAN Legacy Rx FIFO Filter type. */ + flexcan_rx_fifo_priority_t priority; /*!< The FlexCAN Legacy Rx FIFO receive priority. */ +} flexcan_rx_fifo_config_t; + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! @brief FlexCAN Enhanced Rx FIFO Standard ID filter element structure. */ +typedef struct _flexcan_enhanced_rx_fifo_std_id_filter +{ + uint32_t filterType : 2; /*!< FlexCAN internal Free-Running Counter Time Stamp. */ + uint32_t : 2; + uint32_t rtr1 : 1; /*!< CAN FD frame data length code (DLC), range see @ref _flexcan_fd_frame_length, When the + length <= 8, it equal to the data length, otherwise the number of valid frame data is + not equal to the length value. user can + use DLC_LENGTH_DECODE(length) macro to get the number of valid data bytes. */ + uint32_t std1 : 11; /*!< CAN Frame Type(DATA or REMOTE). */ + uint32_t : 4; + uint32_t rtr2 : 1; /*!< CAN Frame Identifier(STD or EXT format). */ + uint32_t std2 : 11; /*!< Substitute Remote request. */ +} flexcan_enhanced_rx_fifo_std_id_filter_t; + +/*! @brief FlexCAN Enhanced Rx FIFO Extended ID filter element structure. */ +typedef struct _flexcan_enhanced_rx_fifo_ext_id_filter +{ + uint32_t filterType : 2; /*!< FlexCAN internal Free-Running Counter Time Stamp. */ + uint32_t rtr1 : 1; /*!< CAN FD frame data length code (DLC), range see @ref _flexcan_fd_frame_length, When the + length <= 8, it equal to the data length, otherwise the number of valid frame data is + not equal to the length value. user can + use DLC_LENGTH_DECODE(length) macro to get the number of valid data bytes. */ + uint32_t std1 : 29; /*!< CAN Frame Type(DATA or REMOTE). */ + uint32_t : 2; + uint32_t rtr2 : 1; /*!< CAN Frame Identifier(STD or EXT format). */ + uint32_t std2 : 29; /*!< Substitute Remote request. */ +} flexcan_enhanced_rx_fifo_ext_id_filter_t; +/*! @brief FlexCAN Enhanced Rx FIFO configuration structure. */ +typedef struct _flexcan_enhanced_rx_fifo_config +{ + uint32_t *idFilterTable; /*!< Pointer to the FlexCAN Enhanced Rx FIFO identifier filter table, each table member + occupies 32 bit word, table size should be equal to idFilterNum. There are two types of + Enhanced Rx FIFO filter elements that can be stored in table : extended-ID filter element + (1 word, occupie 1 table members) and standard-ID filter element (2 words, occupies 2 table + members), the extended-ID filter element needs to be placed in front of the table. */ + uint8_t idFilterPairNum; /*!< idFilterPairNum is the Enhanced Rx FIFO identifier filter element pair numbers, + each pair of filter elements occupies 2 words and can consist of one extended ID filter + element or two standard ID filter elements. */ + uint8_t extendIdFilterNum; /*!< The number of extended ID filter element items in the FlexCAN enhanced Rx FIFO + identifier filter table, each extended-ID filter element occupies 2 words, + extendIdFilterNum need less than or equal to idFilterPairNum. */ + uint8_t fifoWatermark; /*!< (fifoWatermark + 1) is the minimum number of CAN messages stored in the Enhanced RX FIFO + which can trigger FIFO watermark interrupt or a DMA request. */ + flexcan_efifo_dma_per_read_length_t dmaPerReadLength; /*!< Define the length of each read of the Enhanced RX FIFO + element by the DAM, see @ref _flexcan_fd_frame_length. */ + flexcan_rx_fifo_priority_t priority; /*!< The FlexCAN Enhanced Rx FIFO receive priority. */ +} flexcan_enhanced_rx_fifo_config_t; +#endif + +/*! @brief FlexCAN Message Buffer transfer. */ +typedef struct _flexcan_mb_transfer +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + flexcan_fd_frame_t *framefd; +#endif + flexcan_frame_t *frame; /*!< The buffer of CAN Message to be transfer. */ + uint8_t mbIdx; /*!< The index of Message buffer used to transfer Message. */ +} flexcan_mb_transfer_t; + +/*! @brief FlexCAN Rx FIFO transfer. */ +typedef struct _flexcan_fifo_transfer +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + flexcan_fd_frame_t *framefd; /*!< The buffer of CAN Message to be received from Enhanced Rx FIFO. */ +#endif + flexcan_frame_t *frame; /*!< The buffer of CAN Message to be received from Legacy Rx FIFO. */ + size_t frameNum; /*!< Number of CAN Message need to be received from Legacy or Ehanced Rx FIFO. */ +} flexcan_fifo_transfer_t; + +/*! @brief FlexCAN handle structure definition. */ +typedef struct _flexcan_handle flexcan_handle_t; + +/*! @brief FlexCAN transfer callback function. + * + * The FlexCAN transfer callback returns a value from the underlying layer. + * If the status equals to kStatus_FLEXCAN_ErrorStatus, the result parameter is the Content of + * FlexCAN status register which can be used to get the working status(or error status) of FlexCAN module. + * If the status equals to other FlexCAN Message Buffer transfer status, the result is the index of + * Message Buffer that generate transfer event. + * If the status equals to other FlexCAN Message Buffer transfer status, the result is meaningless and should be + * Ignored. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) +#define FLEXCAN_CALLBACK(x) \ + void(x)(CAN_Type * base, flexcan_handle_t * handle, status_t status, uint64_t result, void *userData) +typedef void (*flexcan_transfer_callback_t)( + CAN_Type *base, flexcan_handle_t *handle, status_t status, uint64_t result, void *userData); +#else +#define FLEXCAN_CALLBACK(x) \ + void(x)(CAN_Type * base, flexcan_handle_t * handle, status_t status, uint32_t result, void *userData) +typedef void (*flexcan_transfer_callback_t)( + CAN_Type *base, flexcan_handle_t *handle, status_t status, uint32_t result, void *userData); +#endif + +/*! @brief FlexCAN handle structure. */ +struct _flexcan_handle +{ + flexcan_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< FlexCAN callback function parameter.*/ + flexcan_frame_t + *volatile mbFrameBuf[CAN_WORD1_COUNT]; /*!< The buffer for received CAN data from Message Buffers. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + flexcan_fd_frame_t + *volatile mbFDFrameBuf[CAN_WORD1_COUNT]; /*!< The buffer for received CAN FD data from Message Buffers. */ +#endif + flexcan_frame_t *volatile rxFifoFrameBuf; /*!< The buffer for received CAN data from Legacy Rx FIFO. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + flexcan_fd_frame_t *volatile rxFifoFDFrameBuf; /*!< The buffer for received CAN FD data from Ehanced Rx FIFO. */ +#endif + size_t rxFifoFrameNum; /*!< The number of CAN messages remaining to be received from Legacy or Ehanced Rx FIFO. */ + size_t rxFifoTransferTotalNum; /*!< Total CAN Message number need to be received from Legacy or Ehanced Rx FIFO. */ + volatile uint8_t mbState[CAN_WORD1_COUNT]; /*!< Message Buffer transfer state. */ + volatile uint8_t rxFifoState; /*!< Rx FIFO transfer state. */ + volatile uint32_t timestamp[CAN_WORD1_COUNT]; /*!< Mailbox transfer timestamp. */ +}; + +/****************************************************************************** + * API + *****************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization and deinitialization + * @{ + */ + +/*! + * @brief Enter FlexCAN Freeze Mode. + * + * This function makes the FlexCAN work under Freeze Mode. + * + * @param base FlexCAN peripheral base address. + */ +void FLEXCAN_EnterFreezeMode(CAN_Type *base); + +/*! + * @brief Exit FlexCAN Freeze Mode. + * + * This function makes the FlexCAN leave Freeze Mode. + * + * @param base FlexCAN peripheral base address. + */ +void FLEXCAN_ExitFreezeMode(CAN_Type *base); + +/*! + * @brief Get the FlexCAN instance from peripheral base address. + * + * @param base FlexCAN peripheral base address. + * @return FlexCAN instance. + */ +uint32_t FLEXCAN_GetInstance(CAN_Type *base); + +/*! + * @brief Calculates the improved timing values by specific bit Rates for classical CAN. + * + * This function use to calculates the Classical CAN timing values according to the given bit rate. The Calculated + * timing values will be set in CTRL1/CBT/ENCBT register. The calculation is based on the recommendation of the CiA 301 + * v4.2.0 and previous version document. + * + * @param base FlexCAN peripheral base address. + * @param bitRate The classical CAN speed in bps defined by user, should be less than or equal to 1Mbps. + * @param sourceClock_Hz The Source clock frequency in Hz. + * @param pTimingConfig Pointer to the FlexCAN timing configuration structure. + * + * @return TRUE if timing configuration found, FALSE if failed to find configuration. + */ +bool FLEXCAN_CalculateImprovedTimingValues(CAN_Type *base, + uint32_t bitRate, + uint32_t sourceClock_Hz, + flexcan_timing_config_t *pTimingConfig); + +/*! + * @brief Initializes a FlexCAN instance. + * + * This function initializes the FlexCAN module with user-defined settings. + * This example shows how to set up the flexcan_config_t parameters and how + * to call the FLEXCAN_Init function by passing in these parameters. + * @code + * flexcan_config_t flexcanConfig; + * flexcanConfig.clkSrc = kFLEXCAN_ClkSrc0; + * flexcanConfig.bitRate = 1000000U; + * flexcanConfig.maxMbNum = 16; + * flexcanConfig.enableLoopBack = false; + * flexcanConfig.enableSelfWakeup = false; + * flexcanConfig.enableIndividMask = false; + * flexcanConfig.enableDoze = false; + * flexcanConfig.disableSelfReception = false; + * flexcanConfig.enableListenOnlyMode = false; + * flexcanConfig.timingConfig = timingConfig; + * FLEXCAN_Init(CAN0, &flexcanConfig, 40000000UL); + * @endcode + * + * @param base FlexCAN peripheral base address. + * @param pConfig Pointer to the user-defined configuration structure. + * @param sourceClock_Hz FlexCAN Protocol Engine clock source frequency in Hz. + */ +void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *pConfig, uint32_t sourceClock_Hz); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Calculates the improved timing values by specific bit rates for CANFD. + * + * This function use to calculates the CANFD timing values according to the given nominal phase bit rate and data phase + * bit rate. The Calculated timing values will be set in CBT/ENCBT and FDCBT/EDCBT registers. The calculation is based + * on the recommendation of the CiA 1301 v1.0.0 document. + * + * @param base FlexCAN peripheral base address. + * @param bitRate The CANFD bus control speed in bps defined by user. + * @param bitRateFD The CAN FD data phase speed in bps defined by user. Equal to bitRate means disable bit rate + * switching. + * @param sourceClock_Hz The Source clock frequency in Hz. + * @param pTimingConfig Pointer to the FlexCAN timing configuration structure. + * + * @return TRUE if timing configuration found, FALSE if failed to find configuration + */ +bool FLEXCAN_FDCalculateImprovedTimingValues(CAN_Type *base, + uint32_t bitRate, + uint32_t bitRateFD, + uint32_t sourceClock_Hz, + flexcan_timing_config_t *pTimingConfig); +/*! + * @brief Initializes a FlexCAN instance. + * + * This function initializes the FlexCAN module with user-defined settings. + * This example shows how to set up the flexcan_config_t parameters and how + * to call the FLEXCAN_FDInit function by passing in these parameters. + * @code + * flexcan_config_t flexcanConfig; + * flexcanConfig.clkSrc = kFLEXCAN_ClkSrc0; + * flexcanConfig.bitRate = 1000000U; + * flexcanConfig.bitRateFD = 2000000U; + * flexcanConfig.maxMbNum = 16; + * flexcanConfig.enableLoopBack = false; + * flexcanConfig.enableSelfWakeup = false; + * flexcanConfig.enableIndividMask = false; + * flexcanConfig.disableSelfReception = false; + * flexcanConfig.enableListenOnlyMode = false; + * flexcanConfig.enableDoze = false; + * flexcanConfig.timingConfig = timingConfig; + * FLEXCAN_FDInit(CAN0, &flexcanConfig, 80000000UL, kFLEXCAN_16BperMB, true); + * @endcode + * + * @param base FlexCAN peripheral base address. + * @param pConfig Pointer to the user-defined configuration structure. + * @param sourceClock_Hz FlexCAN Protocol Engine clock source frequency in Hz. + * @param dataSize FlexCAN Message Buffer payload size. The actual transmitted or received CAN FD frame data size needs + * to be less than or equal to this value. + * @param brs True if bit rate switch is enabled in FD mode. + */ +void FLEXCAN_FDInit( + CAN_Type *base, const flexcan_config_t *pConfig, uint32_t sourceClock_Hz, flexcan_mb_size_t dataSize, bool brs); +#endif + +/*! + * @brief De-initializes a FlexCAN instance. + * + * This function disables the FlexCAN module clock and sets all register values + * to the reset value. + * + * @param base FlexCAN peripheral base address. + */ +void FLEXCAN_Deinit(CAN_Type *base); + +/*! + * @brief Gets the default configuration structure. + * + * This function initializes the FlexCAN configuration structure to default values. The default + * values are as follows. + * flexcanConfig->clkSrc = kFLEXCAN_ClkSrc0; + * flexcanConfig->bitRate = 1000000U; + * flexcanConfig->bitRateFD = 2000000U; + * flexcanConfig->maxMbNum = 16; + * flexcanConfig->enableLoopBack = false; + * flexcanConfig->enableSelfWakeup = false; + * flexcanConfig->enableIndividMask = false; + * flexcanConfig->disableSelfReception = false; + * flexcanConfig->enableListenOnlyMode = false; + * flexcanConfig->enableDoze = false; + * flexcanConfig->enableMemoryErrorControl = true; + * flexcanConfig->enableNonCorrectableErrorEnterFreeze = true; + * flexcanConfig.timingConfig = timingConfig; + * + * @param pConfig Pointer to the FlexCAN configuration structure. + */ +void FLEXCAN_GetDefaultConfig(flexcan_config_t *pConfig); + +/* @} */ + +/*! + * @name Configuration. + * @{ + */ + +/*! + * @brief Sets the FlexCAN classical CAN protocol timing characteristic. + * + * This function gives user settings to classical CAN or CAN FD nominal phase timing characteristic. + * The function is for an experienced user. For less experienced users, call the FLEXCAN_SetBitRate() instead. + * + * @note Calling FLEXCAN_SetTimingConfig() overrides the bit rate set in FLEXCAN_Init() or FLEXCAN_SetBitRate(). + * + * @param base FlexCAN peripheral base address. + * @param pConfig Pointer to the timing configuration structure. + */ +void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *pConfig); + +/*! + * @brief Set bit rate of FlexCAN classical CAN frame or CAN FD frame nominal phase. + * + * This function set the bit rate of classical CAN frame or CAN FD frame nominal phase base on + * FLEXCAN_CalculateImprovedTimingValues() API calculated timing values. + * + * @note Calling FLEXCAN_SetBitRate() overrides the bit rate set in FLEXCAN_Init(). + * + * @param base FlexCAN peripheral base address. + * @param sourceClock_Hz Source Clock in Hz. + * @param bitRate_Bps Bit rate in Bps. + * @return kStatus_Success - Set CAN baud rate (only Nominal phase) successfully. + */ +status_t FLEXCAN_SetBitRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t bitRate_Bps); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Sets the FlexCAN CANFD data phase timing characteristic. + * + * This function gives user settings to CANFD data phase timing characteristic. + * The function is for an experienced user. For less experienced users, call the FLEXCAN_SetFDBitRate() + * to set both Nominal/Data bit Rate instead. + * + * @note Calling FLEXCAN_SetFDTimingConfig() overrides the data phase bit rate set in + * FLEXCAN_FDInit()/FLEXCAN_SetFDBitRate(). + * + * @param base FlexCAN peripheral base address. + * @param pConfig Pointer to the timing configuration structure. + */ +void FLEXCAN_SetFDTimingConfig(CAN_Type *base, const flexcan_timing_config_t *pConfig); + +/*! + * @brief Set bit rate of FlexCAN FD frame. + * + * This function set the baud rate of FLEXCAN FD base on FLEXCAN_FDCalculateImprovedTimingValues() API calculated timing + * values. + * + * @param base FlexCAN peripheral base address. + * @param sourceClock_Hz Source Clock in Hz. + * @param bitRateN_Bps Nominal bit Rate in Bps. + * @param bitRateD_Bps Data bit Rate in Bps. + * @return kStatus_Success - Set CAN FD bit rate (include Nominal and Data phase) successfully. + */ +status_t FLEXCAN_SetFDBitRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t bitRateN_Bps, uint32_t bitRateD_Bps); +#endif + +/*! + * @brief Sets the FlexCAN receive message buffer global mask. + * + * This function sets the global mask for the FlexCAN message buffer in a matching process. + * The configuration is only effective when the Rx individual mask is disabled in the FLEXCAN_Init(). + * + * @param base FlexCAN peripheral base address. + * @param mask Rx Message Buffer Global Mask value. + */ +void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask); + +/*! + * @brief Sets the FlexCAN receive FIFO global mask. + * + * This function sets the global mask for FlexCAN FIFO in a matching process. + * + * @param base FlexCAN peripheral base address. + * @param mask Rx Fifo Global Mask value. + */ +void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask); + +/*! + * @brief Sets the FlexCAN receive individual mask. + * + * This function sets the individual mask for the FlexCAN matching process. + * The configuration is only effective when the Rx individual mask is enabled in the FLEXCAN_Init(). + * If the Rx FIFO is disabled, the individual mask is applied to the corresponding Message Buffer. + * If the Rx FIFO is enabled, the individual mask for Rx FIFO occupied Message Buffer is applied to + * the Rx Filter with the same index. Note that only the first 32 + * individual masks can be used as the Rx FIFO filter mask. + * + * @param base FlexCAN peripheral base address. + * @param maskIdx The Index of individual Mask. + * @param mask Rx Individual Mask value. + */ +void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask); + +/*! + * @brief Configures a FlexCAN transmit message buffer. + * + * This function aborts the previous transmission, cleans the Message Buffer, and + * configures it as a Transmit Message Buffer. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The Message Buffer index. + * @param enable Enable/disable Tx Message Buffer. + * - true: Enable Tx Message Buffer. + * - false: Disable Tx Message Buffer. + */ +void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Configures a FlexCAN transmit message buffer. + * + * This function aborts the previous transmission, cleans the Message Buffer, and + * configures it as a Transmit Message Buffer. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The Message Buffer index. + * @param enable Enable/disable Tx Message Buffer. + * - true: Enable Tx Message Buffer. + * - false: Disable Tx Message Buffer. + */ +void FLEXCAN_SetFDTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable); +#endif + +/*! + * @brief Configures a FlexCAN Receive Message Buffer. + * + * This function cleans a FlexCAN build-in Message Buffer and configures it + * as a Receive Message Buffer. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The Message Buffer index. + * @param pRxMbConfig Pointer to the FlexCAN Message Buffer configuration structure. + * @param enable Enable/disable Rx Message Buffer. + * - true: Enable Rx Message Buffer. + * - false: Disable Rx Message Buffer. + */ +void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *pRxMbConfig, bool enable); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Configures a FlexCAN Receive Message Buffer. + * + * This function cleans a FlexCAN build-in Message Buffer and configures it + * as a Receive Message Buffer. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The Message Buffer index. + * @param pRxMbConfig Pointer to the FlexCAN Message Buffer configuration structure. + * @param enable Enable/disable Rx Message Buffer. + * - true: Enable Rx Message Buffer. + * - false: Disable Rx Message Buffer. + */ +void FLEXCAN_SetFDRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *pRxMbConfig, bool enable); +#endif + +/*! + * @brief Configures the FlexCAN Legacy Rx FIFO. + * + * This function configures the FlexCAN Rx FIFO with given configuration. + * @note Legacy Rx FIFO only can receive classic CAN message. + * + * @param base FlexCAN peripheral base address. + * @param pRxFifoConfig Pointer to the FlexCAN Legacy Rx FIFO configuration structure. Can be NULL when enable parameter + * is false. + * @param enable Enable/disable Legacy Rx FIFO. + * - true: Enable Legacy Rx FIFO. + * - false: Disable Legacy Rx FIFO. + */ +void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *pRxFifoConfig, bool enable); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * @brief Configures the FlexCAN Enhanced Rx FIFO. + * + * This function configures the Enhanced Rx FIFO with given configuration. + * @note Enhanced Rx FIFO support receive classic CAN or CAN FD messages, Legacy Rx FIFO and Enhanced Rx FIFO + * cannot be enabled at the same time. + * + * @param base FlexCAN peripheral base address. + * @param pConfig Pointer to the FlexCAN Enhanced Rx FIFO configuration structure. Can be NULL when enable parameter + * is false. + * @param enable Enable/disable Enhanced Rx FIFO. + * - true: Enable Enhanced Rx FIFO. + * - false: Disable Enhanced Rx FIFO. + */ +void FLEXCAN_SetEnhancedRxFifoConfig(CAN_Type *base, const flexcan_enhanced_rx_fifo_config_t *pConfig, bool enable); +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) +/*! + * @brief Configures the FlexCAN Pretended Networking mode. + * + * This function configures the FlexCAN Pretended Networking mode with given configuration. + * + * @param base FlexCAN peripheral base address. + * @param pConfig Pointer to the FlexCAN Rx FIFO configuration structure. + */ +void FLEXCAN_SetPNConfig(CAN_Type *base, const flexcan_pn_config_t *pConfig); +#endif +/* @} */ + +/*! + * @name Status + * @{ + */ + +/*! + * @brief Gets the FlexCAN module interrupt flags. + * + * This function gets all FlexCAN status flags. The flags are returned as the logical + * OR value of the enumerators @ref _flexcan_flags. To check the specific status, + * compare the return value with enumerators in @ref _flexcan_flags. + * + * @param base FlexCAN peripheral base address. + * @return FlexCAN status flags which are ORed by the enumerators in the _flexcan_flags. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) +static inline uint64_t FLEXCAN_GetStatusFlags(CAN_Type *base) +{ + uint64_t tempflag = (uint64_t)base->ESR1; +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) + /* Get PN Wake Up status. */ + tempflag |= FLEXCAN_PN_STATUS_MASK(base->WU_MTC); +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + /* Get Enhanced Rx FIFO status. */ + tempflag |= FLEXCAN_EFIFO_STATUS_MASK(base->ERFSR); +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + /* Get Memory Error status. */ + tempflag |= FLEXCAN_MECR_STATUS_MASK(base->ERRSR); +#endif + return tempflag; +} +#else +static inline uint32_t FLEXCAN_GetStatusFlags(CAN_Type *base) +{ + return base->ESR1; +} +#endif +/*! + * @brief Clears status flags with the provided mask. + * + * This function clears the FlexCAN status flags with a provided mask. An automatically cleared flag + * can't be cleared by this function. + * + * @param base FlexCAN peripheral base address. + * @param mask The status flags to be cleared, it is logical OR value of @ref _flexcan_flags. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) +static inline void FLEXCAN_ClearStatusFlags(CAN_Type *base, uint64_t mask) +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) + /* Clear PN Wake Up status. */ + base->WU_MTC = FLEXCAN_PN_STATUS_UNMASK(mask); +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + /* Clear Enhanced Rx FIFO status. */ + base->ERFSR = FLEXCAN_EFIFO_STATUS_UNMASK(mask); +#endif +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + /* Clear Memory Error status. */ + base->ERRSR = FLEXCAN_MECR_STATUS_UNMASK(mask); +#endif + base->ESR1 = (uint32_t)(mask & 0xFFFFFFFFU); +} +#else +static inline void FLEXCAN_ClearStatusFlags(CAN_Type *base, uint32_t mask) +{ + /* Write 1 to clear status flag. */ + base->ESR1 = mask; +} +#endif +/*! + * @brief Gets the FlexCAN Bus Error Counter value. + * + * This function gets the FlexCAN Bus Error Counter value for both Tx and + * Rx direction. These values may be needed in the upper layer error handling. + * + * @param base FlexCAN peripheral base address. + * @param txErrBuf Buffer to store Tx Error Counter value. + * @param rxErrBuf Buffer to store Rx Error Counter value. + */ +static inline void FLEXCAN_GetBusErrCount(CAN_Type *base, uint8_t *txErrBuf, uint8_t *rxErrBuf) +{ + if (NULL != txErrBuf) + { + *txErrBuf = (uint8_t)((base->ECR & CAN_ECR_TXERRCNT_MASK) >> CAN_ECR_TXERRCNT_SHIFT); + } + + if (NULL != rxErrBuf) + { + *rxErrBuf = (uint8_t)((base->ECR & CAN_ECR_RXERRCNT_MASK) >> CAN_ECR_RXERRCNT_SHIFT); + } +} + +/*! + * @brief Gets the FlexCAN Message Buffer interrupt flags. + * + * This function gets the interrupt flags of a given Message Buffers. + * + * @param base FlexCAN peripheral base address. + * @param mask The ORed FlexCAN Message Buffer mask. + * @return The status of given Message Buffers. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) +static inline uint64_t FLEXCAN_GetMbStatusFlags(CAN_Type *base, uint64_t mask) +#else +static inline uint32_t FLEXCAN_GetMbStatusFlags(CAN_Type *base, uint32_t mask) +#endif +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + uint64_t tempflag = (uint64_t)base->IFLAG1; + return (tempflag | (((uint64_t)base->IFLAG2) << 32)) & mask; +#else + return (base->IFLAG1 & mask); +#endif +} + +/*! + * @brief Clears the FlexCAN Message Buffer interrupt flags. + * + * This function clears the interrupt flags of a given Message Buffers. + * + * @param base FlexCAN peripheral base address. + * @param mask The ORed FlexCAN Message Buffer mask. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) +static inline void FLEXCAN_ClearMbStatusFlags(CAN_Type *base, uint64_t mask) +#else +static inline void FLEXCAN_ClearMbStatusFlags(CAN_Type *base, uint32_t mask) +#endif +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + base->IFLAG1 = (uint32_t)(mask & 0xFFFFFFFFU); + base->IFLAG2 = (uint32_t)(mask >> 32); +#else + base->IFLAG1 = mask; +#endif +} + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) +/*! + * @brief Gets the FlexCAN Memory Error Report registers status. + * + * This function gets the FlexCAN Memory Error Report registers status. + * + * @param base FlexCAN peripheral base address. + * @param errorStatus Pointer to FlexCAN Memory Error Report registers status structure. + */ +void FLEXCAN_GetMemoryErrorReportStatus(CAN_Type *base, flexcan_memory_error_report_status_t *errorStatus); +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) +/*! + * @brief Gets the FlexCAN Number of Matches when in Pretended Networking. + * + * This function gets the number of times a given message has matched the predefined filtering criteria for ID and/or PL + * before a wakeup event. + * + * @param base FlexCAN peripheral base address. + * @return The number of received wake up msessages. + */ +static inline uint8_t FLEXCAN_GetPNMatchCount(CAN_Type *base) +{ + return (uint8_t)((base->WU_MTC & CAN_WU_MTC_MCOUNTER_MASK) >> CAN_WU_MTC_MCOUNTER_SHIFT); +} +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * @brief Gets the number of FlexCAN Enhanced Rx FIFO available frames. + * + * This function gets the number of CAN messages stored in the Enhanced Rx FIFO. + * + * @param base FlexCAN peripheral base address. + * @return The number of available CAN messages stored in the Enhanced Rx FIFO. + */ +static inline uint32_t FLEXCAN_GetEnhancedFifoDataCount(CAN_Type *base) +{ + return (base->ERFSR & CAN_ERFSR_ERFEL_MASK); +} +#endif +/* @} */ + +/*! + * @name Interrupts + * @{ + */ + +/*! + * @brief Enables FlexCAN interrupts according to the provided mask. + * + * This function enables the FlexCAN interrupts according to the provided mask. The mask + * is a logical OR of enumeration members, see @ref _flexcan_interrupt_enable. + * + * @param base FlexCAN peripheral base address. + * @param mask The interrupts to enable. Logical OR of @ref _flexcan_interrupt_enable. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) +static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint64_t mask) +#else +static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint32_t mask) +#endif +{ + /* Solve Self Wake Up interrupt. */ + base->MCR |= (uint32_t)(mask & (uint32_t)kFLEXCAN_WakeUpInterruptEnable); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base)) + { + /* Solve CAN FD frames data phase error interrupt. */ + base->CTRL2 |= (uint32_t)(mask & (uint32_t)kFLEXCAN_FDErrorInterruptEnable); + } +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) + /* Solve PN Wake Up interrupt. */ + base->CTRL1_PN |= FLEXCAN_PN_INT_UNMASK(mask); +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + /* Solve Enhanced Rx FIFO interrupt. */ + base->ERFIER |= FLEXCAN_EFIFO_INT_UNMASK(mask); +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + /* Solve Memory Error interrupt. */ + base->MECR |= FLEXCAN_MECR_INT_UNMASK(mask); +#endif + + /* Solve interrupt enable bits in CTRL1 register. */ + base->CTRL1 |= + (uint32_t)(mask & ((uint32_t)kFLEXCAN_BusOffInterruptEnable | (uint32_t)kFLEXCAN_ErrorInterruptEnable | + (uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable)); +} + +/*! + * @brief Disables FlexCAN interrupts according to the provided mask. + * + * This function disables the FlexCAN interrupts according to the provided mask. The mask + * is a logical OR of enumeration members, see @ref _flexcan_interrupt_enable. + * + * @param base FlexCAN peripheral base address. + * @param mask The interrupts to disable. Logical OR of @ref _flexcan_interrupt_enable. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) || \ + (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) +static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint64_t mask) +#else +static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint32_t mask) +#endif +{ + /* Solve Wake Up Interrupt. */ + base->MCR &= ~(uint32_t)(mask & (uint32_t)kFLEXCAN_WakeUpInterruptEnable); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) + if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base)) + { + /* Solve CAN FD frames data phase error interrupt. */ + base->CTRL2 &= ~(uint32_t)(mask & (uint32_t)kFLEXCAN_FDErrorInterruptEnable); + } +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) + /* Solve PN Wake Up Interrupt. */ + base->CTRL1_PN &= ~FLEXCAN_PN_STATUS_UNMASK(mask); +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + /* Solve Enhanced Rx FIFO interrupt. */ + base->ERFIER &= ~FLEXCAN_EFIFO_INT_UNMASK(mask); +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) + /* Solve Memory Error Interrupt. */ + base->MECR &= ~FLEXCAN_MECR_STATUS_UNMASK(mask); +#endif + + /* Solve interrupt enable bits in CTRL1 register. */ + base->CTRL1 &= + ~(uint32_t)(mask & ((uint32_t)kFLEXCAN_BusOffInterruptEnable | (uint32_t)kFLEXCAN_ErrorInterruptEnable | + (uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable)); +} + +/*! + * @brief Enables FlexCAN Message Buffer interrupts. + * + * This function enables the interrupts of given Message Buffers. + * + * @param base FlexCAN peripheral base address. + * @param mask The ORed FlexCAN Message Buffer mask. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) +static inline void FLEXCAN_EnableMbInterrupts(CAN_Type *base, uint64_t mask) +#else +static inline void FLEXCAN_EnableMbInterrupts(CAN_Type *base, uint32_t mask) +#endif +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + base->IMASK1 |= (uint32_t)(mask & 0xFFFFFFFFU); + base->IMASK2 |= (uint32_t)(mask >> 32); +#else + base->IMASK1 |= mask; +#endif +} + +/*! + * @brief Disables FlexCAN Message Buffer interrupts. + * + * This function disables the interrupts of given Message Buffers. + * + * @param base FlexCAN peripheral base address. + * @param mask The ORed FlexCAN Message Buffer mask. + */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) +static inline void FLEXCAN_DisableMbInterrupts(CAN_Type *base, uint64_t mask) +#else +static inline void FLEXCAN_DisableMbInterrupts(CAN_Type *base, uint32_t mask) +#endif +{ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0) + base->IMASK1 &= ~((uint32_t)(mask & 0xFFFFFFFFU)); + base->IMASK2 &= ~((uint32_t)(mask >> 32)); +#else + base->IMASK1 &= ~mask; +#endif +} + +/* @} */ + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) && FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) +/*! + * @name DMA Control + * @{ + */ + +/*! + * @brief Enables or disables the FlexCAN Rx FIFO DMA request. + * + * This function enables or disables the DMA feature of FlexCAN build-in Rx FIFO. + * + * @param base FlexCAN peripheral base address. + * @param enable true to enable, false to disable. + */ +void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable); + +/*! + * @brief Gets the Rx FIFO Head address. + * + * This function returns the FlexCAN Rx FIFO Head address, which is mainly used for the DMA/eDMA use case. + * + * @param base FlexCAN peripheral base address. + * @return FlexCAN Rx FIFO Head address. + */ +static inline uintptr_t FLEXCAN_GetRxFifoHeadAddr(CAN_Type *base) +{ + return (uintptr_t) & (base->MB[0].CS); +} + +/* @} */ +#endif /* FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA */ + +/*! + * @name Bus Operations + * @{ + */ + +/*! + * @brief Enables or disables the FlexCAN module operation. + * + * This function enables or disables the FlexCAN module. + * + * @param base FlexCAN base pointer. + * @param enable true to enable, false to disable. + */ +static inline void FLEXCAN_Enable(CAN_Type *base, bool enable) +{ + if (enable) + { + base->MCR &= ~CAN_MCR_MDIS_MASK; + + /* Wait FlexCAN exit from low-power mode. */ + while (0U != (base->MCR & CAN_MCR_LPMACK_MASK)) + { + } + } + else + { + base->MCR |= CAN_MCR_MDIS_MASK; + + /* Wait FlexCAN enter low-power mode. */ + while (0U == (base->MCR & CAN_MCR_LPMACK_MASK)) + { + } + } +} + +/*! + * @brief Writes a FlexCAN Message to the Transmit Message Buffer. + * + * This function writes a CAN Message to the specified Transmit Message Buffer + * and changes the Message Buffer state to start CAN Message transmit. After + * that the function returns immediately. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The FlexCAN Message Buffer index. + * @param pTxFrame Pointer to CAN message frame to be sent. + * @retval kStatus_Success - Write Tx Message Buffer Successfully. + * @retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t *pTxFrame); + +/*! + * @brief Reads a FlexCAN Message from Receive Message Buffer. + * + * This function reads a CAN message from a specified Receive Message Buffer. + * The function fills a receive CAN message frame structure with + * just received data and activates the Message Buffer again. + * The function returns immediately. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The FlexCAN Message Buffer index. + * @param pRxFrame Pointer to CAN message frame structure for reception. + * @retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * @retval kStatus_Fail - Rx Message Buffer is empty. + */ +status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Writes a FlexCAN FD Message to the Transmit Message Buffer. + * + * This function writes a CAN FD Message to the specified Transmit Message Buffer + * and changes the Message Buffer state to start CAN FD Message transmit. After + * that the function returns immediately. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The FlexCAN FD Message Buffer index. + * @param pTxFrame Pointer to CAN FD message frame to be sent. + * @retval kStatus_Success - Write Tx Message Buffer Successfully. + * @retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_frame_t *pTxFrame); + +/*! + * @brief Reads a FlexCAN FD Message from Receive Message Buffer. + * + * This function reads a CAN FD message from a specified Receive Message Buffer. + * The function fills a receive CAN FD message frame structure with + * just received data and activates the Message Buffer again. + * The function returns immediately. + * + * @param base FlexCAN peripheral base address. + * @param mbIdx The FlexCAN FD Message Buffer index. + * @param pRxFrame Pointer to CAN FD message frame structure for reception. + * @retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * @retval kStatus_Fail - Rx Message Buffer is empty. + */ +status_t FLEXCAN_ReadFDRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pRxFrame); +#endif + +/*! + * @brief Reads a FlexCAN Message from Legacy Rx FIFO. + * + * This function reads a CAN message from the FlexCAN Legacy Rx FIFO. + * + * @param base FlexCAN peripheral base address. + * @param pRxFrame Pointer to CAN message frame structure for reception. + * @retval kStatus_Success - Read Message from Rx FIFO successfully. + * @retval kStatus_Fail - Rx FIFO is not enabled. + */ +status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *pRxFrame); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * @brief Reads a FlexCAN Message from Enhanced Rx FIFO. + * + * This function reads a CAN or CAN FD message from the FlexCAN Enhanced Rx FIFO. + * + * @param base FlexCAN peripheral base address. + * @param pRxFrame Pointer to CAN FD message frame structure for reception. + * @retval kStatus_Success - Read Message from Rx FIFO successfully. + * @retval kStatus_Fail - Rx FIFO is not enabled. + */ +status_t FLEXCAN_ReadEnhancedRxFifo(CAN_Type *base, flexcan_fd_frame_t *pRxFrame); +#endif + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) +/*! + * @brief Reads a FlexCAN Message from Wake Up MB. + * + * This function reads a CAN message from the FlexCAN Wake up Message Buffers. There are four Wake up Message Buffers + * (WMBs) used to store incoming messages in Pretended Networking mode. The WMB index indicates the arrival order. The + * last message is stored in WMB3. + * + * @param base FlexCAN peripheral base address. + * @param pRxFrame Pointer to CAN message frame structure for reception. + * @param mbIdx The FlexCAN Wake up Message Buffer index. Range in 0x0 ~ 0x3. + * @retval kStatus_Success - Read Message from Wake up Message Buffer successfully. + * @retval kStatus_Fail - Wake up Message Buffer has no valid content. + */ +status_t FLEXCAN_ReadPNWakeUpMB(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame); +#endif +/* @} */ + +/*! + * @name Transactional + * @{ + */ + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) +/*! + * @brief Performs a polling send transaction on the CAN bus. + * + * @note A transfer handle does not need to be created before calling this API. + * + * @param base FlexCAN peripheral base pointer. + * @param mbIdx The FlexCAN FD Message Buffer index. + * @param pTxFrame Pointer to CAN FD message frame to be sent. + * @retval kStatus_Success - Write Tx Message Buffer Successfully. + * @retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t FLEXCAN_TransferFDSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pTxFrame); + +/*! + * @brief Performs a polling receive transaction on the CAN bus. + * + * @note A transfer handle does not need to be created before calling this API. + * + * @param base FlexCAN peripheral base pointer. + * @param mbIdx The FlexCAN FD Message Buffer index. + * @param pRxFrame Pointer to CAN FD message frame structure for reception. + * @retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * @retval kStatus_Fail - Rx Message Buffer is empty. + */ +status_t FLEXCAN_TransferFDReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pRxFrame); + +/*! + * @brief Sends a message using IRQ. + * + * This function sends a message using IRQ. This is a non-blocking function, which returns + * right away. When messages have been sent out, the send callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param pMbXfer FlexCAN FD Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * @retval kStatus_Success Start Tx Message Buffer sending process successfully. + * @retval kStatus_Fail Write Tx Message Buffer failed. + * @retval kStatus_FLEXCAN_TxBusy Tx Message Buffer is in use. + */ +status_t FLEXCAN_TransferFDSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer); + +/*! + * @brief Receives a message using IRQ. + * + * This function receives a message using IRQ. This is non-blocking function, which returns + * right away. When the message has been received, the receive callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param pMbXfer FlexCAN FD Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * @retval kStatus_Success - Start Rx Message Buffer receiving process successfully. + * @retval kStatus_FLEXCAN_RxBusy - Rx Message Buffer is in use. + */ +status_t FLEXCAN_TransferFDReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer); + +/*! + * @brief Aborts the interrupt driven message send process. + * + * This function aborts the interrupt driven message send process. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param mbIdx The FlexCAN FD Message Buffer index. + */ +void FLEXCAN_TransferFDAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx); + +/*! + * @brief Aborts the interrupt driven message receive process. + * + * This function aborts the interrupt driven message receive process. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param mbIdx The FlexCAN FD Message Buffer index. + */ +void FLEXCAN_TransferFDAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx); +#endif + +/*! + * @brief Performs a polling send transaction on the CAN bus. + * + * @note A transfer handle does not need to be created before calling this API. + * + * @param base FlexCAN peripheral base pointer. + * @param mbIdx The FlexCAN Message Buffer index. + * @param pTxFrame Pointer to CAN message frame to be sent. + * @retval kStatus_Success - Write Tx Message Buffer Successfully. + * @retval kStatus_Fail - Tx Message Buffer is currently in use. + */ +status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pTxFrame); + +/*! + * @brief Performs a polling receive transaction on the CAN bus. + * + * @note A transfer handle does not need to be created before calling this API. + * + * @param base FlexCAN peripheral base pointer. + * @param mbIdx The FlexCAN Message Buffer index. + * @param pRxFrame Pointer to CAN message frame structure for reception. + * @retval kStatus_Success - Rx Message Buffer is full and has been read successfully. + * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully. + * @retval kStatus_Fail - Rx Message Buffer is empty. + */ +status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame); + +/*! + * @brief Performs a polling receive transaction from Legacy Rx FIFO on the CAN bus. + * + * @note A transfer handle does not need to be created before calling this API. + * + * @param base FlexCAN peripheral base pointer. + * @param pRxFrame Pointer to CAN message frame structure for reception. + * @retval kStatus_Success - Read Message from Rx FIFO successfully. + * @retval kStatus_Fail - Rx FIFO is not enabled. + */ +status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *pRxFrame); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * @brief Performs a polling receive transaction from Enhanced Rx FIFO on the CAN bus. + * + * @note A transfer handle does not need to be created before calling this API. + * + * @param base FlexCAN peripheral base pointer. + * @param pRxFrame Pointer to CAN FD message frame structure for reception. + * @retval kStatus_Success - Read Message from Rx FIFO successfully. + * @retval kStatus_Fail - Rx FIFO is not enabled. + */ +status_t FLEXCAN_TransferReceiveEnhancedFifoBlocking(CAN_Type *base, flexcan_fd_frame_t *pRxFrame); +#endif + +/*! + * @brief Initializes the FlexCAN handle. + * + * This function initializes the FlexCAN handle, which can be used for other FlexCAN + * transactional APIs. Usually, for a specified FlexCAN instance, + * call this API once to get the initialized handle. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param callback The callback function. + * @param userData The parameter of the callback function. + */ +void FLEXCAN_TransferCreateHandle(CAN_Type *base, + flexcan_handle_t *handle, + flexcan_transfer_callback_t callback, + void *userData); + +/*! + * @brief Sends a message using IRQ. + * + * This function sends a message using IRQ. This is a non-blocking function, which returns + * right away. When messages have been sent out, the send callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param pMbXfer FlexCAN Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * @retval kStatus_Success Start Tx Message Buffer sending process successfully. + * @retval kStatus_Fail Write Tx Message Buffer failed. + * @retval kStatus_FLEXCAN_TxBusy Tx Message Buffer is in use. + */ +status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer); + +/*! + * @brief Receives a message using IRQ. + * + * This function receives a message using IRQ. This is non-blocking function, which returns + * right away. When the message has been received, the receive callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param pMbXfer FlexCAN Message Buffer transfer structure. See the #flexcan_mb_transfer_t. + * @retval kStatus_Success - Start Rx Message Buffer receiving process successfully. + * @retval kStatus_FLEXCAN_RxBusy - Rx Message Buffer is in use. + */ +status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer); + +/*! + * @brief Receives a message from Rx FIFO using IRQ. + * + * This function receives a message using IRQ. This is a non-blocking function, which returns + * right away. When all messages have been received, the receive callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param pFifoXfer FlexCAN Rx FIFO transfer structure. See the @ref flexcan_fifo_transfer_t. + * @retval kStatus_Success - Start Rx FIFO receiving process successfully. + * @retval kStatus_FLEXCAN_RxFifoBusy - Rx FIFO is currently in use. + */ +status_t FLEXCAN_TransferReceiveFifoNonBlocking(CAN_Type *base, + flexcan_handle_t *handle, + flexcan_fifo_transfer_t *pFifoXfer); + +/*! + * @brief Gets the Legacy Rx Fifo transfer status during a interrupt non-blocking receive. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param count Number of CAN messages receive so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ + +status_t FLEXCAN_TransferGetReceiveFifoCount(CAN_Type *base, flexcan_handle_t *handle, size_t *count); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * @brief Receives a message from Enhanced Rx FIFO using IRQ. + * + * This function receives a message using IRQ. This is a non-blocking function, which returns + * right away. When all messages have been received, the receive callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param pFifoXfer FlexCAN Rx FIFO transfer structure. See the ref flexcan_fifo_transfer_t.@ + * @retval kStatus_Success - Start Rx FIFO receiving process successfully. + * @retval kStatus_FLEXCAN_RxFifoBusy - Rx FIFO is currently in use. + */ +status_t FLEXCAN_TransferReceiveEnhancedFifoNonBlocking(CAN_Type *base, + flexcan_handle_t *handle, + flexcan_fifo_transfer_t *pFifoXfer); + +/*! + * @brief Gets the Enhanced Rx Fifo transfer status during a interrupt non-blocking receive. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param count Number of CAN messages receive so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ + +static inline status_t FLEXCAN_TransferGetReceiveEnhancedFifoCount(CAN_Type *base, + flexcan_handle_t *handle, + size_t *count) +{ + return FLEXCAN_TransferGetReceiveFifoCount(base, handle, count); +} +#endif + +/*! + * @brief Gets the detail index of Mailbox's Timestamp by handle. + * + * Then function can only be used when calling non-blocking Data transfer (TX/RX) API, + * After TX/RX data transfer done (User can get the status by handler's callback function), + * we can get the detail index of Mailbox's timestamp by handle, + * Detail non-blocking data transfer API (TX/RX) contain. + * -FLEXCAN_TransferSendNonBlocking + * -FLEXCAN_TransferFDSendNonBlocking + * -FLEXCAN_TransferReceiveNonBlocking + * -FLEXCAN_TransferFDReceiveNonBlocking + * -FLEXCAN_TransferReceiveFifoNonBlocking + * + * @param handle FlexCAN handle pointer. + * @param mbIdx The FlexCAN Message Buffer index. + * @retval the index of mailbox 's timestamp stored in the handle. + * + */ +uint32_t FLEXCAN_GetTimeStamp(flexcan_handle_t *handle, uint8_t mbIdx); + +/*! + * @brief Aborts the interrupt driven message send process. + * + * This function aborts the interrupt driven message send process. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param mbIdx The FlexCAN Message Buffer index. + */ +void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx); + +/*! + * @brief Aborts the interrupt driven message receive process. + * + * This function aborts the interrupt driven message receive process. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param mbIdx The FlexCAN Message Buffer index. + */ +void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx); + +/*! + * @brief Aborts the interrupt driven message receive from Rx FIFO process. + * + * This function aborts the interrupt driven message receive from Rx FIFO process. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + */ +void FLEXCAN_TransferAbortReceiveFifo(CAN_Type *base, flexcan_handle_t *handle); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * @brief Aborts the interrupt driven message receive from Enhanced Rx FIFO process. + * + * This function aborts the interrupt driven message receive from Enhanced Rx FIFO process. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + */ +void FLEXCAN_TransferAbortReceiveEnhancedFifo(CAN_Type *base, flexcan_handle_t *handle); +#endif + +/*! + * @brief FlexCAN IRQ handle function. + * + * This function handles the FlexCAN Error, the Message Buffer, and the Rx FIFO IRQ request. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + */ +void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_FLEXCAN_H_ */ diff --git a/bsps/arm/imxrt/mcux-sdk/drivers/flexcan/fsl_flexcan_edma.h b/bsps/arm/imxrt/mcux-sdk/drivers/flexcan/fsl_flexcan_edma.h new file mode 100644 index 0000000000..5af4aa4028 --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/drivers/flexcan/fsl_flexcan_edma.h @@ -0,0 +1,188 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_FLEXCAN_EDMA_H_ +#define _FSL_FLEXCAN_EDMA_H_ + +#include "fsl_flexcan.h" +#include "fsl_edma.h" + +/*! + * @addtogroup flexcan_edma_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FlexCAN EDMA driver version. */ +#define FSL_FLEXCAN_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 9, 2)) +/*@}*/ + +/* Forward declaration of the handle typedef. */ +typedef struct _flexcan_edma_handle flexcan_edma_handle_t; + +/*! @brief FlexCAN transfer callback function. */ +typedef void (*flexcan_edma_transfer_callback_t)(CAN_Type *base, + flexcan_edma_handle_t *handle, + status_t status, + void *userData); + +/*! + * @brief FlexCAN eDMA handle + */ +struct _flexcan_edma_handle +{ + flexcan_edma_transfer_callback_t callback; /*!< Callback function. */ + void *userData; /*!< FlexCAN callback function parameter.*/ + edma_handle_t *rxFifoEdmaHandle; /*!< The EDMA handler for Rx FIFO. */ + volatile uint8_t rxFifoState; /*!< Rx FIFO transfer state. */ + size_t frameNum; /*!< The number of messages that need to be received. */ +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) + flexcan_fd_frame_t *framefd; /*!< Point to the buffer of CAN Message to be received from Enhanced Rx FIFO. */ +#endif +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eDMA transactional + * @{ + */ + +/*! + * @brief Initializes the FlexCAN handle, which is used in transactional functions. + * + * @param base FlexCAN peripheral base address. + * @param handle Pointer to flexcan_edma_handle_t structure. + * @param callback The callback function. + * @param userData The parameter of the callback function. + * @param rxFifoEdmaHandle User-requested DMA handle for Rx FIFO DMA transfer. + */ +void FLEXCAN_TransferCreateHandleEDMA(CAN_Type *base, + flexcan_edma_handle_t *handle, + flexcan_edma_transfer_callback_t callback, + void *userData, + edma_handle_t *rxFifoEdmaHandle); + +/*! + * @brief Prepares the eDMA transfer configuration for FLEXCAN Legacy RX FIFO. + * + * This function prepares the eDMA transfer configuration structure according to FLEXCAN Legacy RX FIFO. + * + * @param base FlexCAN peripheral base address. + * @param pFifoXfer FlexCAN Rx FIFO EDMA transfer structure, see #flexcan_fifo_transfer_t. + * @param pEdmaConfig The user configuration structure of type edma_transfer_t. + * + */ +void FLEXCAN_PrepareTransfConfiguration(CAN_Type *base, + flexcan_fifo_transfer_t *pFifoXfer, + edma_transfer_config_t *pEdmaConfig); + +/*! + * @brief Start Transfer Data from the FLEXCAN Legacy Rx FIFO using eDMA. + * + * This function to Update edma transfer confiugration and Start eDMA transfer + * + * @param base FlexCAN peripheral base address. + * @param handle Pointer to flexcan_edma_handle_t structure. + * @param pEdmaConfig The user configuration structure of type edma_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_FLEXCAN_RxFifoBusy Previous transfer ongoing. + */ +status_t FLEXCAN_StartTransferDatafromRxFIFO(CAN_Type *base, + flexcan_edma_handle_t *handle, + edma_transfer_config_t *pEdmaConfig); + +/*! + * @brief Receives the CAN Message from the Legacy Rx FIFO using eDMA. + * + * This function receives the CAN Message using eDMA. This is a non-blocking function, which returns + * right away. After the CAN Message is received, the receive callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle Pointer to flexcan_edma_handle_t structure. + * @param pFifoXfer FlexCAN Rx FIFO EDMA transfer structure, see #flexcan_fifo_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_FLEXCAN_RxFifoBusy Previous transfer ongoing. + */ +status_t FLEXCAN_TransferReceiveFifoEDMA(CAN_Type *base, + flexcan_edma_handle_t *handle, + flexcan_fifo_transfer_t *pFifoXfer); +/*! + * @brief Gets the Legacy Rx Fifo transfer status during a interrupt non-blocking receive. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param count Number of CAN messages receive so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ + +status_t FLEXCAN_TransferGetReceiveFifoCountEMDA(CAN_Type *base, flexcan_edma_handle_t *handle, size_t *count); +/*! + * @brief Aborts the receive Legacy/Enhanced Rx FIFO process which used eDMA. + * + * This function aborts the receive Legacy/Enhanced Rx FIFO process which used eDMA. + * + * @param base FlexCAN peripheral base address. + * @param handle Pointer to flexcan_edma_handle_t structure. + */ +void FLEXCAN_TransferAbortReceiveFifoEDMA(CAN_Type *base, flexcan_edma_handle_t *handle); + +#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) +/*! + * @brief Receives the CAN FD Message from the Enhanced Rx FIFO using eDMA. + * + * This function receives the CAN FD Message using eDMA. This is a non-blocking function, which returns + * right away. After the CAN Message is received, the receive callback function is called. + * + * @param base FlexCAN peripheral base address. + * @param handle Pointer to flexcan_edma_handle_t structure. + * @param pFifoXfer FlexCAN Rx FIFO EDMA transfer structure, see #flexcan_fifo_transfer_t. + * @retval kStatus_Success if succeed, others failed. + * @retval kStatus_FLEXCAN_RxFifoBusy Previous transfer ongoing. + */ +status_t FLEXCAN_TransferReceiveEnhancedFifoEDMA(CAN_Type *base, + flexcan_edma_handle_t *handle, + flexcan_fifo_transfer_t *pFifoXfer); +/*! + * @brief Gets the Enhanced Rx Fifo transfer status during a interrupt non-blocking receive. + * + * @param base FlexCAN peripheral base address. + * @param handle FlexCAN handle pointer. + * @param count Number of CAN messages receive so far by the non-blocking transaction. + * @retval kStatus_InvalidArgument count is Invalid. + * @retval kStatus_Success Successfully return the count. + */ + +static inline status_t FLEXCAN_TransferGetReceiveEnhancedFifoCountEMDA(CAN_Type *base, + flexcan_edma_handle_t *handle, + size_t *count) +{ + return FLEXCAN_TransferGetReceiveFifoCountEMDA(base, handle, count); +} +#endif + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_FLEXCAN_EDMA_H_ */ |