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Diffstat (limited to '')
27 files changed, 18001 insertions, 0 deletions
diff --git a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/cm4/fsl_cache.c b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/cm4/fsl_cache.c new file mode 100644 index 0000000000..616cde33bd --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/cm4/fsl_cache.c @@ -0,0 +1,507 @@ +/* + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_cache.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.cache_lmem" +#endif + +#define L1CACHE_ONEWAYSIZE_BYTE (4096U) /*!< Cache size is 4K-bytes one way. */ +#define L1CACHE_CODEBUSADDR_BOUNDARY (0x1FFFFFFFU) /*!< The processor code bus address boundary. */ + +/******************************************************************************* + * Code + ******************************************************************************/ +#if (FSL_FEATURE_SOC_LMEM_COUNT == 1) +/*! + * brief Enables the processor code bus cache. + * + */ +void L1CACHE_EnableCodeCache(void) +{ + if (0U == (LMEM->PCCCR & LMEM_PCCCR_ENCACHE_MASK)) + { + /* First, invalidate the entire cache. */ + L1CACHE_InvalidateCodeCache(); + + /* Now enable the cache. */ + LMEM->PCCCR |= LMEM_PCCCR_ENCACHE_MASK; + } +} + +/*! + * brief Disables the processor code bus cache. + * + */ +void L1CACHE_DisableCodeCache(void) +{ + /* First, push any modified contents. */ + L1CACHE_CleanCodeCache(); + + /* Now disable the cache. */ + LMEM->PCCCR &= ~LMEM_PCCCR_ENCACHE_MASK; +} + +/*! + * brief Invalidates the processor code bus cache. + * + */ +void L1CACHE_InvalidateCodeCache(void) +{ + /* Enables the processor code bus to invalidate all lines in both ways. + and Initiate the processor code bus code cache command. */ + LMEM->PCCCR |= LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_GO_MASK; + + /* Wait until the cache command completes. */ + while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U) + { + } + + /* As a precaution clear the bits to avoid inadvertently re-running this command. */ + LMEM->PCCCR &= ~(LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK); +} + +/*! + * brief Invalidates processor code bus cache by range. + * + * param address The physical address of cache. + * param size_byte size of the memory to be invalidated. + * note Address and size should be aligned to "L1CODCACHE_LINESIZE_BYTE". + * The startAddr here will be forced to align to L1CODEBUSCACHE_LINESIZE_BYTE if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L1CACHE_InvalidateCodeCacheByRange(uint32_t address, uint32_t size_byte) +{ + uint32_t endAddr = address + size_byte; + uint32_t pccReg = 0; + /* Align address to cache line size. */ + uint32_t startAddr = address & ~((uint32_t)L1CODEBUSCACHE_LINESIZE_BYTE - 1U); + + /* Set the invalidate by line command and use the physical address. */ + pccReg = (LMEM->PCCLCR & ~LMEM_PCCLCR_LCMD_MASK) | LMEM_PCCLCR_LCMD(1) | LMEM_PCCLCR_LADSEL_MASK; + LMEM->PCCLCR = pccReg; + + while (startAddr < endAddr) + { + /* Set the address and initiate the command. */ + LMEM->PCCSAR = (startAddr & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; + + /* Wait until the cache command completes. */ + while ((LMEM->PCCSAR & LMEM_PCCSAR_LGO_MASK) != 0U) + { + } + startAddr += (uint32_t)L1CODEBUSCACHE_LINESIZE_BYTE; + } +} + +/*! + * brief Cleans the processor code bus cache. + * + */ +void L1CACHE_CleanCodeCache(void) +{ + /* Enable the processor code bus to push all modified lines. */ + LMEM->PCCCR |= LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK | LMEM_PCCCR_GO_MASK; + + /* Wait until the cache command completes. */ + while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U) + { + } + + /* As a precaution clear the bits to avoid inadvertently re-running this command. */ + LMEM->PCCCR &= ~(LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK); +} + +/*! + * brief Cleans processor code bus cache by range. + * + * param address The physical address of cache. + * param size_byte size of the memory to be cleaned. + * note Address and size should be aligned to "L1CODEBUSCACHE_LINESIZE_BYTE". + * The startAddr here will be forced to align to L1CODEBUSCACHE_LINESIZE_BYTE if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L1CACHE_CleanCodeCacheByRange(uint32_t address, uint32_t size_byte) +{ + uint32_t endAddr = address + size_byte; + uint32_t pccReg = 0; + /* Align address to cache line size. */ + uint32_t startAddr = address & ~((uint32_t)L1CODEBUSCACHE_LINESIZE_BYTE - 1U); + + /* Set the push by line command. */ + pccReg = (LMEM->PCCLCR & ~LMEM_PCCLCR_LCMD_MASK) | LMEM_PCCLCR_LCMD(2) | LMEM_PCCLCR_LADSEL_MASK; + LMEM->PCCLCR = pccReg; + + while (startAddr < endAddr) + { + /* Set the address and initiate the command. */ + LMEM->PCCSAR = (startAddr & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; + + /* Wait until the cache command completes. */ + while ((LMEM->PCCSAR & LMEM_PCCSAR_LGO_MASK) != 0U) + { + } + startAddr += (uint32_t)L1CODEBUSCACHE_LINESIZE_BYTE; + } +} + +/*! + * brief Cleans and invalidates the processor code bus cache. + * + */ +void L1CACHE_CleanInvalidateCodeCache(void) +{ + /* Push and invalidate all. */ + LMEM->PCCCR |= LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK | LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK | + LMEM_PCCCR_GO_MASK; + + /* Wait until the cache command completes. */ + while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U) + { + } + + /* As a precaution clear the bits to avoid inadvertently re-running this command. */ + LMEM->PCCCR &= ~(LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK | LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK); +} + +/*! + * brief Cleans and invalidate processor code bus cache by range. + * + * param address The physical address of cache. + * param size_byte size of the memory to be Cleaned and Invalidated. + * note Address and size should be aligned to "L1CODEBUSCACHE_LINESIZE_BYTE". + * The startAddr here will be forced to align to L1CODEBUSCACHE_LINESIZE_BYTE if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L1CACHE_CleanInvalidateCodeCacheByRange(uint32_t address, uint32_t size_byte) +{ + uint32_t endAddr = address + size_byte; + uint32_t pccReg = 0; + /* Align address to cache line size. */ + uint32_t startAddr = address & ~((uint32_t)L1CODEBUSCACHE_LINESIZE_BYTE - 1U); + + /* Set the push by line command. */ + pccReg = (LMEM->PCCLCR & ~LMEM_PCCLCR_LCMD_MASK) | LMEM_PCCLCR_LCMD(3) | LMEM_PCCLCR_LADSEL_MASK; + LMEM->PCCLCR = pccReg; + + while (startAddr < endAddr) + { + /* Set the address and initiate the command. */ + LMEM->PCCSAR = (startAddr & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; + + /* Wait until the cache command completes. */ + while ((LMEM->PCCSAR & LMEM_PCCSAR_LGO_MASK) != 0U) + { + } + startAddr += (uint32_t)L1CODEBUSCACHE_LINESIZE_BYTE; + } +} + +#if defined(FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE) && FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE +/*! + * brief Enables the processor system bus cache. + * + */ +void L1CACHE_EnableSystemCache(void) +{ + /* Only enable when not enabled. */ + if (0U == (LMEM->PSCCR & LMEM_PSCCR_ENCACHE_MASK)) + { + /* First, invalidate the entire cache. */ + L1CACHE_InvalidateSystemCache(); + + /* Now enable the cache. */ + LMEM->PSCCR |= LMEM_PSCCR_ENCACHE_MASK; + } +} + +/*! + * brief Disables the processor system bus cache. + * + */ +void L1CACHE_DisableSystemCache(void) +{ + /* First, push any modified contents. */ + L1CACHE_CleanSystemCache(); + + /* Now disable the cache. */ + LMEM->PSCCR &= ~LMEM_PSCCR_ENCACHE_MASK; +} + +/*! + * brief Invalidates the processor system bus cache. + * + */ +void L1CACHE_InvalidateSystemCache(void) +{ + /* Enables the processor system bus to invalidate all lines in both ways. + and Initiate the processor system bus cache command. */ + LMEM->PSCCR |= LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_GO_MASK; + + /* Wait until the cache command completes */ + while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U) + { + } + + /* As a precaution clear the bits to avoid inadvertently re-running this command. */ + LMEM->PSCCR &= ~(LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK); +} + +/*! + * brief Invalidates processor system bus cache by range. + * + * param address The physical address of cache. + * param size_byte size of the memory to be invalidated. + * note Address and size should be aligned to "L1SYSTEMBUSCACHE_LINESIZE_BYTE". + * The startAddr here will be forced to align to L1SYSTEMBUSCACHE_LINESIZE_BYTE if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L1CACHE_InvalidateSystemCacheByRange(uint32_t address, uint32_t size_byte) +{ + uint32_t endAddr = address + size_byte; + uint32_t pscReg = 0; + uint32_t startAddr = + address & ~((uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE - 1U); /* Align address to cache line size */ + + /* Set the invalidate by line command and use the physical address. */ + pscReg = (LMEM->PSCLCR & ~LMEM_PSCLCR_LCMD_MASK) | LMEM_PSCLCR_LCMD(1) | LMEM_PSCLCR_LADSEL_MASK; + LMEM->PSCLCR = pscReg; + + while (startAddr < endAddr) + { + /* Set the address and initiate the command. */ + LMEM->PSCSAR = (startAddr & LMEM_PSCSAR_PHYADDR_MASK) | LMEM_PSCSAR_LGO_MASK; + + /* Wait until the cache command completes. */ + while ((LMEM->PSCSAR & LMEM_PSCSAR_LGO_MASK) != 0U) + { + } + startAddr += (uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE; + } +} + +/*! + * brief Cleans the processor system bus cache. + * + */ +void L1CACHE_CleanSystemCache(void) +{ + /* Enable the processor system bus to push all modified lines. */ + LMEM->PSCCR |= LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK | LMEM_PSCCR_GO_MASK; + + /* Wait until the cache command completes. */ + while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U) + { + } + + /* As a precaution clear the bits to avoid inadvertently re-running this command. */ + LMEM->PSCCR &= ~(LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK); +} + +/*! + * brief Cleans processor system bus cache by range. + * + * param address The physical address of cache. + * param size_byte size of the memory to be cleaned. + * note Address and size should be aligned to "L1SYSTEMBUSCACHE_LINESIZE_BYTE". + * The startAddr here will be forced to align to L1SYSTEMBUSCACHE_LINESIZE_BYTE if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L1CACHE_CleanSystemCacheByRange(uint32_t address, uint32_t size_byte) +{ + uint32_t endAddr = address + size_byte; + uint32_t pscReg = 0; + uint32_t startAddr = + address & ~((uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE - 1U); /* Align address to cache line size. */ + + /* Set the push by line command. */ + pscReg = (LMEM->PSCLCR & ~LMEM_PSCLCR_LCMD_MASK) | LMEM_PSCLCR_LCMD(2) | LMEM_PSCLCR_LADSEL_MASK; + LMEM->PSCLCR = pscReg; + + while (startAddr < endAddr) + { + /* Set the address and initiate the command. */ + LMEM->PSCSAR = (startAddr & LMEM_PSCSAR_PHYADDR_MASK) | LMEM_PSCSAR_LGO_MASK; + + /* Wait until the cache command completes. */ + while ((LMEM->PSCSAR & LMEM_PSCSAR_LGO_MASK) != 0U) + { + } + startAddr += (uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE; + } +} + +/*! + * brief Cleans and invalidates the processor system bus cache. + * + */ +void L1CACHE_CleanInvalidateSystemCache(void) +{ + /* Push and invalidate all. */ + LMEM->PSCCR |= LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK | LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK | + LMEM_PSCCR_GO_MASK; + + /* Wait until the cache command completes. */ + while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U) + { + } + + /* As a precaution clear the bits to avoid inadvertently re-running this command. */ + LMEM->PSCCR &= ~(LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK | LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK); +} + +/*! + * brief Cleans and Invalidates processor system bus cache by range. + * + * param address The physical address of cache. + * param size_byte size of the memory to be Clean and Invalidated. + * note Address and size should be aligned to "L1SYSTEMBUSCACHE_LINESIZE_BYTE". + * The startAddr here will be forced to align to L1SYSTEMBUSCACHE_LINESIZE_BYTE if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L1CACHE_CleanInvalidateSystemCacheByRange(uint32_t address, uint32_t size_byte) +{ + uint32_t endAddr = address + size_byte; + uint32_t pscReg = 0; + uint32_t startAddr = + address & ~((uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE - 1U); /* Align address to cache line size. */ + + /* Set the push by line command. */ + pscReg = (LMEM->PSCLCR & ~LMEM_PSCLCR_LCMD_MASK) | LMEM_PSCLCR_LCMD(3) | LMEM_PSCLCR_LADSEL_MASK; + LMEM->PSCLCR = pscReg; + + while (startAddr < endAddr) + { + /* Set the address and initiate the command. */ + LMEM->PSCSAR = (startAddr & LMEM_PSCSAR_PHYADDR_MASK) | LMEM_PSCSAR_LGO_MASK; + + /* Wait until the cache command completes. */ + while ((LMEM->PSCSAR & LMEM_PSCSAR_LGO_MASK) != 0U) + { + } + startAddr += (uint32_t)L1SYSTEMBUSCACHE_LINESIZE_BYTE; + } +} + +#endif /* FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */ +#endif /* FSL_FEATURE_SOC_LMEM_COUNT == 1 */ + +/*! + * brief Invalidates cortex-m4 L1 instrument cache by range. + * + * param address The start address of the memory to be invalidated. + * param size_byte The memory size. + * note The start address and size_byte should be 16-Byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned. + */ +void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte) +{ +#if (FSL_FEATURE_SOC_LMEM_COUNT == 1) + uint32_t endAddr = address + size_byte; + uint32_t size = size_byte; + + if (endAddr <= L1CACHE_CODEBUSADDR_BOUNDARY) + { + L1CACHE_InvalidateCodeCacheByRange(address, size); + } + else if (address <= L1CACHE_CODEBUSADDR_BOUNDARY) + { + size = L1CACHE_CODEBUSADDR_BOUNDARY - address; + L1CACHE_InvalidateCodeCacheByRange(address, size); +#if defined(FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE) && FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE + size = size_byte - size; + L1CACHE_InvalidateSystemCacheByRange((L1CACHE_CODEBUSADDR_BOUNDARY + 1U), size); +#endif /* FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */ + } + else + { +#if defined(FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE) && FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE + L1CACHE_InvalidateSystemCacheByRange(address, size); +#endif /* FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */ + } +#endif /* FSL_FEATURE_SOC_LMEM_COUNT == 1 */ +} + +/*! + * brief Cleans cortex-m4 L1 data cache by range. + * + * param address The start address of the memory to be cleaned. + * param size_byte The memory size. + * note The start address and size_byte should be 16-Byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. + */ +void L1CACHE_CleanDCacheByRange(uint32_t address, uint32_t size_byte) +{ +#if (FSL_FEATURE_SOC_LMEM_COUNT == 1) + uint32_t endAddr = address + size_byte; + uint32_t size = size_byte; + + if (endAddr <= L1CACHE_CODEBUSADDR_BOUNDARY) + { + L1CACHE_CleanCodeCacheByRange(address, size); + } + else if (address <= L1CACHE_CODEBUSADDR_BOUNDARY) + { + size = L1CACHE_CODEBUSADDR_BOUNDARY - address; + L1CACHE_CleanCodeCacheByRange(address, size); +#if defined(FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE) && FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE + size = size_byte - size; + L1CACHE_CleanSystemCacheByRange((L1CACHE_CODEBUSADDR_BOUNDARY + 1U), size); +#endif /* FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */ + } + else + { +#if defined(FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE) && FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE + L1CACHE_CleanSystemCacheByRange(address, size); +#endif /* FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */ + } +#endif /* FSL_FEATURE_SOC_LMEM_COUNT == 1 */ +} + +/*! + * brief Cleans and Invalidates cortex-m4 L1 data cache by range. + * + * param address The start address of the memory to be clean and invalidated. + * param size_byte The memory size. + * note The start address and size_byte should be 16-Byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. + */ +void L1CACHE_CleanInvalidateDCacheByRange(uint32_t address, uint32_t size_byte) +{ +#if (FSL_FEATURE_SOC_LMEM_COUNT == 1) + uint32_t endAddr = address + size_byte; + uint32_t size = size_byte; + + if (endAddr <= L1CACHE_CODEBUSADDR_BOUNDARY) + { + L1CACHE_CleanInvalidateCodeCacheByRange(address, size); + } + else if (address <= L1CACHE_CODEBUSADDR_BOUNDARY) + { + size = L1CACHE_CODEBUSADDR_BOUNDARY - address; + L1CACHE_CleanInvalidateCodeCacheByRange(address, size); +#if defined(FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE) && FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE + size = size_byte - size; + L1CACHE_CleanInvalidateSystemCacheByRange((L1CACHE_CODEBUSADDR_BOUNDARY + 1U), size); +#endif /* FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */ + } + else + { +#if defined(FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE) && FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE + L1CACHE_CleanInvalidateSystemCacheByRange(address, size); +#endif /* FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */ + } +#endif /* FSL_FEATURE_SOC_LMEM_COUNT == 1 */ +} diff --git a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/cm4/fsl_cache.h b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/cm4/fsl_cache.h new file mode 100644 index 0000000000..0f32bb0c61 --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/cm4/fsl_cache.h @@ -0,0 +1,340 @@ +/* + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_CACHE_H_ +#define _FSL_CACHE_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup cache_lmem + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief cache driver version. */ +#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 6)) +/*@}*/ + +/*! @brief code bus cache line size is equal to system bus line size, so the unified I/D cache line size equals too. */ +#define L1CODEBUSCACHE_LINESIZE_BYTE \ + FSL_FEATURE_L1ICACHE_LINESIZE_BYTE /*!< The code bus CACHE line size is 16B = 128b. */ +#define L1SYSTEMBUSCACHE_LINESIZE_BYTE \ + L1CODEBUSCACHE_LINESIZE_BYTE /*!< The system bus CACHE line size is 16B = 128b. */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +#if (FSL_FEATURE_SOC_LMEM_COUNT == 1) +/*! + * @name cache control for L1 cache (local memory controller for code/system bus cache) + *@{ + */ + +/*! + * @brief Enables the processor code bus cache. + * + */ +void L1CACHE_EnableCodeCache(void); + +/*! + * @brief Disables the processor code bus cache. + * + */ +void L1CACHE_DisableCodeCache(void); + +/*! + * @brief Invalidates the processor code bus cache. + * + */ +void L1CACHE_InvalidateCodeCache(void); + +/*! + * @brief Invalidates processor code bus cache by range. + * + * @param address The physical address of cache. + * @param size_byte size of the memory to be invalidated. + * @note Address and size should be aligned to "L1CODCACHE_LINESIZE_BYTE". + * The startAddr here will be forced to align to L1CODEBUSCACHE_LINESIZE_BYTE if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L1CACHE_InvalidateCodeCacheByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Cleans the processor code bus cache. + * + */ +void L1CACHE_CleanCodeCache(void); + +/*! + * @brief Cleans processor code bus cache by range. + * + * @param address The physical address of cache. + * @param size_byte size of the memory to be cleaned. + * @note Address and size should be aligned to "L1CODEBUSCACHE_LINESIZE_BYTE". + * The startAddr here will be forced to align to L1CODEBUSCACHE_LINESIZE_BYTE if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L1CACHE_CleanCodeCacheByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Cleans and invalidates the processor code bus cache. + * + */ +void L1CACHE_CleanInvalidateCodeCache(void); + +/*! + * @brief Cleans and invalidate processor code bus cache by range. + * + * @param address The physical address of cache. + * @param size_byte size of the memory to be Cleaned and Invalidated. + * @note Address and size should be aligned to "L1CODEBUSCACHE_LINESIZE_BYTE". + * The startAddr here will be forced to align to L1CODEBUSCACHE_LINESIZE_BYTE if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L1CACHE_CleanInvalidateCodeCacheByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Enables/disables the processor code bus write buffer. + * + * @param enable The enable or disable flag. + * true - enable the code bus write buffer. + * false - disable the code bus write buffer. + */ +static inline void L1CACHE_EnableCodeCacheWriteBuffer(bool enable) +{ + if (enable) + { + LMEM->PCCCR |= LMEM_PCCCR_ENWRBUF_MASK; + } + else + { + LMEM->PCCCR &= ~LMEM_PCCCR_ENWRBUF_MASK; + } +} + +#if defined(FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE) && FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE +/*! + * @brief Enables the processor system bus cache. + * + */ +void L1CACHE_EnableSystemCache(void); + +/*! + * @brief Disables the processor system bus cache. + * + */ +void L1CACHE_DisableSystemCache(void); + +/*! + * @brief Invalidates the processor system bus cache. + * + */ +void L1CACHE_InvalidateSystemCache(void); + +/*! + * @brief Invalidates processor system bus cache by range. + * + * @param address The physical address of cache. + * @param size_byte size of the memory to be invalidated. + * @note Address and size should be aligned to "L1SYSTEMBUSCACHE_LINESIZE_BYTE". + * The startAddr here will be forced to align to L1SYSTEMBUSCACHE_LINESIZE_BYTE if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L1CACHE_InvalidateSystemCacheByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Cleans the processor system bus cache. + * + */ +void L1CACHE_CleanSystemCache(void); + +/*! + * @brief Cleans processor system bus cache by range. + * + * @param address The physical address of cache. + * @param size_byte size of the memory to be cleaned. + * @note Address and size should be aligned to "L1SYSTEMBUSCACHE_LINESIZE_BYTE". + * The startAddr here will be forced to align to L1SYSTEMBUSCACHE_LINESIZE_BYTE if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L1CACHE_CleanSystemCacheByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Cleans and invalidates the processor system bus cache. + * + */ +void L1CACHE_CleanInvalidateSystemCache(void); + +/*! + * @brief Cleans and Invalidates processor system bus cache by range. + * + * @param address The physical address of cache. + * @param size_byte size of the memory to be Clean and Invalidated. + * @note Address and size should be aligned to "L1SYSTEMBUSCACHE_LINESIZE_BYTE". + * The startAddr here will be forced to align to L1SYSTEMBUSCACHE_LINESIZE_BYTE if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L1CACHE_CleanInvalidateSystemCacheByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Enables/disables the processor system bus write buffer. + * + * @param enable The enable or disable flag. + * true - enable the code bus write buffer. + * false - disable the code bus write buffer. + */ +static inline void L1CACHE_EnableSystemCacheWriteBuffer(bool enable) +{ + if (enable) + { + LMEM->PSCCR |= LMEM_PSCCR_ENWRBUF_MASK; + } + else + { + LMEM->PSCCR &= ~LMEM_PSCCR_ENWRBUF_MASK; + } +} +/*@}*/ +#endif /* FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */ + +/*! + * @name cache control for unified L1 cache driver + *@{ + */ + +/*! + * @brief Invalidates cortex-m4 L1 instrument cache by range. + * + * @param address The start address of the memory to be invalidated. + * @param size_byte The memory size. + * @note The start address and size_byte should be 16-Byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned. + */ +void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Invalidates cortex-m4 L1 data cache by range. + * + * @param address The start address of the memory to be invalidated. + * @param size_byte The memory size. + * @note The start address and size_byte should be 16-Byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. + */ +static inline void L1CACHE_InvalidateDCacheByRange(uint32_t address, uint32_t size_byte) +{ + L1CACHE_InvalidateICacheByRange(address, size_byte); +} + +/*! + * @brief Cleans cortex-m4 L1 data cache by range. + * + * @param address The start address of the memory to be cleaned. + * @param size_byte The memory size. + * @note The start address and size_byte should be 16-Byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. + */ +void L1CACHE_CleanDCacheByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Cleans and Invalidates cortex-m4 L1 data cache by range. + * + * @param address The start address of the memory to be clean and invalidated. + * @param size_byte The memory size. + * @note The start address and size_byte should be 16-Byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. + */ +void L1CACHE_CleanInvalidateDCacheByRange(uint32_t address, uint32_t size_byte); +/*@}*/ +#endif /* FSL_FEATURE_SOC_LMEM_COUNT == 1 */ + +/*! + * @name Unified Cache Control for all caches + *@{ + */ + +/*! + * @brief Invalidates instruction cache by range. + * + * @param address The physical address. + * @param size_byte size of the memory to be invalidated. + * @note Address and size should be aligned to 16-Byte due to the cache operation unit + * FSL_FEATURE_L1ICACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line + * size if startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +static inline void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte) +{ + L1CACHE_InvalidateICacheByRange(address, size_byte); +} + +/*! + * @brief Invalidates data cache by range. + * + * @param address The physical address. + * @param size_byte size of the memory to be invalidated. + * @note Address and size should be aligned to 16-Byte due to the cache operation unit + * FSL_FEATURE_L1DCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line + * size if startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +static inline void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte) +{ + L1CACHE_InvalidateDCacheByRange(address, size_byte); +} + +/*! + * @brief Clean data cache by range. + * + * @param address The physical address. + * @param size_byte size of the memory to be cleaned. + * @note Address and size should be aligned to 16-Byte due to the cache operation unit + * FSL_FEATURE_L1DCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line + * size if startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +static inline void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte) +{ + L1CACHE_CleanDCacheByRange(address, size_byte); +} + +/*! + * @brief Cleans and Invalidates data cache by range. + * + * @param address The physical address. + * @param size_byte size of the memory to be Cleaned and Invalidated. + * @note Address and size should be aligned to 16-Byte due to the cache operation unit + * FSL_FEATURE_L1DCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line + * size if startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +static inline void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte) +{ + L1CACHE_CleanInvalidateDCacheByRange(address, size_byte); +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_CACHE_H_*/ diff --git a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/cm7/fsl_cache.c b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/cm7/fsl_cache.c new file mode 100644 index 0000000000..721a3fb04e --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/cm7/fsl_cache.c @@ -0,0 +1,602 @@ +/* + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_cache.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.cache_armv7_m7" +#endif + +#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT +#define L2CACHE_OPERATION_TIMEOUT 0xFFFFFU +#define L2CACHE_8WAYS_MASK 0xFFU +#define L2CACHE_16WAYS_MASK 0xFFFFU +#define L2CACHE_SMALLWAYS_NUM 8U +#define L2CACHE_1KBCOVERTOB 1024U +#define L2CACHE_SAMLLWAYS_SIZE 16U +#define L2CACHE_LOCKDOWN_REGNUM 8 /*!< Lock down register numbers.*/ + /******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Set for all ways and waiting for the operation finished. + * This is provided for all the background operations. + * + * @param auxCtlReg The auxiliary control register. + * @param regAddr The register address to be operated. + */ +static void L2CACHE_SetAndWaitBackGroundOperate(uint32_t auxCtlReg, uint32_t regAddr); + +/*! + * @brief Invalidates the Level 2 cache line by physical address. + * This function invalidates a cache line by physcial address. + * + * @param address The physical addderss of the cache. + * The format of the address shall be : + * bit 31 ~ bit n+1 | bitn ~ bit5 | bit4 ~ bit0 + * Tag | index | 0 + * Note: the physical address shall be aligned to the line size - 32B (256 bit). + * so keep the last 5 bits (bit 4 ~ bit 0) of the physical address always be zero. + * If the input address is not aligned, it will be changed to 32-byte aligned address. + * The n is varies according to the index width. + * @return The actual 32-byte aligned physical address be operated. + */ +static uint32_t L2CACHE_InvalidateLineByAddr(uint32_t address); + +/*! + * @brief Cleans the Level 2 cache line based on the physical address. + * This function cleans a cache line based on a physcial address. + * + * @param address The physical addderss of the cache. + * The format of the address shall be : + * bit 31 ~ bit n+1 | bitn ~ bit5 | bit4 ~ bit0 + * Tag | index | 0 + * Note: the physical address shall be aligned to the line size - 32B (256 bit). + * so keep the last 5 bits (bit 4 ~ bit 0) of the physical address always be zero. + * If the input address is not aligned, it will be changed to 32-byte aligned address. + * The n is varies according to the index width. + * @return The actual 32-byte aligned physical address be operated. + */ +static uint32_t L2CACHE_CleanLineByAddr(uint32_t address); + +/*! + * @brief Cleans and invalidates the Level 2 cache line based on the physical address. + * This function cleans and invalidates a cache line based on a physcial address. + * + * @param address The physical addderss of the cache. + * The format of the address shall be : + * bit 31 ~ bit n+1 | bitn ~ bit5 | bit4 ~ bit0 + * Tag | index | 0 + * Note: the physical address shall be aligned to the line size - 32B (256 bit). + * so keep the last 5 bits (bit 4 ~ bit 0) of the physical address always be zero. + * If the input address is not aligned, it will be changed to 32-byte aligned address. + * The n is varies according to the index width. + * @return The actual 32-byte aligned physical address be operated. + */ +static uint32_t L2CACHE_CleanInvalidateLineByAddr(uint32_t address); + +/*! + * @brief Gets the number of the Level 2 cache and the way size. + * This function cleans and invalidates a cache line based on a physcial address. + * + * @param num_ways The number of the cache way. + * @param size_way The way size. + */ +static void L2CACHE_GetWayNumSize(uint32_t *num_ways, uint32_t *size_way); +/******************************************************************************* + * Code + ******************************************************************************/ +static void L2CACHE_SetAndWaitBackGroundOperate(uint32_t auxCtlReg, uint32_t regAddr) +{ + uint16_t mask = L2CACHE_8WAYS_MASK; + uint32_t timeout = L2CACHE_OPERATION_TIMEOUT; + + /* Check the ways used at first. */ + if (auxCtlReg & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) + { + mask = L2CACHE_16WAYS_MASK; + } + + /* Set the opeartion for all ways/entries of the cache. */ + *(uint32_t *)regAddr = mask; + /* Waiting for until the operation is complete. */ + while ((*(volatile uint32_t *)regAddr & mask) && timeout) + { + __ASM("nop"); + timeout--; + } +} + +static uint32_t L2CACHE_InvalidateLineByAddr(uint32_t address) +{ + /* Align the address first. */ + address &= ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1); + /* Invalidate the cache line by physical address. */ + L2CACHEC->REG7_INV_PA = address; + + return address; +} + +static uint32_t L2CACHE_CleanLineByAddr(uint32_t address) +{ + /* Align the address first. */ + address &= ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1); + /* Invalidate the cache line by physical address. */ + L2CACHEC->REG7_CLEAN_PA = address; + + return address; +} + +static uint32_t L2CACHE_CleanInvalidateLineByAddr(uint32_t address) +{ + /* Align the address first. */ + address &= ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1); + /* Clean and invalidate the cache line by physical address. */ + L2CACHEC->REG7_CLEAN_INV_PA = address; + + return address; +} + +static void L2CACHE_GetWayNumSize(uint32_t *num_ways, uint32_t *size_way) +{ + assert(num_ways); + assert(size_way); + + uint32_t number = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >> + L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_SHIFT; + uint32_t size = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_MASK) >> + L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_SHIFT; + + *num_ways = (number + 1) * L2CACHE_SMALLWAYS_NUM; + if (!size) + { + /* 0 internally mapped to the same size as 1 - 16KB.*/ + size += 1; + } + *size_way = (1 << (size - 1)) * L2CACHE_SAMLLWAYS_SIZE * L2CACHE_1KBCOVERTOB; +} + +/*! + * brief Initializes the level 2 cache controller module. + * + * param config Pointer to configuration structure. See "l2cache_config_t". + */ +void L2CACHE_Init(l2cache_config_t *config) +{ + assert(config); + + uint16_t waysNum = 0xFFU; /* Default use the 8-way mask. */ + uint8_t count; + uint32_t auxReg = 0; + + /*The aux register must be configured when the cachec is disabled + * So disable first if the cache controller is enabled. + */ + if (L2CACHEC->REG1_CONTROL & L2CACHEC_REG1_CONTROL_CE_MASK) + { + L2CACHE_Disable(); + } + + /* Unlock all entries. */ + if (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) + { + waysNum = 0xFFFFU; + } + + for (count = 0; count < L2CACHE_LOCKDOWN_REGNUM; count++) + { + L2CACHE_LockdownByWayEnable(count, waysNum, false); + } + + /* Set the ways and way-size etc. */ + auxReg = L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY(config->wayNum) | + L2CACHEC_REG1_AUX_CONTROL_WAYSIZE(config->waySize) | L2CACHEC_REG1_AUX_CONTROL_CRP(config->repacePolicy) | + L2CACHEC_REG1_AUX_CONTROL_IPE(config->istrPrefetchEnable) | + L2CACHEC_REG1_AUX_CONTROL_DPE(config->dataPrefetchEnable) | + L2CACHEC_REG1_AUX_CONTROL_NLE(config->nsLockdownEnable) | + L2CACHEC_REG1_AUX_CONTROL_FWA(config->writeAlloc) | L2CACHEC_REG1_AUX_CONTROL_HPSDRE(config->writeAlloc); + L2CACHEC->REG1_AUX_CONTROL = auxReg; + + /* Set the tag/data ram latency. */ + if (config->lateConfig) + { + uint32_t data = 0; + /* Tag latency. */ + data = L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) | + L2CACHEC_REG1_TAG_RAM_CONTROL_SL(config->lateConfig->tagSetupLate) | + L2CACHEC_REG1_TAG_RAM_CONTROL_RAL(config->lateConfig->tagReadLate) | + L2CACHEC_REG1_TAG_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); + L2CACHEC->REG1_TAG_RAM_CONTROL = data; + /* Data latency. */ + data = L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) | + L2CACHEC_REG1_DATA_RAM_CONTROL_SL(config->lateConfig->dataSetupLate) | + L2CACHEC_REG1_DATA_RAM_CONTROL_RAL(config->lateConfig->dataReadLate) | + L2CACHEC_REG1_DATA_RAM_CONTROL_WAL(config->lateConfig->dataWriteLate); + L2CACHEC->REG1_DATA_RAM_CONTROL = data; + } +} + +/*! + * brief Gets an available default settings for the cache controller. + * + * This function initializes the cache controller configuration structure with default settings. + * The default values are: + * code + * config->waysNum = kL2CACHE_8ways; + * config->waySize = kL2CACHE_32KbSize; + * config->repacePolicy = kL2CACHE_Roundrobin; + * config->lateConfig = NULL; + * config->istrPrefetchEnable = false; + * config->dataPrefetchEnable = false; + * config->nsLockdownEnable = false; + * config->writeAlloc = kL2CACHE_UseAwcache; + * endcode + * param config Pointer to the configuration structure. + */ +void L2CACHE_GetDefaultConfig(l2cache_config_t *config) +{ + assert(config); + + /* Initializes the configure structure to zero. */ + memset(config, 0, sizeof(*config)); + + uint32_t number = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >> + L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_SHIFT; + uint32_t size = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_MASK) >> + L2CACHEC_REG1_AUX_CONTROL_WAYSIZE_SHIFT; + + /* Get the default value */ + config->wayNum = (l2cache_way_num_t)number; + config->waySize = (l2cache_way_size)size; + config->repacePolicy = kL2CACHE_Roundrobin; + config->lateConfig = NULL; + config->istrPrefetchEnable = false; + config->dataPrefetchEnable = false; + config->nsLockdownEnable = false; + config->writeAlloc = kL2CACHE_UseAwcache; +} + +/*! + * brief Enables the level 2 cache controller. + * This function enables the cache controller. Must be written using a secure access. + * If write with a Non-secure access will cause a DECERR response. + * + */ +void L2CACHE_Enable(void) +{ + /* Invalidate first. */ + L2CACHE_Invalidate(); + /* Enable the level 2 cache controller. */ + L2CACHEC->REG1_CONTROL = L2CACHEC_REG1_CONTROL_CE_MASK; +} + +/*! + * brief Disables the level 2 cache controller. + * This function disables the cache controller. Must be written using a secure access. + * If write with a Non-secure access will cause a DECERR response. + * + */ +void L2CACHE_Disable(void) +{ + /* First CleanInvalidate all enties in the cache. */ + L2CACHE_CleanInvalidate(); + /* Disable the level 2 cache controller. */ + L2CACHEC->REG1_CONTROL &= ~L2CACHEC_REG1_CONTROL_CE_MASK; + /* DSB - data sync barrier.*/ + __DSB(); +} + +/*! + * brief Invalidates the Level 2 cache. + * This function invalidates all entries in cache. + * + */ +void L2CACHE_Invalidate(void) +{ + /* Invalidate all entries in cache. */ + L2CACHE_SetAndWaitBackGroundOperate(L2CACHEC->REG1_AUX_CONTROL, (uint32_t)&L2CACHEC->REG7_INV_WAY); + /* Cache sync. */ + L2CACHEC->REG7_CACHE_SYNC = 0; +} + +/*! + * brief Cleans the level 2 cache controller. + * This function cleans all entries in the level 2 cache controller. + * + */ +void L2CACHE_Clean(void) +{ + /* Clean all entries of the cache. */ + L2CACHE_SetAndWaitBackGroundOperate(L2CACHEC->REG1_AUX_CONTROL, (uint32_t)&L2CACHEC->REG7_CLEAN_WAY); + /* Cache sync. */ + L2CACHEC->REG7_CACHE_SYNC = 0; +} + +/*! + * brief Cleans and invalidates the level 2 cache controller. + * This function cleans and invalidates all entries in the level 2 cache controller. + * + */ +void L2CACHE_CleanInvalidate(void) +{ + /* Clean all entries of the cache. */ + L2CACHE_SetAndWaitBackGroundOperate(L2CACHEC->REG1_AUX_CONTROL, (uint32_t)&L2CACHEC->REG7_CLEAN_INV_WAY); + /* Cache sync. */ + L2CACHEC->REG7_CACHE_SYNC = 0; +} + +/*! + * brief Invalidates the Level 2 cache lines in the range of two physical addresses. + * This function invalidates all cache lines between two physical addresses. + * + * param address The start address of the memory to be invalidated. + * param size_byte The memory size. + * note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned. + * The startAddr here will be forced to align to L2 line size if startAddr + * is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L2CACHE_InvalidateByRange(uint32_t address, uint32_t size_byte) +{ + uint32_t endAddr = address + size_byte; + + /* Invalidate addresses in the range. */ + while (address < endAddr) + { + address = L2CACHE_InvalidateLineByAddr(address); + /* Update the size. */ + address += FSL_FEATURE_L2CACHE_LINESIZE_BYTE; + } + + /* Cache sync. */ + L2CACHEC->REG7_CACHE_SYNC = 0; +} + +/*! + * brief Cleans the Level 2 cache lines in the range of two physical addresses. + * This function cleans all cache lines between two physical addresses. + * + * param address The start address of the memory to be cleaned. + * param size_byte The memory size. + * note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned. + * The startAddr here will be forced to align to L2 line size if startAddr + * is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L2CACHE_CleanByRange(uint32_t address, uint32_t size_byte) +{ + uint32_t num_ways = 0; + uint32_t size_way = 0; + uint32_t endAddr = address + size_byte; + + /* Get the number and size of the cache way. */ + L2CACHE_GetWayNumSize(&num_ways, &size_way); + + /* Check if the clean size is over the cache size. */ + if ((endAddr - address) > num_ways * size_way) + { + L2CACHE_Clean(); + return; + } + + /* Clean addresses in the range. */ + while ((address & ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1)) < endAddr) + { + /* Clean the address in the range. */ + address = L2CACHE_CleanLineByAddr(address); + address += FSL_FEATURE_L2CACHE_LINESIZE_BYTE; + } + + L2CACHEC->REG7_CACHE_SYNC = 0; +} + +/*! + * brief Cleans and invalidates the Level 2 cache lines in the range of two physical addresses. + * This function cleans and invalidates all cache lines between two physical addresses. + * + * param address The start address of the memory to be cleaned and invalidated. + * param size_byte The memory size. + * note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned. + * The startAddr here will be forced to align to L2 line size if startAddr + * is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L2CACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte) +{ + uint32_t num_ways = 0; + uint32_t size_way = 0; + uint32_t endAddr = address + size_byte; + + /* Get the number and size of the cache way. */ + L2CACHE_GetWayNumSize(&num_ways, &size_way); + + /* Check if the clean size is over the cache size. */ + if ((endAddr - address) > num_ways * size_way) + { + L2CACHE_CleanInvalidate(); + return; + } + + /* Clean addresses in the range. */ + while ((address & ~(uint32_t)(FSL_FEATURE_L2CACHE_LINESIZE_BYTE - 1)) < endAddr) + { + /* Clean the address in the range. */ + address = L2CACHE_CleanInvalidateLineByAddr(address); + address += FSL_FEATURE_L2CACHE_LINESIZE_BYTE; + } + + L2CACHEC->REG7_CACHE_SYNC = 0; +} + +/*! + * brief Enables or disables to lock down the data and instruction by way. + * This function locks down the cached instruction/data by way and prevent the adresses from + * being allocated and prevent dara from being evicted out of the level 2 cache. + * But the normal cache maintenance operations that invalidate, clean or clean + * and validate cache contents affect the locked-down cache lines as normal. + * + * param masterId The master id, range from 0 ~ 7. + * param mask The ways to be enabled or disabled to lockdown. + * each bit in value is related to each way of the cache. for example: + * value: bit 0 ------ way 0. + * value: bit 1 ------ way 1. + * -------------------------- + * value: bit 15 ------ way 15. + * Note: please make sure the value setting is align with your supported ways. + * param enable True enable the lockdown, false to disable the lockdown. + */ +void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable) +{ + uint8_t num_ways = (L2CACHEC->REG1_AUX_CONTROL & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK) >> + L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_SHIFT; + num_ways = (num_ways + 1) * L2CACHE_SMALLWAYS_NUM; + + assert(mask < (1U << num_ways)); + assert(masterId < L2CACHE_LOCKDOWN_REGNUM); + + uint32_t dataReg = L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN; + uint32_t istrReg = L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN; + + if (enable) + { + /* Data lockdown. */ + L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg | mask; + /* Instruction lockdown. */ + L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg | mask; + } + else + { + /* Data lockdown. */ + L2CACHEC->LOCKDOWN[masterId].REG9_D_LOCKDOWN = dataReg & ~mask; + /* Instruction lockdown. */ + L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg & ~mask; + } +} +#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ + +/*! + * brief Invalidate cortex-m7 L1 instruction cache by range. + * + * param address The start address of the memory to be invalidated. + * param size_byte The memory size. + * note The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned. + * The startAddr here will be forced to align to L1 I-cache line size if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte) +{ +#if (__DCACHE_PRESENT == 1U) + uint32_t addr = address & ~((uint32_t)FSL_FEATURE_L1ICACHE_LINESIZE_BYTE - 1U); + uint32_t align_len = address - addr; + int32_t size = (int32_t)size_byte + (int32_t)align_len; + + __DSB(); + while (size > 0) + { + SCB->ICIMVAU = addr; + addr += (uint32_t)FSL_FEATURE_L1ICACHE_LINESIZE_BYTE; + size -= (int32_t)FSL_FEATURE_L1ICACHE_LINESIZE_BYTE; + } + __DSB(); + __ISB(); +#endif +} + +/*! + * brief Invalidates all instruction caches by range. + * + * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte. + * + * param address The physical address. + * param size_byte size of the memory to be invalidated. + * note address and size should be aligned to cache line size + * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced + * to align to the cache line size if startAddr is not aligned. For the size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ +void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte) +{ +#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT +#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT + L2CACHE_InvalidateByRange(address, size_byte); +#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */ +#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ + + L1CACHE_InvalidateICacheByRange(address, size_byte); +} + +/*! + * brief Invalidates all data caches by range. + * + * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte. + * + * param address The physical address. + * param size_byte size of the memory to be invalidated. + * note address and size should be aligned to cache line size + * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced + * to align to the cache line size if startAddr is not aligned. For the size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ +void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte) +{ +#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT +#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT + L2CACHE_InvalidateByRange(address, size_byte); +#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */ +#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ + L1CACHE_InvalidateDCacheByRange(address, size_byte); +} + +/*! + * brief Cleans all data caches by range. + * + * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte. + * + * param address The physical address. + * param size_byte size of the memory to be cleaned. + * note address and size should be aligned to cache line size + * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced + * to align to the cache line size if startAddr is not aligned. For the size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ +void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte) +{ + L1CACHE_CleanDCacheByRange(address, size_byte); +#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT +#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT + L2CACHE_CleanByRange(address, size_byte); +#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */ +#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ +} + +/*! + * brief Cleans and Invalidates all data caches by range. + * + * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte. + * + * param address The physical address. + * param size_byte size of the memory to be cleaned and invalidated. + * note address and size should be aligned to cache line size + * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced + * to align to the cache line size if startAddr is not aligned. For the size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ +void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte) +{ + L1CACHE_CleanInvalidateDCacheByRange(address, size_byte); +#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT +#if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT + L2CACHE_CleanInvalidateByRange(address, size_byte); +#endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */ +#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ +} diff --git a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/cm7/fsl_cache.h b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/cm7/fsl_cache.h new file mode 100644 index 0000000000..1ed0597c0c --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/cm7/fsl_cache.h @@ -0,0 +1,463 @@ +/* + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_CACHE_H_ +#define _FSL_CACHE_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup cache_armv7_m7 + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief cache driver version 2.0.4. */ +#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) +/*@}*/ + +#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT +#ifndef FSL_SDK_DISBLE_L2CACHE_PRESENT +#define FSL_SDK_DISBLE_L2CACHE_PRESENT 0 +#endif +#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ +/******************************************************************************* + * Definitions + ******************************************************************************/ +#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT + +/*! @brief Number of level 2 cache controller ways. */ +typedef enum _l2cache_way_num +{ + kL2CACHE_8ways = 0, /*!< 8 ways. */ +#if defined(FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY) && FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY + kL2CACHE_16ways /*!< 16 ways. */ +#endif /* FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY */ +} l2cache_way_num_t; + +/*! @brief Level 2 cache controller way size. */ +typedef enum _l2cache_way_size +{ + kL2CACHE_16KBSize = 1, /*!< 16 KB way size. */ + kL2CACHE_32KBSize = 2, /*!< 32 KB way size. */ + kL2CACHE_64KBSize = 3, /*!< 64 KB way size. */ + kL2CACHE_128KBSize = 4, /*!< 128 KB way size. */ + kL2CACHE_256KBSize = 5, /*!< 256 KB way size. */ + kL2CACHE_512KBSize = 6 /*!< 512 KB way size. */ +} l2cache_way_size; + +/*! @brief Level 2 cache controller replacement policy. */ +typedef enum _l2cache_replacement +{ + kL2CACHE_Pseudorandom = 0U, /*!< Peseudo-random replacement policy using an lfsr. */ + kL2CACHE_Roundrobin /*!< Round-robin replacemnt policy. */ +} l2cache_replacement_t; + +/*! @brief Level 2 cache controller force write allocate options. */ +typedef enum _l2cache_writealloc +{ + kL2CACHE_UseAwcache = 0, /*!< Use AWCAHE attribute for the write allocate. */ + kL2CACHE_NoWriteallocate, /*!< Force no write allocate. */ + kL2CACHE_forceWriteallocate /*!< Force write allocate when write misses. */ +} l2cache_writealloc_t; + +/*! @brief Level 2 cache controller tag/data ram latency. */ +typedef enum _l2cache_latency +{ + kL2CACHE_1CycleLate = 0, /*!< 1 cycle of latency. */ + kL2CACHE_2CycleLate, /*!< 2 cycle of latency. */ + kL2CACHE_3CycleLate, /*!< 3 cycle of latency. */ + kL2CACHE_4CycleLate, /*!< 4 cycle of latency. */ + kL2CACHE_5CycleLate, /*!< 5 cycle of latency. */ + kL2CACHE_6CycleLate, /*!< 6 cycle of latency. */ + kL2CACHE_7CycleLate, /*!< 7 cycle of latency. */ + kL2CACHE_8CycleLate /*!< 8 cycle of latency. */ +} l2cache_latency_t; + +/*! @brief Level 2 cache controller tag/data ram latency configure structure. */ +typedef struct _l2cache_latency_config +{ + l2cache_latency_t tagWriteLate; /*!< Tag write latency. */ + l2cache_latency_t tagReadLate; /*!< Tag Read latency. */ + l2cache_latency_t tagSetupLate; /*!< Tag setup latency. */ + l2cache_latency_t dataWriteLate; /*!< Data write latency. */ + l2cache_latency_t dataReadLate; /*!< Data Read latency. */ + l2cache_latency_t dataSetupLate; /*!< Data setup latency. */ +} L2cache_latency_config_t; + +/*! @brief Level 2 cache controller configure structure. */ +typedef struct _l2cache_config +{ + /* ------------------------ l2 cachec basic settings ---------------------------- */ + l2cache_way_num_t wayNum; /*!< The number of ways. */ + l2cache_way_size waySize; /*!< The way size = Cache Ram size / wayNum. */ + l2cache_replacement_t repacePolicy; /*!< Replacemnet policy. */ + /* ------------------------ tag/data ram latency settings ----------------------- */ + L2cache_latency_config_t *lateConfig; /*!< Tag/data latency configure. Set NUll if not required. */ + /* ------------------------ Prefetch enable settings ---------------------------- */ + bool istrPrefetchEnable; /*!< Instruction prefetch enable. */ + bool dataPrefetchEnable; /*!< Data prefetch enable. */ + /* ------------------------ Non-secure access settings -------------------------- */ + bool nsLockdownEnable; /*!< None-secure lockdown enable. */ + /* ------------------------ other settings -------------------------------------- */ + l2cache_writealloc_t writeAlloc; /*!< Write allcoate force option. */ +} l2cache_config_t; +#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Control for cortex-m7 L1 cache + *@{ + */ + +/*! + * @brief Enables cortex-m7 L1 instruction cache. + * + */ +static inline void L1CACHE_EnableICache(void) +{ + SCB_EnableICache(); +} + +/*! + * @brief Disables cortex-m7 L1 instruction cache. + * + */ +static inline void L1CACHE_DisableICache(void) +{ + if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR)) + { + SCB_DisableICache(); + } +} + +/*! + * @brief Invalidate cortex-m7 L1 instruction cache. + * + */ +static inline void L1CACHE_InvalidateICache(void) +{ + SCB_InvalidateICache(); +} + +/*! + * @brief Invalidate cortex-m7 L1 instruction cache by range. + * + * @param address The start address of the memory to be invalidated. + * @param size_byte The memory size. + * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned. + * The startAddr here will be forced to align to L1 I-cache line size if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Enables cortex-m7 L1 data cache. + * + */ +static inline void L1CACHE_EnableDCache(void) +{ + SCB_EnableDCache(); +} + +/*! + * @brief Disables cortex-m7 L1 data cache. + * + */ +static inline void L1CACHE_DisableDCache(void) +{ + if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR)) + { + SCB_DisableDCache(); + } +} + +/*! + * @brief Invalidates cortex-m7 L1 data cache. + * + */ +static inline void L1CACHE_InvalidateDCache(void) +{ + SCB_InvalidateDCache(); +} + +/*! + * @brief Cleans cortex-m7 L1 data cache. + * + */ +static inline void L1CACHE_CleanDCache(void) +{ + SCB_CleanDCache(); +} + +/*! + * @brief Cleans and Invalidates cortex-m7 L1 data cache. + * + */ +static inline void L1CACHE_CleanInvalidateDCache(void) +{ + SCB_CleanInvalidateDCache(); +} + +/*! + * @brief Invalidates cortex-m7 L1 data cache by range. + * + * @param address The start address of the memory to be invalidated. + * @param size_byte The memory size. + * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. + * The startAddr here will be forced to align to L1 D-cache line size if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +static inline void L1CACHE_InvalidateDCacheByRange(uint32_t address, uint32_t size_byte) +{ + SCB_InvalidateDCache_by_Addr((uint32_t *)address, (int32_t)size_byte); +} + +/*! + * @brief Cleans cortex-m7 L1 data cache by range. + * + * @param address The start address of the memory to be cleaned. + * @param size_byte The memory size. + * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. + * The startAddr here will be forced to align to L1 D-cache line size if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +static inline void L1CACHE_CleanDCacheByRange(uint32_t address, uint32_t size_byte) +{ + SCB_CleanDCache_by_Addr((uint32_t *)address, (int32_t)size_byte); +} + +/*! + * @brief Cleans and Invalidates cortex-m7 L1 data cache by range. + * + * @param address The start address of the memory to be clean and invalidated. + * @param size_byte The memory size. + * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned. + * The startAddr here will be forced to align to L1 D-cache line size if + * startAddr is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +static inline void L1CACHE_CleanInvalidateDCacheByRange(uint32_t address, uint32_t size_byte) +{ + SCB_CleanInvalidateDCache_by_Addr((uint32_t *)address, (int32_t)size_byte); +} +/*@}*/ + +#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT +/*! + * @name Control for L2 pl310 cache + *@{ + */ + +/*! + * @brief Initializes the level 2 cache controller module. + * + * @param config Pointer to configuration structure. See "l2cache_config_t". + */ +void L2CACHE_Init(l2cache_config_t *config); + +/*! + * @brief Gets an available default settings for the cache controller. + * + * This function initializes the cache controller configuration structure with default settings. + * The default values are: + * @code + * config->waysNum = kL2CACHE_8ways; + * config->waySize = kL2CACHE_32KbSize; + * config->repacePolicy = kL2CACHE_Roundrobin; + * config->lateConfig = NULL; + * config->istrPrefetchEnable = false; + * config->dataPrefetchEnable = false; + * config->nsLockdownEnable = false; + * config->writeAlloc = kL2CACHE_UseAwcache; + * @endcode + * @param config Pointer to the configuration structure. + */ +void L2CACHE_GetDefaultConfig(l2cache_config_t *config); + +/*! + * @brief Enables the level 2 cache controller. + * This function enables the cache controller. Must be written using a secure access. + * If write with a Non-secure access will cause a DECERR response. + * + */ +void L2CACHE_Enable(void); + +/*! + * @brief Disables the level 2 cache controller. + * This function disables the cache controller. Must be written using a secure access. + * If write with a Non-secure access will cause a DECERR response. + * + */ +void L2CACHE_Disable(void); + +/*! + * @brief Invalidates the Level 2 cache. + * This function invalidates all entries in cache. + * + */ +void L2CACHE_Invalidate(void); + +/*! + * @brief Invalidates the Level 2 cache lines in the range of two physical addresses. + * This function invalidates all cache lines between two physical addresses. + * + * @param address The start address of the memory to be invalidated. + * @param size_byte The memory size. + * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned. + * The startAddr here will be forced to align to L2 line size if startAddr + * is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L2CACHE_InvalidateByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Cleans the level 2 cache controller. + * This function cleans all entries in the level 2 cache controller. + * + */ +void L2CACHE_Clean(void); + +/*! + * @brief Cleans the Level 2 cache lines in the range of two physical addresses. + * This function cleans all cache lines between two physical addresses. + * + * @param address The start address of the memory to be cleaned. + * @param size_byte The memory size. + * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned. + * The startAddr here will be forced to align to L2 line size if startAddr + * is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L2CACHE_CleanByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Cleans and invalidates the level 2 cache controller. + * This function cleans and invalidates all entries in the level 2 cache controller. + * + */ +void L2CACHE_CleanInvalidate(void); + +/*! + * @brief Cleans and invalidates the Level 2 cache lines in the range of two physical addresses. + * This function cleans and invalidates all cache lines between two physical addresses. + * + * @param address The start address of the memory to be cleaned and invalidated. + * @param size_byte The memory size. + * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned. + * The startAddr here will be forced to align to L2 line size if startAddr + * is not aligned. For the size_byte, application should make sure the + * alignment or make sure the right operation order if the size_byte is not aligned. + */ +void L2CACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Enables or disables to lock down the data and instruction by way. + * This function locks down the cached instruction/data by way and prevent the adresses from + * being allocated and prevent dara from being evicted out of the level 2 cache. + * But the normal cache maintenance operations that invalidate, clean or clean + * and validate cache contents affect the locked-down cache lines as normal. + * + * @param masterId The master id, range from 0 ~ 7. + * @param mask The ways to be enabled or disabled to lockdown. + * each bit in value is related to each way of the cache. for example: + * value: bit 0 ------ way 0. + * value: bit 1 ------ way 1. + * -------------------------- + * value: bit 15 ------ way 15. + * Note: please make sure the value setting is align with your supported ways. + * @param enable True enable the lockdown, false to disable the lockdown. + */ +void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable); + +/*@}*/ +#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */ + +/*! + * @name Unified Cache Control for all caches (cortex-m7 L1 cache + l2 pl310) + * Mainly used for many drivers for easy cache operation. + *@{ + */ + +/*! + * @brief Invalidates all instruction caches by range. + * + * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte. + * + * @param address The physical address. + * @param size_byte size of the memory to be invalidated. + * @note address and size should be aligned to cache line size + * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced + * to align to the cache line size if startAddr is not aligned. For the size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ +void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Invalidates all data caches by range. + * + * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte. + * + * @param address The physical address. + * @param size_byte size of the memory to be invalidated. + * @note address and size should be aligned to cache line size + * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced + * to align to the cache line size if startAddr is not aligned. For the size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ +void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Cleans all data caches by range. + * + * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte. + * + * @param address The physical address. + * @param size_byte size of the memory to be cleaned. + * @note address and size should be aligned to cache line size + * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced + * to align to the cache line size if startAddr is not aligned. For the size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ +void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte); + +/*! + * @brief Cleans and Invalidates all data caches by range. + * + * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte. + * + * @param address The physical address. + * @param size_byte size of the memory to be cleaned and invalidated. + * @note address and size should be aligned to cache line size + * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced + * to align to the cache line size if startAddr is not aligned. For the size_byte, application should + * make sure the alignment or make sure the right operation order if the size_byte is not aligned. + */ +void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* _FSL_CACHE_H_*/ diff --git a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_anatop_ai.c b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_anatop_ai.c new file mode 100644 index 0000000000..c78ded8d50 --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_anatop_ai.c @@ -0,0 +1,357 @@ +/* + * Copyright 2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_anatop_ai.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.anatop_ai" +#endif + +uint32_t ANATOP_AI_Access(anatop_ai_itf_t itf, bool isWrite, anatop_ai_reg_t addr, uint32_t wdata) +{ + uint32_t temp; + uint32_t rdata; + uint32_t pre_toggle_done; + uint32_t toggle_done; + + switch (itf) + { + case kAI_Itf_Ldo: + if (isWrite) + { + ANADIG_MISC->VDDSOC_AI_CTRL &= ~ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_MASK; + temp = ANADIG_MISC->VDDSOC_AI_CTRL; + temp &= ~ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK; + temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_SHIFT) & + ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK; + ANADIG_MISC->VDDSOC_AI_CTRL = temp; + ANADIG_MISC->VDDSOC_AI_WDATA = wdata; /* write ai data */ + ANADIG_PMU->PMU_LDO_PLL ^= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK; /* toggle */ + } + else /* read */ + { + temp = ANADIG_MISC->VDDSOC_AI_CTRL; + temp &= ~ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_MASK; + temp |= (1UL << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_SHIFT) & + ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_MASK; + ANADIG_MISC->VDDSOC_AI_CTRL = temp; + temp = ANADIG_MISC->VDDSOC_AI_CTRL; + temp &= ~ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK; + temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_SHIFT) & + ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK; + ANADIG_MISC->VDDSOC_AI_CTRL = temp; + ANADIG_PMU->PMU_LDO_PLL ^= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK; /* toggle */ + rdata = ANADIG_MISC->VDDSOC_AI_RDATA; /* read data */ + return rdata; + } + break; + case kAI_Itf_1g: + if (isWrite) + { + pre_toggle_done = + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK; /* get pre_toggle_done */ + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_MASK; + temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G; + temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK; + temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_SHIFT) & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK; + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G = temp; + ANADIG_MISC->VDDSOC2PLL_AI_WDATA_1G = wdata; /* write ai data */ + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G ^= + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_MASK; /* toggle */ + do + { + toggle_done = + (ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK); /* wait toggle done + toggle */ + } while (toggle_done == pre_toggle_done); + } + else + { + pre_toggle_done = + (ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK); /* get pre_toggle_done */ + temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G; + temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_MASK; + temp |= (1UL << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_SHIFT) & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_MASK; + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G = temp; + temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G; + temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK; + temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_SHIFT) & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK; + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G = temp; + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G ^= + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_MASK; /* toggle */ + do + { + toggle_done = + (ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK); /* wait toggle done + toggle */ + } while (toggle_done == pre_toggle_done); + rdata = ANADIG_MISC->VDDSOC2PLL_AI_RDATA_1G; /* read data */ + return rdata; + } + break; + case kAI_Itf_Audio: + if (isWrite) + { + pre_toggle_done = + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK; /* get pre_toggle_done */ + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO &= + ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK; + temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO; + temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK; + temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_SHIFT) & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK; + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO = temp; + ANADIG_MISC->VDDSOC2PLL_AI_WDATA_AUDIO = wdata; /* write ai data */ + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO ^= + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_MASK; /* toggle */ + do + { + toggle_done = + (ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK); /* wait toggle done + toggle */ + } while (toggle_done == pre_toggle_done); + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO &= + ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK; + } + else + { + pre_toggle_done = + (ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK); /* get pre_toggle_done + */ + + temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO; + temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK; + temp |= (1UL << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_SHIFT) & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK; + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO = temp; + + temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO; + temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK; + temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_SHIFT) & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK; + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO = temp; + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO ^= + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_MASK; /* toggle */ + do + { + toggle_done = + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK; /* wait toggle done + toggle */ + } while (toggle_done == pre_toggle_done); + rdata = ANADIG_MISC->VDDSOC2PLL_AI_RDATA_AUDIO; /* read data */ + return rdata; + } + break; + case kAI_Itf_Video: + if (isWrite) + { + pre_toggle_done = + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK; /* get pre_toggle_done */ + + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO &= + ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK; + + temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO; + temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK; + temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_SHIFT) & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK; + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO = temp; + ANADIG_MISC->VDDSOC2PLL_AI_WDATA_VIDEO = wdata; /* write ai data */ + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO ^= + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_MASK; /* toggle */ + do + { + toggle_done = + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK; /* wait toggle done + toggle */ + } while (toggle_done == pre_toggle_done); + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO &= + ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK; + } + else + { + pre_toggle_done = + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK; /* get pre_toggle_done */ + temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO; + temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK; + temp |= (1UL << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_SHIFT) & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK; + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO = temp; + + temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO; + temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK; + temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_SHIFT) & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK; + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO = temp; + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO ^= + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_MASK; /* toggle */ + do + { + toggle_done = + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK; /* wait toggle done + toggle */ + } while (toggle_done == pre_toggle_done); + rdata = ANADIG_MISC->VDDSOC2PLL_AI_RDATA_VIDEO; /* read data */ + return rdata; + } + break; + case kAI_Itf_400m: + if (isWrite) + { + pre_toggle_done = + ANADIG_MISC->VDDLPSR_AI400M_CTRL & + ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK; /* get pre_toggle_done */ + ANADIG_MISC->VDDLPSR_AI400M_CTRL &= ~ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_MASK; + + temp = ANADIG_MISC->VDDLPSR_AI400M_CTRL; + temp &= ~ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK; + temp |= ((uint32_t)addr << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_SHIFT) & + ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK; + ANADIG_MISC->VDDLPSR_AI400M_CTRL = temp; + ANADIG_MISC->VDDLPSR_AI400M_WDATA = wdata; /* write ai data */ + ANADIG_MISC->VDDLPSR_AI400M_CTRL ^= + ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_MASK; /* toggle */ + do + { + toggle_done = + ANADIG_MISC->VDDLPSR_AI400M_CTRL & + ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK; /* wait toggle done toggle */ + } while (toggle_done == pre_toggle_done); + } + else + { + pre_toggle_done = + ANADIG_MISC->VDDLPSR_AI400M_CTRL & + ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK; /* get pre_toggle_done */ + + temp = ANADIG_MISC->VDDLPSR_AI400M_CTRL; + temp &= ~ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_MASK; + temp |= (1UL << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_SHIFT) & + ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_MASK; + ANADIG_MISC->VDDLPSR_AI400M_CTRL = temp; + + temp = ANADIG_MISC->VDDLPSR_AI400M_CTRL; + temp &= ~ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK; + temp |= ((uint32_t)addr << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_SHIFT) & + ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK; + ANADIG_MISC->VDDLPSR_AI400M_CTRL = temp; + ANADIG_MISC->VDDLPSR_AI400M_CTRL ^= + ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_MASK; /* toggle */ + do + { + toggle_done = + ANADIG_MISC->VDDLPSR_AI400M_CTRL & + ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK; /* wait toggle done toggle */ + } while (toggle_done == pre_toggle_done); + rdata = ANADIG_MISC->VDDLPSR_AI400M_RDATA; /* read data */ + return rdata; + } + break; + case kAI_Itf_Temp: + if (isWrite) + { + ANADIG_MISC->VDDLPSR_AI_CTRL &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK; + + temp = ANADIG_MISC->VDDLPSR_AI_CTRL; + temp &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK; + temp |= ((uint32_t)addr << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT) & + ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK; + ANADIG_MISC->VDDLPSR_AI_CTRL = temp; + ANADIG_MISC->VDDLPSR_AI_WDATA = wdata; /* write ai data */ + ANADIG_TEMPSENSOR->TEMPSENSOR ^= ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_MASK; /* toggle */ + } + else + { + temp = ANADIG_MISC->VDDLPSR_AI_CTRL; + temp &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK; + temp |= (1UL << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_SHIFT) & + ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK; + ANADIG_MISC->VDDLPSR_AI_CTRL = temp; + + temp = ANADIG_MISC->VDDLPSR_AI_CTRL; + temp &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK; + temp |= ((uint32_t)addr << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT) & + ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK; + ANADIG_MISC->VDDLPSR_AI_CTRL = temp; + ANADIG_TEMPSENSOR->TEMPSENSOR ^= ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_MASK; /* toggle */ + rdata = ANADIG_MISC->VDDLPSR_AI_RDATA_TMPSNS; /* read data */ + return rdata; + } + break; + case kAI_Itf_Bandgap: + if (isWrite) + { + ANADIG_MISC->VDDLPSR_AI_CTRL &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK; + + temp = ANADIG_MISC->VDDLPSR_AI_CTRL; + temp &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK; + temp |= ((uint32_t)addr << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT) & + ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK; + ANADIG_MISC->VDDLPSR_AI_CTRL = temp; + ANADIG_MISC->VDDLPSR_AI_WDATA = wdata; /* write ai data */ + ANADIG_PMU->PMU_REF_CTRL ^= ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_MASK; /* toggle */ + } + else + { + temp = ANADIG_MISC->VDDLPSR_AI_CTRL; + temp &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK; + temp |= (1UL << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_SHIFT) & + ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK; + ANADIG_MISC->VDDLPSR_AI_CTRL = temp; + + temp = ANADIG_MISC->VDDLPSR_AI_CTRL; + temp &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK; + temp |= ((uint32_t)addr << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT) & + ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK; + ANADIG_MISC->VDDLPSR_AI_CTRL = temp; + ANADIG_PMU->PMU_REF_CTRL ^= ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_MASK; /* toggle */ + rdata = ANADIG_MISC->VDDLPSR_AI_RDATA_REFTOP; /* read data */ + return rdata; + } + break; + default: + /* This branch should never be hit. */ + break; + } + return 0; +} + +void ANATOP_AI_Write(anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata) +{ + (void)ANATOP_AI_Access(itf, true, addr, wdata); +} + +uint32_t ANATOP_AI_Read(anatop_ai_itf_t itf, anatop_ai_reg_t addr) +{ + uint32_t rdata; + rdata = ANATOP_AI_Access(itf, false, addr, 0); + return rdata; +} + +void ANATOP_AI_WriteWithMaskShift( + anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata, uint32_t mask, uint32_t shift) +{ + uint32_t rdata; + rdata = ANATOP_AI_Read(itf, addr); + rdata = (rdata & (~mask)) | ((wdata << shift) & mask); + ANATOP_AI_Write(itf, addr, rdata); +} diff --git a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_anatop_ai.h b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_anatop_ai.h new file mode 100644 index 0000000000..f498672a04 --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_anatop_ai.h @@ -0,0 +1,533 @@ +/* + * Copyright 2019,2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_ANATOP_AI_H_ +#define _FSL_ANATOP_AI_H_ + +#include "fsl_common.h" +/*! @addtogroup anatop_ai */ +/*! @{ */ + +/*! @file */ + +/*! @name Driver version */ +/*@{*/ +/*! @brief Anatop AI driver version 1.0.0. */ +#define FSL_ANATOP_AI_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) +/*@}*/ + +/*! + * @brief Anatop AI ITF enumeration. + */ +typedef enum _anatop_ai_itf +{ + kAI_Itf_Ldo = 0, /*!< LDO ITF. */ + kAI_Itf_1g = 1, /*!< 1G PLL ITF. */ + kAI_Itf_Audio = 2, /*!< Audio PLL ITF. */ + kAI_Itf_Video = 3, /*!< Video PLL ITF. */ + kAI_Itf_400m = 4, /*!< 400M OSC ITF. */ + kAI_Itf_Temp = 5, /*!< Temperature Sensor ITF. */ + kAI_Itf_Bandgap = 6, /*!< Bandgap ITF. */ +} anatop_ai_itf_t; + +/*! + * @brief The enumeration of ANATOP AI Register. + */ +typedef enum _anatop_ai_reg +{ + kAI_PHY_LDO_CTRL0 = 0x0, /*!< PHY LDO CTRL0 Register. */ + kAI_PHY_LDO_CTRL0_SET = 0x4, /*!< PHY LDO CTRL0 Set Register. */ + kAI_PHY_LDO_CTRL0_CLR = 0x8, /*!< PHY LDO CTRL0 Clr Register. */ + kAI_PHY_LDO_CTRL0_TOG = 0xC, /*!< PHY LDO CTRL0 TOG Register. */ + kAI_PHY_LDO_STAT0 = 0x50, /*!< PHY LDO STAT0 Register. */ + kAI_PHY_LDO_STAT0_SET = 0x54, /*!< PHY LDO STAT0 Set Register. */ + kAI_PHY_LDO_STAT0_CLR = 0x58, /*!< PHY LDO STAT0 Clr Register. */ + kAI_PHY_LDO_STAT0_TOG = 0x5C, /*!< PHY LDO STAT0 Tog Register. */ + + kAI_BANDGAP_CTRL0 = 0x0, /*!< BANDGAP CTRL0 Register. */ + kAI_BANDGAP_STAT0 = 0x50, /*!< BANDGAP STAT0 Register. */ + + kAI_RCOSC400M_CTRL0 = 0x0, /*!< RC OSC 400M CTRL0 Register. */ + kAI_RCOSC400M_CTRL0_SET = 0x4, /*!< RC OSC 400M CTRL0 SET Register. */ + kAI_RCOSC400M_CTRL0_CLR = 0x8, /*!< RC OSC 400M CTRL0 CLR Register. */ + kAI_RCOSC400M_CTRL0_TOG = 0xC, /*!< RC OSC 400M CTRL0 TOG Register. */ + kAI_RCOSC400M_CTRL1 = 0x10, /*!< RC OSC 400M CTRL1 Register. */ + kAI_RCOSC400M_CTRL1_SET = 0x14, /*!< RC OSC 400M CTRL1 SET Register. */ + kAI_RCOSC400M_CTRL1_CLR = 0x18, /*!< RC OSC 400M CTRL1 CLR Register. */ + kAI_RCOSC400M_CTRL1_TOG = 0x1C, /*!< RC OSC 400M CTRL1 TOG Register. */ + kAI_RCOSC400M_CTRL2 = 0x20, /*!< RC OSC 400M CTRL2 Register. */ + kAI_RCOSC400M_CTRL2_SET = 0x24, /*!< RC OSC 400M CTRL2 SET Register. */ + kAI_RCOSC400M_CTRL2_CLR = 0x28, /*!< RC OSC 400M CTRL2 CLR Register. */ + kAI_RCOSC400M_CTRL2_TOG = 0x2C, /*!< RC OSC 400M CTRL2 TOG Register. */ + kAI_RCOSC400M_CTRL3 = 0x30, /*!< RC OSC 400M CTRL3 Register. */ + kAI_RCOSC400M_CTRL3_SET = 0x34, /*!< RC OSC 400M CTRL3 SET Register. */ + kAI_RCOSC400M_CTRL3_CLR = 0x38, /*!< RC OSC 400M CTRL3 CLR Register. */ + kAI_RCOSC400M_CTRL3_TOG = 0x3C, /*!< RC OSC 400M CTRL3 TOG Register. */ + kAI_RCOSC400M_STAT0 = 0x50, /*!< RC OSC 400M STAT0 Register. */ + kAI_RCOSC400M_STAT0_SET = 0x54, /*!< RC OSC 400M STAT0 SET Register. */ + kAI_RCOSC400M_STAT0_CLR = 0x58, /*!< RC OSC 400M STAT0 CLR Register. */ + kAI_RCOSC400M_STAT0_TOG = 0x5C, /*!< RC OSC 400M STAT0 TOG Register. */ + kAI_RCOSC400M_STAT1 = 0x60, /*!< RC OSC 400M STAT1 Register. */ + kAI_RCOSC400M_STAT1_SET = 0x64, /*!< RC OSC 400M STAT1 SET Register. */ + kAI_RCOSC400M_STAT1_CLR = 0x68, /*!< RC OSC 400M STAT1 CLR Register. */ + kAI_RCOSC400M_STAT1_TOG = 0x6C, /*!< RC OSC 400M STAT1 TOG Register. */ + kAI_RCOSC400M_STAT2 = 0x70, /*!< RC OSC 400M STAT2 Register. */ + kAI_RCOSC400M_STAT2_SET = 0x74, /*!< RC OSC 400M STAT2 SET Register. */ + kAI_RCOSC400M_STAT2_CLR = 0x78, /*!< RC OSC 400M STAT2 CLR Register. */ + kAI_RCOSC400M_STAT2_TOG = 0x7C, /*!< RC OSC 400M STAT2 TOG Register. */ + + kAI_PLL1G_CTRL0 = 0x0, /*!< 1G PLL CTRL0 Register. */ + kAI_PLL1G_CTRL0_SET = 0x4, /*!< 1G PLL CTRL0 SET Register. */ + kAI_PLL1G_CTRL0_CLR = 0x8, /*!< 1G PLL CTRL0 CLR Register. */ + kAI_PLL1G_CTRL1 = 0x10, /*!< 1G PLL CTRL1 Register. */ + kAI_PLL1G_CTRL1_SET = 0x14, /*!< 1G PLL CTRL1 SET Register. */ + kAI_PLL1G_CTRL1_CLR = 0x18, /*!< 1G PLL CTRL1 CLR Register. */ + kAI_PLL1G_CTRL2 = 0x20, /*!< 1G PLL CTRL2 Register. */ + kAI_PLL1G_CTRL2_SET = 0x24, /*!< 1G PLL CTRL2 SET Register. */ + kAI_PLL1G_CTRL2_CLR = 0x28, /*!< 1G PLL CTRL2 CLR Register. */ + kAI_PLL1G_CTRL3 = 0x30, /*!< 1G PLL CTRL3 Register. */ + kAI_PLL1G_CTRL3_SET = 0x34, /*!< 1G PLL CTRL3 SET Register. */ + kAI_PLL1G_CTRL3_CLR = 0x38, /*!< 1G PLL CTRL3 CLR Register. */ + + kAI_PLLAUDIO_CTRL0 = 0x0, /*!< AUDIO PLL CTRL0 Register. */ + kAI_PLLAUDIO_CTRL0_SET = 0x4, /*!< AUDIO PLL CTRL0 SET Register. */ + kAI_PLLAUDIO_CTRL0_CLR = 0x8, /*!< AUDIO PLL CTRL0 CLR Register. */ + kAI_PLLAUDIO_CTRL1 = 0x10, /*!< AUDIO PLL CTRL1 Register. */ + kAI_PLLAUDIO_CTRL1_SET = 0x14, /*!< AUDIO PLL CTRL1 SET Register. */ + kAI_PLLAUDIO_CTRL1_CLR = 0x18, /*!< AUDIO PLL CTRL1 CLR Register. */ + kAI_PLLAUDIO_CTRL2 = 0x20, /*!< AUDIO PLL CTRL2 Register. */ + kAI_PLLAUDIO_CTRL2_SET = 0x24, /*!< AUDIO PLL CTRL2 SET Register. */ + kAI_PLLAUDIO_CTRL2_CLR = 0x28, /*!< AUDIO PLL CTRL2 CLR Register. */ + kAI_PLLAUDIO_CTRL3 = 0x30, /*!< AUDIO PLL CTRL3 Register. */ + kAI_PLLAUDIO_CTRL3_SET = 0x34, /*!< AUDIO PLL CTRL3 SET Register. */ + kAI_PLLAUDIO_CTRL3_CLR = 0x38, /*!< AUDIO PLL CTRL3 CLR Register. */ + + kAI_PLLVIDEO_CTRL0 = 0x0, /*!< VIDEO PLL CTRL0 Register. */ + kAI_PLLVIDEO_CTRL0_SET = 0x4, /*!< VIDEO PLL CTRL0 SET Register. */ + kAI_PLLVIDEO_CTRL0_CLR = 0x8, /*!< VIDEO PLL CTRL0 CLR Register. */ + kAI_PLLVIDEO_CTRL1 = 0x10, /*!< VIDEO PLL CTRL1 Register. */ + kAI_PLLVIDEO_CTRL1_SET = 0x14, /*!< VIDEO PLL CTRL1 SET Register. */ + kAI_PLLVIDEO_CTRL1_CLR = 0x18, /*!< VIDEO PLL CTRL1 CLR Register. */ + kAI_PLLVIDEO_CTRL2 = 0x20, /*!< VIDEO PLL CTRL2 Register. */ + kAI_PLLVIDEO_CTRL2_SET = 0x24, /*!< VIDEO PLL CTRL2 SET Register. */ + kAI_PLLVIDEO_CTRL2_CLR = 0x28, /*!< VIDEO PLL CTRL2 CLR Register. */ + kAI_PLLVIDEO_CTRL3 = 0x30, /*!< VIDEO PLL CTRL3 Register. */ + kAI_PLLVIDEO_CTRL3_SET = 0x34, /*!< VIDEO PLL CTRL3 SET Register. */ + kAI_PLLVIDEO_CTRL3_CLR = 0x38, /*!< VIDEO PLL CTRL3 CLR Register. */ +} anatop_ai_reg_t; + +/* ---------------------------------------------------------------------------- + -- AI PHY_LDO CTRL0 Register Masks + ---------------------------------------------------------------------------- */ + +/*! @name CTRL0 - CTRL0 Register */ +/*! @{ */ +#define AI_PHY_LDO_CTRL0_LINREG_EN(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_LINREG_EN_SHIFT)) & AI_PHY_LDO_CTRL0_LINREG_EN_MASK) +#define AI_PHY_LDO_CTRL0_LINREG_EN_MASK (0x1U) +#define AI_PHY_LDO_CTRL0_LINREG_EN_SHIFT (0U) + +/*! LINREG_EN - LinReg master enable + * LinReg master enable. Setting this bit will enable the regular + */ + +#define AI_PHY_LDO_CTRL0_PWRUPLOAD_DIS(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_PWRUPLOAD_DIS_SHIFT)) & AI_PHY_LDO_CTRL0_PWRUPLOAD_DIS_MASK) +#define AI_PHY_LDO_CTRL0_PWRUPLOAD_DIS_MASK (0x2U) +#define AI_PHY_LDO_CTRL0_PWRUPLOAD_DIS_SHIFT (1U) +/*! LINREG_PWRUPLOAD_DIS - LinReg power-up load disable + * 0b0..Internal pull-down enabled + * 0b1..Internal pull-down disabled + */ + +#define AI_PHY_LDO_CTRL0_LIMIT_EN(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_LIMIT_EN_SHIFT)) & AI_PHY_LDO_CTRL0_LIMIT_EN_MASK) +#define AI_PHY_LDO_CTRL0_LIMIT_EN_MASK (0x4U) +#define AI_PHY_LDO_CTRL0_LIMIT_EN_SHIFT (2U) +/*! LINREG_LIMIT_EN - LinReg current limit enable + * LinReg current-limit enable. Setting this bit will enable the + * current-limiter in the regulator + */ + +#define AI_PHY_LDO_CTRL0_OUTPUT_TRG(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_OUTPUT_TRG_SHIFT)) & AI_PHY_LDO_CTRL0_OUTPUT_TRG_MASK) +#define AI_PHY_LDO_CTRL0_OUTPUT_TRG_MASK (0x1F0U) +#define AI_PHY_LDO_CTRL0_OUTPUT_TRG_SHIFT (4U) +/*! LINREG_OUTPUT_TRG - LinReg output voltage target setting + * 0b00000..Set output voltage to x.xV + * 0b10000..Set output voltage to 1.0V + * 0b11111..Set output voltage to x.xV + */ + +#define AI_PHY_LDO_CTRL0_PHY_ISO_B(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_PHY_ISO_B_SHIFT)) & AI_PHY_LDO_CTRL0_PHY_ISO_B_MASK) +#define AI_PHY_LDO_CTRL0_PHY_ISO_B_MASK (0x8000U) +#define AI_PHY_LDO_CTRL0_PHY_ISO_B_SHIFT (15U) +/*! LINREG_PHY_ISO_B - Isolation control for attached PHY load + * This control bit is to be used by the system controller to isolate the + * attached PHY load when the LinReg is powered down. During a power-up + * event of the regulator it is expected that this control signal is set high + * at least 100us after the main regulator is enabled. During a power-down + * event of the regulator it is expected that this control signal is set low + * before the main regulator is disabled/power-down. + */ +/*! @} */ + +/*! @name STAT0 - STAT0 Register */ +/*! @{ */ +#define AI_PHY_LDO_STAT0_LINREG_STAT(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_STAT0_LINREG_STAT_SHIFT)) & AI_PHY_LDO_STAT0_LINREG_STAT_MASK) +#define AI_PHY_LDO_STAT0_LINREG_STAT_MASK (0xFU) +#define AI_PHY_LDO_STAT0_LINREG_STAT_SHIFT (0U) + +/*! LINREG_STAT - LinReg status bits + * LinReg status bits. + */ + +/*! @} */ + +/*! @name CTRL0 - CTRL0 Register */ +/*! @{ */ +#define AI_BANDGAP_CTRL0_REFTOP_PWD(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_PWD_SHIFT)) & AI_BANDGAP_CTRL0_REFTOP_PWD_MASK) +#define AI_BANDGAP_CTRL0_REFTOP_PWD_MASK (0x1U) +#define AI_BANDGAP_CTRL0_REFTOP_PWD_SHIFT (0U) +/*! REFTOP_PWD - This bit fully powers down the bandgap module. + * Setting this bit high will disable reference output currents and voltages from the + * bandgap and will affect functionality and validity of the voltage detectors. + */ + +#define AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD_SHIFT)) & \ + AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK) +#define AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK (0x2U) +#define AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD_SHIFT (1U) +/*! + * REFOP_LINREGREF_PWD - This bit powers down only the voltage reference output section of the bandgap. + * Setting this bit high will affect functionality and validity + * of the voltage detectors. + */ + +#define AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP_SHIFT)) & AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP_MASK) +#define AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP_MASK (0x4U) +#define AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP_SHIFT (2U) +/*! + * REFTOP_PWDVBGUP - This bit powers down the VBGUP detector of the bandgap + * without affecting any additional functionality. + */ + +#define AI_BANDGAP_CTRL0_REFTOP_LOWPOWER(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_LOWPOWER_SHIFT)) & AI_BANDGAP_CTRL0_REFTOP_LOWPOWER_MASK) +#define AI_BANDGAP_CTRL0_REFTOP_LOWPOWER_MASK (0x8U) +#define AI_BANDGAP_CTRL0_REFTOP_LOWPOWER_SHIFT (3U) +/*! + * REFTOP_LOWPOWER - This bit enables the low-power operation of the + * bandgap by cutting the bias currents in half to the main amplifiers. + * This will save power but could affect the accuracy of the output voltages and currents. + */ + +#define AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF_SHIFT)) & \ + AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK) +#define AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK (0x10U) +#define AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF_SHIFT (4U) +/*! + * REFTOP_SELFBIASOFF - Control bit to disable the self-bias circuit in the bandgap. + * The self-bias circuit is used by the bandgap during startup. This bit should be + * set high after the bandgap has stabilized and is necessary for best noise performance + * of modules using the outputs of the bandgap. It is expected that this control bit + * be set low any time that either the bandgap is fully powered-down or the 1.8V supply is removed. + */ + +#define AI_BANDGAP_CTRL0_REFTOP_VBGADJ(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_VBGADJ_SHIFT)) & AI_BANDGAP_CTRL0_REFTOP_VBGADJ_MASK) +#define AI_BANDGAP_CTRL0_REFTOP_VBGADJ_MASK (0xE0U) +#define AI_BANDGAP_CTRL0_REFTOP_VBGADJ_SHIFT (5U) +/*! + * REFTOP_VBGADJ - These bits allow the output VBG voltage of the bandgap to be trimmed + * 000 : nominal + * 001 : +10mV + * 010 : +20mV + * 011 : +30mV + * 100 : -10mV + * 101 : -20mV + * 110 : -30mV + * 111 : -40mV + */ + +#define AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ_SHIFT)) & AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ_MASK) +#define AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ_MASK (0x1C00U) +#define AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ_SHIFT (10U) +/*! + * REFTOP_IBZTCADJ - These bits allow trimming of the ZTC bias currents from the bandgap to + * the temperature sensors. Assuming a typical process corner the expected values of output + * currents are: + * 000 : 11.5 uA + * 001 : 11.8 uA + * 010 : 12.1 uA + * 100 : 12.4 uA (Nominal expected from MX8QM tempsensor) + * 101 : 12.7 uA + * 110 : 13.0 uA + * 111 : 13.3 uA + */ + +/*! @} */ + +/*! @name STAT0 - STAT0 Register */ +/*! @{ */ +#define AI_BANDGAP_STAT0_REFTOP_VBGUP(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_STAT0_REFTOP_VBGUP_SHIFT)) & AI_BANDGAP_STAT0_REFTOP_VBGUP_MASK) +#define AI_BANDGAP_STAT0_REFTOP_VBGUP_MASK (0x1U) +#define AI_BANDGAP_STAT0_REFTOP_VBGUP_SHIFT (0U) +/*! @} */ + +/*! @name CTRL0 - CTRL0 Register */ +/*! @{ */ +#define AI_RCOSC400M_CTRL0_REF_CLK_DIV(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL0_REF_CLK_DIV_SHIFT)) & AI_RCOSC400M_CTRL0_REF_CLK_DIV_MASK) +#define AI_RCOSC400M_CTRL0_REF_CLK_DIV_MASK (0x3F000000U) +#define AI_RCOSC400M_CTRL0_REF_CLK_DIV_SHIFT (24U) +/*! @} */ + +/*! @name CTRL1 - CTRL1 Register */ +/*! @{ */ +#define AI_RCOSC400M_CTRL1_HYST_MINUS(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL1_HYST_MINUS_SHIFT)) & AI_RCOSC400M_CTRL1_HYST_MINUS_MASK) +#define AI_RCOSC400M_CTRL1_HYST_MINUS_MASK (0xFU) +#define AI_RCOSC400M_CTRL1_HYST_MINUS_SHIFT (0U) + +#define AI_RCOSC400M_CTRL1_HYST_PLUS(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL1_HYST_PLUS_SHIFT)) & AI_RCOSC400M_CTRL1_HYST_PLUS_MASK) +#define AI_RCOSC400M_CTRL1_HYST_PLUS_MASK (0xF00U) +#define AI_RCOSC400M_CTRL1_HYST_PLUS_SHIFT (8U) + +#define AI_RCOSC400M_CTRL1_TARGET_COUNT(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL1_TARGET_COUNT_SHIFT)) & AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK) +#define AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK (0xFFFF0000U) +#define AI_RCOSC400M_CTRL1_TARGET_COUNT_SHIFT (16U) +/*! @} */ + +/*! @name CTRL2 - CTRL2 Register */ +/*! @{ */ +#define AI_RCOSC400M_CTRL2_TUNE_BYP(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL2_TUNE_BYP_SHIFT)) & AI_RCOSC400M_CTRL2_TUNE_BYP_MASK) +#define AI_RCOSC400M_CTRL2_TUNE_BYP_MASK (0x400U) +#define AI_RCOSC400M_CTRL2_TUNE_BYP_SHIFT (10U) + +#define AI_RCOSC400M_CTRL2_TUNE_EN(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL2_TUNE_EN_SHIFT)) & AI_RCOSC400M_CTRL2_TUNE_EN_MASK) +#define AI_RCOSC400M_CTRL2_TUNE_EN_MASK (0x1000U) +#define AI_RCOSC400M_CTRL2_TUNE_EN_SHIFT (12U) + +#define AI_RCOSC400M_CTRL2_TUNE_START(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL2_TUNE_START_SHIFT)) & AI_RCOSC400M_CTRL2_TUNE_START_MASK) +#define AI_RCOSC400M_CTRL2_TUNE_START_MASK (0x4000U) +#define AI_RCOSC400M_CTRL2_TUNE_START_SHIFT (14U) + +#define AI_RCOSC400M_CTRL2_OSC_TUNE_VAL(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_SHIFT)) & AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_MASK) +#define AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_MASK (0xFF000000U) +#define AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_SHIFT (24U) +/*! @} */ + +/*! @name CTRL3 - CTRL3 Register */ +/*! @{ */ +#define AI_RCOSC400M_CTRL3_CLR_ERR(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL3_CLR_ERR_SHIFT)) & AI_RCOSC400M_CTRL3_CLR_ERR_MASK) +#define AI_RCOSC400M_CTRL3_CLR_ERR_MASK (0x1U) +#define AI_RCOSC400M_CTRL3_CLR_ERR_SHIFT (0U) + +#define AI_RCOSC400M_CTRL3_EN_1M_CLK(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL3_EN_1M_CLK_SHIFT)) & AI_RCOSC400M_CTRL3_EN_1M_CLK_MASK) +#define AI_RCOSC400M_CTRL3_EN_1M_CLK_MASK (0x100U) +#define AI_RCOSC400M_CTRL3_EN_1M_CLK_SHIFT (8U) + +#define AI_RCOSC400M_CTRL3_MUX_1M_CLK(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL3_MUX_1M_CLK_SHIFT)) & AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK) +#define AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK (0x400U) +#define AI_RCOSC400M_CTRL3_MUX_1M_CLK_SHIFT (10U) + +#define AI_RCOSC400M_CTRL3_COUNT_1M_CLK(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL3_COUNT_1M_CLK_SHIFT)) & AI_RCOSC400M_CTRL3_COUNT_1M_CLK_MASK) +#define AI_RCOSC400M_CTRL3_COUNT_1M_CLK_MASK (0xFFFF0000U) +#define AI_RCOSC400M_CTRL3_COUNT_1M_CLK_SHIFT (16U) +/*! @} */ + +/*! @name STAT0 - STAT0 Register */ +/*! @{ */ +#define AI_RCOSC400M_STAT0_CLK1M_ERR(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_STAT0_CLK1M_ERR_SHIFT)) & AI_RCOSC400M_STAT0_CLK1M_ERR_MASK) +#define AI_RCOSC400M_STAT0_CLK1M_ERR_MASK (0x1U) +#define AI_RCOSC400M_STAT0_CLK1M_ERR_SHIFT (0U) +/*! @} */ + +/*! @name STAT1 - STAT1 Register */ +/*! @{ */ +#define AI_RCOSC400M_STAT1_CURR_COUNT_VAL(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_STAT1_CURR_COUNT_VAL_SHIFT)) & AI_RCOSC400M_STAT1_CURR_COUNT_VAL_MASK) +#define AI_RCOSC400M_STAT1_CURR_COUNT_VAL_MASK (0xFFFF0000U) +#define AI_RCOSC400M_STAT1_CURR_COUNT_VAL_SHIFT (16U) +/*! @} */ + +/*! @name STAT2 - STAT2 Register */ +/*! @{ */ +#define AI_RCOSC400M_STAT2_CURR_OSC_TUNE_VAL(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_STAT2_CURR_OSC_TUNE_VAL_SHIFT)) & \ + AI_RCOSC400M_STAT2_CURR_OSC_TUNE_VAL_MASK) +#define AI_RCOSC400M_STAT2_CURR_OSC_TUNE_VAL_MASK (0xFF000000U) +#define AI_RCOSC400M_STAT2_CURR_OSC_TUNE_VAL_SHIFT (24U) +/*! @} */ + +/*! @name CTRL0 - CTRL0 Register */ +/*! @{ */ +#define AI_PLL1G_CTRL0_HOLD_RING_OFF(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PLL1G_CTRL0_HOLD_RING_OFF_SHIFT)) & AI_PLL1G_CTRL0_HOLD_RING_OFF_MASK) +#define AI_PLL1G_CTRL0_HOLD_RING_OFF_MASK (0x2000UL) +#define AI_PLL1G_CTRL0_HOLD_RING_OFF_SHIFT (13U) + +#define AI_PLL1G_CTRL0_POWER_UP(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PLL1G_CTRL0_POWER_UP_SHIFT)) & AI_PLL1G_CTRL0_POWER_UP_MASK) +#define AI_PLL1G_CTRL0_POWER_UP_MASK (0x4000UL) +#define AI_PLL1G_CTRL0_POWER_UP_SHIFT (14U) + +#define AI_PLL1G_CTRL0_ENABLE(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PLL1G_CTRL0_ENABLE_SHIFT)) & AI_PLL1G_CTRL0_ENABLE_MASK) +#define AI_PLL1G_CTRL0_ENABLE_MASK (0x8000UL) +#define AI_PLL1G_CTRL0_ENABLE_SHIFT (15U) + +#define AI_PLL1G_CTRL0_BYPASS(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PLL1G_CTRL0_BYPASS_SHIFT)) & AI_PLL1G_CTRL0_BYPASS_MASK) +#define AI_PLL1G_CTRL0_BYPASS_MASK (0x10000UL) +#define AI_PLL1G_CTRL0_BYPASS_SHIFT (16U) + +#define AI_PLL1G_CTRL0_PLL_REG_EN(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PLL1G_CTRL0_PLL_REG_EN_SHIFT)) & AI_PLL1G_CTRL0_PLL_REG_EN_MASK) +#define AI_PLL1G_CTRL0_PLL_REG_EN_MASK (0x400000UL) +#define AI_PLL1G_CTRL0_PLL_REG_EN_SHIFT (22U) +/*! @} */ + +/*! @name CTRL0 - CTRL0 Register */ +/*! @{ */ +#define AI_PLLAUDIO_CTRL0_HOLD_RING_OFF(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PLLAUDIO_CTRL0_HOLD_RING_OFF_SHIFT)) & AI_PLLAUDIO_CTRL0_HOLD_RING_OFF_MASK) +#define AI_PLLAUDIO_CTRL0_HOLD_RING_OFF_MASK (0x2000UL) +#define AI_PLLAUDIO_CTRL0_HOLD_RING_OFF_SHIFT (13U) + +#define AI_PLLAUDIO_CTRL0_POWER_UP(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PLLAUDIO_CTRL0_POWER_UP_SHIFT)) & AI_PLLAUDIO_CTRL0_POWER_UP_MASK) +#define AI_PLLAUDIO_CTRL0_POWER_UP_MASK (0x4000UL) +#define AI_PLLAUDIO_CTRL0_POWER_UP_SHIFT (14U) + +#define AI_PLLAUDIO_CTRL0_ENABLE(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PLLAUDIO_CTRL0_ENABLE_SHIFT)) & AI_PLLAUDIO_CTRL0_ENABLE_MASK) +#define AI_PLLAUDIO_CTRL0_ENABLE_MASK (0x8000UL) +#define AI_PLLAUDIO_CTRL0_ENABLE_SHIFT (15U) + +#define AI_PLLAUDIO_CTRL0_BYPASS(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PLLAUDIO_CTRL0_BYPASS_SHIFT)) & AI_PLLAUDIO_CTRL0_BYPASS_MASK) +#define AI_PLLAUDIO_CTRL0_BYPASS_MASK (0x10000UL) +#define AI_PLLAUDIO_CTRL0_BYPASS_SHIFT (16U) + +#define AI_PLLAUDIO_CTRL0_PLL_REG_EN(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PLLAUDIO_CTRL0_PLL_REG_EN_SHIFT)) & AI_PLLAUDIO_CTRL0_PLL_REG_EN_MASK) +#define AI_PLLAUDIO_CTRL0_PLL_REG_EN_MASK (0x400000UL) +#define AI_PLLAUDIO_CTRL0_PLL_REG_EN_SHIFT (22U) +/*! @} */ + +/*! @name CTRL0 - CTRL0 Register */ +/*! @{ */ +#define AI_PLLVIDEO_CTRL0_HOLD_RING_OFF(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PLLVIDEO_CTRL0_HOLD_RING_OFF_SHIFT)) & AI_PLLVIDEO_CTRL0_HOLD_RING_OFF_MASK) +#define AI_PLLVIDEO_CTRL0_HOLD_RING_OFF_MASK (0x2000UL) +#define AI_PLLVIDEO_CTRL0_HOLD_RING_OFF_SHIFT (13U) + +#define AI_PLLVIDEO_CTRL0_POWER_UP(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PLLVIDEO_CTRL0_POWER_UP_SHIFT)) & AI_PLLVIDEO_CTRL0_POWER_UP_MASK) +#define AI_PLLVIDEO_CTRL0_POWER_UP_MASK (0x4000UL) +#define AI_PLLVIDEO_CTRL0_POWER_UP_SHIFT (14U) + +#define AI_PLLVIDEO_CTRL0_ENABLE(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PLLVIDEO_CTRL0_ENABLE_SHIFT)) & AI_PLLVIDEO_CTRL0_ENABLE_MASK) +#define AI_PLLVIDEO_CTRL0_ENABLE_MASK (0x8000UL) +#define AI_PLLVIDEO_CTRL0_ENABLE_SHIFT (15U) + +#define AI_PLLVIDEO_CTRL0_BYPASS(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PLLVIDEO_CTRL0_BYPASS_SHIFT)) & AI_PLLVIDEO_CTRL0_BYPASS_MASK) +#define AI_PLLVIDEO_CTRL0_BYPASS_MASK (0x10000UL) +#define AI_PLLVIDEO_CTRL0_BYPASS_SHIFT (16U) + +#define AI_PLLVIDEO_CTRL0_PLL_REG_EN(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PLLVIDEO_CTRL0_PLL_REG_EN_SHIFT)) & AI_PLLVIDEO_CTRL0_PLL_REG_EN_MASK) +#define AI_PLLVIDEO_CTRL0_PLL_REG_EN_MASK (0x400000UL) +#define AI_PLLVIDEO_CTRL0_PLL_REG_EN_SHIFT (22U) +/*! @} */ + +/*! @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @brief AI interface access + * + * @param itf AI interface name + * @param isWrite write enable + * @param addr address + * @param wdata data to be set + * + */ +uint32_t ANATOP_AI_Access(anatop_ai_itf_t itf, bool isWrite, anatop_ai_reg_t addr, uint32_t wdata); + +/*! + * @brief AI interface writing + * + * @param itf AI interface name + * @param addr address + * @param wdata data to be set + * + */ +void ANATOP_AI_Write(anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata); + +/*! + * @brief AI interface reading + * + * @param itf AI interface name + * @param addr address + * @return data read + * + */ +uint32_t ANATOP_AI_Read(anatop_ai_itf_t itf, anatop_ai_reg_t addr); + +/*! + * @brief AI interface write with mask and shift + * + * @param itf AI interface name + * @param addr address + * @param wdata data to be written + * @param mask bit field mask + * @param shift bit field shift + * + */ +void ANATOP_AI_WriteWithMaskShift( + anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata, uint32_t mask, uint32_t shift); + +/* @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_ANATOP_AI_H_ */ diff --git a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_clock.c b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_clock.c new file mode 100644 index 0000000000..4928b1aad7 --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_clock.c @@ -0,0 +1,1937 @@ +/* + * Copyright 2019-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_clock.h" +#include "fsl_pmu.h" +#include "fsl_anatop_ai.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.clock" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* To make full use of CM7 hardware FPU, use double instead of uint64_t in clock driver to +achieve better performance, it is depend on the IDE Floating point settings, if double precision is selected +in IDE, clock_64b_t will switch to double type automatically. only support IAR and MDK here */ +#if __FPU_USED + +#if (defined(__ICCARM__)) + +#if (__ARMVFP__ >= __ARMFPV5__) && \ + (__ARM_FP == 0xE) /*0xe implies support for half, single and double precision operations*/ +typedef double clock_64b_t; +#else +typedef uint64_t clock_64b_t; +#endif + +#elif (defined(__GNUC__)) + +#if (__ARM_FP == 0xE) /*0xe implies support for half, single and double precision operations*/ +typedef double clock_64b_t; +#else +typedef uint64_t clock_64b_t; +#endif + +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) + +#if defined __TARGET_FPU_FPV5_D16 +typedef double clock_64b_t; +#else +typedef uint64_t clock_64b_t; +#endif + +#else +typedef uint64_t clock_64b_t; +#endif + +#else +typedef uint64_t clock_64b_t; +#endif + +#define PLL_AI_CTRL0_REG kAI_PLL1G_CTRL0 +#define PLL_AI_CTRL0_SET_REG kAI_PLL1G_CTRL0_SET +#define PLL_AI_CTRL0_CLR_REG kAI_PLL1G_CTRL0_CLR +#define PLL_AI_CTRL1_REG kAI_PLL1G_CTRL1 +#define PLL_AI_CTRL1_SET_REG kAI_PLL1G_CTRL1_SET +#define PLL_AI_CTRL1_CLR_REG kAI_PLL1G_CTRL1_CLR +#define PLL_AI_CTRL2_REG kAI_PLL1G_CTRL2 +#define PLL_AI_CTRL2_SET_REG kAI_PLL1G_CTRL2_SET +#define PLL_AI_CTRL2_CLR_REG kAI_PLL1G_CTRL2_CLR +#define PLL_AI_CTRL3_REG kAI_PLL1G_CTRL3 +#define PLL_AI_CTRL3_SET_REG kAI_PLL1G_CTRL3_SET +#define PLL_AI_CTRL3_CLR_REG kAI_PLL1G_CTRL3_CLR + +#define PLL_AI_CTRL0_HOLD_RING_OFF_MASK AI_PLL1G_CTRL0_HOLD_RING_OFF_MASK + +#define PLL_AI_CTRL0_POWER_UP_MASK AI_PLL1G_CTRL0_POWER_UP_MASK + +#define PLL_AI_CTRL0_ENABLE_MASK AI_PLL1G_CTRL0_ENABLE_MASK + +#define PLL_AI_CTRL0_BYPASS_MASK AI_PLL1G_CTRL0_BYPASS_MASK + +#define PLL_AI_CTRL0_PLL_REG_EN_MASK AI_PLL1G_CTRL0_PLL_REG_EN_MASK +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static void ANATOP_PllSetPower(anatop_ai_itf_t itf, bool enable); +static void ANATOP_PllBypass(anatop_ai_itf_t itf, bool bypass); +static void ANATOP_PllEnablePllReg(anatop_ai_itf_t itf, bool enable); +static void ANATOP_PllHoldRingOff(anatop_ai_itf_t itf, bool off); +static void ANATOP_PllToggleHoldRingOff(anatop_ai_itf_t itf, uint32_t delay_us); +static void ANATOP_PllEnableClk(anatop_ai_itf_t itf, bool enable); +static void ANATOP_PllConfigure(anatop_ai_itf_t itf, + uint8_t div, + uint32_t numer, + uint8_t post_div, + uint32_t denom, + const clock_pll_ss_config_t *ss); +static void ANATOP_AudioPllGate(bool enable); +static void ANATOP_AudioPllSwEnClk(bool enable); +static void ANATOP_VideoPllGate(bool enable); +static void ANATOP_VideoPllSwEnClk(bool enable); +static void ANATOP_SysPll1Gate(bool enable); +static void ANATOP_SysPll1Div2En(bool enable); +static void ANATOP_SysPll1Div5En(bool enable); +static void ANATOP_SysPll1SwEnClk(bool enable); +static void ANATOP_SysPll1WaitStable(void); +static void ANATOP_PllEnableSs(anatop_ai_itf_t itf, bool enable); +#ifndef GET_FREQ_FROM_OBS +static uint32_t CLOCK_GetAvPllFreq(clock_pll_t pll); +#endif +/******************************************************************************* + * Code + ******************************************************************************/ + +#define ARM_PLL_DIV_SEL_MIN 104 +#define ARM_PLL_DIV_SEL_MAX 208 + +void CLOCK_InitArmPll(const clock_arm_pll_config_t *config) +{ + assert((config->loopDivider <= (uint32_t)ARM_PLL_DIV_SEL_MAX) && + (config->loopDivider >= (uint32_t)ARM_PLL_DIV_SEL_MIN)); + + uint32_t reg; + + if (((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK) != 0UL) && + ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_MASK) == + ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT(config->loopDivider)) && + ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_MASK) == + ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL(config->postDivider))) + { + /* no need to reconfigure the PLL if all the configuration is the same */ + if ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK) == 0UL) + { + ANADIG_PLL->ARM_PLL_CTRL |= ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK; + } + if ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK) != 0UL) + { + ANADIG_PLL->ARM_PLL_CTRL &= ~ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK; + } + return; + } + + PMU_StaticEnablePllLdo(ANADIG_PMU); + + reg = ANADIG_PLL->ARM_PLL_CTRL & (~ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_MASK); + if ((reg & (ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK | ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK)) != 0UL) + { + /* Power down the PLL. */ + reg &= ~(ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK | ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK); + reg |= ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK; + ANADIG_PLL->ARM_PLL_CTRL = reg; + } + + /* Set the configuration. */ + reg &= ~(ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_MASK | ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_MASK); + reg |= (ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT(config->loopDivider) | + ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL(config->postDivider)) | + ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK | ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK; + ANADIG_PLL->ARM_PLL_CTRL = reg; + __DSB(); + __ISB(); + SDK_DelayAtLeastUs(30, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + + /* Wait for the PLL stable, */ + while (0U == (ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_MASK)) + { + } + + /* Enable and ungate the clock. */ + reg |= ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK; + reg &= ~ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK; + ANADIG_PLL->ARM_PLL_CTRL = reg; +} + +void CLOCK_DeinitArmPll(void) +{ + uint32_t reg = ANADIG_PLL->ARM_PLL_CTRL & (~ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_MASK); + + reg &= ~(ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK | ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK); + reg |= ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK; + ANADIG_PLL->ARM_PLL_CTRL = reg; +} + +void CLOCK_CalcPllSpreadSpectrum(uint32_t factor, uint32_t range, uint32_t mod, clock_pll_ss_config_t *ss) +{ + assert(ss != NULL); + + ss->stop = (uint16_t)(factor * range / XTAL_FREQ); + ss->step = (uint16_t)((mod << 1UL) * (uint32_t)(ss->stop) / XTAL_FREQ); +} + +/* 528PLL */ +void CLOCK_InitSysPll2(const clock_sys_pll2_config_t *config) +{ + uint32_t reg; + + if ((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK) != 0UL) + { + if ((config == NULL) || + ((0UL == (ANADIG_PLL->SYS_PLL2_SS & ANADIG_PLL_SYS_PLL2_SS_ENABLE_MASK)) && (!config->ssEnable)) || + ((ANADIG_PLL_SYS_PLL2_SS_ENABLE(config->ssEnable) | ANADIG_PLL_SYS_PLL2_SS_STOP(config->ss->stop) | + ANADIG_PLL_SYS_PLL2_SS_STEP(config->ss->step)) == ANADIG_PLL->SYS_PLL2_SS)) + { + /* no need to reconfigure the PLL if all the configuration is the same */ + if (0UL == (ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK)) + { + ANADIG_PLL->SYS_PLL2_CTRL |= ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK; + } + + if ((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK) != 0UL) + { + ANADIG_PLL->SYS_PLL2_CTRL &= ~ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK; + } + return; + } + } + + PMU_StaticEnablePllLdo(ANADIG_PMU); + /* Gate all PFDs */ + ANADIG_PLL->SYS_PLL2_PFD |= + ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE(1) | ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE(1) | + ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE(1) | ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE(1); + + reg = ANADIG_PLL->SYS_PLL2_CTRL; + if ((reg & (ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK | ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK)) != 0UL) + { + /* Power down the PLL. */ + reg &= ~(ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK | ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK); + reg |= ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK; + ANADIG_PLL->SYS_PLL2_CTRL = reg; + } + + /* Config PLL */ + if ((config != NULL) && (config->ssEnable) && (config->ss != NULL)) + { + ANADIG_PLL->SYS_PLL2_MFD = ANADIG_PLL_SYS_PLL2_MFD_MFD(config->mfd); + ANADIG_PLL->SYS_PLL2_SS = (ANADIG_PLL_SYS_PLL2_SS_ENABLE_MASK | ANADIG_PLL_SYS_PLL2_SS_STOP(config->ss->stop) | + ANADIG_PLL_SYS_PLL2_SS_STEP(config->ss->step)); + } + + /* REG_EN = 1, GATE = 1, DIV_SEL = 0, POWERUP = 0 */ + reg = ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN(1) | ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE(1); + ANADIG_PLL->SYS_PLL2_CTRL = reg; + /* Wait until LDO is stable */ + SDK_DelayAtLeastUs(30, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + + /* REG_EN = 1, GATE = 1, DIV_SEL = 0, POWERUP = 1, HOLDRING_OFF = 1 */ + reg |= ANADIG_PLL_SYS_PLL2_CTRL_POWERUP(1) | ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_MASK; + ANADIG_PLL->SYS_PLL2_CTRL = reg; + SDK_DelayAtLeastUs(250, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + + /* REG_EN = 1, GATE = 1, DIV_SEL = 0, POWERUP = 1, HOLDRING_OFF = 0 */ + reg &= ~ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_MASK; + ANADIG_PLL->SYS_PLL2_CTRL = reg; + /* Wait for PLL stable */ + while (ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_MASK != + (ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_MASK)) + { + } + + /* REG_EN = 1, GATE = 1, DIV_SEL = 0, POWERUP = 1, HOLDRING_OFF = 0, CLK = 1*/ + reg |= ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK; + ANADIG_PLL->SYS_PLL2_CTRL = reg; + + /* REG_EN = 1, GATE = 0, DIV_SEL = 0, POWERUP = 1, HOLDRING_OFF = 0, CLK = 1*/ + reg &= ~ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK; + ANADIG_PLL->SYS_PLL2_CTRL = reg; + ANADIG_PLL->SYS_PLL2_PFD &= + ~(ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE(1) | ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE(1) | + ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE(1) | ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE(1)); +} + +void CLOCK_DeinitSysPll2(void) +{ + ANADIG_PLL->SYS_PLL2_PFD |= + ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE(1) | ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE(1) | + ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE(1) | ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE(1); + + ANADIG_PLL->SYS_PLL2_CTRL |= ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK; + ANADIG_PLL->SYS_PLL2_CTRL &= ~(ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK | ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK | + ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_MASK); + + ANADIG_PLL->SYS_PLL2_SS &= ~ANADIG_PLL_SYS_PLL2_SS_ENABLE_MASK; +} + +/*! + * brief Check if Sys PLL2 PFD is enabled + * + * param pfd PFD control name + * return PFD bypass status. + * - true: power on. + * - false: power off. + * note Only useful in software control mode. + */ +bool CLOCK_IsSysPll2PfdEnabled(clock_pfd_t pfd) +{ + return ((ANADIG_PLL->SYS_PLL2_PFD & (uint32_t)ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_MASK + << (8UL * (uint8_t)pfd)) == 0U); +} + +#define PFD_FRAC_MIN 12U +#define PFD_FRAC_MAX 35U +void CLOCK_InitPfd(clock_pll_t pll, clock_pfd_t pfd, uint8_t frac) +{ + volatile uint32_t *pfdCtrl = NULL, *pfdUpdate = NULL, stable; + uint32_t regFracVal; + bool pfdGated; + + assert(frac <= (uint8_t)PFD_FRAC_MAX); + assert(frac >= (uint8_t)PFD_FRAC_MIN); + + switch (pll) + { + case kCLOCK_PllSys2: + pfdCtrl = &ANADIG_PLL->SYS_PLL2_PFD; + pfdUpdate = &ANADIG_PLL->SYS_PLL2_UPDATE; + break; + case kCLOCK_PllSys3: + pfdCtrl = &ANADIG_PLL->SYS_PLL3_PFD; + pfdUpdate = &ANADIG_PLL->SYS_PLL3_UPDATE; + break; + default: + /* Wrong input parameter pll. */ + assert(false); + break; + } + + regFracVal = ((*pfdCtrl) & ((uint32_t)ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_MASK << (8UL * (uint32_t)pfd))) >> + (8UL * (uint32_t)pfd); + pfdGated = + (bool)(((*pfdCtrl) & ((uint32_t)ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_MASK << (8UL * (uint32_t)pfd))) >> + (8UL >> (uint32_t)pfd)); + if ((regFracVal == (uint32_t)frac) && (!pfdGated)) + { + return; + } + + stable = *pfdCtrl & ((uint32_t)ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_MASK << (8UL * (uint32_t)pfd)); + *pfdCtrl |= ((uint32_t)ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_MASK << (8UL * (uint32_t)pfd)); + + /* all pfds support to be updated on-the-fly after corresponding PLL is stable */ + *pfdCtrl &= ~((uint32_t)ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_MASK << (8UL * (uint32_t)pfd)); + *pfdCtrl |= (ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC(frac) << (8UL * (uint32_t)pfd)); + + *pfdUpdate ^= ((uint32_t)ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_MASK << (uint32_t)pfd); + *pfdCtrl &= ~((uint32_t)ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_MASK << (8UL * (uint32_t)pfd)); + /* Wait for stablizing */ + while (stable == (*pfdCtrl & ((uint32_t)ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_MASK << (8UL * (uint32_t)pfd)))) + { + } +} + +/*! + * brief De-initialize selected PLL PFD. + * + * param pll Which PLL of targeting PFD to be operated. + * param pfd Which PFD clock to enable. + */ +void CLOCK_DeinitPfd(clock_pll_t pll, clock_pfd_t pfd) +{ + volatile uint32_t *pfdCtrl = NULL; + + switch (pll) + { + case kCLOCK_PllSys2: + { + pfdCtrl = &ANADIG_PLL->SYS_PLL2_PFD; + break; + } + case kCLOCK_PllSys3: + { + pfdCtrl = &ANADIG_PLL->SYS_PLL3_PFD; + break; + } + default: + { + /* Wrong input parameter pll. */ + assert(false); + break; + } + } + + /* Clock gate the selected pfd. */ + *pfdCtrl |= ((uint32_t)ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_MASK << (8UL * (uint32_t)pfd)); +} + +#ifndef GET_FREQ_FROM_OBS +uint32_t CLOCK_GetPfdFreq(clock_pll_t pll, clock_pfd_t pfd) +{ + uint32_t pllFreq = 0UL, frac = 0UL; + assert((pll == kCLOCK_PllSys2) || (pll == kCLOCK_PllSys3)); + + switch (pll) + { + case kCLOCK_PllSys2: + frac = (ANADIG_PLL->SYS_PLL2_PFD & + ((uint32_t)ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_MASK << (8UL * (uint32_t)pfd))); + pllFreq = (uint32_t)SYS_PLL2_FREQ; + break; + case kCLOCK_PllSys3: + frac = (ANADIG_PLL->SYS_PLL3_PFD & + ((uint32_t)ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_MASK << (8UL * (uint32_t)pfd))); + pllFreq = (uint32_t)SYS_PLL3_FREQ; + break; + default: + /* Wrong input parameter pll. */ + assert(false); + break; + } + + frac = frac >> (8UL * (uint32_t)pfd); + assert(frac >= (uint32_t)PFD_FRAC_MIN); + assert(frac <= (uint32_t)PFD_FRAC_MAX); + return ((frac != 0UL) ? (pllFreq / frac * 18UL) : 0UL); +} +#else +uint32_t CLOCK_GetPfdFreq(clock_pll_t pll, clock_pfd_t pfd) +{ + uint32_t freq = 0; + assert((pll == kCLOCK_PllSys2) || (pll == kCLOCK_PllSys3)); + + switch (pll) + { + case kCLOCK_PllSys2: + /* SYS_PLL2_PFD0 OBS index starts from 234 */ + freq = CLOCK_GetFreqFromObs(pfd + 234, 2); + break; + case kCLOCK_PllSys3: + /* SYS_PLL3_PFD0 OBS index starts from 241 */ + freq = CLOCK_GetFreqFromObs(pfd + 241, 2); + break; + default: + assert(false); + } + return freq; +} +#endif + +/* 480PLL */ +void CLOCK_InitSysPll3(void) +{ + uint32_t reg; + + if (0UL != (ANADIG_PLL->SYS_PLL3_CTRL & ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_MASK)) + { + /* no need to reconfigure the PLL if all the configuration is the same */ + if (0UL == (ANADIG_PLL->SYS_PLL3_CTRL & ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_MASK)) + { + ANADIG_PLL->SYS_PLL3_CTRL |= ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_MASK; + } + + if (0UL != (ANADIG_PLL->SYS_PLL3_CTRL & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_MASK)) + { + ANADIG_PLL->SYS_PLL3_CTRL &= ~ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_MASK; + } + return; + } + + PMU_StaticEnablePllLdo(ANADIG_PMU); + + /* Gate all PFDs */ + ANADIG_PLL->SYS_PLL3_PFD |= + ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE(1) | ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE(1) | + ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE(1) | ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE(1); + /* + * 1. configure PLL registres + * 2. Enable internal LDO + * 3. Wati LDO stable + * 4. Power up PLL, assert hold_ring_off (only needed for avpll) + * 5. At half lock time, de-asserted hold_ring_off (only needed for avpll) + * 6. Wait PLL lock + * 7. Enable clock output, release pfd_gate + */ + reg = ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN(1) | ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE(1); + ANADIG_PLL->SYS_PLL3_CTRL = reg; + SDK_DelayAtLeastUs(30, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + + reg |= ANADIG_PLL_SYS_PLL3_CTRL_POWERUP(1) | ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_MASK; + ANADIG_PLL->SYS_PLL3_CTRL = reg; + SDK_DelayAtLeastUs(30, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + + reg &= ~ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_MASK; + ANADIG_PLL->SYS_PLL3_CTRL = reg; + + /* Wait for PLL stable */ + while (ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_MASK != + (ANADIG_PLL->SYS_PLL3_CTRL & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_MASK)) + { + } + + reg |= ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK(1) | ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2(1); + ANADIG_PLL->SYS_PLL3_CTRL = reg; + + reg &= ~ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_MASK; + ANADIG_PLL->SYS_PLL3_CTRL = reg; +} + +void CLOCK_DeinitSysPll3(void) +{ + ANADIG_PLL->SYS_PLL3_PFD |= + ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE(1) | ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE(1) | + ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE(1) | ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE(1); + + ANADIG_PLL->SYS_PLL3_CTRL |= ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_MASK; + ANADIG_PLL->SYS_PLL3_CTRL &= ~(ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_MASK | ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_MASK | + ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_MASK); +} + +/*! + * brief Check if Sys PLL3 PFD is enabled + * + * param pfd PFD control name + * return PFD bypass status. + * - true: power on. + * - false: power off. + * note Only useful in software control mode. + */ +bool CLOCK_IsSysPll3PfdEnabled(clock_pfd_t pfd) +{ + return ((ANADIG_PLL->SYS_PLL3_PFD & (uint32_t)ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_MASK + << (8UL * (uint8_t)pfd)) == 0U); +} + +void CLOCK_SetPllBypass(clock_pll_t pll, bool bypass) +{ + switch (pll) + { + case kCLOCK_PllArm: + ANADIG_PLL->ARM_PLL_CTRL = bypass ? (ANADIG_PLL->ARM_PLL_CTRL | ANADIG_PLL_ARM_PLL_CTRL_BYPASS_MASK) : + (ANADIG_PLL->ARM_PLL_CTRL & ~ANADIG_PLL_ARM_PLL_CTRL_BYPASS_MASK); + break; + case kCLOCK_PllSys1: + ANATOP_PllBypass(kAI_Itf_1g, bypass); + break; + case kCLOCK_PllSys2: + ANADIG_PLL->SYS_PLL2_CTRL = bypass ? (ANADIG_PLL->SYS_PLL2_CTRL | ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK) : + (ANADIG_PLL->SYS_PLL2_CTRL & ~ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK); + break; + case kCLOCK_PllSys3: + ANADIG_PLL->SYS_PLL3_CTRL = bypass ? (ANADIG_PLL->SYS_PLL3_CTRL | ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_MASK) : + (ANADIG_PLL->SYS_PLL3_CTRL & ~ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_MASK); + break; + case kCLOCK_PllAudio: + ANATOP_PllBypass(kAI_Itf_Audio, bypass); + break; + case kCLOCK_PllVideo: + ANATOP_PllBypass(kAI_Itf_Video, bypass); + break; + default: + assert(false); + break; + } +} + +static void ANATOP_PllSetPower(anatop_ai_itf_t itf, bool enable) +{ + ANATOP_AI_Write(itf, enable ? PLL_AI_CTRL0_SET_REG : PLL_AI_CTRL0_CLR_REG, + PLL_AI_CTRL0_POWER_UP_MASK | (enable ? PLL_AI_CTRL0_HOLD_RING_OFF_MASK : 0UL)); +} + +static void ANATOP_PllBypass(anatop_ai_itf_t itf, bool bypass) +{ + ANATOP_AI_Write(itf, bypass ? PLL_AI_CTRL0_SET_REG : PLL_AI_CTRL0_CLR_REG, PLL_AI_CTRL0_BYPASS_MASK); +} + +static void ANATOP_PllEnablePllReg(anatop_ai_itf_t itf, bool enable) +{ + ANATOP_AI_Write(itf, enable ? PLL_AI_CTRL0_SET_REG : PLL_AI_CTRL0_CLR_REG, PLL_AI_CTRL0_PLL_REG_EN_MASK); +} + +static void ANATOP_PllHoldRingOff(anatop_ai_itf_t itf, bool off) +{ + ANATOP_AI_Write(itf, off ? PLL_AI_CTRL0_SET_REG : PLL_AI_CTRL0_CLR_REG, PLL_AI_CTRL0_HOLD_RING_OFF_MASK); +} + +static void ANATOP_PllToggleHoldRingOff(anatop_ai_itf_t itf, uint32_t delay_us) +{ + ANATOP_PllHoldRingOff(itf, true); + SDK_DelayAtLeastUs(delay_us, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + ANATOP_PllHoldRingOff(itf, false); +} + +static void ANATOP_PllEnableSs(anatop_ai_itf_t itf, bool enable) +{ + ANATOP_AI_Write(itf, enable ? PLL_AI_CTRL0_SET_REG : PLL_AI_CTRL0_CLR_REG, PLL_AI_CTRL0_ENABLE_MASK); +} + +static void ANATOP_PllEnableClk(anatop_ai_itf_t itf, bool enable) +{ + ANATOP_AI_Write(itf, enable ? PLL_AI_CTRL0_SET_REG : PLL_AI_CTRL0_CLR_REG, PLL_AI_CTRL0_ENABLE_MASK); +} + +static void ANATOP_PllConfigure( + anatop_ai_itf_t itf, uint8_t div, uint32_t numer, uint8_t post_div, uint32_t denom, const clock_pll_ss_config_t *ss) +{ + if (itf != kAI_Itf_1g) + { + ANATOP_PllSetPower(itf, false); + } + if (ss != NULL) + { + ANATOP_AI_Write(itf, PLL_AI_CTRL1_REG, + AUDIO_PLL_SPREAD_SPECTRUM_STEP(ss->step) | AUDIO_PLL_SPREAD_SPECTRUM_STOP(ss->stop) | + AUDIO_PLL_SPREAD_SPECTRUM_ENABLE_MASK); + } + ANATOP_AI_Write(itf, PLL_AI_CTRL3_REG, denom); + ANATOP_AI_Write(itf, PLL_AI_CTRL2_REG, numer); + ANATOP_AI_WriteWithMaskShift(itf, PLL_AI_CTRL0_REG, div, 0x7f, 0); + if (itf != kAI_Itf_1g) + { + ANATOP_AI_WriteWithMaskShift(itf, PLL_AI_CTRL0_REG, post_div, 0xE000000UL, 25UL); + } + ANATOP_PllEnablePllReg(itf, true); + SDK_DelayAtLeastUs(100, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + ANATOP_PllSetPower(itf, true); +} + +static void ANATOP_AudioPllGate(bool enable) +{ + if (!enable) + { + ANADIG_PLL->PLL_AUDIO_CTRL &= ~ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_MASK; + } + else + { + ANADIG_PLL->PLL_AUDIO_CTRL |= ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_MASK; + } +} + +static void ANATOP_AudioPllSwEnClk(bool enable) +{ + if (!enable) + { + ANADIG_PLL->PLL_AUDIO_CTRL &= ~ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_MASK; + } + else + { + ANADIG_PLL->PLL_AUDIO_CTRL |= ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_MASK; + } +} + +status_t CLOCK_InitAudioPllWithFreq(uint32_t freqInMhz, bool ssEnable, uint32_t ssRange, uint32_t ssMod) +{ + clock_audio_pll_config_t config = {0}; + config.ssEnable = ssEnable; + + if (kStatus_Success == CLOCK_CalcAvPllFreq(&config, freqInMhz)) + { + if (config.ssEnable) + { + clock_pll_ss_config_t ss = {0}; + CLOCK_CalcPllSpreadSpectrum(config.denominator, ssRange, ssMod, &ss); + config.ss = &ss; + } + CLOCK_InitAudioPll(&config); + return kStatus_Success; + } + return kStatus_Fail; +} + +void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config) +{ + uint32_t reg; + bool pllStable = false; + + PMU_StaticEnablePllLdo(ANADIG_PMU); + + reg = ANADIG_PLL->PLL_AUDIO_CTRL; + if ((reg & (ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_MASK | ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_MASK)) == + (ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_MASK | ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_MASK)) + { + pllStable = true; + } + /* bypass pll */ + ANATOP_PllBypass(kAI_Itf_Audio, true); + + if (pllStable) + { + /* sw enable clock */ + ANATOP_AudioPllSwEnClk(false); + /* gate clock */ + ANATOP_AudioPllGate(true); + ANATOP_PllEnableClk(kAI_Itf_Audio, false); + ANATOP_PllSetPower(kAI_Itf_Audio, false); + ANATOP_PllEnablePllReg(kAI_Itf_Audio, false); + } + + ANATOP_AudioPllSwEnClk(true); + /* configure pll */ + ANATOP_PllConfigure(kAI_Itf_Audio, config->loopDivider, config->numerator, config->postDivider, config->denominator, + (config->ssEnable && (config->ss != NULL)) ? config->ss : NULL); + + /* toggle hold ring off */ + ANATOP_PllToggleHoldRingOff(kAI_Itf_Audio, 225); + + /* wait pll stable */ + do + { + reg = ANADIG_PLL->PLL_AUDIO_CTRL; + } while ((reg & ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_MASK) != + ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_MASK); /* wait for PLL locked */ + + /* enabled clock */ + ANATOP_PllEnableClk(kAI_Itf_Audio, true); + + /* ungate clock */ + ANATOP_AudioPllGate(false); + + ANATOP_PllBypass(kAI_Itf_Audio, false); +} + +void CLOCK_DeinitAudioPll(void) +{ + ANATOP_AudioPllSwEnClk(false); + ANATOP_AudioPllGate(true); + ANATOP_PllEnableClk(kAI_Itf_Audio, false); + ANATOP_PllSetPower(kAI_Itf_Audio, false); + ANATOP_PllEnableSs(kAI_Itf_Audio, false); + ANATOP_PllEnablePllReg(kAI_Itf_Audio, false); +} + +void CLOCK_GPC_SetAudioPllOutputFreq(const clock_audio_pll_gpc_config_t *config) +{ + assert(config != NULL); + + ANADIG_PLL->PLL_AUDIO_DIV_SELECT = config->loopDivider; + ANADIG_PLL->PLL_AUDIO_NUMERATOR = config->numerator; + ANADIG_PLL->PLL_AUDIO_DENOMINATOR = config->denominator; + if ((config->ss != NULL) && config->ssEnable) + { + ANADIG_PLL->PLL_AUDIO_SS = ANADIG_PLL_PLL_AUDIO_SS_STEP(config->ss->step) | + ANADIG_PLL_PLL_AUDIO_SS_STOP(config->ss->stop) | ANADIG_PLL_PLL_AUDIO_SS_ENABLE_MASK; + } + + ANADIG_PLL->PLL_AUDIO_CTRL |= ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_MASK; +} + +static void ANATOP_VideoPllGate(bool enable) +{ + if (!enable) + { + ANADIG_PLL->PLL_VIDEO_CTRL &= ~ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE_MASK; + } + else + { + ANADIG_PLL->PLL_VIDEO_CTRL |= ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE_MASK; + } +} + +static void ANATOP_VideoPllSwEnClk(bool enable) +{ + if (!enable) + { + ANADIG_PLL->PLL_VIDEO_CTRL &= ~ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_MASK; + } + else + { + ANADIG_PLL->PLL_VIDEO_CTRL |= ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_MASK; + } +} + +status_t CLOCK_CalcArmPllFreq(clock_arm_pll_config_t *config, uint32_t freqInMhz) +{ + assert(config != NULL); + uint32_t refFreq = ((XTAL_FREQ / 1000000UL) * 104UL / 4UL); /* MHz */ + assert((freqInMhz <= refFreq) && (freqInMhz >= 156UL)); + + /* + * ARM_PLL (156Mhz - 624MHz configureable ) + * freqInMhz = osc_freq * loopDivider / (2 * postDivider) + * - loopDivider: 104 - 208 + * postDivider: + * 0 - divide by 8; 1 - divide by 4 + */ + + if (freqInMhz >= refFreq) + { + config->loopDivider = 208; + config->postDivider = kCLOCK_PllPostDiv4; + } + else if (freqInMhz >= (refFreq >> 1UL)) + { + config->postDivider = kCLOCK_PllPostDiv4; + config->loopDivider = freqInMhz / 3UL; + } + else + { + config->postDivider = kCLOCK_PllPostDiv8; + config->loopDivider = freqInMhz * 2UL / 3UL; + } + + return kStatus_Success; +} + +status_t CLOCK_InitArmPllWithFreq(uint32_t freqInMhz) +{ + clock_arm_pll_config_t config; + if (kStatus_Success == CLOCK_CalcArmPllFreq(&config, freqInMhz)) + { + CLOCK_InitArmPll(&config); + return kStatus_Success; + } + return kStatus_Fail; +} + +status_t CLOCK_CalcAvPllFreq(clock_av_pll_config_t *config, uint32_t freqInMhz) +{ + assert(config != NULL); + + uint32_t refFreq = (XTAL_FREQ / 1000000UL) * 54UL; /* MHz */ + + assert((freqInMhz <= refFreq) && (freqInMhz > 20UL)); + + /* + * AUDIO_PLL/VIDEO_PLL (20.3125MHZ--- 1300MHZ configureable ) + * freqInMhz = osc_freq * (loopDivider + numerator / (2^28 - 1) ) / 2^postDivider + * - loopDivider: 27---54 + * - postDivider: 0---5 + * - numerator is a signed number, 30 bit, numer[29] is the sign bit, such as +1--->0x00000001; -1---> 0x20000001 + * such as: div_sel = 27, numer = 0x026EEEEF, post_div =0, fref = 24.0MHZ, output_fre =24.0*(27 + 40824559/(2^28 - + * 1))/2^0 = 651.65M such as: div_sel = 33, numer = 0x0F0AAAAA, post_div =0, fref = 19.2MHZ, output_fre =19.2*(33 + + * 252357290/(2^28 - 1))/2^0= 651.65M + */ + + config->denominator = 0x0FFFFFFF; + + if (freqInMhz >= refFreq) + { + config->postDivider = 0; + config->loopDivider = 54; + config->numerator = 0; + } + else if (freqInMhz >= (refFreq >> 1)) + { + config->postDivider = 0; + config->loopDivider = (uint8_t)(freqInMhz / 24UL); + config->numerator = (config->denominator / 24UL) * (freqInMhz % 24UL); + } + else if (freqInMhz >= (refFreq >> 2)) + { + config->postDivider = 1; + config->loopDivider = (uint8_t)(freqInMhz / 12UL); + config->numerator = (config->denominator / 12UL) * (freqInMhz % 12UL); + } + else if (freqInMhz >= (refFreq >> 3)) + { + config->postDivider = 2; + config->loopDivider = (uint8_t)(freqInMhz / 6UL); + config->numerator = (config->denominator / 6UL) * (freqInMhz % 6UL); + } + else if (freqInMhz >= (refFreq >> 4)) + { + config->postDivider = 3; + config->loopDivider = (uint8_t)(freqInMhz / 3UL); + config->numerator = (config->denominator / 3UL) * (freqInMhz % 3UL); + } + else if (freqInMhz >= (refFreq >> 5)) + { + config->postDivider = 4; + config->loopDivider = (uint8_t)(freqInMhz * 2UL / 3UL); + config->numerator = (config->denominator * 2UL / 3UL) * (freqInMhz * 2UL % 3UL); + } + else if (freqInMhz > (refFreq >> 6)) + { + config->postDivider = 5; + config->loopDivider = (uint8_t)(freqInMhz * 4UL / 3UL); + config->numerator = (config->denominator * 4UL / 3UL) * (freqInMhz * 4UL % 3UL); + } + else + { + return kStatus_Fail; + } + return kStatus_Success; +} + +status_t CLOCK_InitVideoPllWithFreq(uint32_t freqInMhz, bool ssEnable, uint32_t ssRange, uint32_t ssMod) +{ + clock_video_pll_config_t config = {0}; + config.ssEnable = ssEnable; + + if (kStatus_Success == CLOCK_CalcAvPllFreq(&config, freqInMhz)) + { + if (config.ssEnable) + { + clock_pll_ss_config_t ss = {0}; + CLOCK_CalcPllSpreadSpectrum(config.denominator, ssRange, ssMod, &ss); + config.ss = &ss; + } + CLOCK_InitVideoPll(&config); + return kStatus_Success; + } + return kStatus_Fail; +} + +void CLOCK_InitVideoPll(const clock_video_pll_config_t *config) +{ + uint32_t reg; + bool pllStable = false; + + PMU_StaticEnablePllLdo(ANADIG_PMU); + + reg = ANADIG_PLL->PLL_VIDEO_CTRL; + if ((reg & (ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_MASK | ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_MASK)) == + (ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_MASK | ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_MASK)) + { + pllStable = true; + } + /* bypass pll */ + ANATOP_PllBypass(kAI_Itf_Video, true); + + if (pllStable) + { + /* sw enable clock */ + ANATOP_VideoPllSwEnClk(false); + /* gate clock */ + ANATOP_VideoPllGate(true); + ANATOP_PllEnableClk(kAI_Itf_Video, false); + ANATOP_PllSetPower(kAI_Itf_Video, false); + ANATOP_PllEnablePllReg(kAI_Itf_Video, false); + } + + ANATOP_VideoPllSwEnClk(true); + /* configure pll */ + ANATOP_PllConfigure(kAI_Itf_Video, config->loopDivider, config->numerator, config->postDivider, config->denominator, + (config->ssEnable && (config->ss != NULL)) ? config->ss : NULL); + + /* toggle hold ring off */ + ANATOP_PllToggleHoldRingOff(kAI_Itf_Video, 225); + + /* wait pll stable */ + do + { + reg = ANADIG_PLL->PLL_VIDEO_CTRL; + } while ((reg & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_MASK) != + ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_MASK); /* wait for PLL locked */ + + /* enabled clock */ + ANATOP_PllEnableClk(kAI_Itf_Video, true); + + /* ungate clock */ + ANATOP_VideoPllGate(false); + + ANATOP_PllBypass(kAI_Itf_Video, false); +} + +void CLOCK_DeinitVideoPll(void) +{ + ANATOP_VideoPllSwEnClk(false); + ANATOP_VideoPllGate(true); + ANATOP_PllEnableClk(kAI_Itf_Video, false); + ANATOP_PllSetPower(kAI_Itf_Video, false); + ANATOP_PllEnableSs(kAI_Itf_Video, false); + ANATOP_PllEnablePllReg(kAI_Itf_Video, false); +} + +void CLOCK_GPC_SetVideoPllOutputFreq(const clock_video_pll_gpc_config_t *config) +{ + assert(config != NULL); + + ANADIG_PLL->PLL_VIDEO_DIV_SELECT = config->loopDivider; + ANADIG_PLL->PLL_VIDEO_NUMERATOR = config->numerator; + ANADIG_PLL->PLL_VIDEO_DENOMINATOR = config->denominator; + + if ((config->ss != NULL) && config->ssEnable) + { + ANADIG_PLL->PLL_VIDEO_SS = ANADIG_PLL_PLL_VIDEO_SS_STEP(config->ss->step) | + ANADIG_PLL_PLL_VIDEO_SS_STOP(config->ss->stop) | ANADIG_PLL_PLL_VIDEO_SS_ENABLE_MASK; + } + + ANADIG_PLL->PLL_VIDEO_CTRL |= ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_MASK; +} + +static void ANATOP_SysPll1Gate(bool enable) +{ + if (!enable) + { + ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK; + } + else + { + ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK; + } +} + +static void ANATOP_SysPll1Div2En(bool enable) +{ + if (!enable) + { + ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK; + } + else + { + ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK; + } +} + +static void ANATOP_SysPll1Div5En(bool enable) +{ + if (!enable) + { + ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK; + } + else + { + ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK; + } +} + +static void ANATOP_SysPll1SwEnClk(bool enable) +{ + if (!enable) + { + ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK; + } + else + { + ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK; + } +} + +static void ANATOP_SysPll1WaitStable(void) +{ + uint32_t reg; + do + { + reg = ANADIG_PLL->SYS_PLL1_CTRL; + } while ((reg & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_MASK) != + ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_MASK); /* wait for PLL locked */ +} + +/* 1GPLL */ +void CLOCK_InitSysPll1(const clock_sys_pll1_config_t *config) +{ + uint8_t div; + uint32_t numerator, denominator; + + PMU_StaticEnablePllLdo(ANADIG_PMU); + /* bypass pll */ + ANATOP_PllBypass(kAI_Itf_1g, true); + + /* sw enable clock */ + ANATOP_SysPll1SwEnClk(true); + + denominator = 0x0FFFFFFF; + div = 41U; + numerator = 178956970UL; + + if (config->ssEnable && (config->ss != NULL)) + { + return; + } + + /* configure pll */ + ANATOP_PllConfigure(kAI_Itf_1g, div, numerator, 0U, denominator, + (config->ssEnable && (config->ss != NULL)) ? config->ss : NULL); + + /* toggle hold ring off */ + ANATOP_PllToggleHoldRingOff(kAI_Itf_1g, 225); + + /* wait pll stable */ + ANATOP_SysPll1WaitStable(); + + /* enabled clock */ + ANATOP_PllEnableClk(kAI_Itf_1g, true); + + /* ungate clock */ + ANATOP_SysPll1Gate(false); + + ANATOP_SysPll1Div2En(config->pllDiv2En); + ANATOP_SysPll1Div5En(config->pllDiv5En); + + /* bypass pll */ + ANATOP_PllBypass(kAI_Itf_1g, false); +} + +void CLOCK_DeinitSysPll1(void) +{ + ANATOP_SysPll1SwEnClk(false); + ANATOP_SysPll1Div2En(false); + ANATOP_SysPll1Div5En(false); + ANATOP_SysPll1Gate(true); + ANATOP_PllEnableClk(kAI_Itf_1g, false); + ANATOP_PllSetPower(kAI_Itf_1g, false); + ANATOP_PllEnableSs(kAI_Itf_1g, false); + ANATOP_PllEnablePllReg(kAI_Itf_1g, false); +} + +void CLOCK_GPC_SetSysPll1OutputFreq(const clock_sys_pll1_gpc_config_t *config) +{ + assert(config != NULL); + + ANADIG_PLL->SYS_PLL1_DIV_SELECT = config->loopDivider; + ANADIG_PLL->SYS_PLL1_NUMERATOR = config->numerator; + ANADIG_PLL->SYS_PLL1_DENOMINATOR = config->denominator; + + if ((config->ss != NULL) && config->ssEnable) + { + ANADIG_PLL->SYS_PLL1_SS = ANADIG_PLL_SYS_PLL1_SS_STEP(config->ss->step) | + ANADIG_PLL_SYS_PLL1_SS_STOP(config->ss->stop) | ANADIG_PLL_SYS_PLL1_SS_ENABLE_MASK; + } + + ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK; +} + +void CLOCK_OSC_EnableOsc24M(void) +{ + if (0UL == (ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_EN_MASK)) + { + ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN_MASK; + while (ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK != + (ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK)) + { + } + } +} + +/*! + * brief Set the work mode of 24MHz crystal oscillator, the available modes are high gian mode, low power mode, and + * bypass mode. + * + * param workMode The work mode of 24MHz crystal oscillator, please refer to @ref clock_24MOsc_mode_t for details. + */ +void CLOCK_OSC_SetOsc24MWorkMode(clock_24MOsc_mode_t workMode) +{ + uint32_t tmp32; + + tmp32 = ANADIG_OSC->OSC_24M_CTRL; + tmp32 &= ~(ANADIG_OSC_OSC_24M_CTRL_LP_EN_MASK | ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_MASK); + tmp32 |= (((uint32_t)workMode << ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_SHIFT) & + (ANADIG_OSC_OSC_24M_CTRL_LP_EN_MASK | ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_MASK)); + ANADIG_OSC->OSC_24M_CTRL = tmp32; +} + +/*! + * brief Configure the 16MHz oscillator. + * + * param source Used to select the source for 16MHz RC oscillator, please refer to clock_16MOsc_source_t. + * param enablePowerSave Enable/disable power save mode function at 16MHz OSC. + * - \b true Enable power save mode function at 16MHz osc. + * - \b false Disable power save mode function at 16MHz osc. + * param enableClockOut Enable/Disable clock output for 16MHz RCOSC. + * - \b true Enable clock output for 16MHz RCOSC. + * - \b false Disable clock output for 16MHz RCOSC. + */ +void CLOCK_OSC_SetOsc16MConfig(clock_16MOsc_source_t source, bool enablePowerSave, bool enableClockOut) +{ + uint32_t tmp32; + + tmp32 = ANADIG_OSC->OSC_16M_CTRL; + tmp32 &= ~(ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK | ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_MASK | + ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_MASK); + tmp32 |= ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M(enableClockOut) | + ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE(enablePowerSave) | ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M(source); + ANADIG_OSC->OSC_16M_CTRL = tmp32; +} + +/*! + * brief Set the divide value for ref_clk to generate slow clock. + * + * note slow_clk = ref_clk / (divValue + 1), and the recommand divide value is 24. + * + * param divValue The divide value to be set, the available range is 0~63. + */ +void CLOCK_OSC_SetOscRc400MRefClkDiv(uint8_t divValue) +{ + uint32_t tmp32; + + tmp32 = ANATOP_AI_Read(kAI_Itf_400m, kAI_RCOSC400M_CTRL0); + tmp32 = ((tmp32 & ~AI_RCOSC400M_CTRL0_REF_CLK_DIV_MASK) | AI_RCOSC400M_CTRL0_REF_CLK_DIV(divValue)); + ANATOP_AI_Write(kAI_Itf_400m, kAI_RCOSC400M_CTRL0, tmp32); +} + +/*! + * brief Set the target count for the fast clock. + * + * param targetCount The desired target for the fast clock, should be the number of clock cycles of the fast_clk per + * divided ref_clk. + */ +void CLOCK_OSC_SetOscRc400MFastClkCount(uint16_t targetCount) +{ + uint32_t tmp32; + + tmp32 = ANATOP_AI_Read(kAI_Itf_400m, kAI_RCOSC400M_CTRL1); + tmp32 = ((tmp32 & ~AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK) | AI_RCOSC400M_CTRL1_TARGET_COUNT(targetCount)); + ANATOP_AI_Write(kAI_Itf_400m, kAI_RCOSC400M_CTRL1, tmp32); +} + +/*! + * brief Set the negative and positive hysteresis value for the tuned clock. + * + * note The hysteresis value should be set after the clock is tuned. + * + * param negHysteresis The negative hysteresis value for the turned clock, this value in number of clock cycles of the + * fast clock + * param posHysteresis The positive hysteresis value for the turned clock, this value in number of clock cycles of the + * fast clock + */ +void CLOCK_OSC_SetOscRc400MHysteresisValue(uint8_t negHysteresis, uint8_t posHysteresis) +{ + uint32_t tmp32; + + tmp32 = ANATOP_AI_Read(kAI_Itf_400m, kAI_RCOSC400M_CTRL1); + tmp32 = ((tmp32 & ~(AI_RCOSC400M_CTRL1_HYST_PLUS_MASK | AI_RCOSC400M_CTRL1_HYST_MINUS_MASK)) | + (AI_RCOSC400M_CTRL1_HYST_PLUS(posHysteresis) | AI_RCOSC400M_CTRL1_HYST_MINUS(negHysteresis))); + ANATOP_AI_Write(kAI_Itf_400m, kAI_RCOSC400M_CTRL1, tmp32); +} + +/*! + * brief Bypass/un-bypass the tune logic + * + * param enableBypass Used to control whether to bypass the turn logic. + * - \b true Bypass the tune logic and use the programmed oscillator frequency to run the oscillator. + * Function CLOCK_OSC_SetOscRc400MTuneValue() can be used to set oscillator frequency. + * - \b false Use the output of tune logic to run the oscillator. + */ +void CLOCK_OSC_BypassOscRc400MTuneLogic(bool enableBypass) +{ + if (enableBypass) + { + ANATOP_AI_Write(kAI_Itf_400m, kAI_RCOSC400M_CTRL2_SET, AI_RCOSC400M_CTRL2_TUNE_BYP_MASK); + } + else + { + ANATOP_AI_Write(kAI_Itf_400m, kAI_RCOSC400M_CTRL2_CLR, AI_RCOSC400M_CTRL2_TUNE_BYP_MASK); + } +} + +/*! + * brief Start/Stop the tune logic. + * + * param enable Used to start or stop the tune logic. + * - \b true Start tuning + * - \b false Stop tuning and reset the tuning logic. + */ +void CLOCK_OSC_EnableOscRc400MTuneLogic(bool enable) +{ + if (enable) + { + ANATOP_AI_Write(kAI_Itf_400m, kAI_RCOSC400M_CTRL2_SET, AI_RCOSC400M_CTRL2_TUNE_START_MASK); + } + else + { + ANATOP_AI_Write(kAI_Itf_400m, kAI_RCOSC400M_CTRL2_CLR, AI_RCOSC400M_CTRL2_TUNE_START_MASK); + } +} + +/*! + * brief Freeze/Unfreeze the tuning value. + * + * param enableFreeze Used to control whether to freeze the tune value. + * - \b true Freeze the tune at the current tuned value and the oscillator runs at tje frozen tune value. + * - \b false Unfreezes and continues the tune operation. + */ +void CLOCK_OSC_FreezeOscRc400MTuneValue(bool enableFreeze) +{ + if (enableFreeze) + { + ANATOP_AI_Write(kAI_Itf_400m, kAI_RCOSC400M_CTRL2_SET, AI_RCOSC400M_CTRL2_TUNE_EN_MASK); + } + else + { + ANATOP_AI_Write(kAI_Itf_400m, kAI_RCOSC400M_CTRL2_CLR, AI_RCOSC400M_CTRL2_TUNE_EN_MASK); + } +} + +/*! + * @brief Set the 400MHz RC oscillator tune value when the tune logic is disabled. + * + * @param tuneValue The tune value to determine the frequency of Oscillator. + */ +void CLOCK_OSC_SetOscRc400MTuneValue(uint8_t tuneValue) +{ + uint32_t tmp32; + + tmp32 = ANATOP_AI_Read(kAI_Itf_400m, kAI_RCOSC400M_CTRL2); + tmp32 &= ~AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_MASK; + tmp32 |= AI_RCOSC400M_CTRL2_OSC_TUNE_VAL(tuneValue); + ANATOP_AI_Write(kAI_Itf_400m, kAI_RCOSC400M_CTRL2, tmp32); +} + +/*! + * brief Set the behavior of the 1MHz output clock, such as disable the 1MHz clock output, + * enable the free-running 1MHz clock output, enable the locked 1MHz clock output. + * + * note The 1MHz clock is divided from 400M RC Oscillator. + * + * param behavior The behavior of 1MHz output clock, please refer to clock_1MHzOut_behavior_t for details. + */ +void CLOCK_OSC_Set1MHzOutputBehavior(clock_1MHzOut_behavior_t behavior) +{ + uint32_t tmp32; + + tmp32 = ANATOP_AI_Read(kAI_Itf_400m, kAI_RCOSC400M_CTRL3); + tmp32 &= ~(AI_RCOSC400M_CTRL3_EN_1M_CLK_MASK | AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK); + + if (behavior == kCLOCK_1MHzOutDisable) + { + tmp32 |= AI_RCOSC400M_CTRL3_EN_1M_CLK_MASK; + } + else + { + if (behavior == kCLOCK_1MHzOutEnableLocked1Mhz) + { + tmp32 |= AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK; + } + } + ANATOP_AI_Write(kAI_Itf_400m, kAI_RCOSC400M_CTRL3, tmp32); +} + +/*! + * brief Set the count for the locked 1MHz clock out. + * + * param count Used to set the desired target for the locked 1MHz clock out, the value in number of clock cycles of the + * osc_out_400M per divided ref_clk. + */ +void CLOCK_OSC_SetLocked1MHzCount(uint16_t count) +{ + uint32_t tmp32; + uint16_t targetCount; + uint16_t hystMinus; + uint16_t diffCount; + + tmp32 = ANATOP_AI_Read(kAI_Itf_400m, kAI_RCOSC400M_CTRL1); + targetCount = (uint16_t)((tmp32 & AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK) >> AI_RCOSC400M_CTRL1_TARGET_COUNT_SHIFT); + hystMinus = (uint16_t)((tmp32 & AI_RCOSC400M_CTRL1_HYST_MINUS_MASK) >> AI_RCOSC400M_CTRL1_HYST_MINUS_SHIFT); + diffCount = targetCount - hystMinus - count; + + /* The count for the locked 1MHz clock should be 4 to 8 counts less than CTRL[TARGET_COUNT] - CTRL1[HYST_MINUS]. */ + if ((diffCount >= 4U) && (diffCount <= 8U)) + { + tmp32 = (tmp32 & ~AI_RCOSC400M_CTRL3_COUNT_1M_CLK_MASK) | AI_RCOSC400M_CTRL3_COUNT_1M_CLK(count); + ANATOP_AI_Write(kAI_Itf_400m, kAI_RCOSC400M_CTRL3, tmp32); + } +} + +/*! + * brief Check the error flag for locked 1MHz clock out. + * + * return The error flag for locked 1MHz clock out. + * - \b true The count value has been reached within one diviced ref clock period + * - \b false No effect. + */ +bool CLOCK_OSC_CheckLocked1MHzErrorFlag(void) +{ + uint32_t tmp32; + + tmp32 = ANATOP_AI_Read(kAI_Itf_400m, kAI_RCOSC400M_STAT0); + + return ((tmp32 & AI_RCOSC400M_STAT0_CLK1M_ERR_MASK) == AI_RCOSC400M_STAT0_CLK1M_ERR_MASK); +} + +/*! + * brief Clear the error flag for locked 1MHz clock out. + */ +void CLOCK_OSC_ClearLocked1MHzErrorFlag(void) +{ + ANATOP_AI_Write(kAI_Itf_400m, kAI_RCOSC400M_CTRL3_SET, AI_RCOSC400M_CTRL3_CLR_ERR_MASK); +} + +/*! + * brief Get current count for the fast clock during the tune process. + * + * return The current count for the fast clock. + */ +uint16_t CLOCK_OSC_GetCurrentOscRc400MFastClockCount(void) +{ + uint32_t tmp32; + + tmp32 = ANATOP_AI_Read(kAI_Itf_400m, kAI_RCOSC400M_STAT1); + + return (uint16_t)((tmp32 & AI_RCOSC400M_STAT1_CURR_COUNT_VAL_MASK) >> AI_RCOSC400M_STAT1_CURR_COUNT_VAL_SHIFT); +} + +/*! + * brief Get current tune value used by oscillator during tune process. + * + * return The current tune value. + */ +uint8_t CLOCK_OSC_GetCurrentOscRc400MTuneValue(void) +{ + uint32_t tmp32; + + tmp32 = ANATOP_AI_Read(kAI_Itf_400m, kAI_RCOSC400M_STAT2); + + return (uint8_t)((tmp32 & AI_RCOSC400M_STAT2_CURR_OSC_TUNE_VAL_MASK) >> AI_RCOSC400M_STAT2_CURR_OSC_TUNE_VAL_SHIFT); +} + +#ifndef GET_FREQ_FROM_OBS +static uint32_t CLOCK_GetAvPllFreq(clock_pll_t pll) +{ + uint32_t freq = 0; + uint32_t div; + uint32_t post_div; + double tmpDouble; + double denom; + double numer; + + assert((pll == kCLOCK_PllAudio) || (pll == kCLOCK_PllVideo)); + + div = ANATOP_AI_Read(pll == kCLOCK_PllAudio ? kAI_Itf_Audio : kAI_Itf_Video, PLL_AI_CTRL0_REG); + post_div = (div & (0xE000000UL)) >> 25UL; + div &= 0x7fUL; + denom = (double)ANATOP_AI_Read(pll == kCLOCK_PllAudio ? kAI_Itf_Audio : kAI_Itf_Video, PLL_AI_CTRL3_REG); + numer = (double)ANATOP_AI_Read(pll == kCLOCK_PllAudio ? kAI_Itf_Audio : kAI_Itf_Video, PLL_AI_CTRL2_REG); + + tmpDouble = ((double)XTAL_FREQ * ((double)div + (numer / denom)) / (double)(uint32_t)(1UL << post_div)); + freq = (uint32_t)tmpDouble; + + return freq; +} +#endif + +uint32_t CLOCK_GetPllFreq(clock_pll_t pll) +{ + uint32_t freq = 0; +#ifndef GET_FREQ_FROM_OBS + uint32_t divSelect, postDiv; +#endif + + switch (pll) + { + case kCLOCK_PllArm: +#ifndef GET_FREQ_FROM_OBS + divSelect = (ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_MASK) >> + ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_SHIFT; + postDiv = (ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_MASK) >> + ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_SHIFT; + postDiv = (1UL << (postDiv + 1UL)); + freq = XTAL_FREQ / (2UL * postDiv); + freq *= divSelect; +#else + freq = CLOCK_GetFreqFromObs(CCM_OBS_ARM_PLL_OUT); +#endif + break; + case kCLOCK_PllSys1: +#ifndef GET_FREQ_FROM_OBS + freq = SYS_PLL1_FREQ; +#else + freq = CLOCK_GetFreqFromObs(CCM_OBS_SYS_PLL1_OUT); +#endif + break; + case kCLOCK_PllSys2: +#ifndef GET_FREQ_FROM_OBS + freq = SYS_PLL2_FREQ; +#else + freq = CLOCK_GetFreqFromObs(CCM_OBS_SYS_PLL2_OUT); +#endif + break; + case kCLOCK_PllSys3: +#ifndef GET_FREQ_FROM_OBS + freq = SYS_PLL3_FREQ; +#else + freq = CLOCK_GetFreqFromObs(CCM_OBS_SYS_PLL3_OUT); +#endif + break; + case kCLOCK_PllAudio: +#ifndef GET_FREQ_FROM_OBS + freq = CLOCK_GetAvPllFreq(kCLOCK_PllAudio); +#else + freq = CLOCK_GetFreqFromObs(CCM_OBS_PLL_AUDIO_OUT); +#endif + break; + case kCLOCK_PllVideo: +#ifndef GET_FREQ_FROM_OBS + freq = CLOCK_GetAvPllFreq(kCLOCK_PllVideo); +#else + freq = CLOCK_GetFreqFromObs(CCM_OBS_PLL_VIDEO_OUT); +#endif + break; + default: + /* Wrong input parameter pll. */ + assert(false); + break; + } + assert(freq != 0UL); + return freq; +} + +uint32_t CLOCK_GetFreq(clock_name_t name) +{ + uint32_t freq = 0; + + assert(name != kCLOCK_Reserved); + + switch (name) + { + case kCLOCK_OscRc16M: +#ifndef GET_FREQ_FROM_OBS + freq = 16000000U; +#else + freq = CLOCK_GetFreqFromObs(CCM_OBS_OSC_RC_16M); +#endif + break; + case kCLOCK_OscRc48M: +#ifndef GET_FREQ_FROM_OBS + freq = 48000000U; +#else + freq = CLOCK_GetFreqFromObs(CCM_OBS_OSC_RC_48M); +#endif + break; + case kCLOCK_OscRc48MDiv2: +#ifndef GET_FREQ_FROM_OBS + freq = 24000000U; +#else + freq = CLOCK_GetFreqFromObs(CCM_OBS_OSC_RC_48M_DIV2); +#endif + break; + case kCLOCK_OscRc400M: +#ifndef GET_FREQ_FROM_OBS + freq = 400000000U; +#else + freq = CLOCK_GetFreqFromObs(CCM_OBS_OSC_RC_400M); +#endif + break; + case kCLOCK_Osc24MOut: + case kCLOCK_Osc24M: +#ifndef GET_FREQ_FROM_OBS + freq = 24000000U; +#else + freq = CLOCK_GetFreqFromObs(CCM_OBS_OSC_24M_OUT); +#endif + break; + case kCLOCK_ArmPllOut: + case kCLOCK_ArmPll: + freq = CLOCK_GetPllFreq(kCLOCK_PllArm); + break; + case kCLOCK_SysPll2: + case kCLOCK_SysPll2Out: + freq = CLOCK_GetPllFreq(kCLOCK_PllSys2); + break; + case kCLOCK_SysPll2Pfd0: + freq = CLOCK_GetPfdFreq(kCLOCK_PllSys2, kCLOCK_Pfd0); + break; + case kCLOCK_SysPll2Pfd1: + freq = CLOCK_GetPfdFreq(kCLOCK_PllSys2, kCLOCK_Pfd1); + break; + case kCLOCK_SysPll2Pfd2: + freq = CLOCK_GetPfdFreq(kCLOCK_PllSys2, kCLOCK_Pfd2); + break; + case kCLOCK_SysPll2Pfd3: + freq = CLOCK_GetPfdFreq(kCLOCK_PllSys2, kCLOCK_Pfd3); + break; + case kCLOCK_SysPll3Out: + case kCLOCK_SysPll3: + freq = CLOCK_GetPllFreq(kCLOCK_PllSys3); + break; + case kCLOCK_SysPll3Div2: + freq = (CLOCK_GetPllFreq(kCLOCK_PllSys3) / 2UL); + break; + case kCLOCK_SysPll3Pfd0: + freq = CLOCK_GetPfdFreq(kCLOCK_PllSys3, kCLOCK_Pfd0); + break; + case kCLOCK_SysPll3Pfd1: + freq = CLOCK_GetPfdFreq(kCLOCK_PllSys3, kCLOCK_Pfd1); + break; + case kCLOCK_SysPll3Pfd2: + freq = CLOCK_GetPfdFreq(kCLOCK_PllSys3, kCLOCK_Pfd2); + break; + case kCLOCK_SysPll3Pfd3: + freq = CLOCK_GetPfdFreq(kCLOCK_PllSys3, kCLOCK_Pfd3); + break; + case kCLOCK_SysPll1: + case kCLOCK_SysPll1Out: + freq = CLOCK_GetPllFreq(kCLOCK_PllSys1); + break; + case kCLOCK_SysPll1Div2: + freq = CLOCK_GetPllFreq(kCLOCK_PllSys1) / 2UL; + break; + case kCLOCK_SysPll1Div5: + freq = CLOCK_GetPllFreq(kCLOCK_PllSys1) / 5UL; + break; + case kCLOCK_AudioPll: + case kCLOCK_AudioPllOut: + freq = CLOCK_GetPllFreq(kCLOCK_PllAudio); + break; + case kCLOCK_VideoPll: + case kCLOCK_VideoPllOut: + freq = CLOCK_GetPllFreq(kCLOCK_PllVideo); + break; + case kCLOCK_CpuClk: + case kCLOCK_CoreSysClk: + freq = CLOCK_GetCpuClkFreq(); + break; + default: + /* Wrong input parameter name. */ + assert(false); + break; + } + assert(freq != 0UL); + return freq; +} + +void CLOCK_SetGroupConfig(clock_group_t group, const clock_group_config_t *config) +{ + assert(group < kCLOCK_Group_Last); + + CCM->CLOCK_GROUP[group].CONTROL = ((config->clockOff ? CCM_CLOCK_GROUP_CONTROL_OFF_MASK : 0UL) | + ((uint32_t)config->resetDiv << CCM_CLOCK_GROUP_CONTROL_RSTDIV_SHIFT) | + (config->div0 << CCM_CLOCK_GROUP_CONTROL_DIV0_SHIFT)); +} + +void CLOCK_OSC_TrimOscRc400M(bool enable, bool bypass, uint16_t trim) +{ + if (enable) + { + ANADIG_MISC->VDDLPSR_AI400M_CTRL = 0x20UL; + ANADIG_MISC->VDDLPSR_AI400M_WDATA = ((uint32_t)bypass << 10UL) | ((uint32_t)trim << 24UL); + ANADIG_MISC->VDDLPSR_AI400M_CTRL |= 0x100UL; + SDK_DelayAtLeastUs(1, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + ANADIG_MISC->VDDLPSR_AI400M_CTRL &= ~0x100UL; + } +} + +void CLOCK_OSC_EnableOscRc400M(void) +{ + ANADIG_OSC->OSC_400M_CTRL1 &= ~ANADIG_OSC_OSC_400M_CTRL1_PWD_MASK; + ANADIG_OSC->OSC_400M_CTRL2 |= ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_MASK; +} + +uint32_t CLOCK_GetFreqFromObs(uint32_t obsSigIndex, uint32_t obsIndex) +{ + CCM_OBS->OBSERVE[obsIndex].CONTROL = CCM_OBS_OBSERVE_CONTROL_OFF_MASK; /* turn off detect */ + CCM_OBS->OBSERVE[obsIndex].CONTROL_SET = CCM_OBS_OBSERVE_CONTROL_RESET_MASK; /* reset slice */ + CCM_OBS->OBSERVE[obsIndex].CONTROL_CLR = CCM_OBS_OBSERVE_CONTROL_RAW_MASK; /* select raw obsSigIndex */ + CCM_OBS->OBSERVE[obsIndex].CONTROL &= ~CCM_OBS_OBSERVE_CONTROL_SELECT_MASK; /* Select observed obsSigIndex */ + CCM_OBS->OBSERVE[obsIndex].CONTROL |= CCM_OBS_OBSERVE_CONTROL_SELECT(obsSigIndex) | + CCM_OBS_OBSERVE_CONTROL_DIVIDE(CCM_OBS_DIV); /* turn on detection */ + CCM_OBS->OBSERVE[obsIndex].CONTROL_CLR = + CCM_OBS_OBSERVE_CONTROL_RESET_MASK | CCM_OBS_OBSERVE_CONTROL_OFF_MASK; /* unreset and turn on detect */ + + while (CCM_OBS->OBSERVE[obsIndex].FREQUENCY_CURRENT == 0UL) + { + } + + return (CCM_OBS->OBSERVE[obsIndex].FREQUENCY_CURRENT * ((uint32_t)CCM_OBS_DIV + 1UL)); +} + +/*! brief Enable USB HS clock. + * + * This function only enables the access to USB HS prepheral, upper layer + * should first call the ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY + * clock to use USB HS. + * + * param src USB HS does not care about the clock source, here must be ref kCLOCK_UsbSrcUnused. + * param freq USB HS does not care about the clock source, so this parameter is ignored. + * retval true The clock is set successfully. + * retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq) +{ + return true; +} +/*! brief Enable USB HS PHY PLL clock. + * + * This function enables the internal 480MHz USB PHY PLL clock. + * + * param src USB HS PHY PLL clock source. + * param freq The frequency specified by src. + * retval true The clock is set successfully. + * retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) +{ + uint32_t phyPllDiv = 0U; + uint16_t multiplier = 0U; + bool err = false; + CLOCK_EnableClock(kCLOCK_Usb); + + USBPHY1->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK; + + USBPHY1->PLL_SIC_SET = (USBPHY_PLL_SIC_PLL_POWER(1) | USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK); + if ((480000000UL % freq) != 0UL) + { + return false; + } + multiplier = (uint16_t)(480000000UL / freq); + + switch (multiplier) + { + case 13: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(0U); + break; + } + case 15: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(1U); + break; + } + case 16: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(2U); + break; + } + case 20: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(3U); + break; + } + case 22: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(4U); + break; + } + case 25: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(5U); + break; + } + case 30: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(6U); + break; + } + case 240: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(7U); + break; + } + default: + { + err = true; + break; + } + } + + if (err) + { + return false; + } + + USBPHY1->PLL_SIC = (USBPHY1->PLL_SIC & ~(USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)) | phyPllDiv; + + USBPHY1->PLL_SIC_CLR = USBPHY_PLL_SIC_PLL_BYPASS_MASK; + USBPHY1->PLL_SIC_SET = (USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK); + + USBPHY1->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK; +#ifndef __rtems__ + USBPHY1->PWD_SET = 0x0; +#else /* __rtems__ */ + USBPHY1->PWD = 0x0; +#endif /* __rtems__ */ + + while (0UL == (USBPHY1->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK)) + { + } + return true; +} +/*! brief Enable USB HS clock. + * + * This function only enables the access to USB HS prepheral, upper layer + * should first call the ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY + * clock to use USB HS. + * + * param src USB HS does not care about the clock source, here must be ref kCLOCK_UsbSrcUnused. + * param freq USB HS does not care about the clock source, so this parameter is ignored. + * retval true The clock is set successfully. + * retval false The clock source is invalid to get proper USB HS clock. + */ +/*! brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhs0PhyPllClock(void) +{ + USBPHY1->PLL_SIC_CLR = (USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK); + USBPHY1->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ +} +bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq) +{ + return true; +} +bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) +{ + uint32_t phyPllDiv = 0U; + uint16_t multiplier = 0U; + bool err = false; + CLOCK_EnableClock(kCLOCK_Usb); + + USBPHY2->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK; + + USBPHY2->PLL_SIC_SET = (USBPHY_PLL_SIC_PLL_POWER(1) | USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK); + if ((480000000UL % freq) != 0UL) + { + return false; + } + multiplier = (uint16_t)(uint32_t)(480000000UL / freq); + + switch (multiplier) + { + case 13: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(0U); + break; + } + case 15: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(1U); + break; + } + case 16: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(2U); + break; + } + case 20: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(3U); + break; + } + case 22: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(4U); + break; + } + case 25: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(5U); + break; + } + case 30: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(6U); + break; + } + case 240: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(7U); + break; + } + default: + { + err = true; + break; + } + } + + if (err) + { + return false; + } + USBPHY2->PLL_SIC = (USBPHY2->PLL_SIC & ~(USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)) | phyPllDiv; + + USBPHY2->PLL_SIC_CLR = USBPHY_PLL_SIC_PLL_BYPASS_MASK; + USBPHY2->PLL_SIC_SET = (USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK); + + USBPHY2->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK; +#ifndef __rtems__ + USBPHY2->PWD_SET = 0x0; +#else /* __rtems__ */ + USBPHY2->PWD = 0x0; +#endif /* __rtems__ */ + + while (0UL == (USBPHY2->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK)) + { + } + return true; +} +/*! brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhs1PhyPllClock(void) +{ + USBPHY2->PLL_SIC_CLR = (USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK); + USBPHY2->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ +} + +void CLOCK_OSCPLL_ControlBySetPointMode(clock_name_t name, uint16_t spValue, uint16_t stbyValue) +{ + /* Set control mode to unassigned mode. */ + CCM->OSCPLL[name].AUTHEN &= + ~(CCM_OSCPLL_AUTHEN_CPULPM_MASK | CCM_OSCPLL_AUTHEN_DOMAIN_MODE_MASK | CCM_OSCPLL_AUTHEN_SETPOINT_MODE_MASK); + /* Change SetPoint value in unassigned mode. */ + CCM->OSCPLL[name].SETPOINT = CCM_OSCPLL_SETPOINT_STANDBY(stbyValue) | CCM_OSCPLL_SETPOINT_SETPOINT(spValue); + /* Set control mode to SetPoint mode. */ + CCM->OSCPLL[name].AUTHEN |= CCM_OSCPLL_AUTHEN_SETPOINT_MODE_MASK; +} + +void CLOCK_OSCPLL_ControlByCpuLowPowerMode(clock_name_t name, + uint8_t domainId, + clock_level_t level0, + clock_level_t level1) +{ + /* Set control mode to unassigned mode. */ + CCM->OSCPLL[name].AUTHEN &= + ~(CCM_OSCPLL_AUTHEN_SETPOINT_MODE_MASK | CCM_OSCPLL_AUTHEN_DOMAIN_MODE_MASK | CCM_OSCPLL_AUTHEN_CPULPM_MASK); + /* Change clock depend level for each domain in unassigned mode. */ + CCM->OSCPLL[name].DOMAINr = + ((((uint32_t)domainId & (1UL << 1UL)) != 0UL) ? CCM_OSCPLL_DOMAIN_LEVEL1(level1) : 0UL) | + (((domainId & (1UL << 0UL)) != 0UL) ? CCM_OSCPLL_DOMAIN_LEVEL0(level0) : 0UL); + /* Set control mode to CPU low power mode and update whitelist. */ + CCM->OSCPLL[name].AUTHEN = (CCM->OSCPLL[name].AUTHEN & ~CCM_OSCPLL_AUTHEN_WHITE_LIST_MASK) | + CCM_OSCPLL_AUTHEN_CPULPM_MASK | CCM_OSCPLL_AUTHEN_WHITE_LIST(domainId); +} + +void CLOCK_ROOT_ControlBySetPointMode(clock_root_t name, const clock_root_setpoint_config_t *spTable) +{ + uint8_t i; + + /* Set control mode to unassigned mode. */ + CLOCK_ROOT_ControlByUnassignedMode(name); + /* Change SetPoint value in unassigned mode. */ + for (i = 0U; i < 16U; i++) + { + CLOCK_ROOT_ConfigSetPoint(name, i, &spTable[i]); + } + /* Set control mode to SetPoint mode. */ + CLOCK_ROOT_EnableSetPointControl(name); +} + +void CLOCK_LPCG_ControlBySetPointMode(clock_lpcg_t name, uint16_t spValue, uint16_t stbyValue) +{ + /* Set control mode to unassigned mode. */ + CCM->LPCG[name].AUTHEN &= + ~(CCM_LPCG_AUTHEN_CPULPM_MASK | CCM_LPCG_AUTHEN_DOMAIN_MODE_MASK | CCM_LPCG_AUTHEN_SETPOINT_MODE_MASK); + /* Change SetPoint value in unassigned mode. */ + CCM->LPCG[name].SETPOINT = CCM_LPCG_SETPOINT_STANDBY(stbyValue) | CCM_LPCG_SETPOINT_SETPOINT(spValue); + /* Set control mode to SetPoint mode. */ + CCM->LPCG[name].AUTHEN |= CCM_LPCG_AUTHEN_SETPOINT_MODE_MASK; +} + +void CLOCK_LPCG_ControlByCpuLowPowerMode(clock_lpcg_t name, + uint8_t domainId, + clock_level_t level0, + clock_level_t level1) +{ + /* Set control mode to unassigned mode. */ + CCM->LPCG[name].AUTHEN &= + ~(CCM_LPCG_AUTHEN_SETPOINT_MODE_MASK | CCM_LPCG_AUTHEN_DOMAIN_MODE_MASK | CCM_LPCG_AUTHEN_CPULPM_MASK); + /* Change clock depend level for each domain in unassigned mode. */ + CCM->LPCG[name].DOMAINr = ((((uint32_t)domainId & (1UL << 1UL)) != 0UL) ? CCM_LPCG_DOMAIN_LEVEL1(level1) : 0UL) | + ((((uint32_t)domainId & (1UL << 0UL)) != 0UL) ? CCM_LPCG_DOMAIN_LEVEL0(level0) : 0UL); + /* Set control mode to CPU low power mode and update whitelist. */ + CCM->LPCG[name].AUTHEN = (CCM->LPCG[name].AUTHEN & ~CCM_LPCG_AUTHEN_WHITE_LIST_MASK) | CCM_LPCG_AUTHEN_CPULPM_MASK | + CCM_LPCG_AUTHEN_WHITE_LIST(domainId); +} diff --git a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_clock.h b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_clock.h new file mode 100644 index 0000000000..bef1487ea6 --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_clock.h @@ -0,0 +1,3308 @@ +/* + * Copyright 2019-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_CLOCK_H_ +#define _FSL_CLOCK_H_ + +#include "fsl_common.h" + +/*! @addtogroup clock */ +/*! @{ */ + +/*! @file */ + +/******************************************************************************* + * Configurations + ******************************************************************************/ + +/*! @brief Configure whether driver controls clock + * + * When set to 0, peripheral drivers will enable clock in initialize function + * and disable clock in de-initialize function. When set to 1, peripheral + * driver will not control the clock, application could control the clock out of + * the driver. + * + * @note All drivers share this feature switcher. If it is set to 1, application + * should handle clock enable and disable for all drivers. + */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) +#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0 +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief CLOCK driver version. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) + +/* Definition for delay API in clock driver, users can redefine it to the real application. */ +#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY +#if __CORTEX_M == 7 +#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (600000000UL) +#else +#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (240000000UL) +#endif +#endif + +/*@}*/ + +/*! + * @brief CCM registers offset. + */ +#define CCSR_OFFSET 0x0C +#define CBCDR_OFFSET 0x14 +#define CBCMR_OFFSET 0x18 +#define CSCMR1_OFFSET 0x1C +#define CSCMR2_OFFSET 0x20 +#define CSCDR1_OFFSET 0x24 +#define CDCDR_OFFSET 0x30 +#define CSCDR2_OFFSET 0x38 +#define CSCDR3_OFFSET 0x3C +#define CACRR_OFFSET 0x10 +#define CS1CDR_OFFSET 0x28 +#define CS2CDR_OFFSET 0x2C + +/*! + * @brief CCM Analog registers offset. + */ +#define ARM_PLL_OFFSET 0x00 +#define PLL_SYS_OFFSET 0x30 +#define PLL_USB1_OFFSET 0x10 +#define PLL_AUDIO_OFFSET 0x70 +#define PLL_VIDEO_OFFSET 0xA0 +#define PLL_ENET_OFFSET 0xE0 +#define PLL_USB2_OFFSET 0x20 + +#define CCM_TUPLE(reg, shift, mask, busyShift) \ + (int)((reg & 0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U)) +#define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + ((tuple)&0xFFU)))) +#define CCM_TUPLE_SHIFT(tuple) (((tuple) >> 8U) & 0x1FU) +#define CCM_TUPLE_MASK(tuple) ((uint32_t)((((tuple) >> 13U) & 0x1FFFU) << ((((tuple) >> 8U) & 0x1FU)))) +#define CCM_TUPLE_BUSY_SHIFT(tuple) (((tuple) >> 26U) & 0x3FU) + +#define CCM_BUSY_WAIT (0x20U) + +/*! + * @brief CCM ANALOG tuple macros to map corresponding registers and bit fields. + */ +#define CCM_ANALOG_TUPLE(reg, shift) (((reg & 0xFFFU) << 16U) | (shift)) +#define CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)tuple) & 0x1FU) +#define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) \ + (*((volatile uint32_t *)((uint32_t)base + (((uint32_t)tuple >> 16U) & 0xFFFU) + off))) +#define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U) + +/*! + * @brief SYS_PLL_FREQ frequency in Hz. + */ +#define SYS_PLL1_FREQ (1000000000UL) +#define SYS_PLL2_MFI (22UL) +#define SYS_PLL2_FREQ (XTAL_FREQ * SYS_PLL2_MFI) +#define SYS_PLL3_MFI (20UL) +#define SYS_PLL3_FREQ (XTAL_FREQ * SYS_PLL3_MFI) +#define XTAL_FREQ (24000000UL) + +/*! @brief Clock gate name array for ADC. */ +#define LPADC_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpadc1, kCLOCK_Lpadc2 \ + } + +/*! @brief Clock gate name array for ADC. */ +#define ADC_ETC_CLOCKS \ + { \ + kCLOCK_Adc_Etc \ + } + +/*! @brief Clock gate name array for AOI. */ +#define AOI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Aoi1, kCLOCK_Aoi2 \ + } + +/*! @brief Clock gate name array for DCDC. */ +#define DCDC_CLOCKS \ + { \ + kCLOCK_Dcdc \ + } + +/*! @brief Clock gate name array for SRC. */ +#define SRC_CLOCKS \ + { \ + kCLOCK_Src \ + } + +/*! @brief Clock gate name array for GPC. */ +#define GPC_CLOCKS \ + { \ + kCLOCK_Gpc \ + } + +/*! @brief Clock gate name array for SSARC. */ +#define SSARC_CLOCKS \ + { \ + kCLOCK_Ssarc \ + } + +/*! @brief Clock gate name array for WDOG. */ +#define WDOG_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2, kCLOCK_Wdog3, kCLOCK_Wdog4 \ + } + +/*! @brief Clock gate name array for EWM. */ +#define EWM_CLOCKS \ + { \ + kCLOCK_Ewm0 \ + } + +/*! @brief Clock gate name array for Sema. */ +#define SEMA_CLOCKS \ + { \ + kCLOCK_Sema \ + } + +/*! @brief Clock gate name array for MU. */ +#if (__CORTEX_M == 7) +#define MU_CLOCKS \ + { \ + kCLOCK_Mu_A \ + } +#else +#define MU_CLOCKS \ + { \ + kCLOCK_Mu_B \ + } +#endif + +/*! @brief Clock gate name array for EDMA. */ +#define EDMA_CLOCKS \ + { \ + kCLOCK_Edma, kCLOCK_Edma_Lpsr \ + } + +/*! @brief Clock gate name array for FLEXRAM. */ +#define FLEXRAM_CLOCKS \ + { \ + kCLOCK_Flexram \ + } + +/*! @brief Clock gate name array for LMEM. */ +#define LMEM_CLOCKS \ + { \ + kCLOCK_Lmem \ + } + +/*! @brief Clock gate name array for FLEXSPI. */ +#define FLEXSPI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Flexspi1, kCLOCK_Flexspi2 \ + } + +/*! @brief Clock gate name array for RDC. */ +#define RDC_CLOCKS \ + { \ + kCLOCK_Rdc, kCLOCK_M7_Xrdc, kCLOCK_M4_Xrdc \ + } + +/*! @brief Clock ip name array for DCDC. */ +#define DCDC_CLOCKS \ + { \ + kCLOCK_Dcdc \ + } + +/*! @brief Clock ip name array for SEMC. */ +#define SEMC_CLOCKS \ + { \ + kCLOCK_Semc \ + } + +/*! @brief Clock ip name array for XECC. */ +#define XECC_CLOCKS \ + { \ + kCLOCK_Xecc \ + } + +/*! @brief Clock ip name array for IEE. */ +#define IEE_CLOCKS \ + { \ + kCLOCK_Iee \ + } + +/*! @brief Clock ip name array for KEY_MANAGER. */ +#define KEYMANAGER_CLOCKS \ + { \ + kCLOCK_Key_Manager \ + } + +/*! @brief Clock ip name array for PUF. */ +#define PUF_CLOCKS \ + { \ + kCLOCK_Puf \ + } + +/*! @brief Clock ip name array for OCOTP. */ +#define OCOTP_CLOCKS \ + { \ + kCLOCK_Ocotp \ + } + +/*! @brief Clock ip name array for CAAM. */ +#define CAAM_CLOCKS \ + { \ + kCLOCK_Caam \ + } + +/*! @brief Clock ip name array for XBAR. */ +#define XBAR_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Xbar1, kCLOCK_Xbar2, kCLOCK_Xbar3 \ + } + +/*! @brief Clock ip name array for IOMUXC. */ +#define IOMUXC_CLOCKS \ + { \ + kCLOCK_Iomuxc, kCLOCK_Iomuxc_Lpsr \ + } + +/*! @brief Clock ip name array for GPIO. */ +#define GPIO_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, \ + kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, \ + } + +/*! @brief Clock ip name array for KPP. */ +#define KPP_CLOCKS \ + { \ + kCLOCK_Kpp \ + } + +/*! @brief Clock ip name array for FLEXIO. */ +#define FLEXIO_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Flexio1, kCLOCK_Flexio2 \ + } + +/*! @brief Clock ip name array for DAC. */ +#define DAC_CLOCKS \ + { \ + kCLOCK_Dac \ + } + +/*! @brief Clock ip name array for CMP. */ +#define CMP_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Acmp1, kCLOCK_Acmp2, kCLOCK_Acmp3, kCLOCK_Acmp4 \ + } + +/*! @brief Clock ip name array for PIT. */ +#define PIT_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Pit1, kCLOCK_Pit2 \ + } + +/*! @brief Clock ip name array for GPT. */ +#define GPT_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2, kCLOCK_Gpt3, kCLOCK_Gpt4, kCLOCK_Gpt5, kCLOCK_Gpt6 \ + } + +/*! @brief Clock ip name array for QTIMER. */ +#define TMR_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Qtimer1, kCLOCK_Qtimer2, kCLOCK_Qtimer3, kCLOCK_Qtimer4 \ + } + +/*! @brief Clock ip name array for ENC. */ +#define ENC_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Enc1, kCLOCK_Enc2, kCLOCK_Enc3, kCLOCK_Enc4 \ + } + +/*! @brief Clock ip name array for PWM. */ +#define PWM_CLOCKS \ + { \ + {kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid}, \ + {kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1}, \ + {kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2}, \ + {kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3}, \ + { \ + kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4 \ + } \ + } + +/*! @brief Clock ip name array for FLEXCAN. */ +#define FLEXCAN_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2, kCLOCK_Can3 \ + } + +/*! @brief Clock ip name array for LPUART. */ +#define LPUART_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5, \ + kCLOCK_Lpuart6, kCLOCK_Lpuart7, kCLOCK_Lpuart8, kCLOCK_Lpuart9, kCLOCK_Lpuart10, kCLOCK_Lpuart11, \ + kCLOCK_Lpuart12 \ + } + +/*! @brief Clock ip name array for LPI2C. */ +#define LPI2C_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4, kCLOCK_Lpi2c5, kCLOCK_Lpi2c6 \ + } + +/*! @brief Clock ip name array for LPSPI. */ +#define LPSPI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3, kCLOCK_Lpspi4, kCLOCK_Lpspi5, kCLOCK_Lpspi6 \ + } + +/*! @brief Clock ip name array for EMVSIM. */ +#define EMVSIM_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Sim1, kCLOCK_Sim2 \ + } + +/*! @brief Clock ip name array for ENET. */ +#define ENET_CLOCKS \ + { \ + kCLOCK_Enet, kCLOCK_Enet_1g \ + } + +/*! @brief Clock ip name array for USB. */ +#define USB_CLOCKS \ + { \ + kCLOCK_Usb \ + } + +/*! @brief Clock ip name array for CDOG. */ +#define CDOG_CLOCKS \ + { \ + kCLOCK_Cdog \ + } + +/*! @brief Clock ip name array for USDHC. */ +#define USDHC_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 \ + } + +/*! @brief Clock ip name array for ASRC. */ +#define ASRC_CLOCKS \ + { \ + kCLOCK_Asrc \ + } + +/*! @brief Clock ip name array for MQS. */ +#define MQS_CLOCKS \ + { \ + kCLOCK_Mqs \ + } + +/*! @brief Clock ip name array for PDM. */ +#define PDM_CLOCKS \ + { \ + kCLOCK_Pdm \ + } + +/*! @brief Clock ip name array for SPDIF. */ +#define SPDIF_CLOCKS \ + { \ + kCLOCK_Spdif \ + } + +/*! @brief Clock ip name array for SAI. */ +#define SAI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3, kCLOCK_Sai4 \ + } + +/*! @brief Clock ip name array for PXP. */ +#define PXP_CLOCKS \ + { \ + kCLOCK_Pxp \ + } + +/*! @brief Clock ip name array for GPU2d. */ +#define GPU2D_CLOCKS \ + { \ + kCLOCK_Gpu2d \ + } + +/*! @brief Clock ip name array for LCDIF. */ +#define LCDIF_CLOCKS \ + { \ + kCLOCK_Lcdif \ + } + +/*! @brief Clock ip name array for LCDIFV2. */ +#define LCDIFV2_CLOCKS \ + { \ + kCLOCK_Lcdifv2 \ + } + +/*! @brief Clock ip name array for MIPI_DSI. */ +#define MIPI_DSI_HOST_CLOCKS \ + { \ + kCLOCK_Mipi_Dsi \ + } + +/*! @brief Clock ip name array for MIPI_CSI. */ +#define MIPI_CSI2RX_CLOCKS \ + { \ + kCLOCK_Mipi_Csi \ + } + +/*! @brief Clock ip name array for CSI. */ +#define CSI_CLOCKS \ + { \ + kCLOCK_Csi \ + } + +/*! @brief Clock ip name array for DCIC. */ +#define DCIC_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Dcic_Mipi, kCLOCK_Dcic_Lcd \ + } + +/*! @brief Clock ip name array for DMAMUX_CLOCKS. */ +#define DMAMUX_CLOCKS \ + { \ + kCLOCK_Edma, kCLOCK_Edma_Lpsr \ + } + +/*! @brief Clock ip name array for XBARA. */ +#define XBARA_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Xbar1 \ + } + +/*! @brief Clock ip name array for XBARB. */ +#define XBARB_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Xbar2, kCLOCK_Xbar3 \ + } + +/*! + * @brief Clock LPCG index + */ +typedef enum _clock_lpcg +{ + kCLOCK_M7 = 0, /*!< Clock LPCG M7. */ + kCLOCK_M4 = 1, /*!< Clock LPCG M4. */ + kCLOCK_Sim_M7 = 2, /*!< Clock LPCG SIM M7. */ + kCLOCK_Sim_M = 3, /*!< Clock LPCG SIM M4. */ + kCLOCK_Sim_Disp = 4, /*!< Clock LPCG SIM DISP. */ + kCLOCK_Sim_Per = 5, /*!< Clock LPCG SIM PER. */ + kCLOCK_Sim_Lpsr = 6, /*!< Clock LPCG SIM LPSR. */ + kCLOCK_Anadig = 7, /*!< Clock LPCG Anadig. */ + kCLOCK_Dcdc = 8, /*!< Clock LPCG DCDC. */ + kCLOCK_Src = 9, /*!< Clock LPCG SRC. */ + kCLOCK_Ccm = 10, /*!< Clock LPCG CCM. */ + kCLOCK_Gpc = 11, /*!< Clock LPCG GPC. */ + kCLOCK_Ssarc = 12, /*!< Clock LPCG SSARC. */ + kCLOCK_Sim_R = 13, /*!< Clock LPCG SIM_R. */ + kCLOCK_Wdog1 = 14, /*!< Clock LPCG WDOG1. */ + kCLOCK_Wdog2 = 15, /*!< Clock LPCG WDOG2. */ + kCLOCK_Wdog3 = 16, /*!< Clock LPCG WDOG3. */ + kCLOCK_Wdog4 = 17, /*!< Clock LPCG WDOG4. */ + kCLOCK_Ewm0 = 18, /*!< Clock LPCG EWM0. */ + kCLOCK_Sema = 19, /*!< Clock LPCG SEMA. */ + kCLOCK_Mu_A = 20, /*!< Clock LPCG MU_A. */ + kCLOCK_Mu_B = 21, /*!< Clock LPCG MU_B. */ + kCLOCK_Edma = 22, /*!< Clock LPCG EDMA. */ + kCLOCK_Edma_Lpsr = 23, /*!< Clock LPCG EDMA_LPSR. */ + kCLOCK_Romcp = 24, /*!< Clock LPCG ROMCP. */ + kCLOCK_Ocram = 25, /*!< Clock LPCG OCRAM. */ + kCLOCK_Flexram = 26, /*!< Clock LPCG FLEXRAM. */ + kCLOCK_Lmem = 27, /*!< Clock LPCG Lmem. */ + kCLOCK_Flexspi1 = 28, /*!< Clock LPCG Flexspi1. */ + kCLOCK_Flexspi2 = 29, /*!< Clock LPCG Flexspi2. */ + kCLOCK_Rdc = 30, /*!< Clock LPCG RDC. */ + kCLOCK_M7_Xrdc = 31, /*!< Clock LPCG M7 XRDC. */ + kCLOCK_M4_Xrdc = 32, /*!< Clock LPCG M4 XRDC. */ + kCLOCK_Semc = 33, /*!< Clock LPCG SEMC. */ + kCLOCK_Xecc = 34, /*!< Clock LPCG XECC. */ + kCLOCK_Iee = 35, /*!< Clock LPCG IEE. */ + kCLOCK_Key_Manager = 36, /*!< Clock LPCG KEY_MANAGER. */ + kCLOCK_Puf = 36, /*!< Clock LPCG PUF. */ + kCLOCK_Ocotp = 37, /*!< Clock LPCG OSOTP. */ + kCLOCK_Snvs_Hp = 38, /*!< Clock LPCG SNVS_HP. */ + kCLOCK_Snvs = 39, /*!< Clock LPCG SNVS. */ + kCLOCK_Caam = 40, /*!< Clock LPCG Caam. */ + kCLOCK_Jtag_Mux = 41, /*!< Clock LPCG JTAG_MUX. */ + kCLOCK_Cstrace = 42, /*!< Clock LPCG CSTRACE. */ + kCLOCK_Xbar1 = 43, /*!< Clock LPCG XBAR1. */ + kCLOCK_Xbar2 = 44, /*!< Clock LPCG XBAR2. */ + kCLOCK_Xbar3 = 45, /*!< Clock LPCG XBAR3. */ + kCLOCK_Aoi1 = 46, /*!< Clock LPCG AOI1. */ + kCLOCK_Aoi2 = 47, /*!< Clock LPCG AOI2. */ + kCLOCK_Adc_Etc = 48, /*!< Clock LPCG ADC_ETC. */ + kCLOCK_Iomuxc = 49, /*!< Clock LPCG IOMUXC. */ + kCLOCK_Iomuxc_Lpsr = 50, /*!< Clock LPCG IOMUXC_LPSR. */ + kCLOCK_Gpio = 51, /*!< Clock LPCG GPIO. */ + kCLOCK_Kpp = 52, /*!< Clock LPCG KPP. */ + kCLOCK_Flexio1 = 53, /*!< Clock LPCG FLEXIO1. */ + kCLOCK_Flexio2 = 54, /*!< Clock LPCG FLEXIO2. */ + kCLOCK_Lpadc1 = 55, /*!< Clock LPCG LPADC1. */ + kCLOCK_Lpadc2 = 56, /*!< Clock LPCG LPADC2. */ + kCLOCK_Dac = 57, /*!< Clock LPCG DAC. */ + kCLOCK_Acmp1 = 58, /*!< Clock LPCG ACMP1. */ + kCLOCK_Acmp2 = 59, /*!< Clock LPCG ACMP2. */ + kCLOCK_Acmp3 = 60, /*!< Clock LPCG ACMP3. */ + kCLOCK_Acmp4 = 61, /*!< Clock LPCG ACMP4. */ + kCLOCK_Pit1 = 62, /*!< Clock LPCG PIT1. */ + kCLOCK_Pit2 = 63, /*!< Clock LPCG PIT2. */ + kCLOCK_Gpt1 = 64, /*!< Clock LPCG GPT1. */ + kCLOCK_Gpt2 = 65, /*!< Clock LPCG GPT2. */ + kCLOCK_Gpt3 = 66, /*!< Clock LPCG GPT3. */ + kCLOCK_Gpt4 = 67, /*!< Clock LPCG GPT4. */ + kCLOCK_Gpt5 = 68, /*!< Clock LPCG GPT5. */ + kCLOCK_Gpt6 = 69, /*!< Clock LPCG GPT6. */ + kCLOCK_Qtimer1 = 70, /*!< Clock LPCG QTIMER1. */ + kCLOCK_Qtimer2 = 71, /*!< Clock LPCG QTIMER2. */ + kCLOCK_Qtimer3 = 72, /*!< Clock LPCG QTIMER3. */ + kCLOCK_Qtimer4 = 73, /*!< Clock LPCG QTIMER4. */ + kCLOCK_Enc1 = 74, /*!< Clock LPCG Enc1. */ + kCLOCK_Enc2 = 75, /*!< Clock LPCG Enc2. */ + kCLOCK_Enc3 = 76, /*!< Clock LPCG Enc3. */ + kCLOCK_Enc4 = 77, /*!< Clock LPCG Enc4. */ + kCLOCK_Hrtimer = 78, /*!< Clock LPCG Hrtimer. */ + kCLOCK_Pwm1 = 79, /*!< Clock LPCG PWM1. */ + kCLOCK_Pwm2 = 80, /*!< Clock LPCG PWM2. */ + kCLOCK_Pwm3 = 81, /*!< Clock LPCG PWM3. */ + kCLOCK_Pwm4 = 82, /*!< Clock LPCG PWM4. */ + kCLOCK_Can1 = 83, /*!< Clock LPCG CAN1. */ + kCLOCK_Can2 = 84, /*!< Clock LPCG CAN2. */ + kCLOCK_Can3 = 85, /*!< Clock LPCG CAN3. */ + kCLOCK_Lpuart1 = 86, /*!< Clock LPCG LPUART1. */ + kCLOCK_Lpuart2 = 87, /*!< Clock LPCG LPUART2. */ + kCLOCK_Lpuart3 = 88, /*!< Clock LPCG LPUART3. */ + kCLOCK_Lpuart4 = 89, /*!< Clock LPCG LPUART4. */ + kCLOCK_Lpuart5 = 90, /*!< Clock LPCG LPUART5. */ + kCLOCK_Lpuart6 = 91, /*!< Clock LPCG LPUART6. */ + kCLOCK_Lpuart7 = 92, /*!< Clock LPCG LPUART7. */ + kCLOCK_Lpuart8 = 93, /*!< Clock LPCG LPUART8. */ + kCLOCK_Lpuart9 = 94, /*!< Clock LPCG LPUART9. */ + kCLOCK_Lpuart10 = 95, /*!< Clock LPCG LPUART10. */ + kCLOCK_Lpuart11 = 96, /*!< Clock LPCG LPUART11. */ + kCLOCK_Lpuart12 = 97, /*!< Clock LPCG LPUART12. */ + kCLOCK_Lpi2c1 = 98, /*!< Clock LPCG LPI2C1. */ + kCLOCK_Lpi2c2 = 99, /*!< Clock LPCG LPI2C2. */ + kCLOCK_Lpi2c3 = 100, /*!< Clock LPCG LPI2C3. */ + kCLOCK_Lpi2c4 = 101, /*!< Clock LPCG LPI2C4. */ + kCLOCK_Lpi2c5 = 102, /*!< Clock LPCG LPI2C5. */ + kCLOCK_Lpi2c6 = 103, /*!< Clock LPCG LPI2C6. */ + kCLOCK_Lpspi1 = 104, /*!< Clock LPCG LPSPI1. */ + kCLOCK_Lpspi2 = 105, /*!< Clock LPCG LPSPI2. */ + kCLOCK_Lpspi3 = 106, /*!< Clock LPCG LPSPI3. */ + kCLOCK_Lpspi4 = 107, /*!< Clock LPCG LPSPI4. */ + kCLOCK_Lpspi5 = 108, /*!< Clock LPCG LPSPI5. */ + kCLOCK_Lpspi6 = 109, /*!< Clock LPCG LPSPI6. */ + kCLOCK_Sim1 = 110, /*!< Clock LPCG SIM1. */ + kCLOCK_Sim2 = 111, /*!< Clock LPCG SIM2. */ + kCLOCK_Enet = 112, /*!< Clock LPCG ENET. */ + kCLOCK_Enet_1g = 113, /*!< Clock LPCG ENET 1G. */ + kCLOCK_Usb = 115, /*!< Clock LPCG USB. */ + kCLOCK_Cdog = 116, /*!< Clock LPCG CDOG. */ + kCLOCK_Usdhc1 = 117, /*!< Clock LPCG USDHC1. */ + kCLOCK_Usdhc2 = 118, /*!< Clock LPCG USDHC2. */ + kCLOCK_Asrc = 119, /*!< Clock LPCG ASRC. */ + kCLOCK_Mqs = 120, /*!< Clock LPCG MQS. */ + kCLOCK_Pdm = 121, /*!< Clock LPCG PDM. */ + kCLOCK_Spdif = 122, /*!< Clock LPCG SPDIF. */ + kCLOCK_Sai1 = 123, /*!< Clock LPCG SAI1. */ + kCLOCK_Sai2 = 124, /*!< Clock LPCG SAI2. */ + kCLOCK_Sai3 = 125, /*!< Clock LPCG SAI3. */ + kCLOCK_Sai4 = 126, /*!< Clock LPCG SAI4. */ + kCLOCK_Pxp = 127, /*!< Clock LPCG PXP. */ + kCLOCK_Gpu2d = 128, /*!< Clock LPCG GPU2D. */ + kCLOCK_Lcdif = 129, /*!< Clock LPCG LCDIF. */ + kCLOCK_Lcdifv2 = 130, /*!< Clock LPCG LCDIFV2. */ + kCLOCK_Mipi_Dsi = 131, /*!< Clock LPCG MIPI DSI. */ + kCLOCK_Mipi_Csi = 132, /*!< Clock LPCG MIPI CSI. */ + kCLOCK_Csi = 133, /*!< Clock LPCG CSI. */ + kCLOCK_Dcic_Mipi = 134, /*!< Clock LPCG DCIC MIPI. */ + kCLOCK_Dcic_Lcd = 135, /*!< Clock LPCG DCIC LCD. */ + kCLOCK_Video_Mux = 136, /*!< Clock LPCG VIDEO MUX. */ + kCLOCK_Uniq_Edt_I = 137, /*!< Clock LPCG Uniq_Edt_I. */ + + kCLOCK_IpInvalid, /*!< Invalid value. */ +} clock_lpcg_t; + +/*! + * @brief Clock name. + */ +typedef enum _clock_name +{ + kCLOCK_OscRc16M = 0, /*!< 16MHz RC Oscillator. */ + kCLOCK_OscRc48M = 1, /*!< 48MHz RC Oscillator. */ + kCLOCK_OscRc48MDiv2 = 2, /*!< 48MHz RC Oscillator Div2. */ + kCLOCK_OscRc400M = 3, /*!< 400MHz RC Oscillator. */ + kCLOCK_Osc24M = 4, /*!< 24MHz Oscillator. */ + kCLOCK_Osc24MOut = 5, /*!< 48MHz Oscillator Out. */ + kCLOCK_ArmPll = 6, /*!< ARM PLL. */ + kCLOCK_ArmPllOut = 7, /*!< ARM PLL Out. */ + kCLOCK_SysPll2 = 8, /*!< SYS PLL2. */ + kCLOCK_SysPll2Out = 9, /*!< SYS PLL2 OUT. */ + kCLOCK_SysPll2Pfd0 = 10, /*!< SYS PLL2 PFD0. */ + kCLOCK_SysPll2Pfd1 = 11, /*!< SYS PLL2 PFD1. */ + kCLOCK_SysPll2Pfd2 = 12, /*!< SYS PLL2 PFD2. */ + kCLOCK_SysPll2Pfd3 = 13, /*!< SYS PLL2 PFD3. */ + kCLOCK_SysPll3 = 14, /*!< SYS PLL3. */ + kCLOCK_SysPll3Out = 15, /*!< SYS PLL3 OUT. */ + kCLOCK_SysPll3Div2 = 16, /*!< SYS PLL3 DIV2 */ + kCLOCK_SysPll3Pfd0 = 17, /*!< SYS PLL3 PFD0. */ + kCLOCK_SysPll3Pfd1 = 18, /*!< SYS PLL3 PFD1 */ + kCLOCK_SysPll3Pfd2 = 19, /*!< SYS PLL3 PFD2 */ + kCLOCK_SysPll3Pfd3 = 20, /*!< SYS PLL3 PFD3 */ + kCLOCK_SysPll1 = 21, /*!< SYS PLL1. */ + kCLOCK_SysPll1Out = 22, /*!< SYS PLL1 OUT. */ + kCLOCK_SysPll1Div2 = 23, /*!< SYS PLL1 DIV2. */ + kCLOCK_SysPll1Div5 = 24, /*!< SYS PLL1 DIV5. */ + kCLOCK_AudioPll = 25, /*!< SYS AUDIO PLL. */ + kCLOCK_AudioPllOut = 26, /*!< SYS AUDIO PLL OUT. */ + kCLOCK_VideoPll = 27, /*!< SYS VIDEO PLL. */ + kCLOCK_VideoPllOut = 28, /*!< SYS VIDEO PLL OUT. */ + kCLOCK_CpuClk, /*!< SYS CPU CLK. */ + kCLOCK_CoreSysClk, /*!< SYS CORE SYS CLK. */ + kCLOCK_Reserved = 0xFFU, /*!< Reserved. */ +} clock_name_t; + +/* Clock OBSERVE SIGNALS */ +#define CCM_OBS_M7_CLK_ROOT 128, 4 +#define CCM_OBS_M4_CLK_ROOT 129, 0 +#define CCM_OBS_BUS_CLK_ROOT 130, 2 +#define CCM_OBS_BUS_LPSR_CLK_ROOT 131, 0 +#define CCM_OBS_SEMC_CLK_ROOT 132, 2 +#define CCM_OBS_CSSYS_CLK_ROOT 133, 2 +#define CCM_OBS_CSTRACE_CLK_ROOT 134, 2 +#define CCM_OBS_M4_SYSTICK_CLK_ROOT 135, 0 +#define CCM_OBS_M7_SYSTICK_CLK_ROOT 136, 2 +#define CCM_OBS_ADC1_CLK_ROOT 137, 2 +#define CCM_OBS_ADC2_CLK_ROOT 138, 2 +#define CCM_OBS_ACMP_CLK_ROOT 139, 2 +#define CCM_OBS_FLEXIO1_CLK_ROOT 140, 2 +#define CCM_OBS_FLEXIO2_CLK_ROOT 141, 2 +#define CCM_OBS_GPT1_CLK_ROOT 142, 2 +#define CCM_OBS_GPT2_CLK_ROOT 143, 2 +#define CCM_OBS_GPT3_CLK_ROOT 144, 2 +#define CCM_OBS_GPT4_CLK_ROOT 145, 2 +#define CCM_OBS_GPT5_CLK_ROOT 146, 2 +#define CCM_OBS_GPT6_CLK_ROOT 147, 2 +#define CCM_OBS_FLEXSPI1_CLK_ROOT 148, 2 +#define CCM_OBS_FLEXSPI2_CLK_ROOT 149, 2 +#define CCM_OBS_CAN1_CLK_ROOT 150, 2 +#define CCM_OBS_CAN2_CLK_ROOT 151, 2 +#define CCM_OBS_CAN3_CLK_ROOT 152, 0 +#define CCM_OBS_LPUART1_CLK_ROOT 153, 2 +#define CCM_OBS_LPUART2_CLK_ROOT 154, 2 +#define CCM_OBS_LPUART3_CLK_ROOT 155, 2 +#define CCM_OBS_LPUART4_CLK_ROOT 156, 2 +#define CCM_OBS_LPUART5_CLK_ROOT 157, 2 +#define CCM_OBS_LPUART6_CLK_ROOT 158, 2 +#define CCM_OBS_LPUART7_CLK_ROOT 159, 2 +#define CCM_OBS_LPUART8_CLK_ROOT 160, 2 +#define CCM_OBS_LPUART9_CLK_ROOT 161, 2 +#define CCM_OBS_LPUART10_CLK_ROOT 162, 2 +#define CCM_OBS_LPUART11_CLK_ROOT 163, 0 +#define CCM_OBS_LPUART12_CLK_ROOT 164, 0 +#define CCM_OBS_LPI2C1_CLK_ROOT 165, 2 +#define CCM_OBS_LPI2C2_CLK_ROOT 166, 2 +#define CCM_OBS_LPI2C3_CLK_ROOT 167, 2 +#define CCM_OBS_LPI2C4_CLK_ROOT 168, 2 +#define CCM_OBS_LPI2C5_CLK_ROOT 169, 0 +#define CCM_OBS_LPI2C6_CLK_ROOT 170, 0 +#define CCM_OBS_LPSPI1_CLK_ROOT 171, 2 +#define CCM_OBS_LPSPI2_CLK_ROOT 172, 2 +#define CCM_OBS_LPSPI3_CLK_ROOT 173, 2 +#define CCM_OBS_LPSPI4_CLK_ROOT 174, 2 +#define CCM_OBS_LPSPI5_CLK_ROOT 175, 0 +#define CCM_OBS_LPSPI6_CLK_ROOT 176, 0 +#define CCM_OBS_EMV1_CLK_ROOT 177, 2 +#define CCM_OBS_EMV2_CLK_ROOT 178, 2 +#define CCM_OBS_ENET1_CLK_ROOT 179, 2 +#define CCM_OBS_ENET2_CLK_ROOT 180, 2 +#define CCM_OBS_ENET_25M_CLK_ROOT 182, 2 +#define CCM_OBS_ENET_TIMER1_CLK_ROOT 183, 2 +#define CCM_OBS_ENET_TIMER2_CLK_ROOT 184, 2 +#define CCM_OBS_USDHC1_CLK_ROOT 186, 2 +#define CCM_OBS_USDHC2_CLK_ROOT 187, 2 +#define CCM_OBS_ASRC_CLK_ROOT 188, 2 +#define CCM_OBS_MQS_CLK_ROOT 189, 2 +#define CCM_OBS_MIC_CLK_ROOT 190, 0 +#define CCM_OBS_SPDIF_CLK_ROOT 191, 2 +#define CCM_OBS_SAI1_CLK_ROOT 192, 2 +#define CCM_OBS_SAI2_CLK_ROOT 193, 2 +#define CCM_OBS_SAI3_CLK_ROOT 194, 2 +#define CCM_OBS_SAI4_CLK_ROOT 195, 0 +#define CCM_OBS_GC355_CLK_ROOT 196, 2 +#define CCM_OBS_LCDIF_CLK_ROOT 197, 2 +#define CCM_OBS_LCDIFV2_CLK_ROOT 198, 2 +#define CCM_OBS_MIPI_REF_CLK_ROOT 199, 2 +#define CCM_OBS_MIPI_ESC_CLK_ROOT 200, 2 +#define CCM_OBS_CSI2_CLK_ROOT 201, 2 +#define CCM_OBS_CSI2_ESC_CLK_ROOT 202, 2 +#define CCM_OBS_CSI2_UI_CLK_ROOT 203, 2 +#define CCM_OBS_CSI_CLK_ROOT 204, 2 +#define CCM_OBS_CCM_CKO1_CLK_ROOT 205, 0 +#define CCM_OBS_CCM_CKO2_CLK_ROOT 206, 2 +#define CCM_OBS_CM7_CORE_STCLKEN 207, 4 +#define CCM_OBS_CCM_FLEXRAM_CLK_ROOT 208, 4 +#define CCM_OBS_MIPI_DSI_TXESC 209, 2 +#define CCM_OBS_MIPI_DSI_RXESC 210, 2 +#define CCM_OBS_OSC_RC_16M 224, 0 +#define CCM_OBS_OSC_RC_48M 225, 0 +#define CCM_OBS_OSC_RC_48M_DIV2 226, 0 +#define CCM_OBS_OSC_RC_400M 227, 0 +#define CCM_OBS_OSC_24M_OUT 229, 0 +#define CCM_OBS_ARM_PLL_OUT 231, 2 +#define CCM_OBS_SYS_PLL2_OUT 233, 2 +#define CCM_OBS_SYS_PLL2_PFD0 234, 2 +#define CCM_OBS_SYS_PLL2_PFD1 235, 2 +#define CCM_OBS_SYS_PLL2_PFD2 236, 2 +#define CCM_OBS_SYS_PLL2_PFD3 237, 2 +#define CCM_OBS_SYS_PLL3_OUT 239, 2 +#define CCM_OBS_SYS_PLL3_DIV2 240, 2 +#define CCM_OBS_SYS_PLL3_PFD0 241, 2 +#define CCM_OBS_SYS_PLL3_PFD1 242, 2 +#define CCM_OBS_SYS_PLL3_PFD2 243, 2 +#define CCM_OBS_SYS_PLL3_PFD3 244, 2 +#define CCM_OBS_SYS_PLL1_OUT 246, 2 +#define CCM_OBS_SYS_PLL1_DIV2 247, 2 +#define CCM_OBS_SYS_PLL1_DIV5 248, 2 +#define CCM_OBS_PLL_AUDIO_OUT 250, 2 +#define CCM_OBS_PLL_VIDEO_OUT 252, 2 + +#define CCM_OBS_DIV 3 + +/* Clock Source Definitions */ +/* clang-format off */ +static const clock_name_t s_clockSourceName[][8] = { + /*SRC0, SRC1, SRC2, SRC3, SRC4, SRC5, SRC6, SRC7, name index */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_ArmPllOut, kCLOCK_Reserved, kCLOCK_SysPll3Out, kCLOCK_Reserved}, /* M7 0 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd3, kCLOCK_SysPll3Out, kCLOCK_SysPll2Out, kCLOCK_SysPll1Div5}, /* M4 1 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Out, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3}, /* BUS 2 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd3, kCLOCK_SysPll3Out, kCLOCK_SysPll2Out, kCLOCK_SysPll1Div5}, /* BUS_LPSR 3 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd1, kCLOCK_SysPll3Pfd0}, /* SEMC 4 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3}, /* CSSYS 5 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Pfd1, kCLOCK_SysPll2Out}, /* CSTRACE 6 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd3, kCLOCK_SysPll3Out, kCLOCK_SysPll2Pfd0, kCLOCK_SysPll1Div5}, /* M4_SYSTICK 7 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Out, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Pfd0}, /* M7_SYSTICK 8 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3}, /* ADC1 9 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3}, /* ADC2 10 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Out, kCLOCK_SysPll1Div5, kCLOCK_AudioPllOut, kCLOCK_SysPll2Pfd3}, /* ACMP 11 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3}, /* FLEXIO1 12 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3}, /* FLEXIO2 13 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll3Pfd3}, /* GPT1 14 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_AudioPllOut, kCLOCK_VideoPllOut}, /* GPT2 15 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_AudioPllOut, kCLOCK_VideoPllOut}, /* GPT3 16 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll3Pfd3}, /* GPT4 17 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll3Pfd3}, /* GPT5 18 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll3Pfd3}, /* GPT6 19 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd0, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd2, kCLOCK_SysPll3Out}, /* FLEXSPI1 20 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd0, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd2, kCLOCK_SysPll3Out}, /* FLEXSPI2 21 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3}, /* CAN1 22 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3}, /* CAN2 23 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd3, kCLOCK_SysPll3Out, kCLOCK_SysPll2Pfd3, kCLOCK_SysPll1Div5}, /* CAN3 24 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3}, /* LPUART1 25 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3}, /* LPUART2 26 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3}, /* LPUART3 27 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3}, /* LPUART4 28 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3}, /* LPUART5 29 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3}, /* LPUART6 30 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3}, /* LPUART7 31 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3}, /* LPUART8 32 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3}, /* LPUART9 33 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3}, /* LPUART10 34 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd3, kCLOCK_SysPll3Out, kCLOCK_SysPll2Pfd3, kCLOCK_SysPll1Div5}, /* LPUART11 35 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd3, kCLOCK_SysPll3Out, kCLOCK_SysPll2Pfd3, kCLOCK_SysPll1Div5}, /* LPUART12 36 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3}, /* LPI2C1 37 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3}, /* LPI2C2 38 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3}, /* LPI2C3 39 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3}, /* LPI2C4 40 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd3, kCLOCK_SysPll3Out, kCLOCK_SysPll2Pfd3, kCLOCK_SysPll1Div5}, /* LPI2C5 41 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd3, kCLOCK_SysPll3Out, kCLOCK_SysPll2Pfd3, kCLOCK_SysPll1Div5}, /* LPI2C6 42 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3}, /* LPSPI1 43 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3}, /* LPSPI2 44 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3}, /* LPSPI3 45 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3}, /* LPSPI4 46 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd3, kCLOCK_SysPll3Out, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll1Div5}, /* LPSPI5 47 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd3, kCLOCK_SysPll3Out, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll1Div5}, /* LPSPI6 48 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3}, /* EMV1 49 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Div2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3}, /* EMV2 50 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll1Div2, kCLOCK_AudioPllOut, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Pfd1}, /* ENET1 51 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll1Div2, kCLOCK_AudioPllOut, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Pfd1}, /* ENET2 52 */ \ + {kCLOCK_Reserved, kCLOCK_Reserved, kCLOCK_Reserved, kCLOCK_Reserved, kCLOCK_Reserved, kCLOCK_Reserved, kCLOCK_Reserved, kCLOCK_Reserved}, /* RESERVED 53 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll1Div2, kCLOCK_AudioPllOut, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Pfd1}, /* ENET_25M 54 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll1Div2, kCLOCK_AudioPllOut, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Pfd1}, /* ENET_TIMER1 55 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll1Div2, kCLOCK_AudioPllOut, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Pfd1}, /* ENET_TIMER2 56 */ \ + {kCLOCK_Reserved, kCLOCK_Reserved, kCLOCK_Reserved, kCLOCK_Reserved, kCLOCK_Reserved, kCLOCK_Reserved, kCLOCK_Reserved, kCLOCK_Reserved}, /* RESERVED 57 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Pfd2, kCLOCK_SysPll2Pfd0, kCLOCK_SysPll1Div5, kCLOCK_ArmPllOut}, /* USDHC1 58 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Pfd2, kCLOCK_SysPll2Pfd0, kCLOCK_SysPll1Div5, kCLOCK_ArmPllOut}, /* USDHC2 59 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll1Div5, kCLOCK_SysPll3Div2, kCLOCK_AudioPllOut, kCLOCK_SysPll2Pfd3}, /* ASRC 60 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll1Div5, kCLOCK_SysPll3Div2, kCLOCK_AudioPllOut, kCLOCK_SysPll2Pfd3}, /* MQS 61 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd3, kCLOCK_SysPll3Out, kCLOCK_AudioPllOut, kCLOCK_SysPll1Div5}, /* MIC 62 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_AudioPllOut, kCLOCK_SysPll3Out, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll2Pfd3}, /* SPDIF 63 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_AudioPllOut, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Pfd3}, /* SAI1 64 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_AudioPllOut, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Pfd3}, /* SAI2 65 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_AudioPllOut, kCLOCK_SysPll3Pfd2, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Pfd3}, /* SAI3 66 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd3, kCLOCK_SysPll3Out, kCLOCK_AudioPllOut, kCLOCK_SysPll1Div5}, /* SAI4 67 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd1, kCLOCK_SysPll3Out, kCLOCK_VideoPllOut}, /* GC355 68 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd2, kCLOCK_SysPll3Pfd0, kCLOCK_VideoPllOut}, /* LCDIF 69 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd2, kCLOCK_SysPll3Pfd0, kCLOCK_VideoPllOut}, /* LCDIFV2 70 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd0, kCLOCK_SysPll3Pfd0, kCLOCK_VideoPllOut}, /* MIPI_REF 71 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd0, kCLOCK_SysPll3Pfd0, kCLOCK_VideoPllOut}, /* MIPI_ESC 72 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Pfd2, kCLOCK_SysPll3Out, kCLOCK_SysPll2Pfd0, kCLOCK_VideoPllOut}, /* CSI2 73 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Pfd2, kCLOCK_SysPll3Out, kCLOCK_SysPll2Pfd0, kCLOCK_VideoPllOut}, /* CSI2_ESC 74 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Pfd2, kCLOCK_SysPll3Out, kCLOCK_SysPll2Pfd0, kCLOCK_VideoPllOut}, /* CSI2_UI 75 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Pfd2, kCLOCK_SysPll3Out, kCLOCK_SysPll3Pfd1, kCLOCK_VideoPllOut}, /* CSI 76 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Pfd2, kCLOCK_SysPll2Out, kCLOCK_SysPll3Pfd1, kCLOCK_SysPll1Div5}, /* CKO1 77 */ \ + {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Pfd3, kCLOCK_OscRc48M, kCLOCK_SysPll3Pfd1, kCLOCK_AudioPllOut} /* CKO2 78 */ \ +}; +/* clang-format on */ + +/*! + * @brief Root clock index + * + */ +typedef enum _clock_root +{ + kCLOCK_Root_M7 = 0, /*!< CLOCK Root M7. */ + kCLOCK_Root_M4 = 1, /*!< CLOCK Root M4. */ + kCLOCK_Root_Bus = 2, /*!< CLOCK Root Bus. */ + kCLOCK_Root_Bus_Lpsr = 3, /*!< CLOCK Root Bus Lpsr. */ + kCLOCK_Root_Semc = 4, /*!< CLOCK Root Semc. */ + kCLOCK_Root_Cssys = 5, /*!< CLOCK Root Cssys. */ + kCLOCK_Root_Cstrace = 6, /*!< CLOCK Root Cstrace. */ + kCLOCK_Root_M4_Systick = 7, /*!< CLOCK Root M4 Systick. */ + kCLOCK_Root_M7_Systick = 8, /*!< CLOCK Root M7 Systick. */ + kCLOCK_Root_Adc1 = 9, /*!< CLOCK Root Adc1. */ + kCLOCK_Root_Adc2 = 10, /*!< CLOCK Root Adc2. */ + kCLOCK_Root_Acmp = 11, /*!< CLOCK Root Acmp. */ + kCLOCK_Root_Flexio1 = 12, /*!< CLOCK Root Flexio1. */ + kCLOCK_Root_Flexio2 = 13, /*!< CLOCK Root Flexio2. */ + kCLOCK_Root_Gpt1 = 14, /*!< CLOCK Root Gpt1. */ + kCLOCK_Root_Gpt2 = 15, /*!< CLOCK Root Gpt2. */ + kCLOCK_Root_Gpt3 = 16, /*!< CLOCK Root Gpt3. */ + kCLOCK_Root_Gpt4 = 17, /*!< CLOCK Root Gpt4. */ + kCLOCK_Root_Gpt5 = 18, /*!< CLOCK Root Gpt5. */ + kCLOCK_Root_Gpt6 = 19, /*!< CLOCK Root Gpt6. */ + kCLOCK_Root_Flexspi1 = 20, /*!< CLOCK Root Flexspi1. */ + kCLOCK_Root_Flexspi2 = 21, /*!< CLOCK Root Flexspi2. */ + kCLOCK_Root_Can1 = 22, /*!< CLOCK Root Can1. */ + kCLOCK_Root_Can2 = 23, /*!< CLOCK Root Can2. */ + kCLOCK_Root_Can3 = 24, /*!< CLOCK Root Can3. */ + kCLOCK_Root_Lpuart1 = 25, /*!< CLOCK Root Lpuart1. */ + kCLOCK_Root_Lpuart2 = 26, /*!< CLOCK Root Lpuart2. */ + kCLOCK_Root_Lpuart3 = 27, /*!< CLOCK Root Lpuart3. */ + kCLOCK_Root_Lpuart4 = 28, /*!< CLOCK Root Lpuart4. */ + kCLOCK_Root_Lpuart5 = 29, /*!< CLOCK Root Lpuart5. */ + kCLOCK_Root_Lpuart6 = 30, /*!< CLOCK Root Lpuart6. */ + kCLOCK_Root_Lpuart7 = 31, /*!< CLOCK Root Lpuart7. */ + kCLOCK_Root_Lpuart8 = 32, /*!< CLOCK Root Lpuart8. */ + kCLOCK_Root_Lpuart9 = 33, /*!< CLOCK Root Lpuart9. */ + kCLOCK_Root_Lpuart10 = 34, /*!< CLOCK Root Lpuart10. */ + kCLOCK_Root_Lpuart11 = 35, /*!< CLOCK Root Lpuart11. */ + kCLOCK_Root_Lpuart12 = 36, /*!< CLOCK Root Lpuart12. */ + kCLOCK_Root_Lpi2c1 = 37, /*!< CLOCK Root Lpi2c1. */ + kCLOCK_Root_Lpi2c2 = 38, /*!< CLOCK Root Lpi2c2. */ + kCLOCK_Root_Lpi2c3 = 39, /*!< CLOCK Root Lpi2c3. */ + kCLOCK_Root_Lpi2c4 = 40, /*!< CLOCK Root Lpi2c4. */ + kCLOCK_Root_Lpi2c5 = 41, /*!< CLOCK Root Lpi2c5. */ + kCLOCK_Root_Lpi2c6 = 42, /*!< CLOCK Root Lpi2c6. */ + kCLOCK_Root_Lpspi1 = 43, /*!< CLOCK Root Lpspi1. */ + kCLOCK_Root_Lpspi2 = 44, /*!< CLOCK Root Lpspi2. */ + kCLOCK_Root_Lpspi3 = 45, /*!< CLOCK Root Lpspi3. */ + kCLOCK_Root_Lpspi4 = 46, /*!< CLOCK Root Lpspi4. */ + kCLOCK_Root_Lpspi5 = 47, /*!< CLOCK Root Lpspi5. */ + kCLOCK_Root_Lpspi6 = 48, /*!< CLOCK Root Lpspi6. */ + kCLOCK_Root_Emv1 = 49, /*!< CLOCK Root Emv1. */ + kCLOCK_Root_Emv2 = 50, /*!< CLOCK Root Emv2. */ + kCLOCK_Root_Enet1 = 51, /*!< CLOCK Root Enet1. */ + kCLOCK_Root_Enet2 = 52, /*!< CLOCK Root Enet2. */ + kCLOCK_Root_Enet_25m = 54, /*!< CLOCK Root Enet 25M. */ + kCLOCK_Root_Enet_Timer1 = 55, /*!< CLOCK Root Enet Timer1. */ + kCLOCK_Root_Enet_Timer2 = 56, /*!< CLOCK Root Enet Timer2. */ + kCLOCK_Root_Usdhc1 = 58, /*!< CLOCK Root Usdhc1. */ + kCLOCK_Root_Usdhc2 = 59, /*!< CLOCK Root Usdhc2. */ + kCLOCK_Root_Asrc = 60, /*!< CLOCK Root Asrc. */ + kCLOCK_Root_Mqs = 61, /*!< CLOCK Root Mqs. */ + kCLOCK_Root_Mic = 62, /*!< CLOCK Root MIC. */ + kCLOCK_Root_Spdif = 63, /*!< CLOCK Root Spdif */ + kCLOCK_Root_Sai1 = 64, /*!< CLOCK Root Sai1. */ + kCLOCK_Root_Sai2 = 65, /*!< CLOCK Root Sai2. */ + kCLOCK_Root_Sai3 = 66, /*!< CLOCK Root Sai3. */ + kCLOCK_Root_Sai4 = 67, /*!< CLOCK Root Sai4. */ + kCLOCK_Root_Gc355 = 68, /*!< CLOCK Root Gc355. */ + kCLOCK_Root_Lcdif = 69, /*!< CLOCK Root Lcdif. */ + kCLOCK_Root_Lcdifv2 = 70, /*!< CLOCK Root Lcdifv2. */ + kCLOCK_Root_Mipi_Ref = 71, /*!< CLOCK Root Mipi Ref. */ + kCLOCK_Root_Mipi_Esc = 72, /*!< CLOCK Root Mipi Esc. */ + kCLOCK_Root_Csi2 = 73, /*!< CLOCK Root Csi2. */ + kCLOCK_Root_Csi2_Esc = 74, /*!< CLOCK Root Csi2 Esc. */ + kCLOCK_Root_Csi2_Ui = 75, /*!< CLOCK Root Csi2 Ui. */ + kCLOCK_Root_Csi = 76, /*!< CLOCK Root Csi. */ + kCLOCK_Root_Cko1 = 77, /*!< CLOCK Root CKo1. */ + kCLOCK_Root_Cko2 = 78, /*!< CLOCK Root CKo2. */ +} clock_root_t; + +/*! + * @brief The enumerator of clock roots' clock source mux value. + */ +typedef enum _clock_root_mux_source +{ + /* M7 */ + kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< M7 mux from MuxOscRc48MDiv2. */ + kCLOCK_M7_ClockRoot_MuxOsc24MOut = 1U, /*!< M7 mux from MuxOsc24MOut. */ + kCLOCK_M7_ClockRoot_MuxOscRc400M = 2U, /*!< M7 mux from MuxOscRc400M. */ + kCLOCK_M7_ClockRoot_MuxOscRc16M = 3U, /*!< M7 mux from MuxOscRc16M. */ + kCLOCK_M7_ClockRoot_MuxArmPllOut = 4U, /*!< M7 mux from MuxArmPllOut. */ + kCLOCK_M7_ClockRoot_MuxSysPll3Out = 6U, /*!< M7 mux from MuxSysPll3Out. */ + + /* M4 */ + kCLOCK_M4_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< M4 mux from MuxOscRc48MDiv2. */ + kCLOCK_M4_ClockRoot_MuxOsc24MOut = 1U, /*!< M4 mux from MuxOsc24MOut. */ + kCLOCK_M4_ClockRoot_MuxOscRc400M = 2U, /*!< M4 mux from MuxOscRc400M. */ + kCLOCK_M4_ClockRoot_MuxOscRc16M = 3U, /*!< M4 mux from MuxOscRc16M. */ + kCLOCK_M4_ClockRoot_MuxSysPll3Pfd3 = 4U, /*!< M4 mux from MuxSysPll3Pfd3. */ + kCLOCK_M4_ClockRoot_MuxSysPll3Out = 5U, /*!< M4 mux from MuxSysPll3Out. */ + kCLOCK_M4_ClockRoot_MuxSysPll2Out = 6U, /*!< M4 mux from MuxSysPll2Out. */ + kCLOCK_M4_ClockRoot_MuxSysPll1Div5 = 7U, /*!< M4 mux from MuxSysPll1Div5. */ + + /* BUS */ + kCLOCK_BUS_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< BUS mux from MuxOscRc48MDiv2. */ + kCLOCK_BUS_ClockRoot_MuxOsc24MOut = 1U, /*!< BUS mux from MuxOsc24MOut. */ + kCLOCK_BUS_ClockRoot_MuxOscRc400M = 2U, /*!< BUS mux from MuxOscRc400M. */ + kCLOCK_BUS_ClockRoot_MuxOscRc16M = 3U, /*!< BUS mux from MuxOscRc16M. */ + kCLOCK_BUS_ClockRoot_MuxSysPll3Out = 4U, /*!< BUS mux from MuxSysPll3Out. */ + kCLOCK_BUS_ClockRoot_MuxSysPll1Div5 = 5U, /*!< BUS mux from MuxSysPll1Div5. */ + kCLOCK_BUS_ClockRoot_MuxSysPll2Out = 6U, /*!< BUS mux from MuxSysPll2Out. */ + kCLOCK_BUS_ClockRoot_MuxSysPll2Pfd3 = 7U, /*!< BUS mux from MuxSysPll2Pfd3. */ + + /* BUS_LPSR */ + kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< BUS_LPSR mux from MuxOscRc48MDiv2. */ + kCLOCK_BUS_LPSR_ClockRoot_MuxOsc24MOut = 1U, /*!< BUS_LPSR mux from MuxOsc24MOut. */ + kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc400M = 2U, /*!< BUS_LPSR mux from MuxOscRc400M. */ + kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc16M = 3U, /*!< BUS_LPSR mux from MuxOscRc16M. */ + kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Pfd3 = 4U, /*!< BUS_LPSR mux from MuxSysPll3Pfd3. */ + kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out = 5U, /*!< BUS_LPSR mux from MuxSysPll3Out. */ + kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll2Out = 6U, /*!< BUS_LPSR mux from MuxSysPll2Out. */ + kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll1Div5 = 7U, /*!< BUS_LPSR mux from MuxSysPll1Div5. */ + + /* SEMC */ + kCLOCK_SEMC_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< SEMC mux from MuxOscRc48MDiv2. */ + kCLOCK_SEMC_ClockRoot_MuxOsc24MOut = 1U, /*!< SEMC mux from MuxOsc24MOut. */ + kCLOCK_SEMC_ClockRoot_MuxOscRc400M = 2U, /*!< SEMC mux from MuxOscRc400M. */ + kCLOCK_SEMC_ClockRoot_MuxOscRc16M = 3U, /*!< SEMC mux from MuxOscRc16M. */ + kCLOCK_SEMC_ClockRoot_MuxSysPll1Div5 = 4U, /*!< SEMC mux from MuxSysPll1Div5. */ + kCLOCK_SEMC_ClockRoot_MuxSysPll2Out = 5U, /*!< SEMC mux from MuxSysPll2Out. */ + kCLOCK_SEMC_ClockRoot_MuxSysPll2Pfd1 = 6U, /*!< SEMC mux from MuxSysPll2Pfd1. */ + kCLOCK_SEMC_ClockRoot_MuxSysPll3Pfd0 = 7U, /*!< SEMC mux from MuxSysPll3Pfd0. */ + + /* CSSYS */ + kCLOCK_CSSYS_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< CSSYS mux from MuxOscRc48MDiv2. */ + kCLOCK_CSSYS_ClockRoot_MuxOsc24MOut = 1U, /*!< CSSYS mux from MuxOsc24MOut. */ + kCLOCK_CSSYS_ClockRoot_MuxOscRc400M = 2U, /*!< CSSYS mux from MuxOscRc400M. */ + kCLOCK_CSSYS_ClockRoot_MuxOscRc16M = 3U, /*!< CSSYS mux from MuxOscRc16M. */ + kCLOCK_CSSYS_ClockRoot_MuxSysPll3Div2 = 4U, /*!< CSSYS mux from MuxSysPll3Div2. */ + kCLOCK_CSSYS_ClockRoot_MuxSysPll1Div5 = 5U, /*!< CSSYS mux from MuxSysPll1Div5. */ + kCLOCK_CSSYS_ClockRoot_MuxSysPll2Out = 6U, /*!< CSSYS mux from MuxSysPll2Out. */ + kCLOCK_CSSYS_ClockRoot_MuxSysPll2Pfd3 = 7U, /*!< CSSYS mux from MuxSysPll2Pfd3. */ + + /* CSTRACE */ + kCLOCK_CSTRACE_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< CSTRACE mux from MuxOscRc48MDiv2. */ + kCLOCK_CSTRACE_ClockRoot_MuxOsc24MOut = 1U, /*!< CSTRACE mux from MuxOsc24MOut. */ + kCLOCK_CSTRACE_ClockRoot_MuxOscRc400M = 2U, /*!< CSTRACE mux from MuxOscRc400M. */ + kCLOCK_CSTRACE_ClockRoot_MuxOscRc16M = 3U, /*!< CSTRACE mux from MuxOscRc16M. */ + kCLOCK_CSTRACE_ClockRoot_MuxSysPll3Div2 = 4U, /*!< CSTRACE mux from MuxSysPll3Div2. */ + kCLOCK_CSTRACE_ClockRoot_MuxSysPll1Div5 = 5U, /*!< CSTRACE mux from MuxSysPll1Div5. */ + kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Pfd1 = 6U, /*!< CSTRACE mux from MuxSysPll2Pfd1. */ + kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Out = 7U, /*!< CSTRACE mux from MuxSysPll2Out. */ + + /* M4_SYSTICK */ + kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< M4_SYSTICK mux from MuxOscRc48MDiv2. */ + kCLOCK_M4_SYSTICK_ClockRoot_MuxOsc24MOut = 1U, /*!< M4_SYSTICK mux from MuxOsc24MOut. */ + kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc400M = 2U, /*!< M4_SYSTICK mux from MuxOscRc400M. */ + kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc16M = 3U, /*!< M4_SYSTICK mux from MuxOscRc16M. */ + kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll3Pfd3 = 4U, /*!< M4_SYSTICK mux from MuxSysPll3Pfd3. */ + kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll3Out = 5U, /*!< M4_SYSTICK mux from MuxSysPll3Out. */ + kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll2Pfd0 = 6U, /*!< M4_SYSTICK mux from MuxSysPll2Pfd0. */ + kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll1Div5 = 7U, /*!< M4_SYSTICK mux from MuxSysPll1Div5. */ + + /* M7_SYSTICK */ + kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< M7_SYSTICK mux from MuxOscRc48MDiv2. */ + kCLOCK_M7_SYSTICK_ClockRoot_MuxOsc24MOut = 1U, /*!< M7_SYSTICK mux from MuxOsc24MOut. */ + kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc400M = 2U, /*!< M7_SYSTICK mux from MuxOscRc400M. */ + kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc16M = 3U, /*!< M7_SYSTICK mux from MuxOscRc16M. */ + kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll2Out = 4U, /*!< M7_SYSTICK mux from MuxSysPll2Out. */ + kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll3Div2 = 5U, /*!< M7_SYSTICK mux from MuxSysPll3Div2. */ + kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll1Div5 = 6U, /*!< M7_SYSTICK mux from MuxSysPll1Div5. */ + kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll2Pfd0 = 7U, /*!< M7_SYSTICK mux from MuxSysPll2Pfd0. */ + + /* ADC1 */ + kCLOCK_ADC1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< ADC1 mux from MuxOscRc48MDiv2. */ + kCLOCK_ADC1_ClockRoot_MuxOsc24MOut = 1U, /*!< ADC1 mux from MuxOsc24MOut. */ + kCLOCK_ADC1_ClockRoot_MuxOscRc400M = 2U, /*!< ADC1 mux from MuxOscRc400M. */ + kCLOCK_ADC1_ClockRoot_MuxOscRc16M = 3U, /*!< ADC1 mux from MuxOscRc16M. */ + kCLOCK_ADC1_ClockRoot_MuxSysPll3Div2 = 4U, /*!< ADC1 mux from MuxSysPll3Div2. */ + kCLOCK_ADC1_ClockRoot_MuxSysPll1Div5 = 5U, /*!< ADC1 mux from MuxSysPll1Div5. */ + kCLOCK_ADC1_ClockRoot_MuxSysPll2Out = 6U, /*!< ADC1 mux from MuxSysPll2Out. */ + kCLOCK_ADC1_ClockRoot_MuxSysPll2Pfd3 = 7U, /*!< ADC1 mux from MuxSysPll2Pfd3. */ + + /* ADC2 */ + kCLOCK_ADC2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< ADC2 mux from MuxOscRc48MDiv2. */ + kCLOCK_ADC2_ClockRoot_MuxOsc24MOut = 1U, /*!< ADC2 mux from MuxOsc24MOut. */ + kCLOCK_ADC2_ClockRoot_MuxOscRc400M = 2U, /*!< ADC2 mux from MuxOscRc400M. */ + kCLOCK_ADC2_ClockRoot_MuxOscRc16M = 3U, /*!< ADC2 mux from MuxOscRc16M. */ + kCLOCK_ADC2_ClockRoot_MuxSysPll3Div2 = 4U, /*!< ADC2 mux from MuxSysPll3Div2. */ + kCLOCK_ADC2_ClockRoot_MuxSysPll1Div5 = 5U, /*!< ADC2 mux from MuxSysPll1Div5. */ + kCLOCK_ADC2_ClockRoot_MuxSysPll2Out = 6U, /*!< ADC2 mux from MuxSysPll2Out. */ + kCLOCK_ADC2_ClockRoot_MuxSysPll2Pfd3 = 7U, /*!< ADC2 mux from MuxSysPll2Pfd3. */ + + /* ACMP */ + kCLOCK_ACMP_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< ACMP mux from MuxOscRc48MDiv2. */ + kCLOCK_ACMP_ClockRoot_MuxOsc24MOut = 1U, /*!< ACMP mux from MuxOsc24MOut. */ + kCLOCK_ACMP_ClockRoot_MuxOscRc400M = 2U, /*!< ACMP mux from MuxOscRc400M. */ + kCLOCK_ACMP_ClockRoot_MuxOscRc16M = 3U, /*!< ACMP mux from MuxOscRc16M. */ + kCLOCK_ACMP_ClockRoot_MuxSysPll3Out = 4U, /*!< ACMP mux from MuxSysPll3Out. */ + kCLOCK_ACMP_ClockRoot_MuxSysPll1Div5 = 5U, /*!< ACMP mux from MuxSysPll1Div5. */ + kCLOCK_ACMP_ClockRoot_MuxAudioPllOut = 6U, /*!< ACMP mux from MuxAudioPllOut. */ + kCLOCK_ACMP_ClockRoot_MuxSysPll2Pfd3 = 7U, /*!< ACMP mux from MuxSysPll2Pfd3. */ + + /* FLEXIO1 */ + kCLOCK_FLEXIO1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< FLEXIO1 mux from MuxOscRc48MDiv2. */ + kCLOCK_FLEXIO1_ClockRoot_MuxOsc24MOut = 1U, /*!< FLEXIO1 mux from MuxOsc24MOut. */ + kCLOCK_FLEXIO1_ClockRoot_MuxOscRc400M = 2U, /*!< FLEXIO1 mux from MuxOscRc400M. */ + kCLOCK_FLEXIO1_ClockRoot_MuxOscRc16M = 3U, /*!< FLEXIO1 mux from MuxOscRc16M. */ + kCLOCK_FLEXIO1_ClockRoot_MuxSysPll3Div2 = 4U, /*!< FLEXIO1 mux from MuxSysPll3Div2. */ + kCLOCK_FLEXIO1_ClockRoot_MuxSysPll1Div5 = 5U, /*!< FLEXIO1 mux from MuxSysPll1Div5. */ + kCLOCK_FLEXIO1_ClockRoot_MuxSysPll2Out = 6U, /*!< FLEXIO1 mux from MuxSysPll2Out. */ + kCLOCK_FLEXIO1_ClockRoot_MuxSysPll2Pfd3 = 7U, /*!< FLEXIO1 mux from MuxSysPll2Pfd3. */ + + /* FLEXIO2 */ + kCLOCK_FLEXIO2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< FLEXIO2 mux from MuxOscRc48MDiv2. */ + kCLOCK_FLEXIO2_ClockRoot_MuxOsc24MOut = 1U, /*!< FLEXIO2 mux from MuxOsc24MOut. */ + kCLOCK_FLEXIO2_ClockRoot_MuxOscRc400M = 2U, /*!< FLEXIO2 mux from MuxOscRc400M. */ + kCLOCK_FLEXIO2_ClockRoot_MuxOscRc16M = 3U, /*!< FLEXIO2 mux from MuxOscRc16M. */ + kCLOCK_FLEXIO2_ClockRoot_MuxSysPll3Div2 = 4U, /*!< FLEXIO2 mux from MuxSysPll3Div2. */ + kCLOCK_FLEXIO2_ClockRoot_MuxSysPll1Div5 = 5U, /*!< FLEXIO2 mux from MuxSysPll1Div5. */ + kCLOCK_FLEXIO2_ClockRoot_MuxSysPll2Out = 6U, /*!< FLEXIO2 mux from MuxSysPll2Out. */ + kCLOCK_FLEXIO2_ClockRoot_MuxSysPll2Pfd3 = 7U, /*!< FLEXIO2 mux from MuxSysPll2Pfd3. */ + + /* GPT1 */ + kCLOCK_GPT1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< GPT1 mux from MuxOscRc48MDiv2. */ + kCLOCK_GPT1_ClockRoot_MuxOsc24MOut = 1U, /*!< GPT1 mux from MuxOsc24MOut. */ + kCLOCK_GPT1_ClockRoot_MuxOscRc400M = 2U, /*!< GPT1 mux from MuxOscRc400M. */ + kCLOCK_GPT1_ClockRoot_MuxOscRc16M = 3U, /*!< GPT1 mux from MuxOscRc16M. */ + kCLOCK_GPT1_ClockRoot_MuxSysPll3Div2 = 4U, /*!< GPT1 mux from MuxSysPll3Div2. */ + kCLOCK_GPT1_ClockRoot_MuxSysPll1Div5 = 5U, /*!< GPT1 mux from MuxSysPll1Div5. */ + kCLOCK_GPT1_ClockRoot_MuxSysPll3Pfd2 = 6U, /*!< GPT1 mux from MuxSysPll3Pfd2. */ + kCLOCK_GPT1_ClockRoot_MuxSysPll3Pfd3 = 7U, /*!< GPT1 mux from MuxSysPll3Pfd3. */ + + /* GPT2 */ + kCLOCK_GPT2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< GPT2 mux from MuxOscRc48MDiv2. */ + kCLOCK_GPT2_ClockRoot_MuxOsc24MOut = 1U, /*!< GPT2 mux from MuxOsc24MOut. */ + kCLOCK_GPT2_ClockRoot_MuxOscRc400M = 2U, /*!< GPT2 mux from MuxOscRc400M. */ + kCLOCK_GPT2_ClockRoot_MuxOscRc16M = 3U, /*!< GPT2 mux from MuxOscRc16M. */ + kCLOCK_GPT2_ClockRoot_MuxSysPll3Div2 = 4U, /*!< GPT2 mux from MuxSysPll3Div2. */ + kCLOCK_GPT2_ClockRoot_MuxSysPll1Div5 = 5U, /*!< GPT2 mux from MuxSysPll1Div5. */ + kCLOCK_GPT2_ClockRoot_MuxAudioPllOut = 6U, /*!< GPT2 mux from MuxAudioPllOut. */ + kCLOCK_GPT2_ClockRoot_MuxVideoPllOut = 7U, /*!< GPT2 mux from MuxVideoPllOut. */ + + /* GPT3 */ + kCLOCK_GPT3_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< GPT3 mux from MuxOscRc48MDiv2. */ + kCLOCK_GPT3_ClockRoot_MuxOsc24MOut = 1U, /*!< GPT3 mux from MuxOsc24MOut. */ + kCLOCK_GPT3_ClockRoot_MuxOscRc400M = 2U, /*!< GPT3 mux from MuxOscRc400M. */ + kCLOCK_GPT3_ClockRoot_MuxOscRc16M = 3U, /*!< GPT3 mux from MuxOscRc16M. */ + kCLOCK_GPT3_ClockRoot_MuxSysPll3Div2 = 4U, /*!< GPT3 mux from MuxSysPll3Div2. */ + kCLOCK_GPT3_ClockRoot_MuxSysPll1Div5 = 5U, /*!< GPT3 mux from MuxSysPll1Div5. */ + kCLOCK_GPT3_ClockRoot_MuxAudioPllOut = 6U, /*!< GPT3 mux from MuxAudioPllOut. */ + kCLOCK_GPT3_ClockRoot_MuxVideoPllOut = 7U, /*!< GPT3 mux from MuxVideoPllOut. */ + + /* GPT4 */ + kCLOCK_GPT4_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< GPT4 mux from MuxOscRc48MDiv2. */ + kCLOCK_GPT4_ClockRoot_MuxOsc24MOut = 1U, /*!< GPT4 mux from MuxOsc24MOut. */ + kCLOCK_GPT4_ClockRoot_MuxOscRc400M = 2U, /*!< GPT4 mux from MuxOscRc400M. */ + kCLOCK_GPT4_ClockRoot_MuxOscRc16M = 3U, /*!< GPT4 mux from MuxOscRc16M. */ + kCLOCK_GPT4_ClockRoot_MuxSysPll3Div2 = 4U, /*!< GPT4 mux from MuxSysPll3Div2. */ + kCLOCK_GPT4_ClockRoot_MuxSysPll1Div5 = 5U, /*!< GPT4 mux from MuxSysPll1Div5. */ + kCLOCK_GPT4_ClockRoot_MuxSysPll3Pfd2 = 6U, /*!< GPT4 mux from MuxSysPll3Pfd2. */ + kCLOCK_GPT4_ClockRoot_MuxSysPll3Pfd3 = 7U, /*!< GPT4 mux from MuxSysPll3Pfd3. */ + + /* GPT5 */ + kCLOCK_GPT5_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< GPT5 mux from MuxOscRc48MDiv2. */ + kCLOCK_GPT5_ClockRoot_MuxOsc24MOut = 1U, /*!< GPT5 mux from MuxOsc24MOut. */ + kCLOCK_GPT5_ClockRoot_MuxOscRc400M = 2U, /*!< GPT5 mux from MuxOscRc400M. */ + kCLOCK_GPT5_ClockRoot_MuxOscRc16M = 3U, /*!< GPT5 mux from MuxOscRc16M. */ + kCLOCK_GPT5_ClockRoot_MuxSysPll3Div2 = 4U, /*!< GPT5 mux from MuxSysPll3Div2. */ + kCLOCK_GPT5_ClockRoot_MuxSysPll1Div5 = 5U, /*!< GPT5 mux from MuxSysPll1Div5. */ + kCLOCK_GPT5_ClockRoot_MuxSysPll3Pfd2 = 6U, /*!< GPT5 mux from MuxSysPll3Pfd2. */ + kCLOCK_GPT5_ClockRoot_MuxSysPll3Pfd3 = 7U, /*!< GPT5 mux from MuxSysPll3Pfd3. */ + + /* GPT6 */ + kCLOCK_GPT6_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< GPT6 mux from MuxOscRc48MDiv2. */ + kCLOCK_GPT6_ClockRoot_MuxOsc24MOut = 1U, /*!< GPT6 mux from MuxOsc24MOut. */ + kCLOCK_GPT6_ClockRoot_MuxOscRc400M = 2U, /*!< GPT6 mux from MuxOscRc400M. */ + kCLOCK_GPT6_ClockRoot_MuxOscRc16M = 3U, /*!< GPT6 mux from MuxOscRc16M. */ + kCLOCK_GPT6_ClockRoot_MuxSysPll3Div2 = 4U, /*!< GPT6 mux from MuxSysPll3Div2. */ + kCLOCK_GPT6_ClockRoot_MuxSysPll1Div5 = 5U, /*!< GPT6 mux from MuxSysPll1Div5. */ + kCLOCK_GPT6_ClockRoot_MuxSysPll3Pfd2 = 6U, /*!< GPT6 mux from MuxSysPll3Pfd2. */ + kCLOCK_GPT6_ClockRoot_MuxSysPll3Pfd3 = 7U, /*!< GPT6 mux from MuxSysPll3Pfd3. */ + + /* FLEXSPI1 */ + kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< FLEXSPI1 mux from MuxOscRc48MDiv2. */ + kCLOCK_FLEXSPI1_ClockRoot_MuxOsc24MOut = 1U, /*!< FLEXSPI1 mux from MuxOsc24MOut. */ + kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc400M = 2U, /*!< FLEXSPI1 mux from MuxOscRc400M. */ + kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc16M = 3U, /*!< FLEXSPI1 mux from MuxOscRc16M. */ + kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll3Pfd0 = 4U, /*!< FLEXSPI1 mux from MuxSysPll3Pfd0. */ + kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll2Out = 5U, /*!< FLEXSPI1 mux from MuxSysPll2Out. */ + kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll2Pfd2 = 6U, /*!< FLEXSPI1 mux from MuxSysPll2Pfd2. */ + kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll3Out = 7U, /*!< FLEXSPI1 mux from MuxSysPll3Out. */ + + /* FLEXSPI2 */ + kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< FLEXSPI2 mux from MuxOscRc48MDiv2. */ + kCLOCK_FLEXSPI2_ClockRoot_MuxOsc24MOut = 1U, /*!< FLEXSPI2 mux from MuxOsc24MOut. */ + kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc400M = 2U, /*!< FLEXSPI2 mux from MuxOscRc400M. */ + kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc16M = 3U, /*!< FLEXSPI2 mux from MuxOscRc16M. */ + kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll3Pfd0 = 4U, /*!< FLEXSPI2 mux from MuxSysPll3Pfd0. */ + kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll2Out = 5U, /*!< FLEXSPI2 mux from MuxSysPll2Out. */ + kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll2Pfd2 = 6U, /*!< FLEXSPI2 mux from MuxSysPll2Pfd2. */ + kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll3Out = 7U, /*!< FLEXSPI2 mux from MuxSysPll3Out. */ + + /* CAN1 */ + kCLOCK_CAN1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< CAN1 mux from MuxOscRc48MDiv2. */ + kCLOCK_CAN1_ClockRoot_MuxOsc24MOut = 1U, /*!< CAN1 mux from MuxOsc24MOut. */ + kCLOCK_CAN1_ClockRoot_MuxOscRc400M = 2U, /*!< CAN1 mux from MuxOscRc400M. */ + kCLOCK_CAN1_ClockRoot_MuxOscRc16M = 3U, /*!< CAN1 mux from MuxOscRc16M. */ + kCLOCK_CAN1_ClockRoot_MuxSysPll3Div2 = 4U, /*!< CAN1 mux from MuxSysPll3Div2. */ + kCLOCK_CAN1_ClockRoot_MuxSysPll1Div5 = 5U, /*!< CAN1 mux from MuxSysPll1Div5. */ + kCLOCK_CAN1_ClockRoot_MuxSysPll2Out = 6U, /*!< CAN1 mux from MuxSysPll2Out. */ + kCLOCK_CAN1_ClockRoot_MuxSysPll2Pfd3 = 7U, /*!< CAN1 mux from MuxSysPll2Pfd3. */ + + /* CAN2 */ + kCLOCK_CAN2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< CAN2 mux from MuxOscRc48MDiv2. */ + kCLOCK_CAN2_ClockRoot_MuxOsc24MOut = 1U, /*!< CAN2 mux from MuxOsc24MOut. */ + kCLOCK_CAN2_ClockRoot_MuxOscRc400M = 2U, /*!< CAN2 mux from MuxOscRc400M. */ + kCLOCK_CAN2_ClockRoot_MuxOscRc16M = 3U, /*!< CAN2 mux from MuxOscRc16M. */ + kCLOCK_CAN2_ClockRoot_MuxSysPll3Div2 = 4U, /*!< CAN2 mux from MuxSysPll3Div2. */ + kCLOCK_CAN2_ClockRoot_MuxSysPll1Div5 = 5U, /*!< CAN2 mux from MuxSysPll1Div5. */ + kCLOCK_CAN2_ClockRoot_MuxSysPll2Out = 6U, /*!< CAN2 mux from MuxSysPll2Out. */ + kCLOCK_CAN2_ClockRoot_MuxSysPll2Pfd3 = 7U, /*!< CAN2 mux from MuxSysPll2Pfd3. */ + + /* CAN3 */ + kCLOCK_CAN3_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< CAN3 mux from MuxOscRc48MDiv2. */ + kCLOCK_CAN3_ClockRoot_MuxOsc24MOut = 1U, /*!< CAN3 mux from MuxOsc24MOut. */ + kCLOCK_CAN3_ClockRoot_MuxOscRc400M = 2U, /*!< CAN3 mux from MuxOscRc400M. */ + kCLOCK_CAN3_ClockRoot_MuxOscRc16M = 3U, /*!< CAN3 mux from MuxOscRc16M. */ + kCLOCK_CAN3_ClockRoot_MuxSysPll3Pfd3 = 4U, /*!< CAN3 mux from MuxSysPll3Pfd3. */ + kCLOCK_CAN3_ClockRoot_MuxSysPll3Out = 5U, /*!< CAN3 mux from MuxSysPll3Out. */ + kCLOCK_CAN3_ClockRoot_MuxSysPll2Pfd3 = 6U, /*!< CAN3 mux from MuxSysPll2Pfd3. */ + kCLOCK_CAN3_ClockRoot_MuxSysPll1Div5 = 7U, /*!< CAN3 mux from MuxSysPll1Div5. */ + + /* LPUART1 */ + kCLOCK_LPUART1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPUART1 mux from MuxOscRc48MDiv2. */ + kCLOCK_LPUART1_ClockRoot_MuxOsc24MOut = 1U, /*!< LPUART1 mux from MuxOsc24MOut. */ + kCLOCK_LPUART1_ClockRoot_MuxOscRc400M = 2U, /*!< LPUART1 mux from MuxOscRc400M. */ + kCLOCK_LPUART1_ClockRoot_MuxOscRc16M = 3U, /*!< LPUART1 mux from MuxOscRc16M. */ + kCLOCK_LPUART1_ClockRoot_MuxSysPll3Div2 = 4U, /*!< LPUART1 mux from MuxSysPll3Div2. */ + kCLOCK_LPUART1_ClockRoot_MuxSysPll1Div5 = 5U, /*!< LPUART1 mux from MuxSysPll1Div5. */ + kCLOCK_LPUART1_ClockRoot_MuxSysPll2Out = 6U, /*!< LPUART1 mux from MuxSysPll2Out. */ + kCLOCK_LPUART1_ClockRoot_MuxSysPll2Pfd3 = 7U, /*!< LPUART1 mux from MuxSysPll2Pfd3. */ + + /* LPUART2 */ + kCLOCK_LPUART2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPUART2 mux from MuxOscRc48MDiv2. */ + kCLOCK_LPUART2_ClockRoot_MuxOsc24MOut = 1U, /*!< LPUART2 mux from MuxOsc24MOut. */ + kCLOCK_LPUART2_ClockRoot_MuxOscRc400M = 2U, /*!< LPUART2 mux from MuxOscRc400M. */ + kCLOCK_LPUART2_ClockRoot_MuxOscRc16M = 3U, /*!< LPUART2 mux from MuxOscRc16M. */ + kCLOCK_LPUART2_ClockRoot_MuxSysPll3Div2 = 4U, /*!< LPUART2 mux from MuxSysPll3Div2. */ + kCLOCK_LPUART2_ClockRoot_MuxSysPll1Div5 = 5U, /*!< LPUART2 mux from MuxSysPll1Div5. */ + kCLOCK_LPUART2_ClockRoot_MuxSysPll2Out = 6U, /*!< LPUART2 mux from MuxSysPll2Out. */ + kCLOCK_LPUART2_ClockRoot_MuxSysPll2Pfd3 = 7U, /*!< LPUART2 mux from MuxSysPll2Pfd3. */ + + /* LPUART3 */ + kCLOCK_LPUART3_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPUART3 mux from MuxOscRc48MDiv2. */ + kCLOCK_LPUART3_ClockRoot_MuxOsc24MOut = 1U, /*!< LPUART3 mux from MuxOsc24MOut. */ + kCLOCK_LPUART3_ClockRoot_MuxOscRc400M = 2U, /*!< LPUART3 mux from MuxOscRc400M. */ + kCLOCK_LPUART3_ClockRoot_MuxOscRc16M = 3U, /*!< LPUART3 mux from MuxOscRc16M. */ + kCLOCK_LPUART3_ClockRoot_MuxSysPll3Div2 = 4U, /*!< LPUART3 mux from MuxSysPll3Div2. */ + kCLOCK_LPUART3_ClockRoot_MuxSysPll1Div5 = 5U, /*!< LPUART3 mux from MuxSysPll1Div5. */ + kCLOCK_LPUART3_ClockRoot_MuxSysPll2Out = 6U, /*!< LPUART3 mux from MuxSysPll2Out. */ + kCLOCK_LPUART3_ClockRoot_MuxSysPll2Pfd3 = 7U, /*!< LPUART3 mux from MuxSysPll2Pfd3. */ + + /* LPUART4 */ + kCLOCK_LPUART4_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPUART4 mux from MuxOscRc48MDiv2. */ + kCLOCK_LPUART4_ClockRoot_MuxOsc24MOut = 1U, /*!< LPUART4 mux from MuxOsc24MOut. */ + kCLOCK_LPUART4_ClockRoot_MuxOscRc400M = 2U, /*!< LPUART4 mux from MuxOscRc400M. */ + kCLOCK_LPUART4_ClockRoot_MuxOscRc16M = 3U, /*!< LPUART4 mux from MuxOscRc16M. */ + kCLOCK_LPUART4_ClockRoot_MuxSysPll3Div2 = 4U, /*!< LPUART4 mux from MuxSysPll3Div2. */ + kCLOCK_LPUART4_ClockRoot_MuxSysPll1Div5 = 5U, /*!< LPUART4 mux from MuxSysPll1Div5. */ + kCLOCK_LPUART4_ClockRoot_MuxSysPll2Out = 6U, /*!< LPUART4 mux from MuxSysPll2Out. */ + kCLOCK_LPUART4_ClockRoot_MuxSysPll2Pfd3 = 7U, /*!< LPUART4 mux from MuxSysPll2Pfd3. */ + + /* LPUART5 */ + kCLOCK_LPUART5_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPUART5 mux from MuxOscRc48MDiv2. */ + kCLOCK_LPUART5_ClockRoot_MuxOsc24MOut = 1U, /*!< LPUART5 mux from MuxOsc24MOut. */ + kCLOCK_LPUART5_ClockRoot_MuxOscRc400M = 2U, /*!< LPUART5 mux from MuxOscRc400M. */ + kCLOCK_LPUART5_ClockRoot_MuxOscRc16M = 3U, /*!< LPUART5 mux from MuxOscRc16M. */ + kCLOCK_LPUART5_ClockRoot_MuxSysPll3Div2 = 4U, /*!< LPUART5 mux from MuxSysPll3Div2. */ + kCLOCK_LPUART5_ClockRoot_MuxSysPll1Div5 = 5U, /*!< LPUART5 mux from MuxSysPll1Div5. */ + kCLOCK_LPUART5_ClockRoot_MuxSysPll2Out = 6U, /*!< LPUART5 mux from MuxSysPll2Out. */ + kCLOCK_LPUART5_ClockRoot_MuxSysPll2Pfd3 = 7U, /*!< LPUART5 mux from MuxSysPll2Pfd3. */ + + /* LPUART6 */ + kCLOCK_LPUART6_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPUART6 mux from MuxOscRc48MDiv2. */ + kCLOCK_LPUART6_ClockRoot_MuxOsc24MOut = 1U, /*!< LPUART6 mux from MuxOsc24MOut. */ + kCLOCK_LPUART6_ClockRoot_MuxOscRc400M = 2U, /*!< LPUART6 mux from MuxOscRc400M. */ + kCLOCK_LPUART6_ClockRoot_MuxOscRc16M = 3U, /*!< LPUART6 mux from MuxOscRc16M. */ + kCLOCK_LPUART6_ClockRoot_MuxSysPll3Div2 = 4U, /*!< LPUART6 mux from MuxSysPll3Div2. */ + kCLOCK_LPUART6_ClockRoot_MuxSysPll1Div5 = 5U, /*!< LPUART6 mux from MuxSysPll1Div5. */ + kCLOCK_LPUART6_ClockRoot_MuxSysPll2Out = 6U, /*!< LPUART6 mux from MuxSysPll2Out. */ + kCLOCK_LPUART6_ClockRoot_MuxSysPll2Pfd3 = 7U, /*!< LPUART6 mux from MuxSysPll2Pfd3. */ + + /* LPUART7 */ + kCLOCK_LPUART7_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPUART7 mux from MuxOscRc48MDiv2. */ + kCLOCK_LPUART7_ClockRoot_MuxOsc24MOut = 1U, /*!< LPUART7 mux from MuxOsc24MOut. */ + kCLOCK_LPUART7_ClockRoot_MuxOscRc400M = 2U, /*!< LPUART7 mux from MuxOscRc400M. */ + kCLOCK_LPUART7_ClockRoot_MuxOscRc16M = 3U, /*!< LPUART7 mux from MuxOscRc16M. */ + kCLOCK_LPUART7_ClockRoot_MuxSysPll3Div2 = 4U, /*!< LPUART7 mux from MuxSysPll3Div2. */ + kCLOCK_LPUART7_ClockRoot_MuxSysPll1Div5 = 5U, /*!< LPUART7 mux from MuxSysPll1Div5. */ + kCLOCK_LPUART7_ClockRoot_MuxSysPll2Out = 6U, /*!< LPUART7 mux from MuxSysPll2Out. */ + kCLOCK_LPUART7_ClockRoot_MuxSysPll2Pfd3 = 7U, /*!< LPUART7 mux from MuxSysPll2Pfd3. */ + + /* LPUART8 */ + kCLOCK_LPUART8_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPUART8 mux from MuxOscRc48MDiv2. */ + kCLOCK_LPUART8_ClockRoot_MuxOsc24MOut = 1U, /*!< LPUART8 mux from MuxOsc24MOut. */ + kCLOCK_LPUART8_ClockRoot_MuxOscRc400M = 2U, /*!< LPUART8 mux from MuxOscRc400M. */ + kCLOCK_LPUART8_ClockRoot_MuxOscRc16M = 3U, /*!< LPUART8 mux from MuxOscRc16M. */ + kCLOCK_LPUART8_ClockRoot_MuxSysPll3Div2 = 4U, /*!< LPUART8 mux from MuxSysPll3Div2. */ + kCLOCK_LPUART8_ClockRoot_MuxSysPll1Div5 = 5U, /*!< LPUART8 mux from MuxSysPll1Div5. */ + kCLOCK_LPUART8_ClockRoot_MuxSysPll2Out = 6U, /*!< LPUART8 mux from MuxSysPll2Out. */ + kCLOCK_LPUART8_ClockRoot_MuxSysPll2Pfd3 = 7U, /*!< LPUART8 mux from MuxSysPll2Pfd3. */ + + /* LPUART9 */ + kCLOCK_LPUART9_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPUART9 mux from MuxOscRc48MDiv2. */ + kCLOCK_LPUART9_ClockRoot_MuxOsc24MOut = 1U, /*!< LPUART9 mux from MuxOsc24MOut. */ + kCLOCK_LPUART9_ClockRoot_MuxOscRc400M = 2U, /*!< LPUART9 mux from MuxOscRc400M. */ + kCLOCK_LPUART9_ClockRoot_MuxOscRc16M = 3U, /*!< LPUART9 mux from MuxOscRc16M. */ + kCLOCK_LPUART9_ClockRoot_MuxSysPll3Div2 = 4U, /*!< LPUART9 mux from MuxSysPll3Div2. */ + kCLOCK_LPUART9_ClockRoot_MuxSysPll1Div5 = 5U, /*!< LPUART9 mux from MuxSysPll1Div5. */ + kCLOCK_LPUART9_ClockRoot_MuxSysPll2Out = 6U, /*!< LPUART9 mux from MuxSysPll2Out. */ + kCLOCK_LPUART9_ClockRoot_MuxSysPll2Pfd3 = 7U, /*!< LPUART9 mux from MuxSysPll2Pfd3. */ + + /* LPUART10 */ + kCLOCK_LPUART10_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPUART10 mux from MuxOscRc48MDiv2. */ + kCLOCK_LPUART10_ClockRoot_MuxOsc24MOut = 1U, /*!< LPUART10 mux from MuxOsc24MOut. */ + kCLOCK_LPUART10_ClockRoot_MuxOscRc400M = 2U, /*!< LPUART10 mux from MuxOscRc400M. */ + kCLOCK_LPUART10_ClockRoot_MuxOscRc16M = 3U, /*!< LPUART10 mux from MuxOscRc16M. */ + kCLOCK_LPUART10_ClockRoot_MuxSysPll3Div2 = 4U, /*!< LPUART10 mux from MuxSysPll3Div2. */ + kCLOCK_LPUART10_ClockRoot_MuxSysPll1Div5 = 5U, /*!< LPUART10 mux from MuxSysPll1Div5. */ + kCLOCK_LPUART10_ClockRoot_MuxSysPll2Out = 6U, /*!< LPUART10 mux from MuxSysPll2Out. */ + kCLOCK_LPUART10_ClockRoot_MuxSysPll2Pfd3 = 7U, /*!< LPUART10 mux from MuxSysPll2Pfd3. */ + + /* LPUART11 */ + kCLOCK_LPUART11_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPUART11 mux from MuxOscRc48MDiv2. */ + kCLOCK_LPUART11_ClockRoot_MuxOsc24MOut = 1U, /*!< LPUART11 mux from MuxOsc24MOut. */ + kCLOCK_LPUART11_ClockRoot_MuxOscRc400M = 2U, /*!< LPUART11 mux from MuxOscRc400M. */ + kCLOCK_LPUART11_ClockRoot_MuxOscRc16M = 3U, /*!< LPUART11 mux from MuxOscRc16M. */ + kCLOCK_LPUART11_ClockRoot_MuxSysPll3Pfd3 = 4U, /*!< LPUART11 mux from MuxSysPll3Pfd3. */ + kCLOCK_LPUART11_ClockRoot_MuxSysPll3Out = 5U, /*!< LPUART11 mux from MuxSysPll3Out. */ + kCLOCK_LPUART11_ClockRoot_MuxSysPll2Pfd3 = 6U, /*!< LPUART11 mux from MuxSysPll2Pfd3. */ + kCLOCK_LPUART11_ClockRoot_MuxSysPll1Div5 = 7U, /*!< LPUART11 mux from MuxSysPll1Div5. */ + + /* LPUART12 */ + kCLOCK_LPUART12_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPUART12 mux from MuxOscRc48MDiv2. */ + kCLOCK_LPUART12_ClockRoot_MuxOsc24MOut = 1U, /*!< LPUART12 mux from MuxOsc24MOut. */ + kCLOCK_LPUART12_ClockRoot_MuxOscRc400M = 2U, /*!< LPUART12 mux from MuxOscRc400M. */ + kCLOCK_LPUART12_ClockRoot_MuxOscRc16M = 3U, /*!< LPUART12 mux from MuxOscRc16M. */ + kCLOCK_LPUART12_ClockRoot_MuxSysPll3Pfd3 = 4U, /*!< LPUART12 mux from MuxSysPll3Pfd3. */ + kCLOCK_LPUART12_ClockRoot_MuxSysPll3Out = 5U, /*!< LPUART12 mux from MuxSysPll3Out. */ + kCLOCK_LPUART12_ClockRoot_MuxSysPll2Pfd3 = 6U, /*!< LPUART12 mux from MuxSysPll2Pfd3. */ + kCLOCK_LPUART12_ClockRoot_MuxSysPll1Div5 = 7U, /*!< LPUART12 mux from MuxSysPll1Div5. */ + + /* LPI2C1 */ + kCLOCK_LPI2C1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPI2C1 mux from MuxOscRc48MDiv2. */ + kCLOCK_LPI2C1_ClockRoot_MuxOsc24MOut = 1U, /*!< LPI2C1 mux from MuxOsc24MOut. */ + kCLOCK_LPI2C1_ClockRoot_MuxOscRc400M = 2U, /*!< LPI2C1 mux from MuxOscRc400M. */ + kCLOCK_LPI2C1_ClockRoot_MuxOscRc16M = 3U, /*!< LPI2C1 mux from MuxOscRc16M. */ + kCLOCK_LPI2C1_ClockRoot_MuxSysPll3Div2 = 4U, /*!< LPI2C1 mux from MuxSysPll3Div2. */ + kCLOCK_LPI2C1_ClockRoot_MuxSysPll1Div5 = 5U, /*!< LPI2C1 mux from MuxSysPll1Div5. */ + kCLOCK_LPI2C1_ClockRoot_MuxSysPll2Out = 6U, /*!< LPI2C1 mux from MuxSysPll2Out. */ + kCLOCK_LPI2C1_ClockRoot_MuxSysPll2Pfd3 = 7U, /*!< LPI2C1 mux from MuxSysPll2Pfd3. */ + + /* LPI2C2 */ + kCLOCK_LPI2C2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPI2C2 mux from MuxOscRc48MDiv2. */ + kCLOCK_LPI2C2_ClockRoot_MuxOsc24MOut = 1U, /*!< LPI2C2 mux from MuxOsc24MOut. */ + kCLOCK_LPI2C2_ClockRoot_MuxOscRc400M = 2U, /*!< LPI2C2 mux from MuxOscRc400M. */ + kCLOCK_LPI2C2_ClockRoot_MuxOscRc16M = 3U, /*!< LPI2C2 mux from MuxOscRc16M. */ + kCLOCK_LPI2C2_ClockRoot_MuxSysPll3Div2 = 4U, /*!< LPI2C2 mux from MuxSysPll3Div2. */ + kCLOCK_LPI2C2_ClockRoot_MuxSysPll1Div5 = 5U, /*!< LPI2C2 mux from MuxSysPll1Div5. */ + kCLOCK_LPI2C2_ClockRoot_MuxSysPll2Out = 6U, /*!< LPI2C2 mux from MuxSysPll2Out. */ + kCLOCK_LPI2C2_ClockRoot_MuxSysPll2Pfd3 = 7U, /*!< LPI2C2 mux from MuxSysPll2Pfd3. */ + + /* LPI2C3 */ + kCLOCK_LPI2C3_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPI2C3 mux from MuxOscRc48MDiv2. */ + kCLOCK_LPI2C3_ClockRoot_MuxOsc24MOut = 1U, /*!< LPI2C3 mux from MuxOsc24MOut. */ + kCLOCK_LPI2C3_ClockRoot_MuxOscRc400M = 2U, /*!< LPI2C3 mux from MuxOscRc400M. */ + kCLOCK_LPI2C3_ClockRoot_MuxOscRc16M = 3U, /*!< LPI2C3 mux from MuxOscRc16M. */ + kCLOCK_LPI2C3_ClockRoot_MuxSysPll3Div2 = 4U, /*!< LPI2C3 mux from MuxSysPll3Div2. */ + kCLOCK_LPI2C3_ClockRoot_MuxSysPll1Div5 = 5U, /*!< LPI2C3 mux from MuxSysPll1Div5. */ + kCLOCK_LPI2C3_ClockRoot_MuxSysPll2Out = 6U, /*!< LPI2C3 mux from MuxSysPll2Out. */ + kCLOCK_LPI2C3_ClockRoot_MuxSysPll2Pfd3 = 7U, /*!< LPI2C3 mux from MuxSysPll2Pfd3. */ + + /* LPI2C4 */ + kCLOCK_LPI2C4_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPI2C4 mux from MuxOscRc48MDiv2. */ + kCLOCK_LPI2C4_ClockRoot_MuxOsc24MOut = 1U, /*!< LPI2C4 mux from MuxOsc24MOut. */ + kCLOCK_LPI2C4_ClockRoot_MuxOscRc400M = 2U, /*!< LPI2C4 mux from MuxOscRc400M. */ + kCLOCK_LPI2C4_ClockRoot_MuxOscRc16M = 3U, /*!< LPI2C4 mux from MuxOscRc16M. */ + kCLOCK_LPI2C4_ClockRoot_MuxSysPll3Div2 = 4U, /*!< LPI2C4 mux from MuxSysPll3Div2. */ + kCLOCK_LPI2C4_ClockRoot_MuxSysPll1Div5 = 5U, /*!< LPI2C4 mux from MuxSysPll1Div5. */ + kCLOCK_LPI2C4_ClockRoot_MuxSysPll2Out = 6U, /*!< LPI2C4 mux from MuxSysPll2Out. */ + kCLOCK_LPI2C4_ClockRoot_MuxSysPll2Pfd3 = 7U, /*!< LPI2C4 mux from MuxSysPll2Pfd3. */ + + /* LPI2C5 */ + kCLOCK_LPI2C5_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPI2C5 mux from MuxOscRc48MDiv2. */ + kCLOCK_LPI2C5_ClockRoot_MuxOsc24MOut = 1U, /*!< LPI2C5 mux from MuxOsc24MOut. */ + kCLOCK_LPI2C5_ClockRoot_MuxOscRc400M = 2U, /*!< LPI2C5 mux from MuxOscRc400M. */ + kCLOCK_LPI2C5_ClockRoot_MuxOscRc16M = 3U, /*!< LPI2C5 mux from MuxOscRc16M. */ + kCLOCK_LPI2C5_ClockRoot_MuxSysPll3Pfd3 = 4U, /*!< LPI2C5 mux from MuxSysPll3Pfd3. */ + kCLOCK_LPI2C5_ClockRoot_MuxSysPll3Out = 5U, /*!< LPI2C5 mux from MuxSysPll3Out. */ + kCLOCK_LPI2C5_ClockRoot_MuxSysPll2Pfd3 = 6U, /*!< LPI2C5 mux from MuxSysPll2Pfd3. */ + kCLOCK_LPI2C5_ClockRoot_MuxSysPll1Div5 = 7U, /*!< LPI2C5 mux from MuxSysPll1Div5. */ + + /* LPI2C6 */ + kCLOCK_LPI2C6_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPI2C6 mux from MuxOscRc48MDiv2. */ + kCLOCK_LPI2C6_ClockRoot_MuxOsc24MOut = 1U, /*!< LPI2C6 mux from MuxOsc24MOut. */ + kCLOCK_LPI2C6_ClockRoot_MuxOscRc400M = 2U, /*!< LPI2C6 mux from MuxOscRc400M. */ + kCLOCK_LPI2C6_ClockRoot_MuxOscRc16M = 3U, /*!< LPI2C6 mux from MuxOscRc16M. */ + kCLOCK_LPI2C6_ClockRoot_MuxSysPll3Pfd3 = 4U, /*!< LPI2C6 mux from MuxSysPll3Pfd3. */ + kCLOCK_LPI2C6_ClockRoot_MuxSysPll3Out = 5U, /*!< LPI2C6 mux from MuxSysPll3Out. */ + kCLOCK_LPI2C6_ClockRoot_MuxSysPll2Pfd3 = 6U, /*!< LPI2C6 mux from MuxSysPll2Pfd3. */ + kCLOCK_LPI2C6_ClockRoot_MuxSysPll1Div5 = 7U, /*!< LPI2C6 mux from MuxSysPll1Div5. */ + + /* LPSPI1 */ + kCLOCK_LPSPI1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPSPI1 mux from MuxOscRc48MDiv2. */ + kCLOCK_LPSPI1_ClockRoot_MuxOsc24MOut = 1U, /*!< LPSPI1 mux from MuxOsc24MOut. */ + kCLOCK_LPSPI1_ClockRoot_MuxOscRc400M = 2U, /*!< LPSPI1 mux from MuxOscRc400M. */ + kCLOCK_LPSPI1_ClockRoot_MuxOscRc16M = 3U, /*!< LPSPI1 mux from MuxOscRc16M. */ + kCLOCK_LPSPI1_ClockRoot_MuxSysPll3Pfd2 = 4U, /*!< LPSPI1 mux from MuxSysPll3Pfd2. */ + kCLOCK_LPSPI1_ClockRoot_MuxSysPll1Div5 = 5U, /*!< LPSPI1 mux from MuxSysPll1Div5. */ + kCLOCK_LPSPI1_ClockRoot_MuxSysPll2Out = 6U, /*!< LPSPI1 mux from MuxSysPll2Out. */ + kCLOCK_LPSPI1_ClockRoot_MuxSysPll2Pfd3 = 7U, /*!< LPSPI1 mux from MuxSysPll2Pfd3. */ + + /* LPSPI2 */ + kCLOCK_LPSPI2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPSPI2 mux from MuxOscRc48MDiv2. */ + kCLOCK_LPSPI2_ClockRoot_MuxOsc24MOut = 1U, /*!< LPSPI2 mux from MuxOsc24MOut. */ + kCLOCK_LPSPI2_ClockRoot_MuxOscRc400M = 2U, /*!< LPSPI2 mux from MuxOscRc400M. */ + kCLOCK_LPSPI2_ClockRoot_MuxOscRc16M = 3U, /*!< LPSPI2 mux from MuxOscRc16M. */ + kCLOCK_LPSPI2_ClockRoot_MuxSysPll3Pfd2 = 4U, /*!< LPSPI2 mux from MuxSysPll3Pfd2. */ + kCLOCK_LPSPI2_ClockRoot_MuxSysPll1Div5 = 5U, /*!< LPSPI2 mux from MuxSysPll1Div5. */ + kCLOCK_LPSPI2_ClockRoot_MuxSysPll2Out = 6U, /*!< LPSPI2 mux from MuxSysPll2Out. */ + kCLOCK_LPSPI2_ClockRoot_MuxSysPll2Pfd3 = 7U, /*!< LPSPI2 mux from MuxSysPll2Pfd3. */ + + /* LPSPI3 */ + kCLOCK_LPSPI3_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPSPI3 mux from MuxOscRc48MDiv2. */ + kCLOCK_LPSPI3_ClockRoot_MuxOsc24MOut = 1U, /*!< LPSPI3 mux from MuxOsc24MOut. */ + kCLOCK_LPSPI3_ClockRoot_MuxOscRc400M = 2U, /*!< LPSPI3 mux from MuxOscRc400M. */ + kCLOCK_LPSPI3_ClockRoot_MuxOscRc16M = 3U, /*!< LPSPI3 mux from MuxOscRc16M. */ + kCLOCK_LPSPI3_ClockRoot_MuxSysPll3Pfd2 = 4U, /*!< LPSPI3 mux from MuxSysPll3Pfd2. */ + kCLOCK_LPSPI3_ClockRoot_MuxSysPll1Div5 = 5U, /*!< LPSPI3 mux from MuxSysPll1Div5. */ + kCLOCK_LPSPI3_ClockRoot_MuxSysPll2Out = 6U, /*!< LPSPI3 mux from MuxSysPll2Out. */ + kCLOCK_LPSPI3_ClockRoot_MuxSysPll2Pfd3 = 7U, /*!< LPSPI3 mux from MuxSysPll2Pfd3. */ + + /* LPSPI4 */ + kCLOCK_LPSPI4_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPSPI4 mux from MuxOscRc48MDiv2. */ + kCLOCK_LPSPI4_ClockRoot_MuxOsc24MOut = 1U, /*!< LPSPI4 mux from MuxOsc24MOut. */ + kCLOCK_LPSPI4_ClockRoot_MuxOscRc400M = 2U, /*!< LPSPI4 mux from MuxOscRc400M. */ + kCLOCK_LPSPI4_ClockRoot_MuxOscRc16M = 3U, /*!< LPSPI4 mux from MuxOscRc16M. */ + kCLOCK_LPSPI4_ClockRoot_MuxSysPll3Pfd2 = 4U, /*!< LPSPI4 mux from MuxSysPll3Pfd2. */ + kCLOCK_LPSPI4_ClockRoot_MuxSysPll1Div5 = 5U, /*!< LPSPI4 mux from MuxSysPll1Div5. */ + kCLOCK_LPSPI4_ClockRoot_MuxSysPll2Out = 6U, /*!< LPSPI4 mux from MuxSysPll2Out. */ + kCLOCK_LPSPI4_ClockRoot_MuxSysPll2Pfd3 = 7U, /*!< LPSPI4 mux from MuxSysPll2Pfd3. */ + + /* LPSPI5 */ + kCLOCK_LPSPI5_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPSPI5 mux from MuxOscRc48MDiv2. */ + kCLOCK_LPSPI5_ClockRoot_MuxOsc24MOut = 1U, /*!< LPSPI5 mux from MuxOsc24MOut. */ + kCLOCK_LPSPI5_ClockRoot_MuxOscRc400M = 2U, /*!< LPSPI5 mux from MuxOscRc400M. */ + kCLOCK_LPSPI5_ClockRoot_MuxOscRc16M = 3U, /*!< LPSPI5 mux from MuxOscRc16M. */ + kCLOCK_LPSPI5_ClockRoot_MuxSysPll3Pfd3 = 4U, /*!< LPSPI5 mux from MuxSysPll3Pfd3. */ + kCLOCK_LPSPI5_ClockRoot_MuxSysPll3Out = 5U, /*!< LPSPI5 mux from MuxSysPll3Out. */ + kCLOCK_LPSPI5_ClockRoot_MuxSysPll3Pfd2 = 6U, /*!< LPSPI5 mux from MuxSysPll3Pfd2. */ + kCLOCK_LPSPI5_ClockRoot_MuxSysPll1Div5 = 7U, /*!< LPSPI5 mux from MuxSysPll1Div5. */ + + /* LPSPI6 */ + kCLOCK_LPSPI6_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LPSPI6 mux from MuxOscRc48MDiv2. */ + kCLOCK_LPSPI6_ClockRoot_MuxOsc24MOut = 1U, /*!< LPSPI6 mux from MuxOsc24MOut. */ + kCLOCK_LPSPI6_ClockRoot_MuxOscRc400M = 2U, /*!< LPSPI6 mux from MuxOscRc400M. */ + kCLOCK_LPSPI6_ClockRoot_MuxOscRc16M = 3U, /*!< LPSPI6 mux from MuxOscRc16M. */ + kCLOCK_LPSPI6_ClockRoot_MuxSysPll3Pfd3 = 4U, /*!< LPSPI6 mux from MuxSysPll3Pfd3. */ + kCLOCK_LPSPI6_ClockRoot_MuxSysPll3Out = 5U, /*!< LPSPI6 mux from MuxSysPll3Out. */ + kCLOCK_LPSPI6_ClockRoot_MuxSysPll3Pfd2 = 6U, /*!< LPSPI6 mux from MuxSysPll3Pfd2. */ + kCLOCK_LPSPI6_ClockRoot_MuxSysPll1Div5 = 7U, /*!< LPSPI6 mux from MuxSysPll1Div5. */ + + /* EMV1 */ + kCLOCK_EMV1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< EMV1 mux from MuxOscRc48MDiv2. */ + kCLOCK_EMV1_ClockRoot_MuxOsc24MOut = 1U, /*!< EMV1 mux from MuxOsc24MOut. */ + kCLOCK_EMV1_ClockRoot_MuxOscRc400M = 2U, /*!< EMV1 mux from MuxOscRc400M. */ + kCLOCK_EMV1_ClockRoot_MuxOscRc16M = 3U, /*!< EMV1 mux from MuxOscRc16M. */ + kCLOCK_EMV1_ClockRoot_MuxSysPll3Div2 = 4U, /*!< EMV1 mux from MuxSysPll3Div2. */ + kCLOCK_EMV1_ClockRoot_MuxSysPll1Div5 = 5U, /*!< EMV1 mux from MuxSysPll1Div5. */ + kCLOCK_EMV1_ClockRoot_MuxSysPll2Out = 6U, /*!< EMV1 mux from MuxSysPll2Out. */ + kCLOCK_EMV1_ClockRoot_MuxSysPll2Pfd3 = 7U, /*!< EMV1 mux from MuxSysPll2Pfd3. */ + + /* EMV2 */ + kCLOCK_EMV2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< EMV2 mux from MuxOscRc48MDiv2. */ + kCLOCK_EMV2_ClockRoot_MuxOsc24MOut = 1U, /*!< EMV2 mux from MuxOsc24MOut. */ + kCLOCK_EMV2_ClockRoot_MuxOscRc400M = 2U, /*!< EMV2 mux from MuxOscRc400M. */ + kCLOCK_EMV2_ClockRoot_MuxOscRc16M = 3U, /*!< EMV2 mux from MuxOscRc16M. */ + kCLOCK_EMV2_ClockRoot_MuxSysPll3Div2 = 4U, /*!< EMV2 mux from MuxSysPll3Div2. */ + kCLOCK_EMV2_ClockRoot_MuxSysPll1Div5 = 5U, /*!< EMV2 mux from MuxSysPll1Div5. */ + kCLOCK_EMV2_ClockRoot_MuxSysPll2Out = 6U, /*!< EMV2 mux from MuxSysPll2Out. */ + kCLOCK_EMV2_ClockRoot_MuxSysPll2Pfd3 = 7U, /*!< EMV2 mux from MuxSysPll2Pfd3. */ + + /* ENET1 */ + kCLOCK_ENET1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< ENET1 mux from MuxOscRc48MDiv2. */ + kCLOCK_ENET1_ClockRoot_MuxOsc24MOut = 1U, /*!< ENET1 mux from MuxOsc24MOut. */ + kCLOCK_ENET1_ClockRoot_MuxOscRc400M = 2U, /*!< ENET1 mux from MuxOscRc400M. */ + kCLOCK_ENET1_ClockRoot_MuxOscRc16M = 3U, /*!< ENET1 mux from MuxOscRc16M. */ + kCLOCK_ENET1_ClockRoot_MuxSysPll1Div2 = 4U, /*!< ENET1 mux from MuxSysPll1Div2. */ + kCLOCK_ENET1_ClockRoot_MuxAudioPllOut = 5U, /*!< ENET1 mux from MuxAudioPllOut. */ + kCLOCK_ENET1_ClockRoot_MuxSysPll1Div5 = 6U, /*!< ENET1 mux from MuxSysPll1Div5. */ + kCLOCK_ENET1_ClockRoot_MuxSysPll2Pfd1 = 7U, /*!< ENET1 mux from MuxSysPll2Pfd1. */ + + /* ENET2 */ + kCLOCK_ENET2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< ENET2 mux from MuxOscRc48MDiv2. */ + kCLOCK_ENET2_ClockRoot_MuxOsc24MOut = 1U, /*!< ENET2 mux from MuxOsc24MOut. */ + kCLOCK_ENET2_ClockRoot_MuxOscRc400M = 2U, /*!< ENET2 mux from MuxOscRc400M. */ + kCLOCK_ENET2_ClockRoot_MuxOscRc16M = 3U, /*!< ENET2 mux from MuxOscRc16M. */ + kCLOCK_ENET2_ClockRoot_MuxSysPll1Div2 = 4U, /*!< ENET2 mux from MuxSysPll1Div2. */ + kCLOCK_ENET2_ClockRoot_MuxAudioPllOut = 5U, /*!< ENET2 mux from MuxAudioPllOut. */ + kCLOCK_ENET2_ClockRoot_MuxSysPll1Div5 = 6U, /*!< ENET2 mux from MuxSysPll1Div5. */ + kCLOCK_ENET2_ClockRoot_MuxSysPll2Pfd1 = 7U, /*!< ENET2 mux from MuxSysPll2Pfd1. */ + + /* ENET_25M */ + kCLOCK_ENET_25M_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< ENET_25M mux from MuxOscRc48MDiv2. */ + kCLOCK_ENET_25M_ClockRoot_MuxOsc24MOut = 1U, /*!< ENET_25M mux from MuxOsc24MOut. */ + kCLOCK_ENET_25M_ClockRoot_MuxOscRc400M = 2U, /*!< ENET_25M mux from MuxOscRc400M. */ + kCLOCK_ENET_25M_ClockRoot_MuxOscRc16M = 3U, /*!< ENET_25M mux from MuxOscRc16M. */ + kCLOCK_ENET_25M_ClockRoot_MuxSysPll1Div2 = 4U, /*!< ENET_25M mux from MuxSysPll1Div2. */ + kCLOCK_ENET_25M_ClockRoot_MuxAudioPllOut = 5U, /*!< ENET_25M mux from MuxAudioPllOut. */ + kCLOCK_ENET_25M_ClockRoot_MuxSysPll1Div5 = 6U, /*!< ENET_25M mux from MuxSysPll1Div5. */ + kCLOCK_ENET_25M_ClockRoot_MuxSysPll2Pfd1 = 7U, /*!< ENET_25M mux from MuxSysPll2Pfd1. */ + + /* ENET_TIMER1 */ + kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< ENET_TIMER1 mux from MuxOscRc48MDiv2. */ + kCLOCK_ENET_TIMER1_ClockRoot_MuxOsc24MOut = 1U, /*!< ENET_TIMER1 mux from MuxOsc24MOut. */ + kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc400M = 2U, /*!< ENET_TIMER1 mux from MuxOscRc400M. */ + kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc16M = 3U, /*!< ENET_TIMER1 mux from MuxOscRc16M. */ + kCLOCK_ENET_TIMER1_ClockRoot_MuxSysPll1Div2 = 4U, /*!< ENET_TIMER1 mux from MuxSysPll1Div2. */ + kCLOCK_ENET_TIMER1_ClockRoot_MuxAudioPllOut = 5U, /*!< ENET_TIMER1 mux from MuxAudioPllOut. */ + kCLOCK_ENET_TIMER1_ClockRoot_MuxSysPll1Div5 = 6U, /*!< ENET_TIMER1 mux from MuxSysPll1Div5. */ + kCLOCK_ENET_TIMER1_ClockRoot_MuxSysPll2Pfd1 = 7U, /*!< ENET_TIMER1 mux from MuxSysPll2Pfd1. */ + + /* ENET_TIMER2 */ + kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< ENET_TIMER2 mux from MuxOscRc48MDiv2. */ + kCLOCK_ENET_TIMER2_ClockRoot_MuxOsc24MOut = 1U, /*!< ENET_TIMER2 mux from MuxOsc24MOut. */ + kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc400M = 2U, /*!< ENET_TIMER2 mux from MuxOscRc400M. */ + kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc16M = 3U, /*!< ENET_TIMER2 mux from MuxOscRc16M. */ + kCLOCK_ENET_TIMER2_ClockRoot_MuxSysPll1Div2 = 4U, /*!< ENET_TIMER2 mux from MuxSysPll1Div2. */ + kCLOCK_ENET_TIMER2_ClockRoot_MuxAudioPllOut = 5U, /*!< ENET_TIMER2 mux from MuxAudioPllOut. */ + kCLOCK_ENET_TIMER2_ClockRoot_MuxSysPll1Div5 = 6U, /*!< ENET_TIMER2 mux from MuxSysPll1Div5. */ + kCLOCK_ENET_TIMER2_ClockRoot_MuxSysPll2Pfd1 = 7U, /*!< ENET_TIMER2 mux from MuxSysPll2Pfd1. */ + + /* USDHC1 */ + kCLOCK_USDHC1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< USDHC1 mux from MuxOscRc48MDiv2. */ + kCLOCK_USDHC1_ClockRoot_MuxOsc24MOut = 1U, /*!< USDHC1 mux from MuxOsc24MOut. */ + kCLOCK_USDHC1_ClockRoot_MuxOscRc400M = 2U, /*!< USDHC1 mux from MuxOscRc400M. */ + kCLOCK_USDHC1_ClockRoot_MuxOscRc16M = 3U, /*!< USDHC1 mux from MuxOscRc16M. */ + kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd2 = 4U, /*!< USDHC1 mux from MuxSysPll2Pfd2. */ + kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd0 = 5U, /*!< USDHC1 mux from MuxSysPll2Pfd0. */ + kCLOCK_USDHC1_ClockRoot_MuxSysPll1Div5 = 6U, /*!< USDHC1 mux from MuxSysPll1Div5. */ + kCLOCK_USDHC1_ClockRoot_MuxArmPllOut = 7U, /*!< USDHC1 mux from MuxArmPllOut. */ + + /* USDHC2 */ + kCLOCK_USDHC2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< USDHC2 mux from MuxOscRc48MDiv2. */ + kCLOCK_USDHC2_ClockRoot_MuxOsc24MOut = 1U, /*!< USDHC2 mux from MuxOsc24MOut. */ + kCLOCK_USDHC2_ClockRoot_MuxOscRc400M = 2U, /*!< USDHC2 mux from MuxOscRc400M. */ + kCLOCK_USDHC2_ClockRoot_MuxOscRc16M = 3U, /*!< USDHC2 mux from MuxOscRc16M. */ + kCLOCK_USDHC2_ClockRoot_MuxSysPll2Pfd2 = 4U, /*!< USDHC2 mux from MuxSysPll2Pfd2. */ + kCLOCK_USDHC2_ClockRoot_MuxSysPll2Pfd0 = 5U, /*!< USDHC2 mux from MuxSysPll2Pfd0. */ + kCLOCK_USDHC2_ClockRoot_MuxSysPll1Div5 = 6U, /*!< USDHC2 mux from MuxSysPll1Div5. */ + kCLOCK_USDHC2_ClockRoot_MuxArmPllOut = 7U, /*!< USDHC2 mux from MuxArmPllOut. */ + + /* ASRC */ + kCLOCK_ASRC_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< ASRC mux from MuxOscRc48MDiv2. */ + kCLOCK_ASRC_ClockRoot_MuxOsc24MOut = 1U, /*!< ASRC mux from MuxOsc24MOut. */ + kCLOCK_ASRC_ClockRoot_MuxOscRc400M = 2U, /*!< ASRC mux from MuxOscRc400M. */ + kCLOCK_ASRC_ClockRoot_MuxOscRc16M = 3U, /*!< ASRC mux from MuxOscRc16M. */ + kCLOCK_ASRC_ClockRoot_MuxSysPll1Div5 = 4U, /*!< ASRC mux from MuxSysPll1Div5. */ + kCLOCK_ASRC_ClockRoot_MuxSysPll3Div2 = 5U, /*!< ASRC mux from MuxSysPll3Div2. */ + kCLOCK_ASRC_ClockRoot_MuxAudioPllOut = 6U, /*!< ASRC mux from MuxAudioPllOut. */ + kCLOCK_ASRC_ClockRoot_MuxSysPll2Pfd3 = 7U, /*!< ASRC mux from MuxSysPll2Pfd3. */ + + /* MQS */ + kCLOCK_MQS_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< MQS mux from MuxOscRc48MDiv2. */ + kCLOCK_MQS_ClockRoot_MuxOsc24MOut = 1U, /*!< MQS mux from MuxOsc24MOut. */ + kCLOCK_MQS_ClockRoot_MuxOscRc400M = 2U, /*!< MQS mux from MuxOscRc400M. */ + kCLOCK_MQS_ClockRoot_MuxOscRc16M = 3U, /*!< MQS mux from MuxOscRc16M. */ + kCLOCK_MQS_ClockRoot_MuxSysPll1Div5 = 4U, /*!< MQS mux from MuxSysPll1Div5. */ + kCLOCK_MQS_ClockRoot_MuxSysPll3Div2 = 5U, /*!< MQS mux from MuxSysPll3Div2. */ + kCLOCK_MQS_ClockRoot_MuxAudioPllOut = 6U, /*!< MQS mux from MuxAudioPllOut. */ + kCLOCK_MQS_ClockRoot_MuxSysPll2Pfd3 = 7U, /*!< MQS mux from MuxSysPll2Pfd3. */ + + /* MIC */ + kCLOCK_MIC_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< MIC mux from MuxOscRc48MDiv2. */ + kCLOCK_MIC_ClockRoot_MuxOsc24MOut = 1U, /*!< MIC mux from MuxOsc24MOut. */ + kCLOCK_MIC_ClockRoot_MuxOscRc400M = 2U, /*!< MIC mux from MuxOscRc400M. */ + kCLOCK_MIC_ClockRoot_MuxOscRc16M = 3U, /*!< MIC mux from MuxOscRc16M. */ + kCLOCK_MIC_ClockRoot_MuxSysPll3Pfd3 = 4U, /*!< MIC mux from MuxSysPll3Pfd3. */ + kCLOCK_MIC_ClockRoot_MuxSysPll3Out = 5U, /*!< MIC mux from MuxSysPll3Out. */ + kCLOCK_MIC_ClockRoot_MuxAudioPllOut = 6U, /*!< MIC mux from MuxAudioPllOut. */ + kCLOCK_MIC_ClockRoot_MuxSysPll1Div5 = 7U, /*!< MIC mux from MuxSysPll1Div5. */ + + /* SPDIF */ + kCLOCK_SPDIF_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< SPDIF mux from MuxOscRc48MDiv2. */ + kCLOCK_SPDIF_ClockRoot_MuxOsc24MOut = 1U, /*!< SPDIF mux from MuxOsc24MOut. */ + kCLOCK_SPDIF_ClockRoot_MuxOscRc400M = 2U, /*!< SPDIF mux from MuxOscRc400M. */ + kCLOCK_SPDIF_ClockRoot_MuxOscRc16M = 3U, /*!< SPDIF mux from MuxOscRc16M. */ + kCLOCK_SPDIF_ClockRoot_MuxAudioPllOut = 4U, /*!< SPDIF mux from MuxAudioPllOut. */ + kCLOCK_SPDIF_ClockRoot_MuxSysPll3Out = 5U, /*!< SPDIF mux from MuxSysPll3Out. */ + kCLOCK_SPDIF_ClockRoot_MuxSysPll3Pfd2 = 6U, /*!< SPDIF mux from MuxSysPll3Pfd2. */ + kCLOCK_SPDIF_ClockRoot_MuxSysPll2Pfd3 = 7U, /*!< SPDIF mux from MuxSysPll2Pfd3. */ + + /* SAI1 */ + kCLOCK_SAI1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< SAI1 mux from MuxOscRc48MDiv2. */ + kCLOCK_SAI1_ClockRoot_MuxOsc24MOut = 1U, /*!< SAI1 mux from MuxOsc24MOut. */ + kCLOCK_SAI1_ClockRoot_MuxOscRc400M = 2U, /*!< SAI1 mux from MuxOscRc400M. */ + kCLOCK_SAI1_ClockRoot_MuxOscRc16M = 3U, /*!< SAI1 mux from MuxOscRc16M. */ + kCLOCK_SAI1_ClockRoot_MuxAudioPllOut = 4U, /*!< SAI1 mux from MuxAudioPllOut. */ + kCLOCK_SAI1_ClockRoot_MuxSysPll3Pfd2 = 5U, /*!< SAI1 mux from MuxSysPll3Pfd2. */ + kCLOCK_SAI1_ClockRoot_MuxSysPll1Div5 = 6U, /*!< SAI1 mux from MuxSysPll1Div5. */ + kCLOCK_SAI1_ClockRoot_MuxSysPll2Pfd3 = 7U, /*!< SAI1 mux from MuxSysPll2Pfd3. */ + + /* SAI2 */ + kCLOCK_SAI2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< SAI2 mux from MuxOscRc48MDiv2. */ + kCLOCK_SAI2_ClockRoot_MuxOsc24MOut = 1U, /*!< SAI2 mux from MuxOsc24MOut. */ + kCLOCK_SAI2_ClockRoot_MuxOscRc400M = 2U, /*!< SAI2 mux from MuxOscRc400M. */ + kCLOCK_SAI2_ClockRoot_MuxOscRc16M = 3U, /*!< SAI2 mux from MuxOscRc16M. */ + kCLOCK_SAI2_ClockRoot_MuxAudioPllOut = 4U, /*!< SAI2 mux from MuxAudioPllOut. */ + kCLOCK_SAI2_ClockRoot_MuxSysPll3Pfd2 = 5U, /*!< SAI2 mux from MuxSysPll3Pfd2. */ + kCLOCK_SAI2_ClockRoot_MuxSysPll1Div5 = 6U, /*!< SAI2 mux from MuxSysPll1Div5. */ + kCLOCK_SAI2_ClockRoot_MuxSysPll2Pfd3 = 7U, /*!< SAI2 mux from MuxSysPll2Pfd3. */ + + /* SAI3 */ + kCLOCK_SAI3_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< SAI3 mux from MuxOscRc48MDiv2. */ + kCLOCK_SAI3_ClockRoot_MuxOsc24MOut = 1U, /*!< SAI3 mux from MuxOsc24MOut. */ + kCLOCK_SAI3_ClockRoot_MuxOscRc400M = 2U, /*!< SAI3 mux from MuxOscRc400M. */ + kCLOCK_SAI3_ClockRoot_MuxOscRc16M = 3U, /*!< SAI3 mux from MuxOscRc16M. */ + kCLOCK_SAI3_ClockRoot_MuxAudioPllOut = 4U, /*!< SAI3 mux from MuxAudioPllOut. */ + kCLOCK_SAI3_ClockRoot_MuxSysPll3Pfd2 = 5U, /*!< SAI3 mux from MuxSysPll3Pfd2. */ + kCLOCK_SAI3_ClockRoot_MuxSysPll1Div5 = 6U, /*!< SAI3 mux from MuxSysPll1Div5. */ + kCLOCK_SAI3_ClockRoot_MuxSysPll2Pfd3 = 7U, /*!< SAI3 mux from MuxSysPll2Pfd3. */ + + /* SAI4 */ + kCLOCK_SAI4_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< SAI4 mux from MuxOscRc48MDiv2. */ + kCLOCK_SAI4_ClockRoot_MuxOsc24MOut = 1U, /*!< SAI4 mux from MuxOsc24MOut. */ + kCLOCK_SAI4_ClockRoot_MuxOscRc400M = 2U, /*!< SAI4 mux from MuxOscRc400M. */ + kCLOCK_SAI4_ClockRoot_MuxOscRc16M = 3U, /*!< SAI4 mux from MuxOscRc16M. */ + kCLOCK_SAI4_ClockRoot_MuxSysPll3Pfd3 = 4U, /*!< SAI4 mux from MuxSysPll3Pfd3. */ + kCLOCK_SAI4_ClockRoot_MuxSysPll3Out = 5U, /*!< SAI4 mux from MuxSysPll3Out. */ + kCLOCK_SAI4_ClockRoot_MuxAudioPllOut = 6U, /*!< SAI4 mux from MuxAudioPllOut. */ + kCLOCK_SAI4_ClockRoot_MuxSysPll1Div5 = 7U, /*!< SAI4 mux from MuxSysPll1Div5. */ + + /* GC355 */ + kCLOCK_GC355_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< GC355 mux from MuxOscRc48MDiv2. */ + kCLOCK_GC355_ClockRoot_MuxOsc24MOut = 1U, /*!< GC355 mux from MuxOsc24MOut. */ + kCLOCK_GC355_ClockRoot_MuxOscRc400M = 2U, /*!< GC355 mux from MuxOscRc400M. */ + kCLOCK_GC355_ClockRoot_MuxOscRc16M = 3U, /*!< GC355 mux from MuxOscRc16M. */ + kCLOCK_GC355_ClockRoot_MuxSysPll2Out = 4U, /*!< GC355 mux from MuxSysPll2Out. */ + kCLOCK_GC355_ClockRoot_MuxSysPll2Pfd1 = 5U, /*!< GC355 mux from MuxSysPll2Pfd1. */ + kCLOCK_GC355_ClockRoot_MuxSysPll3Out = 6U, /*!< GC355 mux from MuxSysPll3Out. */ + kCLOCK_GC355_ClockRoot_MuxVideoPllOut = 7U, /*!< GC355 mux from MuxVideoPllOut. */ + + /* LCDIF */ + kCLOCK_LCDIF_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LCDIF mux from MuxOscRc48MDiv2. */ + kCLOCK_LCDIF_ClockRoot_MuxOsc24MOut = 1U, /*!< LCDIF mux from MuxOsc24MOut. */ + kCLOCK_LCDIF_ClockRoot_MuxOscRc400M = 2U, /*!< LCDIF mux from MuxOscRc400M. */ + kCLOCK_LCDIF_ClockRoot_MuxOscRc16M = 3U, /*!< LCDIF mux from MuxOscRc16M. */ + kCLOCK_LCDIF_ClockRoot_MuxSysPll2Out = 4U, /*!< LCDIF mux from MuxSysPll2Out. */ + kCLOCK_LCDIF_ClockRoot_MuxSysPll2Pfd2 = 5U, /*!< LCDIF mux from MuxSysPll2Pfd2. */ + kCLOCK_LCDIF_ClockRoot_MuxSysPll3Pfd0 = 6U, /*!< LCDIF mux from MuxSysPll3Pfd0. */ + kCLOCK_LCDIF_ClockRoot_MuxVideoPllOut = 7U, /*!< LCDIF mux from MuxVideoPllOut. */ + + /* LCDIFV2 */ + kCLOCK_LCDIFV2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< LCDIFV2 mux from MuxOscRc48MDiv2. */ + kCLOCK_LCDIFV2_ClockRoot_MuxOsc24MOut = 1U, /*!< LCDIFV2 mux from MuxOsc24MOut. */ + kCLOCK_LCDIFV2_ClockRoot_MuxOscRc400M = 2U, /*!< LCDIFV2 mux from MuxOscRc400M. */ + kCLOCK_LCDIFV2_ClockRoot_MuxOscRc16M = 3U, /*!< LCDIFV2 mux from MuxOscRc16M. */ + kCLOCK_LCDIFV2_ClockRoot_MuxSysPll2Out = 4U, /*!< LCDIFV2 mux from MuxSysPll2Out. */ + kCLOCK_LCDIFV2_ClockRoot_MuxSysPll2Pfd2 = 5U, /*!< LCDIFV2 mux from MuxSysPll2Pfd2. */ + kCLOCK_LCDIFV2_ClockRoot_MuxSysPll3Pfd0 = 6U, /*!< LCDIFV2 mux from MuxSysPll3Pfd0. */ + kCLOCK_LCDIFV2_ClockRoot_MuxVideoPllOut = 7U, /*!< LCDIFV2 mux from MuxVideoPllOut. */ + + /* MIPI_REF */ + kCLOCK_MIPI_REF_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< MIPI_REF mux from MuxOscRc48MDiv2. */ + kCLOCK_MIPI_REF_ClockRoot_MuxOsc24MOut = 1U, /*!< MIPI_REF mux from MuxOsc24MOut. */ + kCLOCK_MIPI_REF_ClockRoot_MuxOscRc400M = 2U, /*!< MIPI_REF mux from MuxOscRc400M. */ + kCLOCK_MIPI_REF_ClockRoot_MuxOscRc16M = 3U, /*!< MIPI_REF mux from MuxOscRc16M. */ + kCLOCK_MIPI_REF_ClockRoot_MuxSysPll2Out = 4U, /*!< MIPI_REF mux from MuxSysPll2Out. */ + kCLOCK_MIPI_REF_ClockRoot_MuxSysPll2Pfd0 = 5U, /*!< MIPI_REF mux from MuxSysPll2Pfd0. */ + kCLOCK_MIPI_REF_ClockRoot_MuxSysPll3Pfd0 = 6U, /*!< MIPI_REF mux from MuxSysPll3Pfd0. */ + kCLOCK_MIPI_REF_ClockRoot_MuxVideoPllOut = 7U, /*!< MIPI_REF mux from MuxVideoPllOut. */ + + /* MIPI_ESC */ + kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< MIPI_ESC mux from MuxOscRc48MDiv2. */ + kCLOCK_MIPI_ESC_ClockRoot_MuxOsc24MOut = 1U, /*!< MIPI_ESC mux from MuxOsc24MOut. */ + kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc400M = 2U, /*!< MIPI_ESC mux from MuxOscRc400M. */ + kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc16M = 3U, /*!< MIPI_ESC mux from MuxOscRc16M. */ + kCLOCK_MIPI_ESC_ClockRoot_MuxSysPll2Out = 4U, /*!< MIPI_ESC mux from MuxSysPll2Out. */ + kCLOCK_MIPI_ESC_ClockRoot_MuxSysPll2Pfd0 = 5U, /*!< MIPI_ESC mux from MuxSysPll2Pfd0. */ + kCLOCK_MIPI_ESC_ClockRoot_MuxSysPll3Pfd0 = 6U, /*!< MIPI_ESC mux from MuxSysPll3Pfd0. */ + kCLOCK_MIPI_ESC_ClockRoot_MuxVideoPllOut = 7U, /*!< MIPI_ESC mux from MuxVideoPllOut. */ + + /* CSI2 */ + kCLOCK_CSI2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< CSI2 mux from MuxOscRc48MDiv2. */ + kCLOCK_CSI2_ClockRoot_MuxOsc24MOut = 1U, /*!< CSI2 mux from MuxOsc24MOut. */ + kCLOCK_CSI2_ClockRoot_MuxOscRc400M = 2U, /*!< CSI2 mux from MuxOscRc400M. */ + kCLOCK_CSI2_ClockRoot_MuxOscRc16M = 3U, /*!< CSI2 mux from MuxOscRc16M. */ + kCLOCK_CSI2_ClockRoot_MuxSysPll2Pfd2 = 4U, /*!< CSI2 mux from MuxSysPll2Pfd2. */ + kCLOCK_CSI2_ClockRoot_MuxSysPll3Out = 5U, /*!< CSI2 mux from MuxSysPll3Out. */ + kCLOCK_CSI2_ClockRoot_MuxSysPll2Pfd0 = 6U, /*!< CSI2 mux from MuxSysPll2Pfd0. */ + kCLOCK_CSI2_ClockRoot_MuxVideoPllOut = 7U, /*!< CSI2 mux from MuxVideoPllOut. */ + + /* CSI2_ESC */ + kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< CSI2_ESC mux from MuxOscRc48MDiv2. */ + kCLOCK_CSI2_ESC_ClockRoot_MuxOsc24MOut = 1U, /*!< CSI2_ESC mux from MuxOsc24MOut. */ + kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc400M = 2U, /*!< CSI2_ESC mux from MuxOscRc400M. */ + kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc16M = 3U, /*!< CSI2_ESC mux from MuxOscRc16M. */ + kCLOCK_CSI2_ESC_ClockRoot_MuxSysPll2Pfd2 = 4U, /*!< CSI2_ESC mux from MuxSysPll2Pfd2. */ + kCLOCK_CSI2_ESC_ClockRoot_MuxSysPll3Out = 5U, /*!< CSI2_ESC mux from MuxSysPll3Out. */ + kCLOCK_CSI2_ESC_ClockRoot_MuxSysPll2Pfd0 = 6U, /*!< CSI2_ESC mux from MuxSysPll2Pfd0. */ + kCLOCK_CSI2_ESC_ClockRoot_MuxVideoPllOut = 7U, /*!< CSI2_ESC mux from MuxVideoPllOut. */ + + /* CSI2_UI */ + kCLOCK_CSI2_UI_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< CSI2_UI mux from MuxOscRc48MDiv2. */ + kCLOCK_CSI2_UI_ClockRoot_MuxOsc24MOut = 1U, /*!< CSI2_UI mux from MuxOsc24MOut. */ + kCLOCK_CSI2_UI_ClockRoot_MuxOscRc400M = 2U, /*!< CSI2_UI mux from MuxOscRc400M. */ + kCLOCK_CSI2_UI_ClockRoot_MuxOscRc16M = 3U, /*!< CSI2_UI mux from MuxOscRc16M. */ + kCLOCK_CSI2_UI_ClockRoot_MuxSysPll2Pfd2 = 4U, /*!< CSI2_UI mux from MuxSysPll2Pfd2. */ + kCLOCK_CSI2_UI_ClockRoot_MuxSysPll3Out = 5U, /*!< CSI2_UI mux from MuxSysPll3Out. */ + kCLOCK_CSI2_UI_ClockRoot_MuxSysPll2Pfd0 = 6U, /*!< CSI2_UI mux from MuxSysPll2Pfd0. */ + kCLOCK_CSI2_UI_ClockRoot_MuxVideoPllOut = 7U, /*!< CSI2_UI mux from MuxVideoPllOut. */ + + /* CSI */ + kCLOCK_CSI_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< CSI mux from MuxOscRc48MDiv2. */ + kCLOCK_CSI_ClockRoot_MuxOsc24MOut = 1U, /*!< CSI mux from MuxOsc24MOut. */ + kCLOCK_CSI_ClockRoot_MuxOscRc400M = 2U, /*!< CSI mux from MuxOscRc400M. */ + kCLOCK_CSI_ClockRoot_MuxOscRc16M = 3U, /*!< CSI mux from MuxOscRc16M. */ + kCLOCK_CSI_ClockRoot_MuxSysPll2Pfd2 = 4U, /*!< CSI mux from MuxSysPll2Pfd2. */ + kCLOCK_CSI_ClockRoot_MuxSysPll3Out = 5U, /*!< CSI mux from MuxSysPll3Out. */ + kCLOCK_CSI_ClockRoot_MuxSysPll3Pfd1 = 6U, /*!< CSI mux from MuxSysPll3Pfd1. */ + kCLOCK_CSI_ClockRoot_MuxVideoPllOut = 7U, /*!< CSI mux from MuxVideoPllOut. */ + + /* CKO1 */ + kCLOCK_CKO1_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< CKO1 mux from MuxOscRc48MDiv2. */ + kCLOCK_CKO1_ClockRoot_MuxOsc24MOut = 1U, /*!< CKO1 mux from MuxOsc24MOut. */ + kCLOCK_CKO1_ClockRoot_MuxOscRc400M = 2U, /*!< CKO1 mux from MuxOscRc400M. */ + kCLOCK_CKO1_ClockRoot_MuxOscRc16M = 3U, /*!< CKO1 mux from MuxOscRc16M. */ + kCLOCK_CKO1_ClockRoot_MuxSysPll2Pfd2 = 4U, /*!< CKO1 mux from MuxSysPll2Pfd2. */ + kCLOCK_CKO1_ClockRoot_MuxSysPll2Out = 5U, /*!< CKO1 mux from MuxSysPll2Out. */ + kCLOCK_CKO1_ClockRoot_MuxSysPll3Pfd1 = 6U, /*!< CKO1 mux from MuxSysPll3Pfd1. */ + kCLOCK_CKO1_ClockRoot_MuxSysPll1Div5 = 7U, /*!< CKO1 mux from MuxSysPll1Div5. */ + + /* CKO2 */ + kCLOCK_CKO2_ClockRoot_MuxOscRc48MDiv2 = 0U, /*!< CKO2 mux from MuxOscRc48MDiv2. */ + kCLOCK_CKO2_ClockRoot_MuxOsc24MOut = 1U, /*!< CKO2 mux from MuxOsc24MOut. */ + kCLOCK_CKO2_ClockRoot_MuxOscRc400M = 2U, /*!< CKO2 mux from MuxOscRc400M. */ + kCLOCK_CKO2_ClockRoot_MuxOscRc16M = 3U, /*!< CKO2 mux from MuxOscRc16M. */ + kCLOCK_CKO2_ClockRoot_MuxSysPll2Pfd3 = 4U, /*!< CKO2 mux from MuxSysPll2Pfd3. */ + kCLOCK_CKO2_ClockRoot_MuxOscRc48M = 5U, /*!< CKO2 mux from MuxOscRc48M. */ + kCLOCK_CKO2_ClockRoot_MuxSysPll3Pfd1 = 6U, /*!< CKO2 mux from MuxSysPll3Pfd1. */ + kCLOCK_CKO2_ClockRoot_MuxAudioPllOut = 7U, /*!< CKO2 mux from MuxAudioPllOut. */ +} clock_root_mux_source_t; + +/*! + * @brief Clock group enumeration. + */ +typedef enum _clock_group +{ + kCLOCK_Group_FlexRAM = 0, /*!< FlexRAM clock group. */ + kCLOCK_Group_MipiDsi = 1, /*!< Mipi Dsi clock group. */ + kCLOCK_Group_Last, /*!< Last clock group. */ +} clock_group_t; + +/*! + * @brief The structure used to configure clock group. + */ +typedef struct _clock_group_config +{ + bool clockOff; /*!< Turn off the clock. */ + uint16_t resetDiv; /*!< resetDiv + 1 should be common multiple of all dividers, valid range 0 ~ 255. */ + uint8_t div0; /*!< Divide root clock by div0 + 1, valid range: 0 ~ 15. */ +} clock_group_config_t; + +#define clock_ip_name_t clock_lpcg_t + +#if (__CORTEX_M == 7) +#define CLOCK_GetCpuClkFreq CLOCK_GetM7Freq +#else +#define CLOCK_GetCpuClkFreq CLOCK_GetM4Freq +#endif + +#define CLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq /*!< For compatible with other platforms without CCM. */ + +/* uncomment the following line if want to use OBS to retrieve frequency */ +/* #define GET_FREQ_FROM_OBS */ + +/*! @brief OSC 24M sorce select */ +typedef enum _clock_osc +{ + kCLOCK_RcOsc = 0U, /*!< On chip OSC. */ + kCLOCK_XtalOsc = 1U, /*!< 24M Xtal OSC */ +} clock_osc_t; + +/*! @brief Clock gate value */ +typedef enum _clock_gate_value +{ + kCLOCK_Off = (int)~CCM_LPCG_DIRECT_ON_MASK, /*!< Clock is off. */ + kCLOCK_On = CCM_LPCG_DIRECT_ON_MASK, /*!< Clock is on*/ +} clock_gate_value_t; + +/*! @brief System clock mode */ +typedef enum _clock_mode_t +{ + kCLOCK_ModeRun = 0U, /*!< Remain in run mode. */ + kCLOCK_ModeWait = 1U, /*!< Transfer to wait mode. */ + kCLOCK_ModeStop = 2U, /*!< Transfer to stop mode. */ +} clock_mode_t; + +/*! @brief USB clock source definition. */ +typedef enum _clock_usb_src +{ + kCLOCK_Usb480M = 0, /*!< Use 480M. */ + kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU, /*!< Used when the function does not + care the clock source. */ +} clock_usb_src_t; + +/*! @brief Source of the USB HS PHY. */ +typedef enum _clock_usb_phy_src +{ + kCLOCK_Usbphy480M = 0, /*!< Use 480M. */ +} clock_usb_phy_src_t; + +/*! @brief PLL clock source, bypass cloco source also */ +enum _clock_pll_clk_src +{ + kCLOCK_PllClkSrc24M = 0U, /*!< Pll clock source 24M */ + kCLOCK_PllSrcClkPN = 1U, /*!< Pll clock source CLK1_P and CLK1_N */ +}; + +/*! + * @brief PLL post divider enumeration. + */ +typedef enum _clock_pll_post_div +{ + kCLOCK_PllPostDiv8 = 0U, /*!< Divide by 8. */ + kCLOCK_PllPostDiv4 = 1U, /*!< Divide by 4. */ +} clock_pll_post_div_t; + +/*! + * @brief PLL configuration for ARM. + * + * The output clock frequency is: + * + * Fout=Fin*loopDivider /(2 * postDivider). + * + * Fin is always 24MHz. + */ +typedef struct _clock_arm_pll_config +{ + clock_pll_post_div_t postDivider; /*!< Post divider. */ + uint32_t loopDivider; /*!< PLL loop divider. Valid range: 104-208. */ +} clock_arm_pll_config_t; + +/*! @brief PLL configuration for USB */ +typedef struct _clock_usb_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. + 0 - Fout=Fref*20; + 1 - Fout=Fref*22 */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ + +} clock_usb_pll_config_t; + +/*! @brief Spread specturm configure Pll */ +typedef struct _clock_pll_ss_config +{ + uint16_t stop; /*!< Spread spectrum stop value to get frequency change. */ + uint16_t step; /*!< Spread spectrum step value to get frequency change step. */ +} clock_pll_ss_config_t; + +/*! @brief PLL configure for Sys Pll2 */ +typedef struct _clock_sys_pll2_config +{ + uint32_t mfd; /*!< Denominator of spread spectrum */ + clock_pll_ss_config_t *ss; /*!< Spread spectrum parameter, + it can be NULL, if ssEnable is set to false */ + bool ssEnable; /*!< Enable spread spectrum flag */ +} clock_sys_pll2_config_t; + +/*! @brief PLL configure for Sys Pll1 */ +typedef struct _clock_sys_pll1_config +{ + bool pllDiv2En; /*!< Enable Sys Pll1 divide-by-2 clock or not. */ + bool pllDiv5En; /*!< Enable Sys Pll1 divide-by-5 clock or not. */ + clock_pll_ss_config_t *ss; /*!< Spread spectrum parameter, + it can be NULL, if ssEnable is set to false */ + bool ssEnable; /*!< Enable spread spectrum flag */ +} clock_sys_pll1_config_t; + +/*! @brief PLL configuration for AUDIO and VIDEO */ +typedef struct _clock_audio_pll_config +{ + uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */ + uint8_t postDivider; /*!< Divider after the PLL, 0x0=divided by 1, 0x1=divided by 2, 0x2=divided by 4, + 0x3=divided by 8, 0x4=divided by 16, 0x5=divided by 32.*/ + uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ + uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ + clock_pll_ss_config_t *ss; /*!< Spread spectrum parameter, + it can be NULL, if ssEnable is set to false */ + bool ssEnable; /*!< Enable spread spectrum flag */ +} clock_av_pll_config_t, clock_audio_pll_config_t, clock_video_pll_config_t; + +/*! + * @brief PLL configuration fro AUDIO PLL, SYSTEM PLL1 and VIDEO PLL. + */ +typedef struct _clock_audio_pll_gpc_config +{ + uint8_t loopDivider; /*!< PLL loop divider. */ + uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ + uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ + clock_pll_ss_config_t *ss; /*!< Spread spectrum parameter, + it can be NULL, if ssEnable is set to false */ + bool ssEnable; /*!< Enable spread spectrum flag */ +} clock_audio_pll_gpc_config_t, clock_video_pll_gpc_config_t, clock_sys_pll1_gpc_config_t; + +/*! @brief PLL configuration for ENET */ +typedef struct _clock_enet_pll_config +{ + bool enableClkOutput; /*!< Power on and enable PLL clock output for ENET0 (ref_enetpll0). */ + bool enableClkOutput25M; /*!< Power on and enable PLL clock output for ENET2 (ref_enetpll2). */ + uint8_t loopDivider; /*!< Controls the frequency of the ENET0 reference clock. + b00 25MHz + b01 50MHz + b10 100MHz (not 50% duty cycle) + b11 125MHz */ + uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */ + bool enableClkOutput1; /*!< Power on and enable PLL clock output for ENET1 (ref_enetpll1). */ + uint8_t loopDivider1; /*!< Controls the frequency of the ENET1 reference clock. + b00 25MHz + b01 50MHz + b10 100MHz (not 50% duty cycle) + b11 125MHz */ +} clock_enet_pll_config_t; + +/*! @brief Clock root configuration */ +typedef struct _clock_root_config_t +{ + bool clockOff; + uint8_t mux; /*!< See #clock_root_mux_source_t for details. */ + uint8_t div; /*!< it's the actual divider */ +} clock_root_config_t; + +/*! @brief Clock root configuration in SetPoint Mode */ +typedef struct _clock_root_setpoint_config_t +{ + uint8_t grade; /*!< Indicate speed grade for each SetPoint */ + bool clockOff; + uint8_t mux; /*!< See #clock_root_mux_source_t for details. */ + uint8_t div; /*!< it's the actual divider */ +} clock_root_setpoint_config_t; + +/*! @brief PLL name */ +typedef enum _clock_pll +{ + kCLOCK_PllArm, /*!< ARM PLL. */ + kCLOCK_PllSys1, /*!< SYS1 PLL, it has a dedicated frequency of 1GHz. */ + kCLOCK_PllSys2, /*!< SYS2 PLL, it has a dedicated frequency of 528MHz. */ + kCLOCK_PllSys3, /*!< SYS3 PLL, it has a dedicated frequency of 480MHz. */ + kCLOCK_PllAudio, /*!< Audio PLL. */ + kCLOCK_PllVideo, /*!< Video PLL. */ + kCLOCK_PllInvalid = -1, /*!< Invalid value. */ +} clock_pll_t; + +#define PLL_PFD_COUNT 4 +/*! @brief PLL PFD name */ +typedef enum _clock_pfd +{ + kCLOCK_Pfd0 = 0U, /*!< PLL PFD0 */ + kCLOCK_Pfd1 = 1U, /*!< PLL PFD1 */ + kCLOCK_Pfd2 = 2U, /*!< PLL PFD2 */ + kCLOCK_Pfd3 = 3U, /*!< PLL PFD3 */ +} clock_pfd_t; + +/*! + * @brief The enumeration of control mode. + * + */ +typedef enum _clock_control_mode +{ + kCLOCK_SoftwareMode = 0U, /*!< Software control mode. */ + kCLOCK_GpcMode, /*!< GPC control mode. */ +} clock_control_mode_t; + +/*! + * @brief The enumeration of 24MHz crystal oscillator mode. + */ +typedef enum _clock_24MOsc_mode +{ + kCLOCK_24MOscHighGainMode = 0U, /*!< 24MHz crystal oscillator work as high gain mode. */ + kCLOCK_24MOscBypassMode = 1U, /*!< 24MHz crystal oscillator work as bypass mode. */ + kCLOCK_24MOscLowPowerMode = 2U, /*!< 24MHz crystal oscillator work as low power mode. */ +} clock_24MOsc_mode_t; + +/*! + * @brief The enumeration of 16MHz RC oscillator clock source. + */ +typedef enum _clock_16MOsc_source +{ + kCLOCK_16MOscSourceFrom16MOsc = 0U, /*!< Source from 16MHz RC oscialltor. */ + kCLOCK_16MOscSourceFrom24MOsc = 1U, /*!< Source from 24MHz crystal oscillator. */ +} clock_16MOsc_source_t; + +/*! + * @brief The enumeration of 1MHz output clock behavior, including disabling 1MHz output, + * enabling locked 1MHz clock output, and enabling free-running 1MHz clock output. + */ +typedef enum _clock_1MHzOut_behavior +{ + kCLOCK_1MHzOutDisable = 0U, /*!< Disable 1MHz output clock. */ + kCLOCK_1MHzOutEnableLocked1Mhz = 1U, /*!< Enable 1MHz output clock, and select locked 1MHz to output. */ + kCLOCK_1MHzOutEnableFreeRunning1Mhz = 2U, /*!< Enable 1MHZ output clock, + and select free-running 1MHz to output. */ +} clock_1MHzOut_behavior_t; + +/*! + * @brief The clock dependence level. + */ +typedef enum _clock_level +{ + kCLOCK_Level0 = 0x0UL, /*!< Not needed in any mode. */ + kCLOCK_Level1 = 0x1UL, /*!< Needed in RUN mode. */ + kCLOCK_Level2 = 0x2UL, /*!< Needed in RUN and WAIT mode. */ + kCLOCK_Level3 = 0x3UL, /*!< Needed in RUN, WAIT and STOP mode. */ + kCLOCK_Level4 = 0x4UL, /*!< Always on in any mode. */ +} clock_level_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @brief Set CCM Root Clock MUX node to certain value. + * + * @param root Which root clock node to set, see \ref clock_root_t. + * @param src Clock mux value to set, different mux has different value range. See \ref clock_root_mux_source_t. + */ +static inline void CLOCK_SetRootClockMux(clock_root_t root, uint8_t src) +{ + assert(src < 8U); + CCM->CLOCK_ROOT[root].CONTROL = + (CCM->CLOCK_ROOT[root].CONTROL & ~(CCM_CLOCK_ROOT_CONTROL_MUX_MASK)) | CCM_CLOCK_ROOT_CONTROL_MUX(src); + __DSB(); + __ISB(); +#if __CORTEX_M == 4 + (void)CCM->CLOCK_ROOT[root].CONTROL; +#endif +} + +/*! + * @brief Get CCM Root Clock MUX value. + * + * @param root Which root clock node to get, see \ref clock_root_t. + * @return Clock mux value. + */ +static inline uint32_t CLOCK_GetRootClockMux(clock_root_t root) +{ + return (CCM->CLOCK_ROOT[root].CONTROL & CCM_CLOCK_ROOT_CONTROL_MUX_MASK) >> CCM_CLOCK_ROOT_CONTROL_MUX_SHIFT; +} + +/*! + * @brief Get CCM Root Clock Source. + * + * @param root Which root clock node to get, see \ref clock_root_t. + * @param src Clock mux value to get, see \ref clock_root_mux_source_t. + * @return Clock source + */ +static inline clock_name_t CLOCK_GetRootClockSource(clock_root_t root, uint32_t src) +{ + return s_clockSourceName[root][src]; +} + +/*! + * @brief Set CCM Root Clock DIV certain value. + * + * @param root Which root clock to set, see \ref clock_root_t. + * @param div Clock div value to set range is 1-256, different divider has different value range. + */ +static inline void CLOCK_SetRootClockDiv(clock_root_t root, uint32_t div) +{ + assert(div); + CCM->CLOCK_ROOT[root].CONTROL = (CCM->CLOCK_ROOT[root].CONTROL & ~CCM_CLOCK_ROOT_CONTROL_DIV_MASK) | + CCM_CLOCK_ROOT_CONTROL_DIV((uint32_t)div - 1UL); + __DSB(); + __ISB(); +#if __CORTEX_M == 4 + (void)CCM->CLOCK_ROOT[root].CONTROL; +#endif +} + +/*! + * @brief Get CCM DIV node value. + * + * @param root Which root clock node to get, see \ref clock_root_t. + * @return divider set for this root + */ +static inline uint32_t CLOCK_GetRootClockDiv(clock_root_t root) +{ + return ((CCM->CLOCK_ROOT[root].CONTROL & CCM_CLOCK_ROOT_CONTROL_DIV_MASK) >> CCM_CLOCK_ROOT_CONTROL_DIV_SHIFT) + + 1UL; +} + +/*! + * @brief Power Off Root Clock + * + * @param root Which root clock node to set, see \ref clock_root_t. + */ +static inline void CLOCK_PowerOffRootClock(clock_root_t root) +{ + if (0UL == (CCM->CLOCK_ROOT[root].CONTROL & CCM_CLOCK_ROOT_CONTROL_OFF_MASK)) + { + CCM->CLOCK_ROOT[root].CONTROL_SET = CCM_CLOCK_ROOT_CONTROL_OFF_MASK; + __DSB(); + __ISB(); +#if __CORTEX_M == 4 + (void)CCM->CLOCK_ROOT[root].CONTROL; +#endif + } +} + +/*! + * @brief Power On Root Clock + * + * @param root Which root clock node to set, see \ref clock_root_t. + */ +static inline void CLOCK_PowerOnRootClock(clock_root_t root) +{ + CCM->CLOCK_ROOT[root].CONTROL_CLR = CCM_CLOCK_ROOT_CONTROL_OFF_MASK; + __DSB(); + __ISB(); +#if __CORTEX_M == 4 + (void)CCM->CLOCK_ROOT[root].CONTROL; +#endif +} + +/*! + * @brief Configure Root Clock + * + * @param root Which root clock node to set, see \ref clock_root_t. + * @param config root clock config, see \ref clock_root_config_t + */ +static inline void CLOCK_SetRootClock(clock_root_t root, const clock_root_config_t *config) +{ + assert(config); + CCM->CLOCK_ROOT[root].CONTROL = CCM_CLOCK_ROOT_CONTROL_MUX(config->mux) | + CCM_CLOCK_ROOT_CONTROL_DIV((uint32_t)config->div - 1UL) | + (config->clockOff ? CCM_CLOCK_ROOT_CONTROL_OFF(config->clockOff) : 0UL); + __DSB(); + __ISB(); +#if __CORTEX_M == 4 + (void)CCM->CLOCK_ROOT[root].CONTROL; +#endif +} + +/*! + * @brief Control the clock gate for specific IP. + * + * @note This API will not have any effect when this clock is in CPULPM or SetPoint Mode + * + * @param name Which clock to enable, see \ref clock_lpcg_t. + * @param value Clock gate value to set, see \ref clock_gate_value_t. + */ +static inline void CLOCK_ControlGate(clock_ip_name_t name, clock_gate_value_t value) +{ + if (((uint32_t)value & CCM_LPCG_DIRECT_ON_MASK) != (CCM->LPCG[name].DIRECT & CCM_LPCG_DIRECT_ON_MASK)) + { + CCM->LPCG[name].DIRECT = ((uint32_t)value & CCM_LPCG_DIRECT_ON_MASK); + __DSB(); + __ISB(); + + while ((CCM->LPCG[name].STATUS0 & CCM_LPCG_STATUS0_ON_MASK) != ((uint32_t)value & CCM_LPCG_STATUS0_ON_MASK)) + { + } + } +} + +/*! + * @brief Enable the clock for specific IP. + * + * @param name Which clock to enable, see \ref clock_lpcg_t. + */ +static inline void CLOCK_EnableClock(clock_ip_name_t name) +{ + CLOCK_ControlGate(name, kCLOCK_On); +} + +/*! + * @brief Disable the clock for specific IP. + * + * @param name Which clock to disable, see \ref clock_lpcg_t. + */ +static inline void CLOCK_DisableClock(clock_ip_name_t name) +{ + CLOCK_ControlGate(name, kCLOCK_Off); +} + +/*! + * @brief Set the clock group configuration. + * + * @param group Which group to configure, see \ref clock_group_t. + * @param config Configuration to set. + */ +void CLOCK_SetGroupConfig(clock_group_t group, const clock_group_config_t *config); + +/*! + * @brief Gets the clock frequency for a specific clock name. + * + * This function checks the current clock configurations and then calculates + * the clock frequency for a specific clock name defined in clock_name_t. + * + * @param name Clock names defined in clock_name_t + * @return Clock frequency value in hertz + */ +uint32_t CLOCK_GetFreq(clock_name_t name); + +/*! + * @brief Gets the clock frequency for a specific root clock name. + * + * This function checks the current clock configurations and then calculates + * the clock frequency for a specific clock name defined in clock_root_t. + * + * @param root Clock names defined in clock_root_t + * @return Clock frequency value in hertz + */ +static inline uint32_t CLOCK_GetRootClockFreq(clock_root_t root) +{ + uint32_t freq, mux; + mux = CLOCK_GetRootClockMux(root); + freq = CLOCK_GetFreq(s_clockSourceName[root][mux]) / (CLOCK_GetRootClockDiv(root)); + assert(freq); + return freq; +} + +/*! + * @brief Get the CCM CPU/core/system frequency. + * + * @return Clock frequency; If the clock is invalid, returns 0. + */ +static inline uint32_t CLOCK_GetM7Freq(void) +{ + return CLOCK_GetRootClockFreq(kCLOCK_Root_M7); +} + +/*! + * @brief Get the CCM CPU/core/system frequency. + * + * @return Clock frequency; If the clock is invalid, returns 0. + */ +static inline uint32_t CLOCK_GetM4Freq(void) +{ + return CLOCK_GetRootClockFreq(kCLOCK_Root_M4); +} + +/*! + * @brief Check if PLL is bypassed + * + * @param pll PLL control name (see @ref clock_pll_t enumeration) + * @return PLL bypass status. + * - true: The PLL is bypassed. + * - false: The PLL is not bypassed. + */ +static inline bool CLOCK_IsPllBypassed(clock_pll_t pll) +{ + if (pll == kCLOCK_PllArm) + { + return (bool)((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_BYPASS_MASK) >> + ANADIG_PLL_ARM_PLL_CTRL_BYPASS_SHIFT); + } + else if (pll == kCLOCK_PllSys2) + { + return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK) >> + ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_SHIFT); + } + else if (pll == kCLOCK_PllSys3) + { + return (bool)((ANADIG_PLL->SYS_PLL3_CTRL & ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_MASK) >> + ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_SHIFT); + } + else + { + return false; + } +} + +/*! + * @brief Check if PLL is enabled + * + * @param pll PLL control name (see @ref clock_pll_t enumeration) + * @return PLL bypass status. + * - true: The PLL is enabled. + * - false: The PLL is not enabled. + */ +static inline bool CLOCK_IsPllEnabled(clock_pll_t pll) +{ + if (pll == kCLOCK_PllArm) + { + return (bool)((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK) >> + ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_SHIFT); + } + else if (pll == kCLOCK_PllSys2) + { + return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK) >> + ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_SHIFT); + } + else if (pll == kCLOCK_PllSys3) + { + return (bool)((ANADIG_PLL->SYS_PLL3_CTRL & ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_MASK) >> + ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_SHIFT); + } + else if (pll == kCLOCK_PllSys1) + { + return (bool)((ANADIG_PLL->SYS_PLL1_CTRL & ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK) >> + ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_SHIFT); + } + else if (pll == kCLOCK_PllAudio) + { + return (bool)((ANADIG_PLL->PLL_AUDIO_CTRL & ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_MASK) >> + ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_SHIFT); + } + else if (pll == kCLOCK_PllVideo) + { + return (bool)((ANADIG_PLL->PLL_VIDEO_CTRL & ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_MASK) >> + ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_SHIFT); + } + else + { + return false; + } +} + +/*! + * @name OSC operations + * @{ + */ + +/*! + * @brief Gets the RTC clock frequency. + * + * @return Clock frequency; If the clock is invalid, returns 0. + */ +static inline uint32_t CLOCK_GetRtcFreq(void) +{ + return 32768U; +} + +/*! + * @brief Set the control mode of 48MHz RC oscillator. + * + * @param controlMode The control mode to be set, please refer to @ref clock_control_mode_t. + */ +static inline void CLOCK_OSC_SetOsc48MControlMode(clock_control_mode_t controlMode) +{ + ANADIG_OSC->OSC_48M_CTRL = (ANADIG_OSC->OSC_48M_CTRL & ~(ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_MASK)) | + ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE(controlMode); +} + +/*! + * @brief Enable/disable 48MHz RC oscillator. + * + * @param enable Used to enable or disable the 48MHz RC oscillator. + * - \b true Enable the 48MHz RC oscillator. + * - \b false Dissable the 48MHz RC oscillator. + */ +static inline void CLOCK_OSC_EnableOsc48M(bool enable) +{ + if (enable) + { + ANADIG_OSC->OSC_48M_CTRL |= ANADIG_OSC_OSC_48M_CTRL_TEN_MASK; + } + else + { + ANADIG_OSC->OSC_48M_CTRL &= ~ANADIG_OSC_OSC_48M_CTRL_TEN_MASK; + } +} + +/*! + * @brief Set the control mode of the 24MHz clock sourced from 48MHz RC oscillator. + * + * @param controlMode The control mode to be set, please refer to @ref clock_control_mode_t. + */ +static inline void CLOCK_OSC_SetOsc48MDiv2ControlMode(clock_control_mode_t controlMode) +{ + ANADIG_OSC->OSC_48M_CTRL = (ANADIG_OSC->OSC_48M_CTRL & ~(ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_MASK)) | + ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE(controlMode); +} + +/*! + * @brief Enable/disable the 24MHz clock sourced from 48MHz RC oscillator. + * + * @note The 48MHz RC oscillator must be enabled before enabling this 24MHz clock. + * + * @param enable Used to enable/disable the 24MHz clock sourced from 48MHz RC oscillator. + * - \b true Enable the 24MHz clock sourced from 48MHz. + * - \b false Disable the 24MHz clock sourced from 48MHz. + */ +static inline void CLOCK_OSC_EnableOsc48MDiv2(bool enable) +{ + if (enable) + { + ANADIG_OSC->OSC_48M_CTRL |= ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_MASK; + } + else + { + ANADIG_OSC->OSC_48M_CTRL &= ~ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_MASK; + } +} + +/*! + * @brief Set the control mode of 24MHz crystal oscillator. + * + * @param controlMode The control mode to be set, please refer to @ref clock_control_mode_t. + */ +static inline void CLOCK_OSC_SetOsc24MControlMode(clock_control_mode_t controlMode) +{ + ANADIG_OSC->OSC_24M_CTRL = (ANADIG_OSC->OSC_24M_CTRL & ~(ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_MASK)) | + ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE(controlMode); +} + +/*! @brief Enable OSC 24Mhz + * + * This function enables OSC 24Mhz. + */ +void CLOCK_OSC_EnableOsc24M(void); + +/*! + * @brief Gate/ungate the 24MHz crystal oscillator output. + * + * @note Gating the 24MHz crystal oscillator can save power. + * + * @param enableGate Used to gate/ungate the 24MHz crystal oscillator. + * - \b true Gate the 24MHz crystal oscillator to save power. + * - \b false Ungate the 24MHz crystal oscillator. + */ +static inline void CLOCK_OSC_GateOsc24M(bool enableGate) +{ + if (enableGate) + { + ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_MASK; + } + else + { + ANADIG_OSC->OSC_24M_CTRL &= ~ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_MASK; + } +} + +/*! + * @brief Set the work mode of 24MHz crystal oscillator, the available modes are high gian mode, low power mode, and + * bypass mode. + * + * @param workMode The work mode of 24MHz crystal oscillator, please refer to @ref clock_24MOsc_mode_t for details. + */ +void CLOCK_OSC_SetOsc24MWorkMode(clock_24MOsc_mode_t workMode); + +/*! + * @brief Set the control mode of 400MHz RC oscillator. + * + * @param controlMode The control mode to be set, please refer to @ref clock_control_mode_t. + */ +static inline void CLOCK_OSC_SetOscRc400MControlMode(clock_control_mode_t controlMode) +{ + ANADIG_OSC->OSC_400M_CTRL1 = (ANADIG_OSC->OSC_400M_CTRL1 & (~ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_MASK)) | + ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE(controlMode); +} + +/*! @brief Enable OSC RC 400Mhz + * + * This function enables OSC RC 400Mhz. + */ +void CLOCK_OSC_EnableOscRc400M(void); + +/*! + * @brief Gate/ungate 400MHz RC oscillator. + * + * @param enableGate Used to gate/ungate 400MHz RC oscillator. + * - \b true Gate the 400MHz RC oscillator. + * - \b false Ungate the 400MHz RC oscillator. + */ +static inline void CLOCK_OSC_GateOscRc400M(bool enableGate) +{ + if (enableGate) + { + ANADIG_OSC->OSC_400M_CTRL1 |= ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_MASK; + } + else + { + ANADIG_OSC->OSC_400M_CTRL1 &= ~ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_MASK; + } +} + +/*! + * @brief Trims OSC RC 400MHz. + * + * @param enable Used to enable trim function. + * @param bypass Bypass the trim function. + * @param trim Trim value. + */ +void CLOCK_OSC_TrimOscRc400M(bool enable, bool bypass, uint16_t trim); + +/*! + * @brief Set the divide value for ref_clk to generate slow clock. + * + * @note slow_clk = ref_clk / (divValue + 1), and the recommand divide value is 24. + * + * @param divValue The divide value to be set, the available range is 0~63. + */ +void CLOCK_OSC_SetOscRc400MRefClkDiv(uint8_t divValue); + +/*! + * @brief Set the target count for the fast clock. + * + * @param targetCount The desired target for the fast clock, should be the number of clock cycles of the fast_clk per + * divided ref_clk. + */ +void CLOCK_OSC_SetOscRc400MFastClkCount(uint16_t targetCount); + +/*! + * @brief Set the negative and positive hysteresis value for the tuned clock. + * + * @note The hysteresis value should be set after the clock is tuned. + * + * @param negHysteresis The negative hysteresis value for the turned clock, this value in number of clock cycles of the + * fast clock + * @param posHysteresis The positive hysteresis value for the turned clock, this value in number of clock cycles of the + * fast clock + */ +void CLOCK_OSC_SetOscRc400MHysteresisValue(uint8_t negHysteresis, uint8_t posHysteresis); + +/*! + * @brief Bypass/un-bypass the tune logic + * + * @param enableBypass Used to control whether to bypass the turn logic. + * - \b true Bypass the tune logic and use the programmed oscillator frequency to run the oscillator. + * Function CLOCK_OSC_SetOscRc400MTuneValue() can be used to set oscillator frequency. + * - \b false Use the output of tune logic to run the oscillator. + */ +void CLOCK_OSC_BypassOscRc400MTuneLogic(bool enableBypass); + +/*! + * @brief Start/Stop the tune logic. + * + * @param enable Used to start or stop the tune logic. + * - \b true Start tuning + * - \b false Stop tuning and reset the tuning logic. + */ +void CLOCK_OSC_EnableOscRc400MTuneLogic(bool enable); + +/*! + * @brief Freeze/Unfreeze the tuning value. + * + * @param enableFreeze Used to control whether to freeze the tune value. + * - \b true Freeze the tune at the current tuned value and the oscillator runs at tje frozen tune value. + * - \b false Unfreezes and continues the tune operation. + */ +void CLOCK_OSC_FreezeOscRc400MTuneValue(bool enableFreeze); + +/*! + * @brief Set the 400MHz RC oscillator tune value when the tune logic is disabled. + * + * @param tuneValue The tune value to determine the frequency of Oscillator. + */ +void CLOCK_OSC_SetOscRc400MTuneValue(uint8_t tuneValue); + +/*! + * @brief Set the behavior of the 1MHz output clock, such as disable the 1MHz clock output, + * enable the free-running 1MHz clock output, enable the locked 1MHz clock output. + * + * @note The 1MHz clock is divided from 400M RC Oscillator. + * + * @param behavior The behavior of 1MHz output clock, please refer to @ref clock_1MHzOut_behavior_t for details. + */ +void CLOCK_OSC_Set1MHzOutputBehavior(clock_1MHzOut_behavior_t behavior); + +/*! + * @brief Set the count for the locked 1MHz clock out. + * + * @param count Used to set the desired target for the locked 1MHz clock out, the value in number of clock cycles of the + * fast clock per divided ref_clk. + */ +void CLOCK_OSC_SetLocked1MHzCount(uint16_t count); + +/*! + * @brief Check the error flag for locked 1MHz clock out. + * + * @return The error flag for locked 1MHz clock out. + * - \b true The count value has been reached within one diviced ref clock period + * - \b false No effect. + */ +bool CLOCK_OSC_CheckLocked1MHzErrorFlag(void); + +/*! + * @brief Clear the error flag for locked 1MHz clock out. + */ +void CLOCK_OSC_ClearLocked1MHzErrorFlag(void); + +/*! + * @brief Get current count for the fast clock during the tune process. + * + * @return The current count for the fast clock. + */ +uint16_t CLOCK_OSC_GetCurrentOscRc400MFastClockCount(void); + +/*! + * @brief Get current tune value used by oscillator during tune process. + * + * @return The current tune value. + */ +uint8_t CLOCK_OSC_GetCurrentOscRc400MTuneValue(void); + +/*! + * @brief Set the control mode of 16MHz crystal oscillator. + * + * @param controlMode The control mode to be set, please refer to @ref clock_control_mode_t. + */ +static inline void CLOCK_OSC_SetOsc16MControlMode(clock_control_mode_t controlMode) +{ + ANADIG_OSC->OSC_16M_CTRL = (ANADIG_OSC->OSC_16M_CTRL & (~ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_MASK)) | + ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE(controlMode); +} + +/*! + * @brief Configure the 16MHz oscillator. + * + * @param source Used to select the source for 16MHz RC oscillator, please refer to @ref clock_16MOsc_source_t. + * @param enablePowerSave Enable/disable power save mode function at 16MHz OSC. + * - \b true Enable power save mode function at 16MHz osc. + * - \b false Disable power save mode function at 16MHz osc. + * @param enableClockOut Enable/Disable clock output for 16MHz RCOSC. + * - \b true Enable clock output for 16MHz RCOSC. + * - \b false Disable clock output for 16MHz RCOSC. + */ +void CLOCK_OSC_SetOsc16MConfig(clock_16MOsc_source_t source, bool enablePowerSave, bool enableClockOut); + +/* @} */ + +/*! + * @brief Initialize the ARM PLL. + * + * This function initialize the ARM PLL with specific settings + * + * @param config configuration to set to PLL. + */ +void CLOCK_InitArmPll(const clock_arm_pll_config_t *config); + +/*! + * @brief Calculate corresponding config values per given frequency + * + * This function calculates config valudes per given frequency for Arm PLL + * + * @param config pll config structure + * @param freqInMhz target frequency + */ +status_t CLOCK_CalcArmPllFreq(clock_arm_pll_config_t *config, uint32_t freqInMhz); + +/*! + * @brief Initializes the Arm PLL with Specific Frequency (in Mhz). + * + * This function initializes the Arm PLL with specific frequency + * + * @param freqInMhz target frequency + */ +status_t CLOCK_InitArmPllWithFreq(uint32_t freqInMhz); + +/*! + * @brief De-initialize the ARM PLL. + */ +void CLOCK_DeinitArmPll(void); + +/*! + * @brief Calculate spread spectrum step and stop. + * + * This function calculate spread spectrum step and stop according to given + * parameters. For integer PLL (syspll2) the factor is mfd, while for other + * fractional PLLs (audio/video/syspll1), the factor is denominator. + * + * @param factor factor to calculate step/stop + * @param range spread spectrum range + * @param mod spread spectrum modulation frequency + * @param ss calculated spread spectrum values + * + */ +void CLOCK_CalcPllSpreadSpectrum(uint32_t factor, uint32_t range, uint32_t mod, clock_pll_ss_config_t *ss); + +/*! + * @brief Initialize the System PLL1. + * + * This function initializes the System PLL1 with specific settings + * + * @param config Configuration to set to PLL1. + */ +void CLOCK_InitSysPll1(const clock_sys_pll1_config_t *config); + +/*! + * @brief De-initialize the System PLL1. + */ +void CLOCK_DeinitSysPll1(void); + +/*! + * @brief Set System PLL1 output frequency in GPC mode. + * + * @param config Pointer to @ref clock_sys_pll1_gpc_config_t. + */ +void CLOCK_GPC_SetSysPll1OutputFreq(const clock_sys_pll1_gpc_config_t *config); + +/*! + * @brief Initialize the System PLL2. + * + * This function initializes the System PLL2 with specific settings + * + * @param config Configuration to configure spread spectrum. This parameter can + * be NULL, if no need to enabled spread spectrum + */ +void CLOCK_InitSysPll2(const clock_sys_pll2_config_t *config); + +/*! + * @brief De-initialize the System PLL2. + */ +void CLOCK_DeinitSysPll2(void); + +/*! + * @brief Check if Sys PLL2 PFD is enabled + * + * @param pfd PFD control name + * @return PFD bypass status. + * - true: power on. + * - false: power off. + * @note Only useful in software control mode. + */ +bool CLOCK_IsSysPll2PfdEnabled(clock_pfd_t pfd); + +/*! + * @brief Initialize the System PLL3. + * + * This function initializes the System PLL3 with specific settings + * + */ +void CLOCK_InitSysPll3(void); + +/*! + * @brief De-initialize the System PLL3. + */ +void CLOCK_DeinitSysPll3(void); + +/*! + * @brief Check if Sys PLL3 PFD is enabled + * + * @param pfd PFD control name + * @return PFD bypass status. + * - true: power on. + * - false: power off. + * @note Only useful in software control mode. + */ +bool CLOCK_IsSysPll3PfdEnabled(clock_pfd_t pfd); + +/*! + * @name PLL/PFD operations + * @{ + */ +/*! + * @brief PLL bypass setting + * + * @param pll PLL control name (see @ref clock_pll_t enumeration) + * @param bypass Bypass the PLL. + * - true: Bypass the PLL. + * - false:Not bypass the PLL. + */ +void CLOCK_SetPllBypass(clock_pll_t pll, bool bypass); + +/*! + * @brief Calculate corresponding config values per given frequency + * + * This function calculates config valudes per given frequency for Audio/Video + * PLL. + * + * @param config pll config structure + * @param freqInMhz target frequency + */ +status_t CLOCK_CalcAvPllFreq(clock_av_pll_config_t *config, uint32_t freqInMhz); + +/*! + * @brief Initializes the Audio PLL with Specific Frequency (in Mhz). + * + * This function initializes the Audio PLL with specific frequency + * + * @param freqInMhz target frequency + * @param ssEnable enable spread spectrum or not + * @param ssRange range spread spectrum range + * @param ssMod spread spectrum modulation frequency + */ +status_t CLOCK_InitAudioPllWithFreq(uint32_t freqInMhz, bool ssEnable, uint32_t ssRange, uint32_t ssMod); + +/*! + * @brief Initializes the Audio PLL. + * + * This function initializes the Audio PLL with specific settings + * + * @param config Configuration to set to PLL. + */ +void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config); + +/*! + * @brief De-initialize the Audio PLL. + */ +void CLOCK_DeinitAudioPll(void); + +/*! + * @brief Set Audio PLL output frequency in GPC mode. + * + * @param config Pointer to clock_audio_pll_gpc_config_t structure. + */ +void CLOCK_GPC_SetAudioPllOutputFreq(const clock_audio_pll_gpc_config_t *config); + +/*! + * @brief Initializes the Video PLL with Specific Frequency (in Mhz). + * + * This function initializes the Video PLL with specific frequency + * + * @param freqInMhz target frequency + * @param ssEnable enable spread spectrum or not + * @param ssRange range spread spectrum range + * @param ssMod spread spectrum modulation frequency + */ +status_t CLOCK_InitVideoPllWithFreq(uint32_t freqInMhz, bool ssEnable, uint32_t ssRange, uint32_t ssMod); + +/*! + * @brief Initialize the video PLL. + * + * This function configures the Video PLL with specific settings + * + * @param config configuration to set to PLL. + */ +void CLOCK_InitVideoPll(const clock_video_pll_config_t *config); + +/*! + * @brief De-initialize the Video PLL. + */ +void CLOCK_DeinitVideoPll(void); + +/*! + * @brief Set Video PLL output frequency in GPC mode. + * + * @param config Pointer to clock_audio_pll_gpc_config_t structure. + */ +void CLOCK_GPC_SetVideoPllOutputFreq(const clock_video_pll_gpc_config_t *config); +/*! + * @brief Get current PLL output frequency. + * + * This function get current output frequency of specific PLL + * + * @param pll pll name to get frequency. + * @return The PLL output frequency in hertz. + */ +uint32_t CLOCK_GetPllFreq(clock_pll_t pll); + +/*! + * @brief Initialize PLL PFD. + * + * This function initializes the System PLL PFD. During new value setting, + * the clock output is disabled to prevent glitch. + * + * @param pll Which PLL of targeting PFD to be operated. + * @param pfd Which PFD clock to enable. + * @param frac The PFD FRAC value. + * @note It is recommended that PFD settings are kept between 12-35. + */ +void CLOCK_InitPfd(clock_pll_t pll, clock_pfd_t pfd, uint8_t frac); + +/*! + * @brief De-initialize selected PLL PFD. + * + * @param pll Which PLL of targeting PFD to be operated. + * @param pfd Which PFD clock to enable. + */ +void CLOCK_DeinitPfd(clock_pll_t pll, clock_pfd_t pfd); + +/*! + * @brief Get current PFD output frequency. + * + * This function get current output frequency of specific System PLL PFD + * + * @param pll Which PLL of targeting PFD to be operated. + * @param pfd pfd name to get frequency. + * @return The PFD output frequency in hertz. + */ +uint32_t CLOCK_GetPfdFreq(clock_pll_t pll, clock_pfd_t pfd); + +uint32_t CLOCK_GetFreqFromObs(uint32_t obsSigIndex, uint32_t obsIndex); + +/*! @brief Enable USB HS clock. + * + * This function only enables the access to USB HS prepheral, upper layer + * should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY + * clock to use USB HS. + * + * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused. + * @param freq USB HS does not care about the clock source, so this parameter is ignored. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq); + +/*! @brief Enable USB HS clock. + * + * This function only enables the access to USB HS prepheral, upper layer + * should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY + * clock to use USB HS. + * + * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused. + * @param freq USB HS does not care about the clock source, so this parameter is ignored. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq); + +/*! @brief Enable USB HS PHY PLL clock. + * + * This function enables the internal 480MHz USB PHY PLL clock. + * + * @param src USB HS PHY PLL clock source. + * @param freq The frequency specified by src. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq); + +/*! @brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhs0PhyPllClock(void); + +/*! @brief Enable USB HS PHY PLL clock. + * + * This function enables the internal 480MHz USB PHY PLL clock. + * + * @param src USB HS PHY PLL clock source. + * @param freq The frequency specified by src. + * @retval true The clock is set successfully. + * @retval false The clock source is invalid to get proper USB HS clock. + */ +bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq); + +/*! @brief Disable USB HS PHY PLL clock. + * + * This function disables USB HS PHY PLL clock. + */ +void CLOCK_DisableUsbhs1PhyPllClock(void); + +/*! + * @brief Lock low power and access control mode for this clock. + * + * @note When this bit is set, bits 16-20 can not be changed until next system reset. + * + * @param name Clock source name, see \ref clock_name_t. + */ +static inline void CLOCK_OSCPLL_LockControlMode(clock_name_t name) +{ + CCM->OSCPLL[name].AUTHEN |= CCM_OSCPLL_AUTHEN_LOCK_MODE_MASK; +} + +/*! + * @brief Lock the value of Domain ID white list for this clock. + * + * @note Once locked, this bit and domain ID white list can not be changed until next system reset. + * + * @param name Clock source name, see \ref clock_name_t. + */ +static inline void CLOCK_OSCPLL_LockWhiteList(clock_name_t name) +{ + CCM->OSCPLL[name].AUTHEN |= CCM_OSCPLL_AUTHEN_LOCK_LIST_MASK; +} + +/*! + * @brief Set domain ID that can change this clock. + * + * @note If LOCK_LIST bit is set, domain ID white list can not be changed until next system reset. + * + * @param name Clock source name, see \ref clock_name_t. + * @param domainId Domains that on the whitelist can change this clock. + */ +static inline void CLOCK_OSCPLL_SetWhiteList(clock_name_t name, uint8_t domainId) +{ + CCM->OSCPLL[name].AUTHEN = + (CCM->OSCPLL[name].AUTHEN & ~CCM_OSCPLL_AUTHEN_WHITE_LIST_MASK) | CCM_OSCPLL_AUTHEN_WHITE_LIST(domainId); +} + +/*! + * @brief Check whether this clock implement SetPoint control scheme. + * + * @param name Clock source name, see \ref clock_name_t. + * @return Clock source SetPoint implement status. + * - true: SetPoint is implemented. + * - false: SetPoint is not implemented. + */ +static inline bool CLOCK_OSCPLL_IsSetPointImplemented(clock_name_t name) +{ + return (((CCM->OSCPLL[name].CONFIG & CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_MASK) >> + CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_SHIFT) != 0UL); +} + +/*! + * @brief Set this clock works in Unassigned Mode. + * + * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset. + * + * @param name Clock source name, see \ref clock_name_t. + */ +static inline void CLOCK_OSCPLL_ControlByUnassignedMode(clock_name_t name) +{ + CCM->OSCPLL[name].AUTHEN &= + ~(CCM_OSCPLL_AUTHEN_CPULPM_MASK | CCM_OSCPLL_AUTHEN_DOMAIN_MODE_MASK | CCM_OSCPLL_AUTHEN_SETPOINT_MODE_MASK); +} + +/*! + * @brief Set this clock works in SetPoint control Mode. + * + * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset. + * + * @param name Clock source name, see \ref clock_name_t. + * @param spValue Bit0~Bit15 hold value for Setpoint 0~16 respectively. + * A bitfield value of 0 implies clock will be shutdown in this Setpoint. + * A bitfield value of 1 implies clock will be turn on in this Setpoint. + * @param stbyValue Bit0~Bit15 hold value for Setpoint 0~16 standby. + * A bitfield value of 0 implies clock will be shutdown during standby. + * A bitfield value of 1 represent clock will keep Setpoint setting during standby. + */ +void CLOCK_OSCPLL_ControlBySetPointMode(clock_name_t name, uint16_t spValue, uint16_t stbyValue); + +/*! + * @brief Set this clock works in CPU Low Power Mode. + * + * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset. + * + * @param name Clock source name, see \ref clock_name_t. + * @param domainId Domains that on the whitelist can change this clock. + * @param level0,level1 Depend level of this clock. + */ +void CLOCK_OSCPLL_ControlByCpuLowPowerMode(clock_name_t name, + uint8_t domainId, + clock_level_t level0, + clock_level_t level1); + +/*! + * @brief Set clock depend level for current accessing domain. + * + * @note This setting only take effects in CPU Low Power Mode. + * + * @param name Clock source name, see \ref clock_name_t. + * @param level Depend level of this clock. + */ +static inline void CLOCK_OSCPLL_SetCurrentClockLevel(clock_name_t name, clock_level_t level) +{ + CCM->OSCPLL[name].DOMAINr = + (CCM->OSCPLL[name].DOMAINr & ~CCM_OSCPLL_DOMAIN_LEVEL_MASK) | CCM_OSCPLL_DOMAIN_LEVEL(level); +} + +/*! + * @brief Set this clock works in Domain Mode. + * + * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset. + * + * @param name Clock source name, see \ref clock_name_t. + * @param domainId Domains that on the whitelist can change this clock. + */ +static inline void CLOCK_OSCPLL_ControlByDomainMode(clock_name_t name, uint8_t domainId) +{ + CCM->OSCPLL[name].AUTHEN = + (CCM->OSCPLL[name].AUTHEN & + ~(CCM_OSCPLL_AUTHEN_CPULPM_MASK | CCM_OSCPLL_AUTHEN_SETPOINT_MODE_MASK | CCM_OSCPLL_AUTHEN_WHITE_LIST_MASK)) | + CCM_OSCPLL_AUTHEN_DOMAIN_MODE_MASK | CCM_OSCPLL_AUTHEN_WHITE_LIST(domainId); +} + +/*! + * @brief Lock low power and access control mode for this clock. + * + * @note When this bit is set, bits 16-20 can not be changed until next system reset. + * + * @param name Clock root name, see \ref clock_root_t. + */ +static inline void CLOCK_ROOT_LockControlMode(clock_root_t name) +{ + CCM->CLOCK_ROOT[name].AUTHEN |= CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE_MASK; +} + +/*! + * @brief Lock the value of Domain ID white list for this clock. + * + * @note Once locked, this bit and domain ID white list can not be changed until next system reset. + * + * @param name Clock root name, see \ref clock_root_t. + */ +static inline void CLOCK_ROOT_LockWhiteList(clock_root_t name) +{ + CCM->CLOCK_ROOT[name].AUTHEN |= CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_MASK; +} + +/*! + * @brief Set domain ID that can change this clock. + * + * @note If LOCK_LIST bit is set, domain ID white list can not be changed until next system reset. + * + * @param name Clock root name, see \ref clock_root_t. + * @param domainId Domains that on the whitelist can change this clock. + */ +static inline void CLOCK_ROOT_SetWhiteList(clock_root_t name, uint8_t domainId) +{ + CCM->CLOCK_ROOT[name].AUTHEN = (CCM->CLOCK_ROOT[name].AUTHEN & ~CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_MASK) | + CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST(domainId); +} + +/*! + * @brief Check whether this clock implement SetPoint control scheme. + * + * @param name Clock root name, see \ref clock_root_t. + * @return Clock root SetPoint implement status. + * - true: SetPoint is implemented. + * - false: SetPoint is not implemented. + */ +static inline bool CLOCK_ROOT_IsSetPointImplemented(clock_root_t name) +{ + return (((CCM->CLOCK_ROOT[name].CONFIG & CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT_MASK) >> + CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT_SHIFT) != 0UL); +} + +/*! + * @brief Set this clock works in Unassigned Mode. + * + * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset. + * + * @param name Clock root name, see \ref clock_root_t. + */ +static inline void CLOCK_ROOT_ControlByUnassignedMode(clock_root_t name) +{ + CCM->CLOCK_ROOT[name].AUTHEN &= + ~(CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_MASK | CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_MASK); +} + +/*! + * @brief Configure one SetPoint for this clock. + * + * @note SetPoint value could only be changed in Unassigend Mode. + * + * @param name Which clock root to set, see \ref clock_root_t. + * @param spIndex Which SetPoint of this clock root to set. + * @param config SetPoint config, see \ref clock_root_setpoint_config_t + */ +static inline void CLOCK_ROOT_ConfigSetPoint(clock_root_t name, + uint16_t spIndex, + const clock_root_setpoint_config_t *config) +{ + assert(config != NULL); + CCM->CLOCK_ROOT[name].SETPOINT[spIndex] = + CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_GRADE(config->grade) | + CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX(config->mux) | + CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV((uint32_t)config->div - 1UL) | + CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF(config->clockOff); +} + +/*! + * @brief Enable SetPoint control for this clock root. + * + * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset. + * + * @param name Clock root name, see \ref clock_root_t. + */ +static inline void CLOCK_ROOT_EnableSetPointControl(clock_root_t name) +{ + CCM->CLOCK_ROOT[name].AUTHEN = (CCM->CLOCK_ROOT[name].AUTHEN & ~CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_MASK) | + CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_MASK; +} + +/*! + * @brief Set this clock works in SetPoint controlled Mode. + * + * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset. + * + * @param name Clock root name, see \ref clock_root_t. + * @param spTable Point to the array that stores clock root settings for each setpoint. Note that the pointed array must + * have 16 elements. + */ +void CLOCK_ROOT_ControlBySetPointMode(clock_root_t name, const clock_root_setpoint_config_t *spTable); + +/*! + * @brief Set this clock works in CPU Low Power Mode. + * + * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset. + * + * @param name Clock root name, see \ref clock_root_t. + * @param domainId Domains that on the whitelist can change this clock. + */ +static inline void CLOCK_ROOT_ControlByDomainMode(clock_root_t name, uint8_t domainId) +{ + CCM->CLOCK_ROOT[name].AUTHEN = (CCM->CLOCK_ROOT[name].AUTHEN & ~(CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_MASK | + CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_MASK)) | + CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_MASK | CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST(domainId); +} + +/*! + * @brief Lock low power and access control mode for this clock. + * + * @note When this bit is set, bits 16-20 can not be changed until next system reset. + * + * @param name Clock gate name, see \ref clock_lpcg_t. + */ +static inline void CLOCK_LPCG_LockControlMode(clock_lpcg_t name) +{ + CCM->LPCG[name].AUTHEN |= CCM_LPCG_AUTHEN_LOCK_MODE_MASK; +} + +/*! + * @brief Lock the value of Domain ID white list for this clock. + * + * @note Once locked, this bit and domain ID white list can not be changed until next system reset. + * + * @param name Clock gate name, see \ref clock_lpcg_t. + */ +static inline void CLOCK_LPCG_LockWhiteList(clock_lpcg_t name) +{ + CCM->LPCG[name].AUTHEN |= CCM_LPCG_AUTHEN_LOCK_LIST_MASK; +} + +/*! + * @brief Set domain ID that can change this clock. + * + * @note If LOCK_LIST bit is set, domain ID white list can not be changed until next system reset. + * + * @param name Clock gate name, see \ref clock_lpcg_t. + * @param domainId Domains that on the whitelist can change this clock. + */ +static inline void CLOCK_LPCG_SetWhiteList(clock_lpcg_t name, uint8_t domainId) +{ + CCM->LPCG[name].AUTHEN = + (CCM->LPCG[name].AUTHEN & ~CCM_LPCG_AUTHEN_WHITE_LIST_MASK) | CCM_LPCG_AUTHEN_WHITE_LIST(domainId); +} + +/*! + * @brief Check whether this clock implement SetPoint control scheme. + * + * @param name Clock gate name, see \ref clock_lpcg_t. + * @return Clock gate SetPoint implement status. + * - true: SetPoint is implemented. + * - false: SetPoint is not implemented. + */ +static inline bool CLOCK_LPCG_IsSetPointImplemented(clock_lpcg_t name) +{ + return (((CCM->LPCG[name].CONFIG & CCM_LPCG_CONFIG_SETPOINT_PRESENT_MASK) >> + CCM_LPCG_CONFIG_SETPOINT_PRESENT_SHIFT) != 0UL); +} + +/*! + * @brief Set this clock works in Unassigned Mode. + * + * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset. + * + * @param name Clock gate name, see \ref clock_lpcg_t. + */ +static inline void CLOCK_LPCG_ControlByUnassignedMode(clock_lpcg_t name) +{ + CCM->LPCG[name].AUTHEN &= + ~(CCM_LPCG_AUTHEN_CPULPM_MASK | CCM_LPCG_AUTHEN_DOMAIN_MODE_MASK | CCM_LPCG_AUTHEN_SETPOINT_MODE_MASK); +} + +/*! + * @brief Set this clock works in SetPoint control Mode. + * + * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset. + * + * @param name Clock gate name, see \ref clock_lpcg_t. + * @param spValue Bit0~Bit15 hold value for Setpoint 0~16 respectively. + * A bitfield value of 0 implies clock will be shutdown in this Setpoint. + * A bitfield value of 1 implies clock will be turn on in this Setpoint. + * @param stbyValue Bit0~Bit15 hold value for Setpoint 0~16 standby. + * A bitfield value of 0 implies clock will be shutdown during standby. + * A bitfield value of 1 represent clock will keep Setpoint setting during standby. + */ +void CLOCK_LPCG_ControlBySetPointMode(clock_lpcg_t name, uint16_t spValue, uint16_t stbyValue); + +/*! + * @brief Set this clock works in CPU Low Power Mode. + * + * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset. + * + * @param name Clock gate name, see \ref clock_lpcg_t. + * @param domainId Domains that on the whitelist can change this clock. + * @param level0,level1 Depend level of this clock. + */ +void CLOCK_LPCG_ControlByCpuLowPowerMode(clock_lpcg_t name, + uint8_t domainId, + clock_level_t level0, + clock_level_t level1); + +/*! + * @brief Set clock depend level for current accessing domain. + * + * @note This setting only take effects in CPU Low Power Mode. + * + * @param name Clock gate name, see \ref clock_lpcg_t. + * @param level Depend level of this clock. + */ +static inline void CLOCK_LPCG_SetCurrentClockLevel(clock_lpcg_t name, clock_level_t level) +{ + CCM->LPCG[name].DOMAINr = (CCM->LPCG[name].DOMAINr & ~CCM_LPCG_DOMAIN_LEVEL_MASK) | CCM_LPCG_DOMAIN_LEVEL(level); +} + +/*! + * @brief Set this clock works in Domain Mode. + * + * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset. + * + * @param name Clock gate name, see \ref clock_lpcg_t. + * @param domainId Domains that on the whitelist can change this clock. + */ +static inline void CLOCK_LPCG_ControlByDomainMode(clock_lpcg_t name, uint8_t domainId) +{ + CCM->LPCG[name].AUTHEN = + (CCM->LPCG[name].AUTHEN & + ~(CCM_LPCG_AUTHEN_SETPOINT_MODE_MASK | CCM_LPCG_AUTHEN_CPULPM_MASK | CCM_LPCG_AUTHEN_WHITE_LIST_MASK)) | + CCM_LPCG_AUTHEN_DOMAIN_MODE_MASK | CCM_LPCG_AUTHEN_WHITE_LIST(domainId); +} + +/* @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_CLOCK_H_ */ diff --git a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_dcdc.c b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_dcdc.c new file mode 100644 index 0000000000..350c327afc --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_dcdc.c @@ -0,0 +1,518 @@ +/* + * Copyright 2020-2021 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_dcdc.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.dcdc_soc" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * brief Gets instance number for DCDC module. + * + * param base DCDC peripheral base address + */ +static uint32_t DCDC_GetInstance(DCDC_Type *base); + +/*! + * brief Converts the byte array to word. + * + * param ptrArray Pointer to the byte array. + * return The converted result. + */ +static uint32_t DCDC_ConvertByteArrayToWord(uint8_t *ptrArray); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! brief Pointers to DCDC bases for each instance. */ +static DCDC_Type *const s_dcdcBases[] = DCDC_BASE_PTRS; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +/*! brief Pointers to DCDC clocks for each instance. */ +static const clock_ip_name_t s_dcdcClocks[] = DCDC_CLOCKS; +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + +/******************************************************************************* + * CodDCDC_GetstatusFlagse + ******************************************************************************/ + +static uint32_t DCDC_GetInstance(DCDC_Type *base) +{ + uint32_t instance; + + /* Find the instance index from base address mappings. */ + for (instance = 0; instance < ARRAY_SIZE(s_dcdcBases); instance++) + { + if (s_dcdcBases[instance] == base) + { + break; + } + } + + assert(instance < ARRAY_SIZE(s_dcdcBases)); + + return instance; +} + +static uint32_t DCDC_ConvertByteArrayToWord(uint8_t *ptrArray) +{ + assert(ptrArray != NULL); + + uint32_t temp32 = 0UL; + uint32_t index; + + for (index = 0U; index < 4U; index++) + { + temp32 |= (uint32_t)ptrArray[index] << ((index % 4UL) * 8UL); + } + + return temp32; +} + +/*! + * brief Initializes the basic resource of DCDC module, such as control mode, etc. + * + * param base DCDC peripheral base address. + * param config Pointer to the configuration structure. + */ +void DCDC_Init(DCDC_Type *base, const dcdc_config_t *config) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_EnableClock(s_dcdcClocks[DCDC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + + uint32_t tmp32 = base->CTRL0; + + tmp32 |= DCDC_CTRL0_CONTROL_MODE(config->controlMode) | DCDC_CTRL0_TRIM_HOLD(config->trimInputMode); + + if (config->enableDcdcTimeout) + { + tmp32 |= DCDC_CTRL0_ENABLE_DCDC_CNT_MASK; + } + if (config->enableSwitchingConverterOutput) + { + tmp32 |= DCDC_CTRL0_DIG_EN_MASK; + } + tmp32 |= DCDC_CTRL0_ENABLE_MASK; + base->CTRL0 = tmp32; +} + +/*! + * brief De-initializes the DCDC module. + * + * param base DCDC peripheral base address. + */ +void DCDC_Deinit(DCDC_Type *base) +{ + /* Disables DCDC. */ + base->CTRL0 &= ~DCDC_CTRL0_ENABLE_MASK; +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ + CLOCK_DisableClock(s_dcdcClocks[DCDC_GetInstance(base)]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + +/*! + * brief Gets the default setting for DCDC, such as control mode, etc. + * + * This function initializes the user configuration structure to a default value. The default values are: + * code + * config->controlMode = kDCDC_StaticControl; + * config->trimInputMode = kDCDC_SampleTrimInput; + * config->enableDcdcTimeout = false; + * config->enableSwitchingConverterOutput = false; + * endcode + * + * param config Pointer to configuration structure. See to dcdc_config_t. + */ +void DCDC_GetDefaultConfig(dcdc_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->controlMode = kDCDC_StaticControl; + config->trimInputMode = kDCDC_SampleTrimInput; + config->enableDcdcTimeout = false; + config->enableSwitchingConverterOutput = false; +} + +/*! + * brief Gets the default setting for detection configuration. + * + * The default configuration are set according to responding registers' setting when powered on. + * They are: + * code + * config->enableXtalokDetection = false; + * config->powerDownOverVoltageVdd1P8Detection = true; + * config->powerDownOverVoltageVdd1P0Detection = true; + * config->powerDownLowVoltageDetection = false; + * config->powerDownOverCurrentDetection = true; + * config->powerDownPeakCurrentDetection = true; + * config->powerDownZeroCrossDetection = true; + * config->PeakCurrentThreshold = kDCDC_PeakCurrentRunMode250mALPMode1P5A; + * endcode + * + * param config Pointer to configuration structure. See to "dcdc_detection_config_t" + */ +void DCDC_GetDefaultDetectionConfig(dcdc_detection_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->enableXtalokDetection = false; + config->powerDownOverVoltageVdd1P8Detection = true; + config->powerDownOverVoltageVdd1P0Detection = true; + config->powerDownLowVoltageDetection = false; + config->powerDownOverCurrentDetection = true; + config->powerDownPeakCurrentDetection = true; + config->powerDownZeroCrossDetection = true; + config->PeakCurrentThreshold = kDCDC_PeakCurrentRunMode250mALPMode1P5A; +} + +/*! + * breif Configures the DCDC detection. + * + * param base DCDC peripheral base address. + * param config Pointer to configuration structure. See to "dcdc_detection_config_t" + */ +void DCDC_SetDetectionConfig(DCDC_Type *base, const dcdc_detection_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp32; + /* Configure the DCDC_REG0 register. */ + tmp32 = base->REG0 & + ~(DCDC_REG0_XTALOK_DISABLE_MASK | DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK | DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK | + DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK | DCDC_REG0_PWD_OVERCUR_DET_MASK | DCDC_REG0_PWD_CUR_SNS_CMP_MASK | + DCDC_REG0_PWD_ZCD_MASK | DCDC_REG0_CUR_SNS_THRSH_MASK); + + tmp32 |= DCDC_REG0_CUR_SNS_THRSH(config->PeakCurrentThreshold); + if (false == config->enableXtalokDetection) + { + tmp32 |= DCDC_REG0_XTALOK_DISABLE_MASK; + } + if (config->powerDownOverVoltageVdd1P8Detection) + { + tmp32 |= DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK; + } + if (config->powerDownOverVoltageVdd1P0Detection) + { + tmp32 |= DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK; + } + if (config->powerDownLowVoltageDetection) + { + tmp32 |= DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK; + } + if (config->powerDownOverCurrentDetection) + { + tmp32 |= DCDC_REG0_PWD_OVERCUR_DET_MASK; + } + if (config->powerDownPeakCurrentDetection) + { + tmp32 |= DCDC_REG0_PWD_CUR_SNS_CMP_MASK; + } + if (config->powerDownZeroCrossDetection) + { + tmp32 |= DCDC_REG0_PWD_ZCD_MASK; + } + base->REG0 = tmp32; +} + +/*! + * brief Configures the DCDC clock source. + * + * param base DCDC peripheral base address. + * param clockSource Clock source for DCDC. See to "dcdc_clock_source_t". + */ +void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource) +{ + uint32_t tmp32; + + /* Configure the DCDC_REG0 register. */ + tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | + DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_MASK); + switch (clockSource) + { + case kDCDC_ClockInternalOsc: + tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK; + break; + case kDCDC_ClockExternalOsc: + /* Choose the external clock and disable the internal clock. */ + tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_MASK; + break; + case kDCDC_ClockAutoSwitch: + /* Set to switch from internal ring osc to xtal 24M if auto mode is enabled. */ + tmp32 |= DCDC_REG0_XTAL_24M_OK_MASK; + break; + default: + assert(false); + break; + } + base->REG0 = tmp32; +} + +/*! + * brief Gets the default setting for low power configuration. + * + * The default configuration are set according to responding registers' setting when powered on. + * They are: + * code + * config->enableAdjustHystereticValue = false; + * endcode + * + * param config Pointer to configuration structure. See to "dcdc_low_power_config_t" + */ +void DCDC_GetDefaultLowPowerConfig(dcdc_low_power_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + config->enableAdjustHystereticValue = false; +} + +/*! + * brief Configures the DCDC low power. + * + * param base DCDC peripheral base address. + * param config Pointer to configuration structure. See to "dcdc_low_power_config_t". + */ +void DCDC_SetLowPowerConfig(DCDC_Type *base, const dcdc_low_power_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp32; + /* Configure the DCDC_REG0 register. */ + tmp32 = base->REG0 & ~(DCDC_REG0_LP_HIGH_HYS_MASK); + + if (config->enableAdjustHystereticValue) + { + tmp32 |= DCDC_REG0_LP_HIGH_HYS_MASK; + } + base->REG0 = tmp32; +} + +/*! + * brief Gets the default setting for loop control configuration. + * + * The default configuration are set according to responding registers' setting when powered on. + * They are: + * code + * config->enableCommonHysteresis = false; + * config->enableCommonThresholdDetection = false; + * config->enableInvertHysteresisSign = false; + * config->enableRCThresholdDetection = false; + * config->enableRCScaleCircuit = 0U; + * config->complementFeedForwardStep = 0U; + * config->controlParameterMagnitude = 2U; + * config->integralProportionalRatio = 2U; + * endcode + * + * param config Pointer to configuration structure. See to "dcdc_loop_control_config_t" + */ +void DCDC_GetDefaultLoopControlConfig(dcdc_loop_control_config_t *config) +{ + assert(NULL != config); + + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->enableCommonHysteresis = false; + config->enableCommonThresholdDetection = false; + config->enableInvertHysteresisSign = false; + config->enableRCThresholdDetection = false; + config->enableRCScaleCircuit = 0U; + config->complementFeedForwardStep = 0U; + config->controlParameterMagnitude = 2U; + config->integralProportionalRatio = 2U; +} + +/*! + * brief Configures the DCDC loop control. + * + * param base DCDC peripheral base address. + * param config Pointer to configuration structure. See to "dcdc_loop_control_config_t". + */ +void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp32; + + /* Configure the DCDC_REG1 register. */ + tmp32 = base->REG1 & ~(DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK | DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK | + DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK | DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK); + if (config->enableCommonHysteresis) + { + tmp32 |= DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK; + } + if (config->enableCommonThresholdDetection) + { + tmp32 |= DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK; + } + if (config->enableDifferentialHysteresis) + { + tmp32 |= DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK; + } + if (config->enableDifferentialThresholdDetection) + { + tmp32 |= DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK; + } + + base->REG1 = tmp32; + + /* configure the DCDC_REG2 register. */ + tmp32 = base->REG2 & ~(DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK | DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK | + DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK | DCDC_REG2_LOOPCTRL_DC_FF_MASK | + DCDC_REG2_LOOPCTRL_DC_R_MASK | DCDC_REG2_LOOPCTRL_DC_C_MASK); + tmp32 |= DCDC_REG2_LOOPCTRL_DC_FF(config->complementFeedForwardStep) | + DCDC_REG2_LOOPCTRL_DC_R(config->controlParameterMagnitude) | + DCDC_REG2_LOOPCTRL_DC_C(config->integralProportionalRatio) | + DCDC_REG2_LOOPCTRL_EN_RCSCALE(config->enableRCScaleCircuit); + if (config->enableInvertHysteresisSign) + { + tmp32 |= DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK; + } + if (config->enableRCThresholdDetection) + { + tmp32 |= DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK; + } + base->REG2 = tmp32; +} + +/*! + * brief Configures for the min power. + * + * param base DCDC peripheral base address. + * param config Pointer to configuration structure. See to "dcdc_min_power_config_t". + */ +void DCDC_SetMinPowerConfig(DCDC_Type *base, const dcdc_min_power_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp32; + + tmp32 = base->REG3 & ~DCDC_REG3_MINPWR_DC_HALFCLK_MASK; + if (config->enableUseHalfFreqForContinuous) + { + tmp32 |= DCDC_REG3_MINPWR_DC_HALFCLK_MASK; + } + base->REG3 = tmp32; +} + +/*! + * brief Configures the DCDC internal regulator. + * + * param base DCDC peripheral base address. + * param config Pointer to configuration structure. See to "dcdc_internal_regulator_config_t". + */ +void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regulator_config_t *config) +{ + assert(NULL != config); + + uint32_t tmp32; + + tmp32 = base->REG3 & ~DCDC_REG3_REG_FBK_SEL_MASK; + tmp32 |= DCDC_REG3_REG_FBK_SEL(config->feedbackPoint); + base->REG3 = tmp32; +} + +/*! + * brief Initializes DCDC module when the control mode selected as setpoint mode. + * + * note The function should be invoked in the initial step to config the + * DCDC via setpoint control mode. + * + * param base DCDC peripheral base address. + * param config The pointer to the structure dcdc_setpoint_config_t. + */ +void DCDC_SetPointInit(DCDC_Type *base, const dcdc_setpoint_config_t *config) +{ + assert(config != NULL); + + /* Enable DCDC Dig Logic. */ + base->REG5 = config->enableDigLogicMap; + + /* Set DCDC power mode. */ + base->REG6 = config->lowpowerMap; + base->REG7 = config->standbyMap; + base->REG7P = config->standbyLowpowerMap; + + /* Set target voltage of VDD1P8 in buck mode. */ + base->REG8 = DCDC_ConvertByteArrayToWord((uint8_t *)config->buckVDD1P8TargetVoltage); + base->REG9 = DCDC_ConvertByteArrayToWord((uint8_t *)config->buckVDD1P8TargetVoltage + 4U); + base->REG10 = DCDC_ConvertByteArrayToWord((uint8_t *)config->buckVDD1P8TargetVoltage + 8U); + base->REG11 = DCDC_ConvertByteArrayToWord((uint8_t *)config->buckVDD1P8TargetVoltage + 12U); + + /* Set target voltage of VDD1P0 in buck mode. */ + base->REG12 = DCDC_ConvertByteArrayToWord((uint8_t *)config->buckVDD1P0TargetVoltage); + base->REG13 = DCDC_ConvertByteArrayToWord((uint8_t *)config->buckVDD1P0TargetVoltage + 4U); + base->REG14 = DCDC_ConvertByteArrayToWord((uint8_t *)config->buckVDD1P0TargetVoltage + 8U); + base->REG15 = DCDC_ConvertByteArrayToWord((uint8_t *)config->buckVDD1P0TargetVoltage + 12U); + + /* Set target voltage of VDD1P8 in low power mode. */ + base->REG16 = DCDC_ConvertByteArrayToWord((uint8_t *)config->standbyVDD1P8TargetVoltage); + base->REG17 = DCDC_ConvertByteArrayToWord((uint8_t *)config->standbyVDD1P8TargetVoltage + 4U); + base->REG18 = DCDC_ConvertByteArrayToWord((uint8_t *)config->standbyVDD1P8TargetVoltage + 8U); + base->REG19 = DCDC_ConvertByteArrayToWord((uint8_t *)config->standbyVDD1P8TargetVoltage + 12U); + + /* Set target voltage of VDD1P0 in low power mode. */ + base->REG20 = DCDC_ConvertByteArrayToWord((uint8_t *)config->standbyVDD1P0TargetVoltage); + base->REG21 = DCDC_ConvertByteArrayToWord((uint8_t *)config->standbyVDD1P0TargetVoltage + 4U); + base->REG22 = DCDC_ConvertByteArrayToWord((uint8_t *)config->standbyVDD1P0TargetVoltage + 8U); + base->REG23 = DCDC_ConvertByteArrayToWord((uint8_t *)config->standbyVDD1P0TargetVoltage + 12U); + + /* Enable DCDC module. */ + base->REG4 = config->enableDCDCMap; +} + +/*! + * brief Boots DCDC into DCM(discontinous conduction mode). + * + * pwd_zcd=0x0; + * DM_CTRL = 1'b1; + * pwd_cmp_offset=0x0; + * dcdc_loopctrl_en_rcscale=0x3 or 0x5; + * DCM_set_ctrl=1'b1; + * + * param base DCDC peripheral base address. + */ +void DCDC_BootIntoDCM(DCDC_Type *base) +{ + base->REG0 &= ~(DCDC_REG0_PWD_ZCD_MASK | DCDC_REG0_PWD_CMP_OFFSET_MASK); + base->REG1 &= ~DCDC_REG1_RLOAD_REG_EN_LPSR_MASK; + base->REG1 |= DCDC_REG1_DM_CTRL_MASK; + base->REG2 = (~DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK & base->REG2) | DCDC_REG2_LOOPCTRL_EN_RCSCALE(0x5U); + base->REG3 &= ~(DCDC_REG3_DISABLE_IDLE_SKIP_MASK | DCDC_REG3_DISABLE_PULSE_SKIP_MASK); + base->REG3 |= DCDC_REG3_ENABLE_FF_MASK; +} + +/*! + * brief Boots DCDC into CCM(continous conduction mode). + * + * pwd_zcd=0x1; + * pwd_cmp_offset=0x0; + * dcdc_loopctrl_en_rcscale=0x3; + * + * param base DCDC peripheral base address. + */ +void DCDC_BootIntoCCM(DCDC_Type *base) +{ + base->REG0 = (~DCDC_REG0_PWD_CMP_OFFSET_MASK & base->REG0) | DCDC_REG0_PWD_ZCD_MASK; + base->REG2 = (~DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK & base->REG2) | DCDC_REG2_LOOPCTRL_EN_RCSCALE(0x3U); +} diff --git a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_dcdc.h b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_dcdc.h new file mode 100644 index 0000000000..e81d76d2d0 --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_dcdc.h @@ -0,0 +1,1013 @@ +/* + * Copyright 2020-2021 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __FSL_DCDC_H__ +#define __FSL_DCDC_H__ + +#include "fsl_common.h" + +/*! + * @addtogroup dcdc_soc + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief DCDC driver version. */ +#define FSL_DCDC_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*!< Version 2.1.1. */ + +/*! @brief The array of VDD1P0 target voltage in standby mode. */ +#define STANDBY_MODE_VDD1P0_TARGET_VOLTAGE \ + { \ + 625, 650, 675, 700, 725, 750, 775, 800, 825, 850, 875, 900, 925, 950, 975, 1000, 1025, 1050, 1075, 1100, 1125, \ + 1150, 1175, 1200, 1225, 1250, 1275, 1300, 1325, 1350, 1375, 1400 \ + } + +/*! @brief The array of VDD1P8 target voltage in standby mode. */ +#define STANDBY_MODE_VDD1P8_TARGET_VOLTAGE \ + { \ + 1525, 1550, 1575, 1600, 1625, 1650, 1675, 1700, 1725, 1750, 1775, 1800, 1825, 1850, 1875, 1900, 1925, 1950, \ + 1975, 2000, 2025, 2050, 2075, 2100, 2125, 2150, 2175, 2200, 2225, 2250, 2275, 2300 \ + } + +/*! @brief The array of VDD1P0 target voltage in buck mode. */ +#define BUCK_MODE_VDD1P0_TARGET_VOLTAGE \ + { \ + 600, 625, 650, 675, 700, 725, 750, 775, 800, 825, 850, 875, 900, 925, 950, 975, 1000, 1025, 1050, 1075, 1100, \ + 1125, 1150, 1175, 1200, 1225, 1250, 1275, 1300, 1325, 1350, 1375 \ + } + +/*! @brief The array of VDD1P8 target voltage in buck mode. */ +#define BUCK_MODE_VDD1P8_TARGET_VOLTAGE \ + { \ + 1500, 1525, 1550, 1575, 1600, 1625, 1650, 1675, 1700, 1725, 1750, 1775, 1800, 1825, 1850, 1875, 1900, 1925, \ + 1950, 1975, 2000, 2025, 2050, 2075, 2100, 2125, 2150, 2175, 2200, 2225, 2250, 2275 \ + } + +/*! + * @brief The enumeration of DCDC status flags. + */ +enum _dcdc_status_flags +{ + kDCDC_AlreadySettledStatusFlag = DCDC_REG0_STS_DC_OK_MASK, /*!< Indicate DCDC status. + 1'b1: DCDC already settled + 1'b0: DCDC is settling. */ +}; + +/*! + * @brief System setpoints enumeration. + */ +enum _dcdc_setpoint_map +{ + kDCDC_SetPoint0 = 1UL << 0UL, /*!< Set point 0. */ + kDCDC_SetPoint1 = 1UL << 1UL, /*!< Set point 1. */ + kDCDC_SetPoint2 = 1UL << 2UL, /*!< Set point 2. */ + kDCDC_SetPoint3 = 1UL << 3UL, /*!< Set point 3. */ + kDCDC_SetPoint4 = 1UL << 4UL, /*!< Set point 4. */ + kDCDC_SetPoint5 = 1UL << 5UL, /*!< Set point 5. */ + kDCDC_SetPoint6 = 1UL << 6UL, /*!< Set point 6. */ + kDCDC_SetPoint7 = 1UL << 7UL, /*!< Set point 7. */ + kDCDC_SetPoint8 = 1UL << 8UL, /*!< Set point 8. */ + kDCDC_SetPoint9 = 1UL << 9UL, /*!< Set point 9. */ + kDCDC_SetPoint10 = 1UL << 10UL, /*!< Set point 10. */ + kDCDC_SetPoint11 = 1UL << 11UL, /*!< Set point 11. */ + kDCDC_SetPoint12 = 1UL << 12UL, /*!< Set point 12. */ + kDCDC_SetPoint13 = 1UL << 13UL, /*!< Set point 13. */ + kDCDC_SetPoint14 = 1UL << 14UL, /*!< Set point 14. */ + kDCDC_SetPoint15 = 1UL << 15UL /*!< Set point 15. */ +}; + +/*! + * @brief DCDC control mode, including setpoint control mode and static control mode. + */ +typedef enum _dcdc_control_mode +{ + kDCDC_StaticControl = 0U, /*!< Static control. */ + kDCDC_SetPointControl = 1U, /*!< Controlled by GPC set points. */ +} dcdc_control_mode_t; + +/*! + * @brief DCDC trim input mode, including sample trim input and hold trim input. + */ +typedef enum _dcdc_trim_input_mode +{ + kDCDC_SampleTrimInput = 0U, /*!< Sample trim input. */ + kDCDC_HoldTrimInput = 1U, /*!< Hold trim input. */ +} dcdc_trim_input_mode_t; + +/*! + * @brief The enumeration VDD1P0's target voltage value in standby mode. + */ +typedef enum _dcdc_standby_mode_1P0_target_vol +{ + kDCDC_1P0StbyTarget0P625V = 0U, /*!< In standby mode, the target voltage value of VDD1P0 is 0.625V. */ + kDCDC_1P0StbyTarget0P65V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.65V. */ + kDCDC_1P0StbyTarget0P675V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.675V. */ + + kDCDC_1P0StbyTarget0P7V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.7V. */ + kDCDC_1P0StbyTarget0P725V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.725V. */ + kDCDC_1P0StbyTarget0P75V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.75V. */ + kDCDC_1P0StbyTarget0P775V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.775V. */ + + kDCDC_1P0StbyTarget0P8V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.8V. */ + kDCDC_1P0StbyTarget0P825V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.825V. */ + kDCDC_1P0StbyTarget0P85V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.85V. */ + kDCDC_1P0StbyTarget0P875V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.875V. */ + + kDCDC_1P0StbyTarget0P9V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.9V. */ + kDCDC_1P0StbyTarget0P925V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.925V. */ + kDCDC_1P0StbyTarget0P95V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.95V. */ + kDCDC_1P0StbyTarget0P975V, /*!< In standby mode, the target voltage value of VDD1P0 is 0.975V. */ + + kDCDC_1P0StbyTarget1P0V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.0V. */ + kDCDC_1P0StbyTarget1P025V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.025V. */ + kDCDC_1P0StbyTarget1P05V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.05V. */ + kDCDC_1P0StbyTarget1P075V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.075V. */ + + kDCDC_1P0StbyTarget1P1V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.1V. */ + kDCDC_1P0StbyTarget1P125V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.125V. */ + kDCDC_1P0StbyTarget1P15V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.15V. */ + kDCDC_1P0StbyTarget1P175V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.175V. */ + + kDCDC_1P0StbyTarget1P2V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.2V. */ + kDCDC_1P0StbyTarget1P225V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.225V. */ + kDCDC_1P0StbyTarget1P25V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.25V. */ + kDCDC_1P0StbyTarget1P275V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.275V. */ + + kDCDC_1P0StbyTarget1P3V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.3V. */ + kDCDC_1P0StbyTarget1P325V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.325V. */ + kDCDC_1P0StbyTarget1P35V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.35V. */ + kDCDC_1P0StbyTarget1P375V, /*!< In standby mode, the target voltage value of VDD1P0 is 1.375V. */ + + kDCDC_1P0StbyTarget1P4V = 0x1FU, /*!< In standby mode, The target voltage value of VDD1P0 is 1.4V */ +} dcdc_standby_mode_1P0_target_vol_t; + +/*! + * @brief The enumeration VDD1P8's target voltage value in standby mode. + */ +typedef enum _dcdc_standby_mode_1P8_target_vol +{ + kDCDC_1P8StbyTarget1P525V = 0U, /*!< In standby mode, the target voltage value of VDD1P8 is 1.525V. */ + kDCDC_1P8StbyTarget1P55V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.55V. */ + kDCDC_1P8StbyTarget1P575V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.575V. */ + + kDCDC_1P8StbyTarget1P6V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.6V. */ + kDCDC_1P8StbyTarget1P625V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.625V. */ + kDCDC_1P8StbyTarget1P65V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.65V. */ + kDCDC_1P8StbyTarget1P675V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.675V. */ + + kDCDC_1P8StbyTarget1P7V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.7V. */ + kDCDC_1P8StbyTarget1P725V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.725V. */ + kDCDC_1P8StbyTarget1P75V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.75V. */ + kDCDC_1P8StbyTarget1P775V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.775V. */ + + kDCDC_1P8StbyTarget1P8V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.8V. */ + kDCDC_1P8StbyTarget1P825V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.825V. */ + kDCDC_1P8StbyTarget1P85V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.85V. */ + kDCDC_1P8StbyTarget1P875V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.875V. */ + + kDCDC_1P8StbyTarget1P9V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.9V. */ + kDCDC_1P8StbyTarget1P925V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.925V. */ + kDCDC_1P8StbyTarget1P95V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.95V. */ + kDCDC_1P8StbyTarget1P975V, /*!< In standby mode, the target voltage value of VDD1P8 is 1.975V. */ + + kDCDC_1P8StbyTarget2P0V, /*!< In standby mode, the target voltage value of VDD1P8 is 2.0V. */ + kDCDC_1P8StbyTarget2P025V, /*!< In standby mode, the target voltage value of VDD1P8 is 2.025V. */ + kDCDC_1P8StbyTarget2P05V, /*!< In standby mode, the target voltage value of VDD1P8 is 2.05V. */ + kDCDC_1P8StbyTarget2P075V, /*!< In standby mode, the target voltage value of VDD1P8 is 2.075V. */ + + kDCDC_1P8StbyTarget2P1V, /*!< In standby mode, the target voltage value of VDD1P8 is 2.1V. */ + kDCDC_1P8StbyTarget2P125V, /*!< In standby mode, the target voltage value of VDD1P8 is 2.125V. */ + kDCDC_1P8StbyTarget2P15V, /*!< In standby mode, the target voltage value of VDD1P8 is 2.15V. */ + kDCDC_1P8StbyTarget2P175V, /*!< In standby mode, the target voltage value of VDD1P8 is 2.175V. */ + + kDCDC_1P8StbyTarget2P2V, /*!< In standby mode, the target voltage value of VDD1P8 is 2.2V. */ + kDCDC_1P8StbyTarget2P225V, /*!< In standby mode, the target voltage value of VDD1P8 is 2.225V. */ + kDCDC_1P8StbyTarget2P25V, /*!< In standby mode, the target voltage value of VDD1P8 is 2.25V. */ + kDCDC_1P8StbyTarget2P275V, /*!< In standby mode, the target voltage value of VDD1P8 is 2.275V. */ + + kDCDC_1P8StbyTarget2P3V = 0x1FU, /*!< In standby mode, the target voltage value is 2.3V. */ +} dcdc_standby_mode_1P8_target_vol_t; + +/*! + * @brief The enumeration VDD1P0's target voltage value in buck mode. + */ +typedef enum _dcdc_buck_mode_1P0_target_vol +{ + kDCDC_1P0BuckTarget0P6V = 0U, /*!< In buck mode, the target voltage value of VDD1P0 is 0.6V. */ + kDCDC_1P0BuckTarget0P625V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.625V. */ + kDCDC_1P0BuckTarget0P65V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.65V. */ + kDCDC_1P0BuckTarget0P675V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.675V. */ + + kDCDC_1P0BuckTarget0P7V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.7V. */ + kDCDC_1P0BuckTarget0P725V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.725V. */ + kDCDC_1P0BuckTarget0P75V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.75V. */ + kDCDC_1P0BuckTarget0P775V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.775V. */ + + kDCDC_1P0BuckTarget0P8V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.8V. */ + kDCDC_1P0BuckTarget0P825V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.825V. */ + kDCDC_1P0BuckTarget0P85V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.85V. */ + kDCDC_1P0BuckTarget0P875V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.875V. */ + + kDCDC_1P0BuckTarget0P9V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.9V. */ + kDCDC_1P0BuckTarget0P925V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.925V. */ + kDCDC_1P0BuckTarget0P95V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.95V. */ + kDCDC_1P0BuckTarget0P975V, /*!< In buck mode, the target voltage value of VDD1P0 is 0.975V. */ + + kDCDC_1P0BuckTarget1P0V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.0V. */ + kDCDC_1P0BuckTarget1P025V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.025V. */ + kDCDC_1P0BuckTarget1P05V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.05V. */ + kDCDC_1P0BuckTarget1P075V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.075V. */ + + kDCDC_1P0BuckTarget1P1V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.1V. */ + kDCDC_1P0BuckTarget1P125V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.125V. */ + kDCDC_1P0BuckTarget1P15V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.15V. */ + kDCDC_1P0BuckTarget1P175V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.175V. */ + + kDCDC_1P0BuckTarget1P2V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.2V. */ + kDCDC_1P0BuckTarget1P225V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.225V. */ + kDCDC_1P0BuckTarget1P25V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.25V. */ + kDCDC_1P0BuckTarget1P275V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.275V. */ + + kDCDC_1P0BuckTarget1P3V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.3V. */ + kDCDC_1P0BuckTarget1P325V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.325V. */ + kDCDC_1P0BuckTarget1P35V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.35V. */ + kDCDC_1P0BuckTarget1P375V = 0x1FU, /*!< In buck mode, the target voltage value of VDD1P0 is 1.375V. */ +} dcdc_buck_mode_1P0_target_vol_t; + +/*! + * @brief The enumeration VDD1P8's target voltage value in buck mode. + */ +typedef enum _dcdc_buck_mode_1P8_target_vol +{ + kDCDC_1P8BuckTarget1P5V = 0U, /*!< In buck mode, the target voltage value of VDD1P0 is 1.5V. */ + kDCDC_1P8BuckTarget1P525V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.525V. */ + kDCDC_1P8BuckTarget1P55V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.55V. */ + kDCDC_1P8BuckTarget1P575V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.575V. */ + + kDCDC_1P8BuckTarget1P6V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.6V. */ + kDCDC_1P8BuckTarget1P625V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.625V. */ + kDCDC_1P8BuckTarget1P65V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.65V. */ + kDCDC_1P8BuckTarget1P675V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.675V. */ + + kDCDC_1P8BuckTarget1P7V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.7V. */ + kDCDC_1P8BuckTarget1P725V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.725V. */ + kDCDC_1P8BuckTarget1P75V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.75V. */ + kDCDC_1P8BuckTarget1P775V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.775V. */ + + kDCDC_1P8BuckTarget1P8V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.8V. */ + kDCDC_1P8BuckTarget1P825V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.825V. */ + kDCDC_1P8BuckTarget1P85V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.85V. */ + kDCDC_1P8BuckTarget1P875V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.875V. */ + + kDCDC_1P8BuckTarget1P9V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.9V. */ + kDCDC_1P8BuckTarget1P925V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.925V. */ + kDCDC_1P8BuckTarget1P95V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.95V. */ + kDCDC_1P8BuckTarget1P975V, /*!< In buck mode, the target voltage value of VDD1P0 is 1.975V. */ + + kDCDC_1P8BuckTarget2P0V, /*!< In buck mode, the target voltage value of VDD1P0 is 2.0V. */ + kDCDC_1P8BuckTarget2P025V, /*!< In buck mode, the target voltage value of VDD1P0 is 2.025V. */ + kDCDC_1P8BuckTarget2P05V, /*!< In buck mode, the target voltage value of VDD1P0 is 2.05V. */ + kDCDC_1P8BuckTarget2P075V, /*!< In buck mode, the target voltage value of VDD1P0 is 2.075V. */ + + kDCDC_1P8BuckTarget2P1V, /*!< In buck mode, the target voltage value of VDD1P0 is 2.1V. */ + kDCDC_1P8BuckTarget2P125V, /*!< In buck mode, the target voltage value of VDD1P0 is 2.125V. */ + kDCDC_1P8BuckTarget2P15V, /*!< In buck mode, the target voltage value of VDD1P0 is 2.15V. */ + kDCDC_1P8BuckTarget2P175V, /*!< In buck mode, the target voltage value of VDD1P0 is 2.175V. */ + + kDCDC_1P8BuckTarget2P2V, /*!< In buck mode, the target voltage value of VDD1P0 is 2.2V. */ + kDCDC_1P8BuckTarget2P225V, /*!< In buck mode, the target voltage value of VDD1P0 is 2.225V. */ + kDCDC_1P8BuckTarget2P25V, /*!< In buck mode, the target voltage value of VDD1P0 is 2.25V. */ + kDCDC_1P8BuckTarget2P275V = 0x1FU, /*!< In buck mode, the target voltage value of VDD1P0 is 2.275V. */ +} dcdc_buck_mode_1P8_target_vol_t; + +/*! + * @brief The current bias of low power comparator. + */ +typedef enum _dcdc_comparator_current_bias +{ + kDCDC_ComparatorCurrentBias50nA = 0U, /*!< The current bias of low power comparator is 50nA. */ + kDCDC_ComparatorCurrentBias100nA = 1U, /*!< The current bias of low power comparator is 100nA. */ + kDCDC_ComparatorCurrentBias200nA = 2U, /*!< The current bias of low power comparator is 200nA. */ + kDCDC_ComparatorCurrentBias400nA = 3U, /*!< The current bias of low power comparator is 400nA. */ +} dcdc_comparator_current_bias_t; + +/*! + * @brief The threshold if peak current detection. + */ +typedef enum _dcdc_peak_current_threshold +{ + kDCDC_PeakCurrentRunMode250mALPMode1P5A = 0U, /*!< Over peak current threshold in low power mode is 250mA, + in run mode is 1.5A */ + kDCDC_PeakCurrentRunMode200mALPMode1P5A, /*!< Over peak current threshold in low power mode is 200mA, + in run mode is 1.5A */ + kDCDC_PeakCurrentRunMode250mALPMode2A, /*!< Over peak current threshold in low power mode is 250mA, + in run mode is 2A */ + kDCDC_PeakCurrentRunMode200mALPMode2A, /*!< Over peak current threshold in low power mode is 200mA, + in run mode is 2A */ +} dcdc_peak_current_threshold_t; + +/*! + * @brief Oscillator clock option. + */ +typedef enum _dcdc_clock_source +{ + kDCDC_ClockAutoSwitch = 0U, /*!< Automatic clock switch from internal oscillator to external clock. */ + kDCDC_ClockInternalOsc = 1U, /*!< Use internal oscillator. */ + kDCDC_ClockExternalOsc = 2U, /*!< Use external 24M crystal oscillator. */ +} dcdc_clock_source_t; + +/*! + * @brief Voltage output option. + */ +typedef enum _dcdc_voltage_output_sel +{ + kDCDC_VoltageOutput1P8 = 0U, /*!< 1.8V output. */ + kDCDC_VoltageOutput1P0 = 1U, /*!< 1.0V output. */ +} dcdc_voltage_output_sel_t; + +/*! + * @brief Configuration for DCDC. + */ +typedef struct _dcdc_config +{ + dcdc_control_mode_t controlMode; /*!< DCDC control mode. */ + dcdc_trim_input_mode_t trimInputMode; /*!< Hold trim input. */ + bool enableDcdcTimeout; /*!< Enable internal count for DCDC_OK timeout. */ + bool enableSwitchingConverterOutput; /*!< Enable the VDDIO switching converter output.*/ +} dcdc_config_t; + +/*! + * @brief Configuration for min power setting. + */ +typedef struct _dcdc_min_power_config +{ + bool enableUseHalfFreqForContinuous; /*!< Set DCDC clock to half frequency for the continuous mode. */ +} dcdc_min_power_config_t; + +/*! + * @brief Configuration for DCDC detection. + */ +typedef struct _dcdc_detection_config +{ + bool enableXtalokDetection; /*!< Enable xtalok detection circuit. */ + bool powerDownOverVoltageVdd1P8Detection; /*!< Power down over-voltage detection comparator for VDD1P8. */ + bool powerDownOverVoltageVdd1P0Detection; /*!< Power down over-voltage detection comparator for VDD1P0. */ + bool powerDownLowVoltageDetection; /*!< Power down low-voltage detection comparator. */ + bool powerDownOverCurrentDetection; /*!< Power down over-current detection. */ + bool powerDownPeakCurrentDetection; /*!< Power down peak-current detection. */ + bool powerDownZeroCrossDetection; /*!< Power down the zero cross detection function for discontinuous conductor + mode. */ + dcdc_peak_current_threshold_t PeakCurrentThreshold; /*!< The threshold of peak current detection. */ +} dcdc_detection_config_t; + +/*! + * @brief Configuration for the loop control. + */ +typedef struct _dcdc_loop_control_config +{ + bool enableCommonHysteresis; /*!< Enable hysteresis in switching converter common mode analog comparators. + This feature will improve transient supply ripple and efficiency. */ + bool enableCommonThresholdDetection; /*!< Increase the threshold detection for common mode analog comparator. */ + bool enableDifferentialHysteresis; /*!< Enable hysteresis in switching converter differential mode analog + comparators. This feature will improve transient supply ripple and + efficiency. */ + bool enableDifferentialThresholdDetection; /*!< Increase the threshold detection for differential mode analog + comparators. */ + bool enableInvertHysteresisSign; /*!< Invert the sign of the hysteresis in DC-DC analog comparators. */ + bool enableRCThresholdDetection; /*!< Increase the threshold detection for RC scale circuit. */ + uint32_t enableRCScaleCircuit; /*!< Available range is 0~7. Enable analog circuit of DC-DC converter to respond + faster under transient load conditions. */ + uint32_t complementFeedForwardStep; /*!< Available range is 0~7. Two's complement feed forward step in duty cycle in + the switching DC-DC converter. Each time this field makes a transition from + 0x0, the loop filter of the DC-DC converter is stepped once by a value + proportional to the change. This can be used to force a certain control loop + behavior, such as improving response under known heavy load transients. */ + uint32_t controlParameterMagnitude; /*!< Available range is 0~15. Magnitude of proportional control parameter in the + switching DC-DC converter control loop. */ + uint32_t integralProportionalRatio; /*!< Available range is 0~3.Ratio of integral control parameter to proportional + control parameter in the switching DC-DC converter, and can be used to + optimize efficiency and loop response. */ +} dcdc_loop_control_config_t; + +/*! + * @brief Configuration for DCDC internal regulator. + */ +typedef struct _dcdc_internal_regulator_config +{ + uint32_t feedbackPoint; /*!< Available range is 0~3. Select the feedback point of the internal regulator. */ +} dcdc_internal_regulator_config_t; + +/*! + * @brief Configuration for DCDC low power. + */ +typedef struct _dcdc_low_power_config +{ + bool enableAdjustHystereticValue; /*!< Adjust hysteretic value in low power from 12.5mV to 25mV. */ +} dcdc_low_power_config_t; + +/*! + * @brief DCDC configuration in set point mode. + */ +typedef struct _dcdc_setpoint_config +{ + uint32_t enableDCDCMap; /*!< The setpoint map that enable the DCDC module. Should be the OR'ed value of @ref + _dcdc_setpoint_map. */ + uint32_t enableDigLogicMap; /*!< The setpoint map that enable the DCDC dig logic. Should be the OR'ed value of @ref + _dcdc_setpoint_map. */ + uint32_t lowpowerMap; /*!< The setpoint map that enable the DCDC Low powermode. Should be the OR'ed value of @ref + _dcdc_setpoint_map. */ + uint32_t standbyMap; /*!< The setpoint map that enable the DCDC standby mode. Should be the OR'ed value of @ref + _dcdc_setpoint_map. */ + uint32_t standbyLowpowerMap; /*!< The setpoint map that enable the DCDC low power mode, when the related setpoint is + in standby mode. Please refer to @ref _dcdc_setpoint_map. */ + dcdc_buck_mode_1P8_target_vol_t *buckVDD1P8TargetVoltage; /*!< Point to the array that store the target voltage + level of VDD1P8 in buck mode, please refer to + @ref dcdc_buck_mode_1P8_target_vol_t. Note that the + pointed array must have 16 elements. */ + dcdc_buck_mode_1P0_target_vol_t *buckVDD1P0TargetVoltage; /*!< Point to the array that store the target voltage + level of VDD1P0 in buck mode, please refer to + @ref dcdc_buck_mode_1P0_target_vol_t. Note that the + pointed array must have 16 elements. */ + dcdc_standby_mode_1P8_target_vol_t *standbyVDD1P8TargetVoltage; /*!< Point to the array that store the target + voltage level of VDD1P8 in standby mode, please + refer to @ref dcdc_standby_mode_1P8_target_vol_t. + Note that the pointed array must have 16 elements. */ + dcdc_standby_mode_1P0_target_vol_t *standbyVDD1P0TargetVoltage; /*!< Point to the array that store the target + voltage level of VDD1P0 in standby mode, please + refer to @ref dcdc_standby_mode_1P0_target_vol_t. + Note that the pointed array must have 16 elements. */ +} dcdc_setpoint_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +/*! + * @name Initialization and De-initialization Interfaces + * @{ + */ + +/*! + * @brief Initializes the basic resource of DCDC module, such as control mode, etc. + * + * @param base DCDC peripheral base address. + * @param config Pointer to the @ref dcdc_config_t structure. + */ +void DCDC_Init(DCDC_Type *base, const dcdc_config_t *config); + +/*! + * @brief De-initializes the DCDC module. + * + * @param base DCDC peripheral base address. + */ +void DCDC_Deinit(DCDC_Type *base); + +/*! + * @brief Gets the default setting for DCDC, such as control mode, etc. + * + * This function initializes the user configuration structure to a default value. The default values are: + * @code + * config->controlMode = kDCDC_StaticControl; + * config->trimInputMode = kDCDC_SampleTrimInput; + * config->enableDcdcTimeout = false; + * config->enableSwitchingConverterOutput = false; + * @endcode + * + * @param config Pointer to configuration structure. See to @ref dcdc_config_t. + */ +void DCDC_GetDefaultConfig(dcdc_config_t *config); + +/*! @} */ + +/*! + * @name Power Mode Related Interfaces + * @{ + */ + +/*! + * @brief Makes the DCDC enter into low power mode for GPC standby request or not. + * + * @param base DCDC peripheral base address. + * @param enable Used to control the behavior. + * - \b true Makes DCDC enter into low power mode for GPC standby mode. + */ +static inline void DCDC_EnterLowPowerModeViaStandbyRequest(DCDC_Type *base, bool enable) +{ + if (enable) + { + base->CTRL0 |= DCDC_CTRL0_STBY_LP_MODE_EN_MASK; + } + else + { + base->CTRL0 &= ~DCDC_CTRL0_STBY_LP_MODE_EN_MASK; + } +} + +/*! + * @brief Makes DCDC enter into low power mode or not, before entering low power mode must disable stepping for VDD1P8 + * and VDD1P0. + * + * @param base DCDC peripheral base address. + * @param enable Used to control the behavior. + * - \b true Makes DCDC enter into low power mode. + */ +static inline void DCDC_EnterLowPowerMode(DCDC_Type *base, bool enable) +{ + if (enable) + { + base->REG3 |= DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK | DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; + base->CTRL0 |= DCDC_CTRL0_LP_MODE_EN_MASK; + } + else + { + base->CTRL0 &= ~DCDC_CTRL0_LP_MODE_EN_MASK; + } +} + +/*! + * @brief Makes DCDC enter into standby mode or not. + * + * @param base DCDC peripheral base address. + * @param enable Used to control the behavior. + * - \b true Makes DCDC enter into standby mode. + */ +static inline void DCDC_EnterStandbyMode(DCDC_Type *base, bool enable) +{ + if (enable) + { + base->CTRL0 |= DCDC_CTRL0_STBY_EN_MASK; + } + else + { + base->CTRL0 &= ~DCDC_CTRL0_STBY_EN_MASK; + } +} + +/*! @} */ + +/*! + * @name Outputs' Target Voltage Related Interfaces + * @{ + */ + +/*! + * @brief Sets the target value(ranges from 0.625V to 1.4V) of VDD1P0 in standby mode, 25mV each step. + * + * @param base DCDC peripheral base address. + * @param targetVoltage The target value of VDD1P0 in standby mode, see @ref dcdc_standby_mode_1P0_target_vol_t. + */ +static inline void DCDC_SetVDD1P0StandbyModeTargetVoltage(DCDC_Type *base, + dcdc_standby_mode_1P0_target_vol_t targetVoltage) +{ + base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; + base->CTRL1 = + ((base->CTRL1) & (~DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK)) | DCDC_CTRL1_VDD1P0CTRL_STBY_TRG(targetVoltage); + while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) + { + } +} + +/*! + * @brief Gets the target value of VDD1P0 in standby mode, the result takes "mV" as the unit. + * + * @param base DCDC peripheral base address. + * + * @return The VDD1P0's voltage value in standby mode and the unit is "mV". + */ +static inline uint16_t DCDC_GetVDD1P0StandbyModeTargetVoltage(DCDC_Type *base) +{ + const uint16_t vdd1P0TargetVoltage[] = STANDBY_MODE_VDD1P0_TARGET_VOLTAGE; + uint32_t voltageValue = (base->CTRL1 & DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK) >> DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_SHIFT; + + return vdd1P0TargetVoltage[voltageValue]; +} + +/*! + * @brief Sets the target value(ranges from 1.525V to 2.3V) of VDD1P8 in standby mode, 25mV each step. + * + * @param base DCDC peripheral base address. + * @param targetVoltage The target value of VDD1P8 in standby mode, see @ref dcdc_standby_mode_1P8_target_vol_t. + */ +static inline void DCDC_SetVDD1P8StandbyModeTargetVoltage(DCDC_Type *base, + dcdc_standby_mode_1P8_target_vol_t targetVoltage) +{ + base->REG3 &= ~DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK; + base->CTRL1 = + ((base->CTRL1) & (~DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK)) | DCDC_CTRL1_VDD1P0CTRL_STBY_TRG(targetVoltage); + while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) + { + } +} + +/*! + * @brief Gets the target value of VDD1P8 in standby mode, the result takes "mV" as the unit. + * + * @param base DCDC peripheral base address. + * + * @return The VDD1P8's voltage value in standby mode and the unit is "mV". + */ +static inline uint16_t DCDC_GetVDD1P8StandbyModeTargetVoltage(DCDC_Type *base) +{ + const uint16_t vdd1P8TargetVoltage[] = STANDBY_MODE_VDD1P8_TARGET_VOLTAGE; + uint32_t voltageValue = (base->CTRL1 & DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_MASK) >> DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_SHIFT; + + return vdd1P8TargetVoltage[voltageValue]; +} + +/*! + * @brief Sets the target value(ranges from 0.6V to 1.375V) of VDD1P0 in buck mode, 25mV each step. + * + * @param base DCDC peripheral base address. + * @param targetVoltage The target value of VDD1P0 in buck mode, see @ref dcdc_buck_mode_1P0_target_vol_t. + */ +static inline void DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC_Type *base, dcdc_buck_mode_1P0_target_vol_t targetVoltage) +{ + base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; + base->CTRL1 = ((base->CTRL1 & (~DCDC_CTRL1_VDD1P0CTRL_TRG_MASK)) | DCDC_CTRL1_VDD1P0CTRL_TRG(targetVoltage)); + while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) + { + } +} + +/*! + * @brief Gets the target value of VDD1P0 in buck mode, the result takes "mV" as the unit. + * + * @param base DCDC peripheral base address. + * + * @return The VDD1P0's voltage value in buck mode and the unit is "mV". + */ +static inline uint16_t DCDC_GetVDD1P0BuckModeTargetVoltage(DCDC_Type *base) +{ + const uint16_t vdd1P0TargetVoltage[] = BUCK_MODE_VDD1P0_TARGET_VOLTAGE; + uint32_t voltageValue = (base->CTRL1 & DCDC_CTRL1_VDD1P0CTRL_TRG_MASK) >> DCDC_CTRL1_VDD1P0CTRL_TRG_SHIFT; + + return vdd1P0TargetVoltage[voltageValue]; +} + +/*! + * @brief Sets the target value(ranges from 1.5V to 2.275V) of VDD1P8 in buck mode, 25mV each step. + * + * @param base DCDC peripheral base address. + * @param targetVoltage The target value of VDD1P8 in buck mode, see @ref dcdc_buck_mode_1P8_target_vol_t. + */ +static inline void DCDC_SetVDD1P8BuckModeTargetVoltage(DCDC_Type *base, dcdc_buck_mode_1P8_target_vol_t targetVoltage) +{ + base->REG3 &= ~DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK; + base->CTRL1 = ((base->CTRL1 & (~DCDC_CTRL1_VDD1P8CTRL_TRG_MASK)) | DCDC_CTRL1_VDD1P8CTRL_TRG(targetVoltage)); + while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) + { + } +} + +/*! + * @brief Gets the target value of VDD1P8 in buck mode, the result takes "mV" as the unit. + * + * @param base DCDC peripheral base address. + * + * @return The VDD1P8's voltage value in buck mode and the unit is "mV". + */ +static inline uint16_t DCDC_GetVDD1P8BuckModeTargetVoltage(DCDC_Type *base) +{ + const uint16_t vdd1P8TargetVoltage[] = BUCK_MODE_VDD1P8_TARGET_VOLTAGE; + uint32_t voltageValue = (base->CTRL1 & DCDC_CTRL1_VDD1P8CTRL_TRG_MASK) >> DCDC_CTRL1_VDD1P8CTRL_TRG_SHIFT; + + return vdd1P8TargetVoltage[voltageValue]; +} + +/*! + * @brief Enables/Disables stepping for VDD1P0, before entering low power modes the stepping for VDD1P0 must be + * disabled. + * + * @param base DCDC peripheral base address. + * @param enable Used to control the behavior. + * - \b true Enables stepping for VDD1P0. + * - \b false Disables stepping for VDD1P0. + */ +static inline void DCDC_EnableVDD1P0TargetVoltageStepping(DCDC_Type *base, bool enable) +{ + if (enable) + { + base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; + } + else + { + base->REG3 |= DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; + } +} + +/*! + * @brief Enables/Disables stepping for VDD1P8, before entering low power modes the stepping for VDD1P8 must be + * disabled. + * + * @param base DCDC peripheral base address. + * @param enable Used to control the behavior. + * - \b true Enables stepping for VDD1P8. + * - \b false Disables stepping for VDD1P8. + */ +static inline void DCDC_EnableVDD1P8TargetVoltageStepping(DCDC_Type *base, bool enable) +{ + if (enable) + { + base->REG3 &= ~DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK; + } + else + { + base->REG3 |= DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK; + } +} + +/*! @} */ + +/*! + * @name Detection Related Inferfaces + * @{ + */ + +/*! + * @brief Gets the default setting for detection configuration. + * + * The default configuration are set according to responding registers' setting when powered on. + * They are: + * @code + * config->enableXtalokDetection = false; + * config->powerDownOverVoltageVdd1P8Detection = true; + * config->powerDownOverVoltageVdd1P0Detection = true; + * config->powerDownLowVoltageDetection = false; + * config->powerDownOverCurrentDetection = true; + * config->powerDownPeakCurrentDetection = true; + * config->powerDownZeroCrossDetection = true; + * config->OverCurrentThreshold = kDCDC_OverCurrentThresholdAlt0; + * config->PeakCurrentThreshold = kDCDC_PeakCurrentThresholdAlt0; + * @endcode + * + * @param config Pointer to configuration structure. See to @ref dcdc_detection_config_t. + */ +void DCDC_GetDefaultDetectionConfig(dcdc_detection_config_t *config); + +/*! + * @brief Configures the DCDC detection. + * + * @param base DCDC peripheral base address. + * @param config Pointer to configuration structure. See to @ref dcdc_detection_config_t. + */ +void DCDC_SetDetectionConfig(DCDC_Type *base, const dcdc_detection_config_t *config); + +/*! @} */ + +/*! + * @name DCDC Miscellaneous Inferfaces + * @{ + */ + +/*! + * @brief Enables/Disables the output range comparator. + * + * The output range comparator is disabled by default. + * + * @param base DCDC peripheral base address. + * @param enable Enable the feature or not. + * - \b true Enable the output range comparator. + * - \b false Disable the output range comparator. + */ +static inline void DCDC_EnableOutputRangeComparator(DCDC_Type *base, bool enable) +{ + if (enable) + { + base->REG0 &= ~DCDC_REG0_PWD_CMP_OFFSET_MASK; + } + else + { + base->REG0 |= DCDC_REG0_PWD_CMP_OFFSET_MASK; + } +} + +/*! + * @brief Configures the DCDC clock source. + * + * @param base DCDC peripheral base address. + * @param clockSource Clock source for DCDC. See to @ref dcdc_clock_source_t. + */ +void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource); + +/*! + * @brief Gets the default setting for low power configuration. + * + * The default configuration are set according to responding registers' setting when powered on. + * They are: + * @code + * config->enableAdjustHystereticValue = false; + * @endcode + * + * @param config Pointer to configuration structure. See to @ref dcdc_low_power_config_t. + */ +void DCDC_GetDefaultLowPowerConfig(dcdc_low_power_config_t *config); + +/*! + * @brief Configures the DCDC low power. + * + * @param base DCDC peripheral base address. + * @param config Pointer to configuration structure. See to @ref dcdc_low_power_config_t. + */ +void DCDC_SetLowPowerConfig(DCDC_Type *base, const dcdc_low_power_config_t *config); + +/*! + * @brief Sets the bangap trim value(0~31) to trim bandgap voltage. + * + * @param base DCDC peripheral base address. + * @param trimValue The bangap trim value. Available range is 0U-31U. + */ +static inline void DCDC_SetBandgapVoltageTrimValue(DCDC_Type *base, uint32_t trimValue) +{ + base->REG1 &= ~DCDC_REG1_VBG_TRIM_MASK; + base->REG1 |= DCDC_REG1_VBG_TRIM(trimValue); +} + +/*! + * @brief Gets the default setting for loop control configuration. + * + * The default configuration are set according to responding registers' setting when powered on. + * They are: + * @code + * config->enableCommonHysteresis = false; + * config->enableCommonThresholdDetection = false; + * config->enableInvertHysteresisSign = false; + * config->enableRCThresholdDetection = false; + * config->enableRCScaleCircuit = 0U; + * config->complementFeedForwardStep = 0U; + * config->controlParameterMagnitude = 2U; + * config->integralProportionalRatio = 2U; + * @endcode + * + * @param config Pointer to configuration structure. See to @ref dcdc_loop_control_config_t. + */ +void DCDC_GetDefaultLoopControlConfig(dcdc_loop_control_config_t *config); + +/*! + * @brief Configures the DCDC loop control. + * + * @param base DCDC peripheral base address. + * @param config Pointer to configuration structure. See to @ref dcdc_loop_control_config_t. + */ +void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t *config); + +/*! + * @brief Configures for the min power. + * + * @param base DCDC peripheral base address. + * @param config Pointer to configuration structure. See to @ref dcdc_min_power_config_t. + */ +void DCDC_SetMinPowerConfig(DCDC_Type *base, const dcdc_min_power_config_t *config); + +/*! + * @brief Sets the current bias of low power comparator. + * + * @param base DCDC peripheral base address. + * @param biasValue The current bias of low power comparator. Refer to @ref dcdc_comparator_current_bias_t. + */ +static inline void DCDC_SetLPComparatorBiasValue(DCDC_Type *base, dcdc_comparator_current_bias_t biasValue) +{ + base->REG1 &= ~DCDC_REG1_LP_CMP_ISRC_SEL_MASK; + base->REG1 |= DCDC_REG1_LP_CMP_ISRC_SEL(biasValue); +} + +/*! + * @brief Configures the DCDC internal regulator. + * + * @param base DCDC peripheral base address. + * @param config Pointer to configuration structure. See to @ref dcdc_internal_regulator_config_t. + */ +void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regulator_config_t *config); + +/*! + * @brief Adjusts delay to reduce ground noise. + * + * @param base DCDC peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void DCDC_EnableAdjustDelay(DCDC_Type *base, bool enable) +{ + if (enable) + { + base->REG3 |= DCDC_REG3_MISC_DELAY_TIMING_MASK; + } + else + { + base->REG3 &= ~DCDC_REG3_MISC_DELAY_TIMING_MASK; + } +} + +/*! + * @brief Enables/Disables to improve the transition from heavy load to light load. + * + * @note It is valid while zero cross detection is enabled. If ouput exceeds the threshold, DCDC would return CCM from + * DCM. + * + * @param base DCDC peripheral base address. + * @param enable Enable the feature or not. + */ +static inline void DCDC_EnableImproveTransition(DCDC_Type *base, bool enable) +{ + if (enable) + { + base->REG2 |= DCDC_REG2_DCM_SET_CTRL_MASK; + } + else + { + base->REG2 &= ~DCDC_REG2_DCM_SET_CTRL_MASK; + } +} +/*! @} */ + +/*! + * @name Setpoint Control Related Interfaces + */ + +/*! + * @brief Initializes DCDC module when the control mode selected as setpoint mode. + * + * @note The function should be invoked in the initial step to config the + * DCDC via setpoint control mode. + * + * @param base DCDC peripheral base address. + * @param config The pointer to the structure @ref dcdc_setpoint_config_t. + */ +void DCDC_SetPointInit(DCDC_Type *base, const dcdc_setpoint_config_t *config); + +/*! + * @brief Disable DCDC module when the control mode selected as setpoint mode. + * + * @param base DCDC peripheral base address. + * @param setpointMap The map of the setpoint to disable the DCDC module, + * Should be the OR'ed value of _dcdc_setpoint_map. + */ +static inline void DCDC_SetPointDeinit(DCDC_Type *base, uint32_t setpointMap) +{ + base->REG4 &= ~setpointMap; +} + +/*! @} */ + +/*! + * @name DCDC Status Related Interfaces + * @{ + */ + +/*! + * @brief Get DCDC status flags. + * + * @param base peripheral base address. + * @return Mask of asserted status flags. See to @ref _dcdc_status_flags. + */ +static inline uint32_t DCDC_GetStatusFlags(DCDC_Type *base) +{ + return (base->REG0 & DCDC_REG0_STS_DC_OK_MASK); +} + +/* @} */ + +/*! + * @name Application Guideline Interfaces + * @{ + */ + +/*! + * @brief Boots DCDC into DCM(discontinous conduction mode). + * + * @code + * pwd_zcd=0x0; + * DM_CTRL = 1'b1; + * pwd_cmp_offset=0x0; + * dcdc_loopctrl_en_rcscale=0x3 or 0x5; + * DCM_set_ctrl=1'b1; + * @endcode + * + * @param base DCDC peripheral base address. + */ +void DCDC_BootIntoDCM(DCDC_Type *base); + +/*! + * @brief Boots DCDC into CCM(continous conduction mode). + * + * @code + * pwd_zcd=0x1; + * pwd_cmp_offset=0x0; + * dcdc_loopctrl_en_rcscale=0x3; + * @endcode + * + * @param base DCDC peripheral base address. + */ +void DCDC_BootIntoCCM(DCDC_Type *base); + +/*! @} */ + +/*! + * @} + */ + +#endif /* __FSL_DCDC_H__ */ diff --git a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_flexram_allocate.c b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_flexram_allocate.c new file mode 100644 index 0000000000..32d99f7b4c --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_flexram_allocate.c @@ -0,0 +1,92 @@ +/* + * Copyright 2019-2021 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_flexram_allocate.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.soc_flexram_allocate" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * brief FLEXRAM allocate on-chip ram for OCRAM,ITCM,DTCM + * This function is independent of FLEXRAM_Init, it can be called directly if ram re-allocate + * is needed. + * param config allocate configuration. + * retval kStatus_InvalidArgument the argument is invalid + * kStatus_Success allocate success + */ +status_t FLEXRAM_AllocateRam(flexram_allocate_ram_t *config) +{ + assert(config != NULL); + + uint8_t dtcmBankNum = config->dtcmBankNum; + uint8_t itcmBankNum = config->itcmBankNum; + uint8_t ocramBankNum = config->ocramBankNum; + uint8_t i = 0U; + uint32_t bankCfg = 0U; + status_t status = kStatus_Success; + uint32_t tempGPR17 = 0U; + uint32_t tempGPR18 = 0U; + + /* check the arguments */ + if ((uint8_t)FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS < (dtcmBankNum + itcmBankNum + ocramBankNum)) + { + status = kStatus_InvalidArgument; + } + else + { + /* flexram bank config value */ + for (i = 0U; i < (uint8_t)FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS; i++) + { + if (i < ocramBankNum) + { + bankCfg |= ((uint32_t)kFLEXRAM_BankOCRAM) << (i * 2U); + continue; + } + + if (i < (dtcmBankNum + ocramBankNum)) + { + bankCfg |= ((uint32_t)kFLEXRAM_BankDTCM) << (i * 2U); + continue; + } + + if (i < (dtcmBankNum + ocramBankNum + itcmBankNum)) + { + bankCfg |= ((uint32_t)kFLEXRAM_BankITCM) << (i * 2U); + continue; + } + } + + tempGPR17 = IOMUXC_GPR->GPR17; + tempGPR18 = IOMUXC_GPR->GPR18; + + IOMUXC_GPR->GPR17 = (tempGPR17 & ~IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_MASK) | (bankCfg & 0xFFFFU); + IOMUXC_GPR->GPR18 = (tempGPR18 & ~IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_MASK) | ((bankCfg >> 16) & 0xFFFFU); + + /* select ram allocate source from FLEXRAM_BANK_CFG */ + FLEXRAM_SetAllocateRamSrc(kFLEXRAM_BankAllocateThroughBankCfg); + } + + return status; +} diff --git a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_flexram_allocate.h b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_flexram_allocate.h new file mode 100644 index 0000000000..6ba4152bcb --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_flexram_allocate.h @@ -0,0 +1,87 @@ +/* + * Copyright 2019-2021 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_FLEXRAM_ALLOCATE_H_ +#define _FSL_FLEXRAM_ALLOCATE_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup flexram + * @{ + */ + +/****************************************************************************** + * Definitions. + *****************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief SOC_FLEXRAM_ALLOCATE driver version 2.0.2. */ +#define FSL_SOC_FLEXRAM_ALLOCATE_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*@}*/ + +/*! @brief FLEXRAM bank type */ +enum +{ + kFLEXRAM_BankNotUsed = 0U, /*!< bank is not used */ + kFLEXRAM_BankOCRAM = 1U, /*!< bank is OCRAM */ + kFLEXRAM_BankDTCM = 2U, /*!< bank is DTCM */ + kFLEXRAM_BankITCM = 3U, /*!< bank is ITCM */ +}; + +/*! @brief FLEXRAM bank allocate source */ +typedef enum _flexram_bank_allocate_src +{ + kFLEXRAM_BankAllocateThroughHardwareFuse = 0U, /*!< allocate ram through hardware fuse value */ + kFLEXRAM_BankAllocateThroughBankCfg = 1U, /*!< allocate ram through FLEXRAM_BANK_CFG */ +} flexram_bank_allocate_src_t; + +/*! @brief FLEXRAM allocates OCRAM, ITCM, DTCM size. */ +typedef struct _flexram_allocate_ram +{ + const uint8_t ocramBankNum; /*!< OCRAM banknumber which the SOC support. */ + const uint8_t dtcmBankNum; /*!< DTCM bank number to allocate, the number should be power of 2. */ + const uint8_t itcmBankNum; /*!< ITCM bank number to allocate, the number should be power of 2. */ +} flexram_allocate_ram_t; + +/******************************************************************************* + * APIs + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief FLEXRAM allocates an on-chip ram for OCRAM, ITCM and DTCM. + * This function is independent from FLEXRAM_Init, and can be called directly if ram re-allocate + * is needed. + * @param config Allocate configuration. + * @retval #kStatus_InvalidArgument When the argument is invalid. + * @retval #kStatus_Success Upon allocate success. + */ +status_t FLEXRAM_AllocateRam(flexram_allocate_ram_t *config); + +/*! + * @brief FLEXRAM set allocate on-chip ram source. + * @param src Bank config source select value. + */ +static inline void FLEXRAM_SetAllocateRamSrc(flexram_bank_allocate_src_t src) +{ + IOMUXC_GPR->GPR16 &= ~IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK; + IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(src); +} + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif diff --git a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_gpc.c b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_gpc.c new file mode 100644 index 0000000000..4002aeb980 --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_gpc.c @@ -0,0 +1,335 @@ +/* + * Copyright 2019-2021 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_gpc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.gpc_3" +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*! @brief GPC submodule step registers offset */ +static uint32_t const s_cmRegOffset[] = GPC_CM_STEP_REG_OFFSET; + +static uint32_t const s_spRegOffset[] = GPC_SP_STEP_REG_OFFSET; + +static uint32_t const s_stbyRegOffset[] = GPC_STBY_STEP_REG_OFFSET; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Enable IRQ wakeup request. + * + * This function enables the IRQ request which can wakeup the CPU platform. + * + * param base GPC CPU module base address. + * param irqId ID of the IRQ, accessible range is 0-255. + * param enable Enable the IRQ request or not. + */ +void GPC_CM_EnableIrqWakeup(GPC_CPU_MODE_CTRL_Type *base, uint32_t irqId, bool enable) +{ + assert(irqId < (GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_COUNT * 32UL)); + + uint32_t irqGroup = irqId / 32UL; + uint32_t irqMask = irqId % 32UL; + + if (true == enable) + { + base->CM_IRQ_WAKEUP_MASK[irqGroup] &= ~(1UL << irqMask); + } + else + { + base->CM_IRQ_WAKEUP_MASK[irqGroup] |= (1UL << irqMask); + } +} + +/*! + * brief Get the status of the IRQ wakeup request. + * + * param base GPC CPU module base address. + * param irqId ID of the IRQ, accessible range is 0-255. + * return Indicate the IRQ request is asserted or not. + */ +bool GPC_CM_GetIrqWakeupStatus(GPC_CPU_MODE_CTRL_Type *base, uint32_t irqId) +{ + assert(irqId < (GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_COUNT * 32UL)); + + uint32_t irqGroup = irqId / 32UL; + uint32_t irqMask = irqId % 32UL; + bool irqStatus = false; + + irqStatus = (((base->CM_IRQ_WAKEUP_STAT[irqGroup] >> irqMask) & 0x1UL) == 0x1UL) ? true : false; + return irqStatus; +} + +/*! + * brief Config the cpu mode transition step. + * + * note This function can not config the setpoint sleep/wakeup operation for those + * operation is controlled by setpoint control. This funcion can not config the standby + * sleep/wakeup too, because those operation is controlled by standby controlled. + * + * param base GPC CPU module base address. + * param step step type, refer to "gpc_cm_tran_step_t". + * param config transition step configuration, refer to "gpc_tran_step_config_t". + */ +void GPC_CM_ConfigCpuModeTransitionStep(GPC_CPU_MODE_CTRL_Type *base, + gpc_cm_tran_step_t step, + const gpc_tran_step_config_t *config) +{ + if (!((step >= kGPC_CM_SleepSP) && (step <= kGPC_CM_WakeupSP))) + { + uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_cmRegOffset[step]); + + if (config->enableStep) + { + tmp32 &= ~(GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_MASK | + GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE_MASK); + tmp32 |= GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE(config->cntMode); + if (config->cntMode != kGPC_StepCounterDisableMode) + { + tmp32 |= GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT(config->stepCount); + } + tmp32 &= ~GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_MASK; + } + else + { + tmp32 |= GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_MASK; + } + *(uint32_t *)((uint32_t)base + s_cmRegOffset[step]) = tmp32; + } +} + +/*! + * brief Request a set point transition before the CPU transfers into a sleep mode. + * + * This function triggers the set point transition during a CPU Sleep/wakeup event and selects which one the CMC want + * to transfer to. + * + * param base GPC CPU module base address. + * param setPointSleep The set point CPU want the system to transit to on next CPU platform sleep sequence. + * param setPointWakeup The set point CPU want the system to transit to on next CPU platform wakeup sequence. + * param wakeupSel Select the set point transition on the next CPU platform wakeup sequence. + */ +void GPC_CM_RequestSleepModeSetPointTransition(GPC_CPU_MODE_CTRL_Type *base, + uint8_t setPointSleep, + uint8_t setPointWakeup, + gpc_cm_wakeup_sp_sel_t wakeupSel) +{ + uint32_t tmp32 = base->CM_SP_CTRL; + + tmp32 &= ~(GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN_MASK | GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_MASK | + GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_MASK | GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL_MASK); + /* Config set point transition in the next sleep sequence. */ + tmp32 |= + GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_EN_MASK | GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP(setPointSleep); + /* Config set point transition in the next wakeup sequence. */ + tmp32 |= GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_EN_MASK | + GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP(setPointWakeup) | + GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL(wakeupSel); + + base->CM_SP_CTRL = tmp32; +} + +/*! + * brief Request a set point transition during run mode. + * + * This function triggers the set point transition and selects which one the CMC want to transfer to. + * + * param base GPC CPU module base address. + * param setPointRun The set point CPU want the system to transit in the run mode. + */ +void GPC_CM_RequestRunModeSetPointTransition(GPC_CPU_MODE_CTRL_Type *base, uint8_t setPointRun) +{ + uint32_t tmp32 = base->CM_SP_CTRL; + + tmp32 &= ~(GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_MASK); + tmp32 |= GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN_MASK | GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN(setPointRun); + + base->CM_SP_CTRL = tmp32; + while ((base->CM_SP_CTRL & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN_MASK) != 0UL) + { + } +} + +/* + * brief Set the set point mapping value for each cpu mode. + * + * This function configures which set point is allowed when CPU enters RUN/WAIT/STOP/SUSPEND. If there are multiple + * setpoints, use: + * code + * map = kkGPC_SetPoint0 | kGPC_SetPoint1 | ... | kGPC_SetPoint15; + * encode + * + * param base GPC CPU module base address. + * param mode CPU mode. Refer to "gpc_cpu_mode_t". + * param map Map value of the set point. Refer to "_gpc_setpoint_map". + */ +void GPC_CM_SetCpuModeSetPointMapping(GPC_CPU_MODE_CTRL_Type *base, gpc_cpu_mode_t mode, uint32_t map) +{ + /* Ensure the allowed set point is in the accessible range (0-15). */ + map = map & 0xFFFFUL; + + switch (mode) + { + case kGPC_RunMode: + base->CM_RUN_MODE_MAPPING = map; + break; + case kGPC_WaitMode: + base->CM_WAIT_MODE_MAPPING = map; + break; + case kGPC_StopMode: + base->CM_STOP_MODE_MAPPING = map; + break; + case kGPC_SuspendMode: + base->CM_SUSPEND_MODE_MAPPING = map; + break; + default: + assert(false); + break; + } +} + +/* + * brief Request the chip into standby mode. + * + * param base GPC CPU module base address. + * param mode CPU mode. Refer to "gpc_cpu_mode_t". + */ +void GPC_CM_RequestStandbyMode(GPC_CPU_MODE_CTRL_Type *base, const gpc_cpu_mode_t mode) +{ + assert(mode != kGPC_RunMode); + + switch (mode) + { + case kGPC_WaitMode: + base->CM_STBY_CTRL |= GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAIT_MASK; + break; + case kGPC_StopMode: + base->CM_STBY_CTRL |= GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_STOP_MASK; + break; + case kGPC_SuspendMode: + base->CM_STBY_CTRL |= GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SUSPEND_MASK; + break; + default: + /* This branch should never be hit. */ + break; + } +} + +/* + * brief Clear the standby mode request. + * + * param base GPC CPU module base address. + * param mode CPU mode. Refer to "gpc_cpu_mode_t". + */ +void GPC_CM_ClearStandbyModeRequest(GPC_CPU_MODE_CTRL_Type *base, const gpc_cpu_mode_t mode) +{ + assert(mode != kGPC_RunMode); + + switch (mode) + { + case kGPC_WaitMode: + base->CM_STBY_CTRL &= ~GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAIT_MASK; + break; + case kGPC_StopMode: + base->CM_STBY_CTRL &= ~GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_STOP_MASK; + break; + case kGPC_SuspendMode: + base->CM_STBY_CTRL &= ~GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SUSPEND_MASK; + break; + default: + /* This branch should never be hit. */ + break; + } +} + +/*! + * brief Clears CPU module interrut status flags. + * + * param base GPC CPU module base address. + * param mask The interrupt status flags to be cleared. Should be the OR'ed value of _gpc_cm_interrupt_status_flag. + */ +void GPC_CM_ClearInterruptStatusFlags(GPC_CPU_MODE_CTRL_Type *base, uint32_t mask) +{ + uint32_t temp32; + + temp32 = base->CM_INT_CTRL; + temp32 &= ~(GPC_CM_ALL_INTERRUPT_STATUS); + base->CM_INT_CTRL = (mask | temp32); +} + +/*! + * brief Config the set point transition step. + * + * param base GPC Setpoint controller base address. + * param step step type, refer to "gpc_sp_tran_step_t". + * param config transition step configuration, refer to "gpc_tran_step_config_t". + */ +void GPC_SP_ConfigSetPointTransitionStep(GPC_SET_POINT_CTRL_Type *base, + gpc_sp_tran_step_t step, + const gpc_tran_step_config_t *config) +{ + uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_spRegOffset[step]); + + if (config->enableStep) + { + tmp32 &= + ~(GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT_MASK | GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_CNT_MODE_MASK); + tmp32 |= GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_CNT_MODE(config->cntMode); + if (config->cntMode != kGPC_StepCounterDisableMode) + { + tmp32 |= GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT(config->stepCount); + } + tmp32 &= ~GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_DISABLE_MASK; + } + else + { + tmp32 |= GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_DISABLE_MASK; + } + *(uint32_t *)((uint32_t)base + s_spRegOffset[step]) = tmp32; +} + +/*! + * brief Config the standby transition step. + * + * param base GPC Setpoint controller base address. + * param step step type, refer to "gpc_stby_tran_step_t". + * param config transition step configuration, refer to "gpc_tran_step_config_t". + */ +void GPC_STBY_ConfigStandbyTransitionStep(GPC_STBY_CTRL_Type *base, + gpc_stby_tran_step_t step, + const gpc_tran_step_config_t *config) +{ + uint32_t tmp32 = *(uint32_t *)((uint32_t)base + s_stbyRegOffset[step]); + + if (config->enableStep) + { + tmp32 &= ~(GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT_MASK | GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_CNT_MODE_MASK); + tmp32 |= GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_CNT_MODE(config->cntMode); + if (config->cntMode != kGPC_StepCounterDisableMode) + { + tmp32 |= GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT(config->stepCount); + } + tmp32 &= ~GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_DISABLE_MASK; + } + else + { + tmp32 |= GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_DISABLE_MASK; + } + *(uint32_t *)((uint32_t)base + s_stbyRegOffset[step]) = tmp32; +} diff --git a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_gpc.h b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_gpc.h new file mode 100644 index 0000000000..d1066e0831 --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_gpc.h @@ -0,0 +1,651 @@ +/* + * Copyright 2019-2021 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_GPC_H_ +#define _FSL_GPC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup gpc + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief GPC driver version 2.2.0. */ +#define FSL_GPC_RIVER_VERSION (MAKE_VERSION(2, 2, 0)) +/*! @}*/ + +#define GPC_RESERVED_USE_MACRO 0xFFFFFFFFU + +/* GPC CPU module step control register offset. */ +#define GPC_CM_SLEEP_SSAR_CTRL_OFFSET (0x200) +#define GPC_CM_SLEEP_LPCG_CTRL_OFFSET (0x208) +#define GPC_CM_SLEEP_PLL_CTRL_OFFSET (0x210) +#define GPC_CM_SLEEP_ISO_CTRL_OFFSET (0x218) +#define GPC_CM_SLEEP_RESET_CTRL_OFFSET (0x220) +#define GPC_CM_SLEEP_POWER_CTRL_OFFSET (0x228) +#define GPC_CM_WAKEUP_POWER_CTRL_OFFSET (0x290) +#define GPC_CM_WAKEUP_RESET_CTRL_OFFSET (0x298) +#define GPC_CM_WAKEUP_ISO_CTRL_OFFSET (0x2A0) +#define GPC_CM_WAKEUP_PLL_CTRL_OFFSET (0x2A8) +#define GPC_CM_WAKEUP_LPCG_CTRL_OFFSET (0x2B0) +#define GPC_CM_WAKEUP_SSAR_CTRL_OFFSET (0x2B8) + +/* GPC set point module step control register offset. */ +#define GPC_SP_SSAR_SAVE_CTRL_OFFSET (0x100) +#define GPC_SP_LPCG_OFF_CTRL_OFFSET (0x110) +#define GPC_SP_GROUP_DOWN_CTRL_OFFSET (0x120) +#define GPC_SP_ROOT_DOWN_CTRL_OFFSET (0x130) +#define GPC_SP_PLL_OFF_CTRL_OFFSET (0x140) +#define GPC_SP_ISO_ON_CTRL_OFFSET (0x150) +#define GPC_SP_RESET_EARLY_CTRL_OFFSET (0x160) +#define GPC_SP_POWER_OFF_CTRL_OFFSET (0x170) +#define GPC_SP_BIAS_OFF_CTRL_OFFSET (0x180) +#define GPC_SP_BG_PLDO_OFF_CTRL_OFFSET (0x190) +#define GPC_SP_LDO_PRE_CTRL_OFFSET (0x1A0) +#define GPC_SP_DCDC_DOWN_CTRL_OFFSET (0x1B0) +#define GPC_SP_DCDC_UP_CTRL_OFFSET (0x2B0) +#define GPC_SP_LDO_POST_CTRL_OFFSET (0x210) +#define GPC_SP_BG_PLDO_ON_CTRL_OFFSET (0x220) +#define GPC_SP_BIAS_ON_CTRL_OFFSET (0x230) +#define GPC_SP_POWER_ON_CTRL_OFFSET (0x240) +#define GPC_SP_RESET_LATE_CTRL_OFFSET (0x250) +#define GPC_SP_ISO_OFF_CTRL_OFFSET (0x260) +#define GPC_SP_PLL_ON_CTRL_OFFSET (0x270) +#define GPC_SP_ROOT_UP_CTRL_OFFSET (0x280) +#define GPC_SP_GROUP_UP_CTRL_OFFSET (0x290) +#define GPC_SP_LPCG_ON_CTRL_OFFSET (0x2A0) +#define GPC_SP_SSAR_RESTORE_CTRL_OFFSET (0x2B0) + +/* GPC standby module step control register offset. */ +#define GPC_STBY_LPCG_IN_CTRL_OFFSET (0xF0) +#define GPC_STBY_PLL_IN_CTRL_OFFSET (0x100) +#define GPC_STBY_BIAS_IN_CTRL_OFFSET (0x110) +#define GPC_STBY_PLDO_IN_CTRL_OFFSET (0x120) +#define GPC_STBY_BANDGAP_IN_CTRL_OFFSET (0x128) +#define GPC_STBY_LDO_IN_CTRL_OFFSET (0x130) +#define GPC_STBY_DCDC_IN_CTRL_OFFSET (0x140) +#define GPC_STBY_PMIC_IN_CTRL_OFFSET (0x150) +#define GPC_STBY_PMIC_OUT_CTRL_OFFSET (0x200) +#define GPC_STBY_DCDC_OUT_CTRL_OFFSET (0x210) +#define GPC_STBY_LDO_OUT_CTRL_OFFSET (0x220) +#define GPC_STBY_BANDGAP_OUT_CTRL_OFFSET (0x238) +#define GPC_STBY_PLDO_OUT_CTRL_OFFSET (0x238) +#define GPC_STBY_BIAS_OUT_CTRL_OFFSET (0x240) +#define GPC_STBY_PLL_OUT_CTRL_OFFSET (0x250) +#define GPC_STBY_LPCG_OUT_CTRL_OFFSET (0x260) + +/* GPC CPU module step register offset. */ +#define GPC_CM_STEP_REG_OFFSET \ + { \ + GPC_CM_SLEEP_SSAR_CTRL_OFFSET, GPC_CM_SLEEP_LPCG_CTRL_OFFSET, GPC_CM_SLEEP_PLL_CTRL_OFFSET, \ + GPC_CM_SLEEP_ISO_CTRL_OFFSET, GPC_CM_SLEEP_RESET_CTRL_OFFSET, GPC_CM_SLEEP_POWER_CTRL_OFFSET, \ + GPC_RESERVED_USE_MACRO, GPC_RESERVED_USE_MACRO, GPC_RESERVED_USE_MACRO, GPC_RESERVED_USE_MACRO, \ + GPC_CM_WAKEUP_POWER_CTRL_OFFSET, GPC_CM_WAKEUP_RESET_CTRL_OFFSET, GPC_CM_WAKEUP_ISO_CTRL_OFFSET, \ + GPC_CM_WAKEUP_PLL_CTRL_OFFSET, GPC_CM_WAKEUP_LPCG_CTRL_OFFSET, GPC_CM_WAKEUP_SSAR_CTRL_OFFSET, \ + } + +/* GPC set point module step control register offset. */ +#define GPC_SP_STEP_REG_OFFSET \ + { \ + GPC_SP_SSAR_SAVE_CTRL_OFFSET, GPC_SP_LPCG_OFF_CTRL_OFFSET, GPC_SP_GROUP_DOWN_CTRL_OFFSET, \ + GPC_SP_ROOT_DOWN_CTRL_OFFSET, GPC_SP_PLL_OFF_CTRL_OFFSET, GPC_SP_ISO_ON_CTRL_OFFSET, \ + GPC_SP_RESET_EARLY_CTRL_OFFSET, GPC_SP_POWER_OFF_CTRL_OFFSET, GPC_SP_BIAS_OFF_CTRL_OFFSET, \ + GPC_SP_BG_PLDO_OFF_CTRL_OFFSET, GPC_SP_LDO_PRE_CTRL_OFFSET, GPC_SP_DCDC_DOWN_CTRL_OFFSET, \ + GPC_SP_DCDC_UP_CTRL_OFFSET, GPC_SP_LDO_POST_CTRL_OFFSET, GPC_SP_BG_PLDO_ON_CTRL_OFFSET, \ + GPC_SP_BIAS_ON_CTRL_OFFSET, GPC_SP_POWER_ON_CTRL_OFFSET, GPC_SP_RESET_LATE_CTRL_OFFSET, \ + GPC_SP_ISO_OFF_CTRL_OFFSET, GPC_SP_PLL_ON_CTRL_OFFSET, GPC_SP_ROOT_UP_CTRL_OFFSET, \ + GPC_SP_GROUP_UP_CTRL_OFFSET, GPC_SP_LPCG_ON_CTRL_OFFSET, GPC_SP_SSAR_RESTORE_CTRL_OFFSET, \ + } + +/* GPC standby module step register offset. */ +#define GPC_STBY_STEP_REG_OFFSET \ + { \ + GPC_STBY_LPCG_IN_CTRL_OFFSET, GPC_STBY_PLL_IN_CTRL_OFFSET, GPC_STBY_BIAS_IN_CTRL_OFFSET, \ + GPC_STBY_PLDO_IN_CTRL_OFFSET, GPC_STBY_BANDGAP_IN_CTRL_OFFSET, GPC_STBY_LDO_IN_CTRL_OFFSET, \ + GPC_STBY_DCDC_IN_CTRL_OFFSET, GPC_STBY_PMIC_IN_CTRL_OFFSET, GPC_STBY_PMIC_OUT_CTRL_OFFSET, \ + GPC_STBY_DCDC_OUT_CTRL_OFFSET, GPC_STBY_LDO_OUT_CTRL_OFFSET, GPC_STBY_BANDGAP_OUT_CTRL_OFFSET, \ + GPC_STBY_PLDO_OUT_CTRL_OFFSET, GPC_STBY_BIAS_OUT_CTRL_OFFSET, GPC_STBY_PLL_OUT_CTRL_OFFSET, \ + GPC_STBY_LPCG_OUT_CTRL_OFFSET, \ + } + +/* Make/Get status. */ +/* Make the mask/shift value of GPC status register in a variable. */ +#define GPC_STAT(mask, shift) (uint32_t)(((uint32_t)(shift) << 16UL) + ((uint32_t)(mask) >> (uint32_t)(shift))) + +#define GPC_CM_ALL_INTERRUPT_STATUS \ + (GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_MASK | \ + GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_MASK | \ + GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_MASK) + +/*! @brief _gpc_cm_non_irq_wakeup_request GPC Non-IRQ wakeup request. */ +enum +{ + kGPC_CM_EventWakeupRequest = + GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_MASK, /*!< Event wakeup request. */ + kGPC_CM_DebugWakeupRequest = + GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_MASK, /*!< Debug wakeup request. */ +}; + +/* @brief _gpc_setpoint_map GPC setpoint map. */ +enum +{ + kGPC_SetPoint0 = 1UL << 0UL, /*!< GPC set point 0. */ + kGPC_SetPoint1 = 1UL << 1UL, /*!< GPC set point 1. */ + kGPC_SetPoint2 = 1UL << 2UL, /*!< GPC set point 2. */ + kGPC_SetPoint3 = 1UL << 3UL, /*!< GPC set point 3. */ + kGPC_SetPoint4 = 1UL << 4UL, /*!< GPC set point 4. */ + kGPC_SetPoint5 = 1UL << 5UL, /*!< GPC set point 5. */ + kGPC_SetPoint6 = 1UL << 6UL, /*!< GPC set point 6. */ + kGPC_SetPoint7 = 1UL << 7UL, /*!< GPC set point 7. */ + kGPC_SetPoint8 = 1UL << 8UL, /*!< GPC set point 8. */ + kGPC_SetPoint9 = 1UL << 9UL, /*!< GPC set point 9. */ + kGPC_SetPoint10 = 1UL << 10UL, /*!< GPC set point 10. */ + kGPC_SetPoint11 = 1UL << 11UL, /*!< GPC set point 11. */ + kGPC_SetPoint12 = 1UL << 12UL, /*!< GPC set point 12. */ + kGPC_SetPoint13 = 1UL << 13UL, /*!< GPC set point 13. */ + kGPC_SetPoint14 = 1UL << 14UL, /*!< GPC set point 14. */ + kGPC_SetPoint15 = 1UL << 15UL, /*!< GPC set point 15. */ +}; + +/*! + * @brief _gpc_cm_interrupt_status_flag + */ +enum +{ + kGPC_CM_SoftSPNotAllowedStatusFlag = GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_MASK, + kGPC_CM_WaitSPNotAllowedStatusFlag = GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_MASK, + kGPC_CM_SleepSPNotAllowedStatusFlag = GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_MASK, +}; + +/*! @brief CPU standby mode status. */ +typedef enum _gpc_cm_standby_mode_status +{ + kGPC_CM_SleepBusy = GPC_STAT( + GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY_MASK, + GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY_SHIFT), /*!< Indicate the CPU is busy entering standby mode. */ + kGPC_CM_WakeupBusy = GPC_STAT( + GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY_MASK, + GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY_SHIFT), /*!< Indicate the CPU is busy exiting standby mode. */ +} gpc_cm_standby_mode_status_t; + +/*! @brief CPU mode transition step in sleep/wakeup sequence. */ +typedef enum _gpc_cm_tran_step +{ + kGPC_CM_SleepSsar = 0UL, /*!< SSAR (State Save And Restore) sleep step. */ + kGPC_CM_SleepLpcg = 1UL, /*!< LPCG (Low Power Clock Gating) sleep step. */ + kGPC_CM_SleepPll = 2UL, /*!< PLL sleep step. */ + kGPC_CM_SleepIso = 3UL, /*!< ISO (Isolation) sleep step. */ + kGPC_CM_SleepReset = 4UL, /*!< Reset sleep step. */ + kGPC_CM_SleepPower = 5UL, /*!< Power sleep step. */ + kGPC_CM_SleepSP = 6UL, /*!< Setpoint sleep step. Note that this step is controlled by setpoint controller. */ + kGPC_CM_SleepSTBY = 7UL, /*!< Standby sleep step. Note that this step is controlled by standby controller. */ + kGPC_CM_WakeupSTBY = 8UL, /*!< Standby wakeup step. Note that this step is controlled by standby controller. */ + kGPC_CM_WakeupSP = 9UL, /*!< Setpoint wakeup step. Note that this step is controlled by setpoint countroller. */ + kGPC_CM_WakeupPower = 10UL, /*!< Power wakeup step. */ + kGPC_CM_WakeupReset = 11UL, /*!< Reset wakeup step. */ + kGPC_CM_WakeupIso = 12UL, /*!< ISO wakeup step. */ + kGPC_CM_WakeupPll = 13UL, /*!< PLL wakeup step. */ + kGPC_CM_WakeupLpcg = 14UL, /*!< LPCG wakeup step. */ + kGPC_CM_WakeupSsar = 15UL, /*!< SSAR wakeup step. */ +} gpc_cm_tran_step_t; + +/*! @brief Step counter work mode. */ +typedef enum _gpc_tran_step_counter_mode +{ + kGPC_StepCounterDisableMode = + 0UL, /*!< Counter disable mode: not use step counter, step completes once receiving step_done. */ + kGPC_StepCounterDelayMode = + 1UL, /*!< Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT */ + kGPC_StepCounterIgnoreResponseMode = 2UL, /*!< Ignore step_done response, the counter starts to count once step + begins, when counter reaches STEP_CNT value, the step completes. */ + kGPC_StepCounterTimeOutMode = 3UL, /*!< Time out mode, the counter starts to count once step begins, the step + completes when either step_done received or counting to STEP_CNT value. */ +} gpc_tran_step_counter_mode_t; + +/*! @brief GPC set point transition steps. */ +typedef enum _gpc_sp_tran_step +{ + kGPC_SP_SsarSave = 0UL, /*!< SSAR save step. */ + kGPC_SP_LpcgOff = 1UL, /*!< LPCG off step. */ + kGPC_SP_GroupDown = 2UL, /*!< Group down step. */ + kGPC_SP_RootDown = 3UL, /*!< Root down step. */ + kGPC_SP_PllOff = 4UL, /*!< PLL off step. */ + kGPC_SP_IsoOn = 5UL, /*!< ISO on. */ + kGPC_SP_ResetEarly = 6UL, /*!< Reset early step. */ + kGPC_SP_PowerOff = 7UL, /*!< Power off step. */ + kGPC_SP_BiasOff = 8UL, /*!< Bias off step. */ + kGPC_SP_BandgapPllLdoOff = 9UL, /*!< Bandgap and PLL_LDO off step. */ + kGPC_SP_LdoPre = 10UL, /*!< LDO (Low-Dropout) pre step. */ + kGPC_SP_DcdcDown = 11UL, /*!< DCDC down step. */ + kGPC_SP_DcdcUp = 12UL, /*!< DCDC up step. */ + kGPC_SP_LdoPost = 13UL, /*!< LDO post step. */ + kGPC_SP_BandgapPllLdoOn = 14UL, /*!< Bandgap and PLL_LDO on step. */ + kGPC_SP_BiasOn = 15UL, /*!< Bias on step. */ + kGPC_SP_PowerOn = 16UL, /*!< Power on step. */ + kGPC_SP_ResetLate = 17UL, /*!< Reset late step. */ + kGPC_SP_IsoOff = 18UL, /*!< ISO off step. */ + kGPC_SP_PllOn = 19UL, /*!< PLL on step */ + kGPC_SP_RootUp = 20UL, /*!< Root up step. */ + kGPC_SP_GroupUp = 21UL, /*!< Group up step. */ + kGPC_SP_LpcgOn = 22UL, /*!< LPCG on step. */ + kGPC_SP_SsarRestore = 23UL, /*!< SSAR restore step. */ +} gpc_sp_tran_step_t; + +/*! @brief CPU mode. */ +typedef enum _gpc_cpu_mode +{ + kGPC_RunMode = 0x0UL, /*!< Stay in RUN mode. */ + kGPC_WaitMode = 0x1UL, /*!< Transit to WAIT mode. */ + kGPC_StopMode = 0x2UL, /*!< Transit to STOP mode. */ + kGPC_SuspendMode = 0x3UL, /*!< Transit to SUSPEND mode. */ +} gpc_cpu_mode_t; + +/*! @brief Configuration for GPC transition step. */ +typedef struct _gpc_tran_step_config +{ + uint32_t stepCount; /*!< Step count, which is depended on the value of cntMode. */ + gpc_tran_step_counter_mode_t cntMode; /*!< Step counter working mode. */ + bool enableStep; /*!< Enable the step. */ +} gpc_tran_step_config_t; + +/*! @brief CPU wakeup sequence setpoint options. */ +typedef enum _gpc_cm_wakeup_sp_sel +{ + kGPC_CM_WakeupSetpoint = + 0UL, /*!< Request SP transition to CPU_SP_WAKEUP (param "setPointWakeup" in gpc_cm_sleep_sp_tran_config_t). */ + kGPC_CM_RequestPreviousSetpoint = 1UL, /*!< Request SP transition to the set point when the sleep event happens. */ +} gpc_cm_wakeup_sp_sel_t; + +/*! @brief GPC standby mode transition steps. */ +typedef enum _gpc_stby_tran_step +{ + kGPC_STBY_LpcgIn = 0UL, /*!< LPCG in step. */ + kGPC_STBY_PllIn = 1UL, /*!< PLL in step. */ + kGPC_STBY_BiasIn = 2UL, /*!< Bias in step. */ + kGPC_STBY_PldoIn = 3UL, /*!< PLDO in step. */ + kGPC_STBY_BandgapIn = 4UL, /*!< Bandgap in step. */ + kGPC_STBY_LdoIn = 5UL, /*!< LDO in step. */ + kGPC_STBY_DcdcIn = 6UL, /*!< DCDC in step. */ + kGPC_STBY_PmicIn = 7UL, /*!< PMIC in step. */ + kGPC_STBY_PmicOut = 8UL, /*!< PMIC out step. */ + kGPC_STBY_DcdcOut = 9UL, /*!< DCDC out step. */ + kGPC_STBY_LdoOut = 10UL, /*!< LDO out step. */ + kGPC_STBY_BandgapOut = 11UL, /*!< Bandgap out step. */ + kGPC_STBY_PldoOut = 12UL, /*!< PLDO out step. */ + kGPC_STBY_BiasOut = 13UL, /*!< Bias out step. */ + kGPC_STBY_PllOut = 14UL, /*!< PLL out step. */ + kGPC_STBY_LpcgOut = 15UL, /*!< LPCG out step. */ +} gpc_stby_tran_step_t; +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name CPU mode control + * @{ + */ + +/* + * @brief Hold core in sleep state. + * + * This function is used to hold the core in sleep state once it enters WFI, and until finishing wakeup sequence. If a + * wakeup IRQ happens during the delay between core sleeps and core clock stops, the core will be woken up but GPC is on + * sleep sequence and shut off the clock when core is processing the IRQ, this may leads to an unpredictable status. + * + * @param base GPC CPU module base address. + */ +static inline void GPC_CM_EnableCpuSleepHold(GPC_CPU_MODE_CTRL_Type *base, bool enable) +{ + if (enable) + { + base->CM_MISC |= GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN_MASK; + } + else + { + base->CM_MISC &= ~GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN_MASK; + } +} + +/*! + * @brief Set the CPU mode on the next sleep event. + * + * This function configures the CPU mode that the CPU core will transmit to on next sleep event. + * + * @note This API must be called each time before entering sleep. + * + * @param base GPC CPU module base address. + * @param mode The CPU mode that the core will transmit to, refer to "gpc_cpu_mode_t". + */ +static inline void GPC_CM_SetNextCpuMode(GPC_CPU_MODE_CTRL_Type *base, gpc_cpu_mode_t mode) +{ + base->CM_MODE_CTRL = (base->CM_MODE_CTRL & ~GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_MASK) | + GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET(mode); +} + +/*! + * @brief Get current CPU mode. + * + * @param base GPC CPU module base address. + * @return The current CPU mode, in type of @ref gpc_cpu_mode_t. + */ +static inline gpc_cpu_mode_t GPC_CM_GetCurrentCpuMode(GPC_CPU_MODE_CTRL_Type *base) +{ + return (gpc_cpu_mode_t)(uint32_t)((base->CM_MODE_STAT & GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_MASK) >> + GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_SHIFT); +} + +/*! + * @brief Get previous CPU mode. + * + * @param base GPC CPU module base address. + * @return The previous CPU mode, in type of @ref gpc_cpu_mode_t. + */ +static inline gpc_cpu_mode_t GPC_CM_GetPreviousCpuMode(GPC_CPU_MODE_CTRL_Type *base) +{ + return (gpc_cpu_mode_t)(uint32_t)((base->CM_MODE_STAT & GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_MASK) >> + GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_SHIFT); +} + +/*! + * @brief Enable IRQ wakeup request. + * + * This function enables the IRQ request which can wakeup the CPU platform. + * + * @param base GPC CPU module base address. + * @param irqId ID of the IRQ, accessible range is 0-255. + * @param enable Enable the IRQ request or not. + */ +void GPC_CM_EnableIrqWakeup(GPC_CPU_MODE_CTRL_Type *base, uint32_t irqId, bool enable); + +/*! + * @brief Enable Non-IRQ wakeup request. + * + * This function enables the non-IRQ request which can wakeup the CPU platform. + * + * @param base GPC CPU module base address. + * @param mask Non-IRQ type, refer to "_gpc_cm_non_irq_wakeup_request". + * @param enable Enable the Non-IRQ request or not. + */ +static inline void GPC_CM_EnableNonIrqWakeup(GPC_CPU_MODE_CTRL_Type *base, uint32_t mask, bool enable) +{ + assert(mask < 2UL); + + if (true == enable) + { + base->CM_NON_IRQ_WAKEUP_MASK &= ~mask; + } + else + { + base->CM_NON_IRQ_WAKEUP_MASK |= mask; + } +} + +/*! + * @brief Get the status of the IRQ wakeup request. + * + * @param base GPC CPU module base address. + * @param irqId ID of the IRQ, accessible range is 0-255. + * @return Indicate the IRQ request is asserted or not. + */ +bool GPC_CM_GetIrqWakeupStatus(GPC_CPU_MODE_CTRL_Type *base, uint32_t irqId); + +/*! + * @brief Get the status of the Non-IRQ wakeup request. + * + * @param base GPC CPU module base address. + * @param mask Non-IRQ type, refer to "_gpc_cm_non_irq_wakeup_request". + * @return Indicate the Non-IRQ request is asserted or not. + */ +static inline bool GPC_CM_GetNonIrqWakeupStatus(GPC_CPU_MODE_CTRL_Type *base, uint32_t mask) +{ + return (mask == (base->CM_NON_IRQ_WAKEUP_STAT & mask)); +} + +/*! + * @brief Config the cpu mode transition step. + * + * @note This function can not config the setpoint sleep/wakeup operation for those + * operation is controlled by setpoint control. This funcion can not config the standby + * sleep/wakeup too, because those operation is controlled by standby controlled. + * + * @param base GPC CPU module base address. + * @param step step type, refer to "gpc_cm_tran_step_t". + * @param config transition step configuration, refer to "gpc_tran_step_config_t". + */ +void GPC_CM_ConfigCpuModeTransitionStep(GPC_CPU_MODE_CTRL_Type *base, + gpc_cm_tran_step_t step, + const gpc_tran_step_config_t *config); + +/*! + * @brief Request a set point transition before the CPU transfers into a sleep mode. + * + * This function triggers the set point transition during a CPU Sleep/wakeup event and selects which one the CMC want + * to transfer to. + * + * @param base GPC CPU module base address. + * @param setPointSleep The set point CPU want the system to transit to on next CPU platform sleep sequence. + * @param setPointWakeup The set point CPU want the system to transit to on next CPU platform wakeup sequence. + * @param wakeupSel Select the set point transition on the next CPU platform wakeup sequence. + */ +void GPC_CM_RequestSleepModeSetPointTransition(GPC_CPU_MODE_CTRL_Type *base, + uint8_t setPointSleep, + uint8_t setPointWakeup, + gpc_cm_wakeup_sp_sel_t wakeupSel); + +/*! + * @brief Request a set point transition during run mode. + * + * This function triggers the set point transition and selects which one the CMC want to transfer to. + * + * @param base GPC CPU module base address. + * @param setPointRun The set point CPU want the system to transit in the run mode. + */ +void GPC_CM_RequestRunModeSetPointTransition(GPC_CPU_MODE_CTRL_Type *base, uint8_t setPointRun); + +/*! + * @brief Set the set point mapping value for each set point. + * + * This function configures which set point is allowed after current set point. If there are multiple setpoints, use: + * @code + * map = kkGPC_SetPoint0 | kGPC_SetPoint1 | ... | kGPC_SetPoint15; + * @endcode + * + * @param base GPC CPU module base address. + * @param setPoint Set point index, available range is 0-15. + * @param map Map value of the set point. Refer to "_gpc_setpoint_map". + */ +static inline void GPC_CM_SetSetPointMapping(GPC_CPU_MODE_CTRL_Type *base, uint32_t setPoint, uint32_t map) +{ + assert(setPoint < 16UL); + + base->CM_SP_MAPPING[setPoint] = (map & 0xFFFFUL); +} + +/*! + * @brief Set the set point mapping value for each cpu mode. + * + * This function configures which set point is allowed when CPU enters RUN/WAIT/STOP/SUSPEND. If there are multiple + * setpoints, use: + * @code + * map = kkGPC_SetPoint0 | kGPC_SetPoint1 | ... | kGPC_SetPoint15; + * @endcode + * + * @param base GPC CPU module base address. + * @param mode CPU mode. Refer to "gpc_cpu_mode_t". + * @param map Map value of the set point. Refer to "_gpc_setpoint_map". + */ +void GPC_CM_SetCpuModeSetPointMapping(GPC_CPU_MODE_CTRL_Type *base, gpc_cpu_mode_t mode, uint32_t map); + +/*! + * @brief Request the chip into standby mode. + * + * @param base GPC CPU module base address. + * @param mode CPU mode. Refer to "gpc_cpu_mode_t". + */ +void GPC_CM_RequestStandbyMode(GPC_CPU_MODE_CTRL_Type *base, const gpc_cpu_mode_t mode); + +/*! + * @brief Clear the standby mode request. + * + * @param base GPC CPU module base address. + * @param mode CPU mode. Refer to "gpc_cpu_mode_t". + */ +void GPC_CM_ClearStandbyModeRequest(GPC_CPU_MODE_CTRL_Type *base, const gpc_cpu_mode_t mode); + +/*! + * @brief Get the status of the CPU standby mode transition. + * + * @param base GPC CPU module base address. + * @param mask Standby mode transition status mask, refer to "gpc_cm_standby_mode_status_t". + * @return Indicate the CPU's standby transition status. + */ +static inline bool GPC_CM_GetStandbyModeStatus(GPC_CPU_MODE_CTRL_Type *base, uint32_t mask) +{ + return (mask == (base->CM_STBY_CTRL & mask)); +} + +/*! + * @brief Get the status flags of the GPC CPU module. + * + * @param base GPC CPU module base address. + * @return The OR'ed value of status flags. + */ +static inline uint32_t GPC_CM_GetInterruptStatusFlags(GPC_CPU_MODE_CTRL_Type *base) +{ + return ((base->CM_INT_CTRL) & GPC_CM_ALL_INTERRUPT_STATUS); +} + +/*! + * @brief Clears CPU module interrut status flags. + * + * @param base GPC CPU module base address. + * @param mask The interrupt status flags to be cleared. Should be the OR'ed value of _gpc_cm_interrupt_status_flag. + */ +void GPC_CM_ClearInterruptStatusFlags(GPC_CPU_MODE_CTRL_Type *base, uint32_t mask); + +/*! + * @} + */ + +/*! + * @name Set point request control + * @{ + */ + +/*! + * @brief Set the priority of set point. + * + * This function will configure the priority of the set point. If the result of API GPC_SP_GetAllowedSetPointMap() has + * more than one valid bit, high priority set point will be taken. + * + * @param base GPC Setpoint controller base address. + * @param setPoint Set point index, available range is 0-15. + * @param priority Priority level, available range is 0-15. + */ +static inline void GPC_SP_SetSetpointPriority(GPC_SET_POINT_CTRL_Type *base, uint32_t setPoint, uint32_t priority) +{ + assert(priority < 16UL); + assert(setPoint < 16UL); + + if (setPoint < 8UL) + { + base->SP_PRIORITY_0_7 |= (priority << (setPoint * 4UL)); + } + else + { + base->SP_PRIORITY_8_15 |= (priority << ((setPoint - 8UL) * 4UL)); + } +} + +/*! + * @brief Config the set point transition step. + * + * @param base GPC Setpoint controller base address. + * @param step step type, refer to "gpc_sp_tran_step_t". + * @param config transition step configuration, refer to "gpc_tran_step_config_t". + */ +void GPC_SP_ConfigSetPointTransitionStep(GPC_SET_POINT_CTRL_Type *base, + gpc_sp_tran_step_t step, + const gpc_tran_step_config_t *config); + +/*! + * @brief Get system current setpoint, only valid when setpoint trans not busy. + * + * @param base GPC Setpoint controller base address. + * @return The current setpoint number, range from 0 to 15. + */ +static inline uint8_t GPC_SP_GetCurrentSetPoint(GPC_SET_POINT_CTRL_Type *base) +{ + return (uint8_t)((base->SP_SYS_STAT & GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT_MASK) >> + GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT_SHIFT); +} + +/*! + * @brief Get system previous setpoint, only valid when setpoint trans not busy. + * + * @param base GPC Setpoint controller base address. + * @return The previous setpoint number, range from 0 to 15. + */ +static inline uint8_t GPC_SP_GetPreviousSetPoint(GPC_SET_POINT_CTRL_Type *base) +{ + return (uint8_t)((base->SP_SYS_STAT & GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS_MASK) >> + GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS_SHIFT); +} + +/*! + * @brief Get target setpoint. + * + * @param base GPC Setpoint controller base address. + * @return The target setpoint number, range from 0 to 15. + */ +static inline uint8_t GPC_SP_GetTargetSetPoint(GPC_SET_POINT_CTRL_Type *base) +{ + return (uint8_t)((base->SP_SYS_STAT & GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET_MASK) >> + GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET_SHIFT); +} +/*! + * @} + */ + +/*! + * @name Standby mode control + * @{ + */ + +/*! + * @brief Config the standby transition step. + * + * @param base GPC Setpoint controller base address. + * @param step step type, refer to "gpc_stby_tran_step_t". + * @param config transition step configuration, refer to "gpc_tran_step_config_t". + */ +void GPC_STBY_ConfigStandbyTransitionStep(GPC_STBY_CTRL_Type *base, + gpc_stby_tran_step_t step, + const gpc_tran_step_config_t *config); + +/*! + * @} + */ + +#if defined(__cplusplus) +} +#endif +/*! + * @} + */ +#endif /* _FSL_GPC_H_ */ diff --git a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_iomuxc.h b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_iomuxc.h new file mode 100644 index 0000000000..657bbaeb52 --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_iomuxc.h @@ -0,0 +1,1770 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_IOMUXC_H_ +#define _FSL_IOMUXC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup iomuxc_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.iomuxc" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief IOMUXC driver version 2.0.0 */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/*! + * @name Pin function ID + * The pin function ID is a tuple of \<muxRegister muxMode inputRegister inputDaisy configRegister\> + * + * @{ + */ +#define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x40C08000U, 0x0U, 0, 0, 0x40C08040U +#define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x40C08000U, 0x1U, 0, 0, 0x40C08040U +#define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x40C08000U, 0x2U, 0, 0, 0x40C08040U +#define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x40C08000U, 0x3U, 0, 0, 0x40C08040U +#define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x40C08000U, 0x5U, 0, 0, 0x40C08040U +#define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x40C08000U, 0x6U, 0x40C080B0U, 0x0U, 0x40C08040U +#define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x40C08000U, 0x7U, 0x40C080C8U, 0x0U, 0x40C08040U +#define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x40C08000U, 0xAU, 0, 0, 0x40C08040U + +#define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x40C08004U, 0x0U, 0x40C08080U, 0x0U, 0x40C08044U +#define IOMUXC_GPIO_LPSR_01_MIC_BITSTREAM0 0x40C08004U, 0x1U, 0x40C080B4U, 0x0U, 0x40C08044U +#define IOMUXC_GPIO_LPSR_01_MQS_LEFT 0x40C08004U, 0x2U, 0, 0, 0x40C08044U +#define IOMUXC_GPIO_LPSR_01_ARM_CM4_EVENTI 0x40C08004U, 0x3U, 0, 0, 0x40C08044U +#define IOMUXC_GPIO_LPSR_01_GPIO_MUX6_IO01 0x40C08004U, 0x5U, 0, 0, 0x40C08044U +#define IOMUXC_GPIO_LPSR_01_LPUART12_RXD 0x40C08004U, 0x6U, 0x40C080ACU, 0x0U, 0x40C08044U +#define IOMUXC_GPIO_LPSR_01_GPIO12_IO01 0x40C08004U, 0xAU, 0, 0, 0x40C08044U + +#define IOMUXC_GPIO_LPSR_02_GPIO12_IO02 0x40C08008U, 0xAU, 0, 0, 0x40C08048U +#define IOMUXC_GPIO_LPSR_02_SRC_BOOT_MODE00 0x40C08008U, 0x0U, 0, 0, 0x40C08048U +#define IOMUXC_GPIO_LPSR_02_LPSPI5_SCK 0x40C08008U, 0x1U, 0x40C08098U, 0x0U, 0x40C08048U +#define IOMUXC_GPIO_LPSR_02_SAI4_TX_DATA 0x40C08008U, 0x2U, 0, 0, 0x40C08048U +#define IOMUXC_GPIO_LPSR_02_MQS_RIGHT 0x40C08008U, 0x3U, 0, 0, 0x40C08048U +#define IOMUXC_GPIO_LPSR_02_GPIO_MUX6_IO02 0x40C08008U, 0x5U, 0, 0, 0x40C08048U + +#define IOMUXC_GPIO_LPSR_03_SRC_BOOT_MODE01 0x40C0800CU, 0x0U, 0, 0, 0x40C0804CU +#define IOMUXC_GPIO_LPSR_03_LPSPI5_PCS0 0x40C0800CU, 0x1U, 0x40C08094U, 0x0U, 0x40C0804CU +#define IOMUXC_GPIO_LPSR_03_SAI4_TX_SYNC 0x40C0800CU, 0x2U, 0x40C080DCU, 0x0U, 0x40C0804CU +#define IOMUXC_GPIO_LPSR_03_MQS_LEFT 0x40C0800CU, 0x3U, 0, 0, 0x40C0804CU +#define IOMUXC_GPIO_LPSR_03_GPIO_MUX6_IO03 0x40C0800CU, 0x5U, 0, 0, 0x40C0804CU +#define IOMUXC_GPIO_LPSR_03_GPIO12_IO03 0x40C0800CU, 0xAU, 0, 0, 0x40C0804CU + +#define IOMUXC_GPIO_LPSR_04_LPI2C5_SDA 0x40C08010U, 0x0U, 0x40C08088U, 0x0U, 0x40C08050U +#define IOMUXC_GPIO_LPSR_04_LPSPI5_SOUT 0x40C08010U, 0x1U, 0x40C080A0U, 0x0U, 0x40C08050U +#define IOMUXC_GPIO_LPSR_04_SAI4_TX_BCLK 0x40C08010U, 0x2U, 0x40C080D8U, 0x0U, 0x40C08050U +#define IOMUXC_GPIO_LPSR_04_LPUART12_RTS_B 0x40C08010U, 0x3U, 0, 0, 0x40C08050U +#define IOMUXC_GPIO_LPSR_04_GPIO_MUX6_IO04 0x40C08010U, 0x5U, 0, 0, 0x40C08050U +#define IOMUXC_GPIO_LPSR_04_LPUART11_TXD 0x40C08010U, 0x6U, 0x40C080A8U, 0x0U, 0x40C08050U +#define IOMUXC_GPIO_LPSR_04_GPIO12_IO04 0x40C08010U, 0xAU, 0, 0, 0x40C08050U + +#define IOMUXC_GPIO_LPSR_05_GPIO12_IO05 0x40C08014U, 0xAU, 0, 0, 0x40C08054U +#define IOMUXC_GPIO_LPSR_05_LPI2C5_SCL 0x40C08014U, 0x0U, 0x40C08084U, 0x0U, 0x40C08054U +#define IOMUXC_GPIO_LPSR_05_LPSPI5_SIN 0x40C08014U, 0x1U, 0x40C0809CU, 0x0U, 0x40C08054U +#define IOMUXC_GPIO_LPSR_05_SAI4_MCLK 0x40C08014U, 0x2U, 0x40C080C8U, 0x1U, 0x40C08054U +#define IOMUXC_GPIO_LPSR_05_LPUART12_CTS_B 0x40C08014U, 0x3U, 0, 0, 0x40C08054U +#define IOMUXC_GPIO_LPSR_05_GPIO_MUX6_IO05 0x40C08014U, 0x5U, 0, 0, 0x40C08054U +#define IOMUXC_GPIO_LPSR_05_LPUART11_RXD 0x40C08014U, 0x6U, 0x40C080A4U, 0x0U, 0x40C08054U +#define IOMUXC_GPIO_LPSR_05_NMI_GLUE_NMI 0x40C08014U, 0x7U, 0x40C080C4U, 0x0U, 0x40C08054U + +#define IOMUXC_GPIO_LPSR_06_LPI2C6_SDA 0x40C08018U, 0x0U, 0x40C08090U, 0x0U, 0x40C08058U +#define IOMUXC_GPIO_LPSR_06_SAI4_RX_DATA 0x40C08018U, 0x2U, 0x40C080D0U, 0x0U, 0x40C08058U +#define IOMUXC_GPIO_LPSR_06_LPUART12_TXD 0x40C08018U, 0x3U, 0x40C080B0U, 0x1U, 0x40C08058U +#define IOMUXC_GPIO_LPSR_06_LPSPI6_PCS3 0x40C08018U, 0x4U, 0, 0, 0x40C08058U +#define IOMUXC_GPIO_LPSR_06_GPIO_MUX6_IO06 0x40C08018U, 0x5U, 0, 0, 0x40C08058U +#define IOMUXC_GPIO_LPSR_06_FLEXCAN3_TX 0x40C08018U, 0x6U, 0, 0, 0x40C08058U +#define IOMUXC_GPIO_LPSR_06_PIT2_TRIGGER3 0x40C08018U, 0x7U, 0, 0, 0x40C08058U +#define IOMUXC_GPIO_LPSR_06_LPSPI5_PCS1 0x40C08018U, 0x8U, 0, 0, 0x40C08058U +#define IOMUXC_GPIO_LPSR_06_GPIO12_IO06 0x40C08018U, 0xAU, 0, 0, 0x40C08058U + +#define IOMUXC_GPIO_LPSR_07_LPI2C6_SCL 0x40C0801CU, 0x0U, 0x40C0808CU, 0x0U, 0x40C0805CU +#define IOMUXC_GPIO_LPSR_07_SAI4_RX_BCLK 0x40C0801CU, 0x2U, 0x40C080CCU, 0x0U, 0x40C0805CU +#define IOMUXC_GPIO_LPSR_07_LPUART12_RXD 0x40C0801CU, 0x3U, 0x40C080ACU, 0x1U, 0x40C0805CU +#define IOMUXC_GPIO_LPSR_07_LPSPI6_PCS2 0x40C0801CU, 0x4U, 0, 0, 0x40C0805CU +#define IOMUXC_GPIO_LPSR_07_GPIO_MUX6_IO07 0x40C0801CU, 0x5U, 0, 0, 0x40C0805CU +#define IOMUXC_GPIO_LPSR_07_FLEXCAN3_RX 0x40C0801CU, 0x6U, 0x40C08080U, 0x1U, 0x40C0805CU +#define IOMUXC_GPIO_LPSR_07_PIT2_TRIGGER2 0x40C0801CU, 0x7U, 0, 0, 0x40C0805CU +#define IOMUXC_GPIO_LPSR_07_LPSPI5_PCS2 0x40C0801CU, 0x8U, 0, 0, 0x40C0805CU +#define IOMUXC_GPIO_LPSR_07_GPIO12_IO07 0x40C0801CU, 0xAU, 0, 0, 0x40C0805CU + +#define IOMUXC_GPIO_LPSR_08_GPIO12_IO08 0x40C08020U, 0xAU, 0, 0, 0x40C08060U +#define IOMUXC_GPIO_LPSR_08_LPUART11_TXD 0x40C08020U, 0x0U, 0x40C080A8U, 0x1U, 0x40C08060U +#define IOMUXC_GPIO_LPSR_08_FLEXCAN3_TX 0x40C08020U, 0x1U, 0, 0, 0x40C08060U +#define IOMUXC_GPIO_LPSR_08_SAI4_RX_SYNC 0x40C08020U, 0x2U, 0x40C080D4U, 0x0U, 0x40C08060U +#define IOMUXC_GPIO_LPSR_08_MIC_CLK 0x40C08020U, 0x3U, 0, 0, 0x40C08060U +#define IOMUXC_GPIO_LPSR_08_LPSPI6_PCS1 0x40C08020U, 0x4U, 0, 0, 0x40C08060U +#define IOMUXC_GPIO_LPSR_08_GPIO_MUX6_IO08 0x40C08020U, 0x5U, 0, 0, 0x40C08060U +#define IOMUXC_GPIO_LPSR_08_LPI2C5_SDA 0x40C08020U, 0x6U, 0x40C08088U, 0x1U, 0x40C08060U +#define IOMUXC_GPIO_LPSR_08_PIT2_TRIGGER1 0x40C08020U, 0x7U, 0, 0, 0x40C08060U +#define IOMUXC_GPIO_LPSR_08_LPSPI5_PCS3 0x40C08020U, 0x8U, 0, 0, 0x40C08060U + +#define IOMUXC_GPIO_LPSR_09_GPIO12_IO09 0x40C08024U, 0xAU, 0, 0, 0x40C08064U +#define IOMUXC_GPIO_LPSR_09_LPUART11_RXD 0x40C08024U, 0x0U, 0x40C080A4U, 0x1U, 0x40C08064U +#define IOMUXC_GPIO_LPSR_09_FLEXCAN3_RX 0x40C08024U, 0x1U, 0x40C08080U, 0x2U, 0x40C08064U +#define IOMUXC_GPIO_LPSR_09_PIT2_TRIGGER0 0x40C08024U, 0x2U, 0, 0, 0x40C08064U +#define IOMUXC_GPIO_LPSR_09_MIC_BITSTREAM0 0x40C08024U, 0x3U, 0x40C080B4U, 0x1U, 0x40C08064U +#define IOMUXC_GPIO_LPSR_09_LPSPI6_PCS0 0x40C08024U, 0x4U, 0, 0, 0x40C08064U +#define IOMUXC_GPIO_LPSR_09_GPIO_MUX6_IO09 0x40C08024U, 0x5U, 0, 0, 0x40C08064U +#define IOMUXC_GPIO_LPSR_09_LPI2C5_SCL 0x40C08024U, 0x6U, 0x40C08084U, 0x1U, 0x40C08064U +#define IOMUXC_GPIO_LPSR_09_SAI4_TX_DATA 0x40C08024U, 0x7U, 0, 0, 0x40C08064U + +#define IOMUXC_GPIO_LPSR_10_GPIO12_IO10 0x40C08028U, 0xAU, 0, 0, 0x40C08068U +#define IOMUXC_GPIO_LPSR_10_JTAG_MUX_TRSTB 0x40C08028U, 0x0U, 0, 0, 0x40C08068U +#define IOMUXC_GPIO_LPSR_10_LPUART11_CTS_B 0x40C08028U, 0x1U, 0, 0, 0x40C08068U +#define IOMUXC_GPIO_LPSR_10_LPI2C6_SDA 0x40C08028U, 0x2U, 0x40C08090U, 0x1U, 0x40C08068U +#define IOMUXC_GPIO_LPSR_10_MIC_BITSTREAM1 0x40C08028U, 0x3U, 0x40C080B8U, 0x0U, 0x40C08068U +#define IOMUXC_GPIO_LPSR_10_LPSPI6_SCK 0x40C08028U, 0x4U, 0, 0, 0x40C08068U +#define IOMUXC_GPIO_LPSR_10_GPIO_MUX6_IO10 0x40C08028U, 0x5U, 0, 0, 0x40C08068U +#define IOMUXC_GPIO_LPSR_10_LPI2C5_SCLS 0x40C08028U, 0x6U, 0, 0, 0x40C08068U +#define IOMUXC_GPIO_LPSR_10_SAI4_TX_SYNC 0x40C08028U, 0x7U, 0x40C080DCU, 0x1U, 0x40C08068U +#define IOMUXC_GPIO_LPSR_10_LPUART12_TXD 0x40C08028U, 0x8U, 0x40C080B0U, 0x2U, 0x40C08068U + +#define IOMUXC_GPIO_LPSR_11_JTAG_MUX_TDO 0x40C0802CU, 0x0U, 0, 0, 0x40C0806CU +#define IOMUXC_GPIO_LPSR_11_LPUART11_RTS_B 0x40C0802CU, 0x1U, 0, 0, 0x40C0806CU +#define IOMUXC_GPIO_LPSR_11_LPI2C6_SCL 0x40C0802CU, 0x2U, 0x40C0808CU, 0x1U, 0x40C0806CU +#define IOMUXC_GPIO_LPSR_11_MIC_BITSTREAM2 0x40C0802CU, 0x3U, 0x40C080BCU, 0x0U, 0x40C0806CU +#define IOMUXC_GPIO_LPSR_11_LPSPI6_SOUT 0x40C0802CU, 0x4U, 0, 0, 0x40C0806CU +#define IOMUXC_GPIO_LPSR_11_GPIO_MUX6_IO11 0x40C0802CU, 0x5U, 0, 0, 0x40C0806CU +#define IOMUXC_GPIO_LPSR_11_LPI2C5_SDAS 0x40C0802CU, 0x6U, 0, 0, 0x40C0806CU +#define IOMUXC_GPIO_LPSR_11_ARM_TRACE_SWO 0x40C0802CU, 0x7U, 0, 0, 0x40C0806CU +#define IOMUXC_GPIO_LPSR_11_LPUART12_RXD 0x40C0802CU, 0x8U, 0x40C080ACU, 0x2U, 0x40C0806CU +#define IOMUXC_GPIO_LPSR_11_GPIO12_IO11 0x40C0802CU, 0xAU, 0, 0, 0x40C0806CU + +#define IOMUXC_GPIO_LPSR_12_GPIO12_IO12 0x40C08030U, 0xAU, 0, 0, 0x40C08070U +#define IOMUXC_GPIO_LPSR_12_JTAG_MUX_TDI 0x40C08030U, 0x0U, 0, 0, 0x40C08070U +#define IOMUXC_GPIO_LPSR_12_PIT2_TRIGGER0 0x40C08030U, 0x1U, 0, 0, 0x40C08070U +#define IOMUXC_GPIO_LPSR_12_MIC_BITSTREAM3 0x40C08030U, 0x3U, 0x40C080C0U, 0x0U, 0x40C08070U +#define IOMUXC_GPIO_LPSR_12_LPSPI6_SIN 0x40C08030U, 0x4U, 0, 0, 0x40C08070U +#define IOMUXC_GPIO_LPSR_12_GPIO_MUX6_IO12 0x40C08030U, 0x5U, 0, 0, 0x40C08070U +#define IOMUXC_GPIO_LPSR_12_LPI2C5_HREQ 0x40C08030U, 0x6U, 0, 0, 0x40C08070U +#define IOMUXC_GPIO_LPSR_12_SAI4_TX_BCLK 0x40C08030U, 0x7U, 0x40C080D8U, 0x1U, 0x40C08070U +#define IOMUXC_GPIO_LPSR_12_LPSPI5_SCK 0x40C08030U, 0x8U, 0x40C08098U, 0x1U, 0x40C08070U + +#define IOMUXC_GPIO_LPSR_13_GPIO12_IO13 0x40C08034U, 0xAU, 0, 0, 0x40C08074U +#define IOMUXC_GPIO_LPSR_13_JTAG_MUX_MOD 0x40C08034U, 0x0U, 0, 0, 0x40C08074U +#define IOMUXC_GPIO_LPSR_13_MIC_BITSTREAM1 0x40C08034U, 0x1U, 0x40C080B8U, 0x1U, 0x40C08074U +#define IOMUXC_GPIO_LPSR_13_PIT2_TRIGGER1 0x40C08034U, 0x2U, 0, 0, 0x40C08074U +#define IOMUXC_GPIO_LPSR_13_GPIO_MUX6_IO13 0x40C08034U, 0x5U, 0, 0, 0x40C08074U +#define IOMUXC_GPIO_LPSR_13_SAI4_RX_DATA 0x40C08034U, 0x7U, 0x40C080D0U, 0x1U, 0x40C08074U +#define IOMUXC_GPIO_LPSR_13_LPSPI5_PCS0 0x40C08034U, 0x8U, 0x40C08094U, 0x1U, 0x40C08074U + +#define IOMUXC_GPIO_LPSR_14_JTAG_MUX_TCK 0x40C08038U, 0x0U, 0, 0, 0x40C08078U +#define IOMUXC_GPIO_LPSR_14_MIC_BITSTREAM2 0x40C08038U, 0x1U, 0x40C080BCU, 0x1U, 0x40C08078U +#define IOMUXC_GPIO_LPSR_14_PIT2_TRIGGER2 0x40C08038U, 0x2U, 0, 0, 0x40C08078U +#define IOMUXC_GPIO_LPSR_14_GPIO_MUX6_IO14 0x40C08038U, 0x5U, 0, 0, 0x40C08078U +#define IOMUXC_GPIO_LPSR_14_SAI4_RX_BCLK 0x40C08038U, 0x7U, 0x40C080CCU, 0x1U, 0x40C08078U +#define IOMUXC_GPIO_LPSR_14_LPSPI5_SOUT 0x40C08038U, 0x8U, 0x40C080A0U, 0x1U, 0x40C08078U +#define IOMUXC_GPIO_LPSR_14_GPIO12_IO14 0x40C08038U, 0xAU, 0, 0, 0x40C08078U + +#define IOMUXC_GPIO_LPSR_15_GPIO12_IO15 0x40C0803CU, 0xAU, 0, 0, 0x40C0807CU +#define IOMUXC_GPIO_LPSR_15_JTAG_MUX_TMS 0x40C0803CU, 0x0U, 0, 0, 0x40C0807CU +#define IOMUXC_GPIO_LPSR_15_MIC_BITSTREAM3 0x40C0803CU, 0x1U, 0x40C080C0U, 0x1U, 0x40C0807CU +#define IOMUXC_GPIO_LPSR_15_PIT2_TRIGGER3 0x40C0803CU, 0x2U, 0, 0, 0x40C0807CU +#define IOMUXC_GPIO_LPSR_15_GPIO_MUX6_IO15 0x40C0803CU, 0x5U, 0, 0, 0x40C0807CU +#define IOMUXC_GPIO_LPSR_15_SAI4_RX_SYNC 0x40C0803CU, 0x7U, 0x40C080D4U, 0x1U, 0x40C0807CU +#define IOMUXC_GPIO_LPSR_15_LPSPI5_SIN 0x40C0803CU, 0x8U, 0x40C0809CU, 0x1U, 0x40C0807CU + +#define IOMUXC_WAKEUP_DIG_GPIO13_IO00 0x40C94000U, 0x5U, 0, 0, 0x40C94040U +#define IOMUXC_WAKEUP_DIG_NMI_GLUE_NMI 0x40C94000U, 0x7U, 0x40C080C4U, 0x1U, 0x40C94040U + +#define IOMUXC_PMIC_ON_REQ_DIG_SNVS_LP_PMIC_ON_REQ 0x40C94004U, 0x0U, 0, 0, 0x40C94044U +#define IOMUXC_PMIC_ON_REQ_DIG_GPIO13_IO01 0x40C94004U, 0x5U, 0, 0, 0x40C94044U + +#define IOMUXC_PMIC_STBY_REQ_DIG_CCM_PMIC_VSTBY_REQ 0x40C94008U, 0x0U, 0, 0, 0x40C94048U +#define IOMUXC_PMIC_STBY_REQ_DIG_GPIO13_IO02 0x40C94008U, 0x5U, 0, 0, 0x40C94048U + +#define IOMUXC_GPIO_SNVS_00_DIG_SNVS_TAMPER0 0x40C9400CU, 0x0U, 0, 0, 0x40C9404CU +#define IOMUXC_GPIO_SNVS_00_DIG_GPIO13_IO03 0x40C9400CU, 0x5U, 0, 0, 0x40C9404CU + +#define IOMUXC_GPIO_SNVS_01_DIG_SNVS_TAMPER1 0x40C94010U, 0x0U, 0, 0, 0x40C94050U +#define IOMUXC_GPIO_SNVS_01_DIG_GPIO13_IO04 0x40C94010U, 0x5U, 0, 0, 0x40C94050U + +#define IOMUXC_GPIO_SNVS_02_DIG_SNVS_TAMPER2 0x40C94014U, 0x0U, 0, 0, 0x40C94054U +#define IOMUXC_GPIO_SNVS_02_DIG_GPIO13_IO05 0x40C94014U, 0x5U, 0, 0, 0x40C94054U + +#define IOMUXC_GPIO_SNVS_03_DIG_SNVS_TAMPER3 0x40C94018U, 0x0U, 0, 0, 0x40C94058U +#define IOMUXC_GPIO_SNVS_03_DIG_GPIO13_IO06 0x40C94018U, 0x5U, 0, 0, 0x40C94058U + +#define IOMUXC_GPIO_SNVS_04_DIG_SNVS_TAMPER4 0x40C9401CU, 0x0U, 0, 0, 0x40C9405CU +#define IOMUXC_GPIO_SNVS_04_DIG_GPIO13_IO07 0x40C9401CU, 0x5U, 0, 0, 0x40C9405CU + +#define IOMUXC_GPIO_SNVS_05_DIG_SNVS_TAMPER5 0x40C94020U, 0x0U, 0, 0, 0x40C94060U +#define IOMUXC_GPIO_SNVS_05_DIG_GPIO13_IO08 0x40C94020U, 0x5U, 0, 0, 0x40C94060U + +#define IOMUXC_GPIO_SNVS_06_DIG_SNVS_TAMPER6 0x40C94024U, 0x0U, 0, 0, 0x40C94064U +#define IOMUXC_GPIO_SNVS_06_DIG_GPIO13_IO09 0x40C94024U, 0x5U, 0, 0, 0x40C94064U + +#define IOMUXC_GPIO_SNVS_07_DIG_SNVS_TAMPER7 0x40C94028U, 0x0U, 0, 0, 0x40C94068U +#define IOMUXC_GPIO_SNVS_07_DIG_GPIO13_IO10 0x40C94028U, 0x5U, 0, 0, 0x40C94068U + +#define IOMUXC_GPIO_SNVS_08_DIG_SNVS_TAMPER8 0x40C9402CU, 0x0U, 0, 0, 0x40C9406CU +#define IOMUXC_GPIO_SNVS_08_DIG_GPIO13_IO11 0x40C9402CU, 0x5U, 0, 0, 0x40C9406CU + +#define IOMUXC_GPIO_SNVS_09_DIG_SNVS_TAMPER9 0x40C94030U, 0x0U, 0, 0, 0x40C94070U +#define IOMUXC_GPIO_SNVS_09_DIG_GPIO13_IO12 0x40C94030U, 0x5U, 0, 0, 0x40C94070U + +#define IOMUXC_TEST_MODE_DIG 0, 0, 0, 0, 0x40C94034U + +#define IOMUXC_POR_B_DIG 0, 0, 0, 0, 0x40C94038U + +#define IOMUXC_ONOFF_DIG 0, 0, 0, 0, 0x40C9403CU + +#define IOMUXC_GPIO_EMC_B1_00_SEMC_DATA00 0x400E8010U, 0x0U, 0, 0, 0x400E8254U +#define IOMUXC_GPIO_EMC_B1_00_FLEXPWM4_PWM0_A 0x400E8010U, 0x1U, 0, 0, 0x400E8254U +#define IOMUXC_GPIO_EMC_B1_00_GPIO_MUX1_IO00 0x400E8010U, 0x5U, 0, 0, 0x400E8254U +#define IOMUXC_GPIO_EMC_B1_00_FLEXIO1_D00 0x400E8010U, 0x8U, 0, 0, 0x400E8254U +#define IOMUXC_GPIO_EMC_B1_00_GPIO7_IO00 0x400E8010U, 0xAU, 0, 0, 0x400E8254U + +#define IOMUXC_GPIO_EMC_B1_01_GPIO7_IO01 0x400E8014U, 0xAU, 0, 0, 0x400E8258U +#define IOMUXC_GPIO_EMC_B1_01_SEMC_DATA01 0x400E8014U, 0x0U, 0, 0, 0x400E8258U +#define IOMUXC_GPIO_EMC_B1_01_FLEXPWM4_PWM0_B 0x400E8014U, 0x1U, 0, 0, 0x400E8258U +#define IOMUXC_GPIO_EMC_B1_01_GPIO_MUX1_IO01 0x400E8014U, 0x5U, 0, 0, 0x400E8258U +#define IOMUXC_GPIO_EMC_B1_01_FLEXIO1_D01 0x400E8014U, 0x8U, 0, 0, 0x400E8258U + +#define IOMUXC_GPIO_EMC_B1_02_SEMC_DATA02 0x400E8018U, 0x0U, 0, 0, 0x400E825CU +#define IOMUXC_GPIO_EMC_B1_02_FLEXPWM4_PWM1_A 0x400E8018U, 0x1U, 0, 0, 0x400E825CU +#define IOMUXC_GPIO_EMC_B1_02_GPIO_MUX1_IO02 0x400E8018U, 0x5U, 0, 0, 0x400E825CU +#define IOMUXC_GPIO_EMC_B1_02_FLEXIO1_D02 0x400E8018U, 0x8U, 0, 0, 0x400E825CU +#define IOMUXC_GPIO_EMC_B1_02_GPIO7_IO02 0x400E8018U, 0xAU, 0, 0, 0x400E825CU + +#define IOMUXC_GPIO_EMC_B1_03_SEMC_DATA03 0x400E801CU, 0x0U, 0, 0, 0x400E8260U +#define IOMUXC_GPIO_EMC_B1_03_FLEXPWM4_PWM1_B 0x400E801CU, 0x1U, 0, 0, 0x400E8260U +#define IOMUXC_GPIO_EMC_B1_03_GPIO_MUX1_IO03 0x400E801CU, 0x5U, 0, 0, 0x400E8260U +#define IOMUXC_GPIO_EMC_B1_03_FLEXIO1_D03 0x400E801CU, 0x8U, 0, 0, 0x400E8260U +#define IOMUXC_GPIO_EMC_B1_03_GPIO7_IO03 0x400E801CU, 0xAU, 0, 0, 0x400E8260U + +#define IOMUXC_GPIO_EMC_B1_04_GPIO7_IO04 0x400E8020U, 0xAU, 0, 0, 0x400E8264U +#define IOMUXC_GPIO_EMC_B1_04_SEMC_DATA04 0x400E8020U, 0x0U, 0, 0, 0x400E8264U +#define IOMUXC_GPIO_EMC_B1_04_FLEXPWM4_PWM2_A 0x400E8020U, 0x1U, 0, 0, 0x400E8264U +#define IOMUXC_GPIO_EMC_B1_04_GPIO_MUX1_IO04 0x400E8020U, 0x5U, 0, 0, 0x400E8264U +#define IOMUXC_GPIO_EMC_B1_04_FLEXIO1_D04 0x400E8020U, 0x8U, 0, 0, 0x400E8264U + +#define IOMUXC_GPIO_EMC_B1_05_SEMC_DATA05 0x400E8024U, 0x0U, 0, 0, 0x400E8268U +#define IOMUXC_GPIO_EMC_B1_05_FLEXPWM4_PWM2_B 0x400E8024U, 0x1U, 0, 0, 0x400E8268U +#define IOMUXC_GPIO_EMC_B1_05_GPIO_MUX1_IO05 0x400E8024U, 0x5U, 0, 0, 0x400E8268U +#define IOMUXC_GPIO_EMC_B1_05_FLEXIO1_D05 0x400E8024U, 0x8U, 0, 0, 0x400E8268U +#define IOMUXC_GPIO_EMC_B1_05_GPIO7_IO05 0x400E8024U, 0xAU, 0, 0, 0x400E8268U + +#define IOMUXC_GPIO_EMC_B1_06_SEMC_DATA06 0x400E8028U, 0x0U, 0, 0, 0x400E826CU +#define IOMUXC_GPIO_EMC_B1_06_FLEXPWM2_PWM0_A 0x400E8028U, 0x1U, 0x400E8518U, 0x0U, 0x400E826CU +#define IOMUXC_GPIO_EMC_B1_06_GPIO_MUX1_IO06 0x400E8028U, 0x5U, 0, 0, 0x400E826CU +#define IOMUXC_GPIO_EMC_B1_06_FLEXIO1_D06 0x400E8028U, 0x8U, 0, 0, 0x400E826CU +#define IOMUXC_GPIO_EMC_B1_06_GPIO7_IO06 0x400E8028U, 0xAU, 0, 0, 0x400E826CU + +#define IOMUXC_GPIO_EMC_B1_07_GPIO7_IO07 0x400E802CU, 0xAU, 0, 0, 0x400E8270U +#define IOMUXC_GPIO_EMC_B1_07_SEMC_DATA07 0x400E802CU, 0x0U, 0, 0, 0x400E8270U +#define IOMUXC_GPIO_EMC_B1_07_FLEXPWM2_PWM0_B 0x400E802CU, 0x1U, 0x400E8524U, 0x0U, 0x400E8270U +#define IOMUXC_GPIO_EMC_B1_07_GPIO_MUX1_IO07 0x400E802CU, 0x5U, 0, 0, 0x400E8270U +#define IOMUXC_GPIO_EMC_B1_07_FLEXIO1_D07 0x400E802CU, 0x8U, 0, 0, 0x400E8270U + +#define IOMUXC_GPIO_EMC_B1_08_SEMC_DM00 0x400E8030U, 0x0U, 0, 0, 0x400E8274U +#define IOMUXC_GPIO_EMC_B1_08_FLEXPWM2_PWM1_A 0x400E8030U, 0x1U, 0x400E851CU, 0x0U, 0x400E8274U +#define IOMUXC_GPIO_EMC_B1_08_GPIO_MUX1_IO08 0x400E8030U, 0x5U, 0, 0, 0x400E8274U +#define IOMUXC_GPIO_EMC_B1_08_FLEXIO1_D08 0x400E8030U, 0x8U, 0, 0, 0x400E8274U +#define IOMUXC_GPIO_EMC_B1_08_GPIO7_IO08 0x400E8030U, 0xAU, 0, 0, 0x400E8274U + +#define IOMUXC_GPIO_EMC_B1_09_SEMC_ADDR00 0x400E8034U, 0x0U, 0, 0, 0x400E8278U +#define IOMUXC_GPIO_EMC_B1_09_FLEXPWM2_PWM1_B 0x400E8034U, 0x1U, 0x400E8528U, 0x0U, 0x400E8278U +#define IOMUXC_GPIO_EMC_B1_09_GPT5_CAPTURE1 0x400E8034U, 0x2U, 0, 0, 0x400E8278U +#define IOMUXC_GPIO_EMC_B1_09_GPIO_MUX1_IO09 0x400E8034U, 0x5U, 0, 0, 0x400E8278U +#define IOMUXC_GPIO_EMC_B1_09_FLEXIO1_D09 0x400E8034U, 0x8U, 0, 0, 0x400E8278U +#define IOMUXC_GPIO_EMC_B1_09_GPIO7_IO09 0x400E8034U, 0xAU, 0, 0, 0x400E8278U + +#define IOMUXC_GPIO_EMC_B1_10_SEMC_ADDR01 0x400E8038U, 0x0U, 0, 0, 0x400E827CU +#define IOMUXC_GPIO_EMC_B1_10_FLEXPWM2_PWM2_A 0x400E8038U, 0x1U, 0x400E8520U, 0x0U, 0x400E827CU +#define IOMUXC_GPIO_EMC_B1_10_GPT5_CAPTURE2 0x400E8038U, 0x2U, 0, 0, 0x400E827CU +#define IOMUXC_GPIO_EMC_B1_10_GPIO_MUX1_IO10 0x400E8038U, 0x5U, 0, 0, 0x400E827CU +#define IOMUXC_GPIO_EMC_B1_10_FLEXIO1_D10 0x400E8038U, 0x8U, 0, 0, 0x400E827CU +#define IOMUXC_GPIO_EMC_B1_10_GPIO7_IO10 0x400E8038U, 0xAU, 0, 0, 0x400E827CU + +#define IOMUXC_GPIO_EMC_B1_11_GPIO7_IO11 0x400E803CU, 0xAU, 0, 0, 0x400E8280U +#define IOMUXC_GPIO_EMC_B1_11_SEMC_ADDR02 0x400E803CU, 0x0U, 0, 0, 0x400E8280U +#define IOMUXC_GPIO_EMC_B1_11_FLEXPWM2_PWM2_B 0x400E803CU, 0x1U, 0x400E852CU, 0x0U, 0x400E8280U +#define IOMUXC_GPIO_EMC_B1_11_GPT5_COMPARE1 0x400E803CU, 0x2U, 0, 0, 0x400E8280U +#define IOMUXC_GPIO_EMC_B1_11_GPIO_MUX1_IO11 0x400E803CU, 0x5U, 0, 0, 0x400E8280U +#define IOMUXC_GPIO_EMC_B1_11_FLEXIO1_D11 0x400E803CU, 0x8U, 0, 0, 0x400E8280U + +#define IOMUXC_GPIO_EMC_B1_12_SEMC_ADDR03 0x400E8040U, 0x0U, 0, 0, 0x400E8284U +#define IOMUXC_GPIO_EMC_B1_12_XBAR1_INOUT04 0x400E8040U, 0x1U, 0, 0, 0x400E8284U +#define IOMUXC_GPIO_EMC_B1_12_GPT5_COMPARE2 0x400E8040U, 0x2U, 0, 0, 0x400E8284U +#define IOMUXC_GPIO_EMC_B1_12_GPIO_MUX1_IO12 0x400E8040U, 0x5U, 0, 0, 0x400E8284U +#define IOMUXC_GPIO_EMC_B1_12_FLEXIO1_D12 0x400E8040U, 0x8U, 0, 0, 0x400E8284U +#define IOMUXC_GPIO_EMC_B1_12_GPIO7_IO12 0x400E8040U, 0xAU, 0, 0, 0x400E8284U + +#define IOMUXC_GPIO_EMC_B1_13_SEMC_ADDR04 0x400E8044U, 0x0U, 0, 0, 0x400E8288U +#define IOMUXC_GPIO_EMC_B1_13_XBAR1_INOUT05 0x400E8044U, 0x1U, 0, 0, 0x400E8288U +#define IOMUXC_GPIO_EMC_B1_13_GPT5_COMPARE3 0x400E8044U, 0x2U, 0, 0, 0x400E8288U +#define IOMUXC_GPIO_EMC_B1_13_GPIO_MUX1_IO13 0x400E8044U, 0x5U, 0, 0, 0x400E8288U +#define IOMUXC_GPIO_EMC_B1_13_FLEXIO1_D13 0x400E8044U, 0x8U, 0, 0, 0x400E8288U +#define IOMUXC_GPIO_EMC_B1_13_GPIO7_IO13 0x400E8044U, 0xAU, 0, 0, 0x400E8288U + +#define IOMUXC_GPIO_EMC_B1_14_GPIO7_IO14 0x400E8048U, 0xAU, 0, 0, 0x400E828CU +#define IOMUXC_GPIO_EMC_B1_14_SEMC_ADDR05 0x400E8048U, 0x0U, 0, 0, 0x400E828CU +#define IOMUXC_GPIO_EMC_B1_14_XBAR1_INOUT06 0x400E8048U, 0x1U, 0, 0, 0x400E828CU +#define IOMUXC_GPIO_EMC_B1_14_GPT5_CLK 0x400E8048U, 0x2U, 0, 0, 0x400E828CU +#define IOMUXC_GPIO_EMC_B1_14_GPIO_MUX1_IO14 0x400E8048U, 0x5U, 0, 0, 0x400E828CU +#define IOMUXC_GPIO_EMC_B1_14_FLEXIO1_D14 0x400E8048U, 0x8U, 0, 0, 0x400E828CU + +#define IOMUXC_GPIO_EMC_B1_15_SEMC_ADDR06 0x400E804CU, 0x0U, 0, 0, 0x400E8290U +#define IOMUXC_GPIO_EMC_B1_15_XBAR1_INOUT07 0x400E804CU, 0x1U, 0, 0, 0x400E8290U +#define IOMUXC_GPIO_EMC_B1_15_GPIO_MUX1_IO15 0x400E804CU, 0x5U, 0, 0, 0x400E8290U +#define IOMUXC_GPIO_EMC_B1_15_FLEXIO1_D15 0x400E804CU, 0x8U, 0, 0, 0x400E8290U +#define IOMUXC_GPIO_EMC_B1_15_GPIO7_IO15 0x400E804CU, 0xAU, 0, 0, 0x400E8290U + +#define IOMUXC_GPIO_EMC_B1_16_SEMC_ADDR07 0x400E8050U, 0x0U, 0, 0, 0x400E8294U +#define IOMUXC_GPIO_EMC_B1_16_XBAR1_INOUT08 0x400E8050U, 0x1U, 0, 0, 0x400E8294U +#define IOMUXC_GPIO_EMC_B1_16_GPIO_MUX1_IO16 0x400E8050U, 0x5U, 0, 0, 0x400E8294U +#define IOMUXC_GPIO_EMC_B1_16_FLEXIO1_D16 0x400E8050U, 0x8U, 0, 0, 0x400E8294U +#define IOMUXC_GPIO_EMC_B1_16_GPIO7_IO16 0x400E8050U, 0xAU, 0, 0, 0x400E8294U + +#define IOMUXC_GPIO_EMC_B1_17_GPIO7_IO17 0x400E8054U, 0xAU, 0, 0, 0x400E8298U +#define IOMUXC_GPIO_EMC_B1_17_SEMC_ADDR08 0x400E8054U, 0x0U, 0, 0, 0x400E8298U +#define IOMUXC_GPIO_EMC_B1_17_FLEXPWM4_PWM3_A 0x400E8054U, 0x1U, 0, 0, 0x400E8298U +#define IOMUXC_GPIO_EMC_B1_17_TMR1_TIMER0 0x400E8054U, 0x2U, 0x400E863CU, 0x0U, 0x400E8298U +#define IOMUXC_GPIO_EMC_B1_17_GPIO_MUX1_IO17 0x400E8054U, 0x5U, 0, 0, 0x400E8298U +#define IOMUXC_GPIO_EMC_B1_17_FLEXIO1_D17 0x400E8054U, 0x8U, 0, 0, 0x400E8298U + +#define IOMUXC_GPIO_EMC_B1_18_SEMC_ADDR09 0x400E8058U, 0x0U, 0, 0, 0x400E829CU +#define IOMUXC_GPIO_EMC_B1_18_FLEXPWM4_PWM3_B 0x400E8058U, 0x1U, 0, 0, 0x400E829CU +#define IOMUXC_GPIO_EMC_B1_18_TMR2_TIMER0 0x400E8058U, 0x2U, 0x400E8648U, 0x0U, 0x400E829CU +#define IOMUXC_GPIO_EMC_B1_18_GPIO_MUX1_IO18 0x400E8058U, 0x5U, 0, 0, 0x400E829CU +#define IOMUXC_GPIO_EMC_B1_18_FLEXIO1_D18 0x400E8058U, 0x8U, 0, 0, 0x400E829CU +#define IOMUXC_GPIO_EMC_B1_18_GPIO7_IO18 0x400E8058U, 0xAU, 0, 0, 0x400E829CU + +#define IOMUXC_GPIO_EMC_B1_19_SEMC_ADDR11 0x400E805CU, 0x0U, 0, 0, 0x400E82A0U +#define IOMUXC_GPIO_EMC_B1_19_FLEXPWM2_PWM3_A 0x400E805CU, 0x1U, 0, 0, 0x400E82A0U +#define IOMUXC_GPIO_EMC_B1_19_TMR3_TIMER0 0x400E805CU, 0x2U, 0x400E8654U, 0x0U, 0x400E82A0U +#define IOMUXC_GPIO_EMC_B1_19_GPIO_MUX1_IO19 0x400E805CU, 0x5U, 0, 0, 0x400E82A0U +#define IOMUXC_GPIO_EMC_B1_19_FLEXIO1_D19 0x400E805CU, 0x8U, 0, 0, 0x400E82A0U +#define IOMUXC_GPIO_EMC_B1_19_GPIO7_IO19 0x400E805CU, 0xAU, 0, 0, 0x400E82A0U + +#define IOMUXC_GPIO_EMC_B1_20_SEMC_ADDR12 0x400E8060U, 0x0U, 0, 0, 0x400E82A4U +#define IOMUXC_GPIO_EMC_B1_20_FLEXPWM2_PWM3_B 0x400E8060U, 0x1U, 0, 0, 0x400E82A4U +#define IOMUXC_GPIO_EMC_B1_20_TMR4_TIMER0 0x400E8060U, 0x2U, 0x400E8660U, 0x0U, 0x400E82A4U +#define IOMUXC_GPIO_EMC_B1_20_GPIO_MUX1_IO20 0x400E8060U, 0x5U, 0, 0, 0x400E82A4U +#define IOMUXC_GPIO_EMC_B1_20_FLEXIO1_D20 0x400E8060U, 0x8U, 0, 0, 0x400E82A4U +#define IOMUXC_GPIO_EMC_B1_20_GPIO7_IO20 0x400E8060U, 0xAU, 0, 0, 0x400E82A4U + +#define IOMUXC_GPIO_EMC_B1_21_GPIO7_IO21 0x400E8064U, 0xAU, 0, 0, 0x400E82A8U +#define IOMUXC_GPIO_EMC_B1_21_SEMC_BA0 0x400E8064U, 0x0U, 0, 0, 0x400E82A8U +#define IOMUXC_GPIO_EMC_B1_21_FLEXPWM3_PWM3_A 0x400E8064U, 0x1U, 0x400E853CU, 0x0U, 0x400E82A8U +#define IOMUXC_GPIO_EMC_B1_21_GPIO_MUX1_IO21 0x400E8064U, 0x5U, 0, 0, 0x400E82A8U +#define IOMUXC_GPIO_EMC_B1_21_FLEXIO1_D21 0x400E8064U, 0x8U, 0, 0, 0x400E82A8U + +#define IOMUXC_GPIO_EMC_B1_22_GPIO7_IO22 0x400E8068U, 0xAU, 0, 0, 0x400E82ACU +#define IOMUXC_GPIO_EMC_B1_22_SEMC_BA1 0x400E8068U, 0x0U, 0, 0, 0x400E82ACU +#define IOMUXC_GPIO_EMC_B1_22_FLEXPWM3_PWM3_B 0x400E8068U, 0x1U, 0x400E854CU, 0x0U, 0x400E82ACU +#define IOMUXC_GPIO_EMC_B1_22_GPIO_MUX1_IO22 0x400E8068U, 0x5U, 0, 0, 0x400E82ACU +#define IOMUXC_GPIO_EMC_B1_22_FLEXIO1_D22 0x400E8068U, 0x8U, 0, 0, 0x400E82ACU + +#define IOMUXC_GPIO_EMC_B1_23_SEMC_ADDR10 0x400E806CU, 0x0U, 0, 0, 0x400E82B0U +#define IOMUXC_GPIO_EMC_B1_23_FLEXPWM1_PWM0_A 0x400E806CU, 0x1U, 0x400E8500U, 0x0U, 0x400E82B0U +#define IOMUXC_GPIO_EMC_B1_23_GPIO_MUX1_IO23 0x400E806CU, 0x5U, 0, 0, 0x400E82B0U +#define IOMUXC_GPIO_EMC_B1_23_FLEXIO1_D23 0x400E806CU, 0x8U, 0, 0, 0x400E82B0U +#define IOMUXC_GPIO_EMC_B1_23_GPIO7_IO23 0x400E806CU, 0xAU, 0, 0, 0x400E82B0U + +#define IOMUXC_GPIO_EMC_B1_24_GPIO7_IO24 0x400E8070U, 0xAU, 0, 0, 0x400E82B4U +#define IOMUXC_GPIO_EMC_B1_24_SEMC_CAS 0x400E8070U, 0x0U, 0, 0, 0x400E82B4U +#define IOMUXC_GPIO_EMC_B1_24_FLEXPWM1_PWM0_B 0x400E8070U, 0x1U, 0x400E850CU, 0x0U, 0x400E82B4U +#define IOMUXC_GPIO_EMC_B1_24_GPIO_MUX1_IO24 0x400E8070U, 0x5U, 0, 0, 0x400E82B4U +#define IOMUXC_GPIO_EMC_B1_24_FLEXIO1_D24 0x400E8070U, 0x8U, 0, 0, 0x400E82B4U + +#define IOMUXC_GPIO_EMC_B1_25_GPIO7_IO25 0x400E8074U, 0xAU, 0, 0, 0x400E82B8U +#define IOMUXC_GPIO_EMC_B1_25_SEMC_RAS 0x400E8074U, 0x0U, 0, 0, 0x400E82B8U +#define IOMUXC_GPIO_EMC_B1_25_FLEXPWM1_PWM1_A 0x400E8074U, 0x1U, 0x400E8504U, 0x0U, 0x400E82B8U +#define IOMUXC_GPIO_EMC_B1_25_GPIO_MUX1_IO25 0x400E8074U, 0x5U, 0, 0, 0x400E82B8U +#define IOMUXC_GPIO_EMC_B1_25_FLEXIO1_D25 0x400E8074U, 0x8U, 0, 0, 0x400E82B8U + +#define IOMUXC_GPIO_EMC_B1_26_SEMC_CLK 0x400E8078U, 0x0U, 0, 0, 0x400E82BCU +#define IOMUXC_GPIO_EMC_B1_26_FLEXPWM1_PWM1_B 0x400E8078U, 0x1U, 0x400E8510U, 0x0U, 0x400E82BCU +#define IOMUXC_GPIO_EMC_B1_26_GPIO_MUX1_IO26 0x400E8078U, 0x5U, 0, 0, 0x400E82BCU +#define IOMUXC_GPIO_EMC_B1_26_FLEXIO1_D26 0x400E8078U, 0x8U, 0, 0, 0x400E82BCU +#define IOMUXC_GPIO_EMC_B1_26_GPIO7_IO26 0x400E8078U, 0xAU, 0, 0, 0x400E82BCU + +#define IOMUXC_GPIO_EMC_B1_27_GPIO7_IO27 0x400E807CU, 0xAU, 0, 0, 0x400E82C0U +#define IOMUXC_GPIO_EMC_B1_27_SEMC_CKE 0x400E807CU, 0x0U, 0, 0, 0x400E82C0U +#define IOMUXC_GPIO_EMC_B1_27_FLEXPWM1_PWM2_A 0x400E807CU, 0x1U, 0x400E8508U, 0x0U, 0x400E82C0U +#define IOMUXC_GPIO_EMC_B1_27_GPIO_MUX1_IO27 0x400E807CU, 0x5U, 0, 0, 0x400E82C0U +#define IOMUXC_GPIO_EMC_B1_27_FLEXIO1_D27 0x400E807CU, 0x8U, 0, 0, 0x400E82C0U + +#define IOMUXC_GPIO_EMC_B1_28_GPIO7_IO28 0x400E8080U, 0xAU, 0, 0, 0x400E82C4U +#define IOMUXC_GPIO_EMC_B1_28_SEMC_WE 0x400E8080U, 0x0U, 0, 0, 0x400E82C4U +#define IOMUXC_GPIO_EMC_B1_28_FLEXPWM1_PWM2_B 0x400E8080U, 0x1U, 0x400E8514U, 0x0U, 0x400E82C4U +#define IOMUXC_GPIO_EMC_B1_28_GPIO_MUX1_IO28 0x400E8080U, 0x5U, 0, 0, 0x400E82C4U +#define IOMUXC_GPIO_EMC_B1_28_FLEXIO1_D28 0x400E8080U, 0x8U, 0, 0, 0x400E82C4U + +#define IOMUXC_GPIO_EMC_B1_29_SEMC_CS0 0x400E8084U, 0x0U, 0, 0, 0x400E82C8U +#define IOMUXC_GPIO_EMC_B1_29_FLEXPWM3_PWM0_A 0x400E8084U, 0x1U, 0x400E8530U, 0x0U, 0x400E82C8U +#define IOMUXC_GPIO_EMC_B1_29_GPIO_MUX1_IO29 0x400E8084U, 0x5U, 0, 0, 0x400E82C8U +#define IOMUXC_GPIO_EMC_B1_29_FLEXIO1_D29 0x400E8084U, 0x8U, 0, 0, 0x400E82C8U +#define IOMUXC_GPIO_EMC_B1_29_GPIO7_IO29 0x400E8084U, 0xAU, 0, 0, 0x400E82C8U + +#define IOMUXC_GPIO_EMC_B1_30_SEMC_DATA08 0x400E8088U, 0x0U, 0, 0, 0x400E82CCU +#define IOMUXC_GPIO_EMC_B1_30_FLEXPWM3_PWM0_B 0x400E8088U, 0x1U, 0x400E8540U, 0x0U, 0x400E82CCU +#define IOMUXC_GPIO_EMC_B1_30_GPIO_MUX1_IO30 0x400E8088U, 0x5U, 0, 0, 0x400E82CCU +#define IOMUXC_GPIO_EMC_B1_30_FLEXIO1_D30 0x400E8088U, 0x8U, 0, 0, 0x400E82CCU +#define IOMUXC_GPIO_EMC_B1_30_GPIO7_IO30 0x400E8088U, 0xAU, 0, 0, 0x400E82CCU + +#define IOMUXC_GPIO_EMC_B1_31_GPIO7_IO31 0x400E808CU, 0xAU, 0, 0, 0x400E82D0U +#define IOMUXC_GPIO_EMC_B1_31_SEMC_DATA09 0x400E808CU, 0x0U, 0, 0, 0x400E82D0U +#define IOMUXC_GPIO_EMC_B1_31_FLEXPWM3_PWM1_A 0x400E808CU, 0x1U, 0x400E8534U, 0x0U, 0x400E82D0U +#define IOMUXC_GPIO_EMC_B1_31_GPIO_MUX1_IO31 0x400E808CU, 0x5U, 0, 0, 0x400E82D0U +#define IOMUXC_GPIO_EMC_B1_31_FLEXIO1_D31 0x400E808CU, 0x8U, 0, 0, 0x400E82D0U + +#define IOMUXC_GPIO_EMC_B1_32_GPIO8_IO00 0x400E8090U, 0xAU, 0, 0, 0x400E82D4U +#define IOMUXC_GPIO_EMC_B1_32_SEMC_DATA10 0x400E8090U, 0x0U, 0, 0, 0x400E82D4U +#define IOMUXC_GPIO_EMC_B1_32_FLEXPWM3_PWM1_B 0x400E8090U, 0x1U, 0x400E8544U, 0x0U, 0x400E82D4U +#define IOMUXC_GPIO_EMC_B1_32_GPIO_MUX2_IO00 0x400E8090U, 0x5U, 0, 0, 0x400E82D4U + +#define IOMUXC_GPIO_EMC_B1_33_SEMC_DATA11 0x400E8094U, 0x0U, 0, 0, 0x400E82D8U +#define IOMUXC_GPIO_EMC_B1_33_FLEXPWM3_PWM2_A 0x400E8094U, 0x1U, 0x400E8538U, 0x0U, 0x400E82D8U +#define IOMUXC_GPIO_EMC_B1_33_GPIO_MUX2_IO01 0x400E8094U, 0x5U, 0, 0, 0x400E82D8U +#define IOMUXC_GPIO_EMC_B1_33_GPIO8_IO01 0x400E8094U, 0xAU, 0, 0, 0x400E82D8U + +#define IOMUXC_GPIO_EMC_B1_34_GPIO8_IO02 0x400E8098U, 0xAU, 0, 0, 0x400E82DCU +#define IOMUXC_GPIO_EMC_B1_34_SEMC_DATA12 0x400E8098U, 0x0U, 0, 0, 0x400E82DCU +#define IOMUXC_GPIO_EMC_B1_34_FLEXPWM3_PWM2_B 0x400E8098U, 0x1U, 0x400E8548U, 0x0U, 0x400E82DCU +#define IOMUXC_GPIO_EMC_B1_34_GPIO_MUX2_IO02 0x400E8098U, 0x5U, 0, 0, 0x400E82DCU + +#define IOMUXC_GPIO_EMC_B1_35_GPIO8_IO03 0x400E809CU, 0xAU, 0, 0, 0x400E82E0U +#define IOMUXC_GPIO_EMC_B1_35_SEMC_DATA13 0x400E809CU, 0x0U, 0, 0, 0x400E82E0U +#define IOMUXC_GPIO_EMC_B1_35_XBAR1_INOUT09 0x400E809CU, 0x1U, 0, 0, 0x400E82E0U +#define IOMUXC_GPIO_EMC_B1_35_GPIO_MUX2_IO03 0x400E809CU, 0x5U, 0, 0, 0x400E82E0U + +#define IOMUXC_GPIO_EMC_B1_36_SEMC_DATA14 0x400E80A0U, 0x0U, 0, 0, 0x400E82E4U +#define IOMUXC_GPIO_EMC_B1_36_XBAR1_INOUT10 0x400E80A0U, 0x1U, 0, 0, 0x400E82E4U +#define IOMUXC_GPIO_EMC_B1_36_GPIO_MUX2_IO04 0x400E80A0U, 0x5U, 0, 0, 0x400E82E4U +#define IOMUXC_GPIO_EMC_B1_36_GPIO8_IO04 0x400E80A0U, 0xAU, 0, 0, 0x400E82E4U + +#define IOMUXC_GPIO_EMC_B1_37_GPIO8_IO05 0x400E80A4U, 0xAU, 0, 0, 0x400E82E8U +#define IOMUXC_GPIO_EMC_B1_37_SEMC_DATA15 0x400E80A4U, 0x0U, 0, 0, 0x400E82E8U +#define IOMUXC_GPIO_EMC_B1_37_XBAR1_INOUT11 0x400E80A4U, 0x1U, 0, 0, 0x400E82E8U +#define IOMUXC_GPIO_EMC_B1_37_GPIO_MUX2_IO05 0x400E80A4U, 0x5U, 0, 0, 0x400E82E8U + +#define IOMUXC_GPIO_EMC_B1_38_GPIO8_IO06 0x400E80A8U, 0xAU, 0, 0, 0x400E82ECU +#define IOMUXC_GPIO_EMC_B1_38_SEMC_DM01 0x400E80A8U, 0x0U, 0, 0, 0x400E82ECU +#define IOMUXC_GPIO_EMC_B1_38_FLEXPWM1_PWM3_A 0x400E80A8U, 0x1U, 0, 0, 0x400E82ECU +#define IOMUXC_GPIO_EMC_B1_38_TMR1_TIMER1 0x400E80A8U, 0x2U, 0x400E8640U, 0x0U, 0x400E82ECU +#define IOMUXC_GPIO_EMC_B1_38_GPIO_MUX2_IO06 0x400E80A8U, 0x5U, 0, 0, 0x400E82ECU + +#define IOMUXC_GPIO_EMC_B1_39_SEMC_DQS 0x400E80ACU, 0x0U, 0, 0, 0x400E82F0U +#define IOMUXC_GPIO_EMC_B1_39_FLEXPWM1_PWM3_B 0x400E80ACU, 0x1U, 0, 0, 0x400E82F0U +#define IOMUXC_GPIO_EMC_B1_39_TMR2_TIMER1 0x400E80ACU, 0x2U, 0x400E864CU, 0x0U, 0x400E82F0U +#define IOMUXC_GPIO_EMC_B1_39_GPIO_MUX2_IO07 0x400E80ACU, 0x5U, 0, 0, 0x400E82F0U +#define IOMUXC_GPIO_EMC_B1_39_GPIO8_IO07 0x400E80ACU, 0xAU, 0, 0, 0x400E82F0U + +#define IOMUXC_GPIO_EMC_B1_40_SEMC_RDY 0x400E80B0U, 0x0U, 0, 0, 0x400E82F4U +#define IOMUXC_GPIO_EMC_B1_40_XBAR1_INOUT12 0x400E80B0U, 0x1U, 0, 0, 0x400E82F4U +#define IOMUXC_GPIO_EMC_B1_40_MQS_RIGHT 0x400E80B0U, 0x2U, 0, 0, 0x400E82F4U +#define IOMUXC_GPIO_EMC_B1_40_LPUART6_TXD 0x400E80B0U, 0x3U, 0, 0, 0x400E82F4U +#define IOMUXC_GPIO_EMC_B1_40_GPIO_MUX2_IO08 0x400E80B0U, 0x5U, 0, 0, 0x400E82F4U +#define IOMUXC_GPIO_EMC_B1_40_ENET_1G_MDC 0x400E80B0U, 0x7U, 0, 0, 0x400E82F4U +#define IOMUXC_GPIO_EMC_B1_40_CCM_CLKO1 0x400E80B0U, 0x9U, 0, 0, 0x400E82F4U +#define IOMUXC_GPIO_EMC_B1_40_GPIO8_IO08 0x400E80B0U, 0xAU, 0, 0, 0x400E82F4U + +#define IOMUXC_GPIO_EMC_B1_41_GPIO8_IO09 0x400E80B4U, 0xAU, 0, 0, 0x400E82F8U +#define IOMUXC_GPIO_EMC_B1_41_SEMC_CSX00 0x400E80B4U, 0x0U, 0, 0, 0x400E82F8U +#define IOMUXC_GPIO_EMC_B1_41_XBAR1_INOUT13 0x400E80B4U, 0x1U, 0, 0, 0x400E82F8U +#define IOMUXC_GPIO_EMC_B1_41_MQS_LEFT 0x400E80B4U, 0x2U, 0, 0, 0x400E82F8U +#define IOMUXC_GPIO_EMC_B1_41_LPUART6_RXD 0x400E80B4U, 0x3U, 0, 0, 0x400E82F8U +#define IOMUXC_GPIO_EMC_B1_41_FLEXSPI2_B_DATA07 0x400E80B4U, 0x4U, 0, 0, 0x400E82F8U +#define IOMUXC_GPIO_EMC_B1_41_GPIO_MUX2_IO09 0x400E80B4U, 0x5U, 0, 0, 0x400E82F8U +#define IOMUXC_GPIO_EMC_B1_41_ENET_1G_MDIO 0x400E80B4U, 0x7U, 0x400E84C8U, 0x0U, 0x400E82F8U +#define IOMUXC_GPIO_EMC_B1_41_CCM_CLKO2 0x400E80B4U, 0x9U, 0, 0, 0x400E82F8U + +#define IOMUXC_GPIO_EMC_B2_00_SEMC_DATA16 0x400E80B8U, 0x0U, 0, 0, 0x400E82FCU +#define IOMUXC_GPIO_EMC_B2_00_CCM_ENET_REF_CLK_25M 0x400E80B8U, 0x1U, 0, 0, 0x400E82FCU +#define IOMUXC_GPIO_EMC_B2_00_TMR3_TIMER1 0x400E80B8U, 0x2U, 0x400E8658U, 0x0U, 0x400E82FCU +#define IOMUXC_GPIO_EMC_B2_00_LPUART6_CTS_B 0x400E80B8U, 0x3U, 0, 0, 0x400E82FCU +#define IOMUXC_GPIO_EMC_B2_00_FLEXSPI2_B_DATA06 0x400E80B8U, 0x4U, 0, 0, 0x400E82FCU +#define IOMUXC_GPIO_EMC_B2_00_GPIO_MUX2_IO10 0x400E80B8U, 0x5U, 0, 0, 0x400E82FCU +#define IOMUXC_GPIO_EMC_B2_00_XBAR1_INOUT20 0x400E80B8U, 0x6U, 0x400E86D8U, 0x0U, 0x400E82FCU +#define IOMUXC_GPIO_EMC_B2_00_ENET_QOS_1588_EVENT1_OUT 0x400E80B8U, 0x7U, 0, 0, 0x400E82FCU +#define IOMUXC_GPIO_EMC_B2_00_LPSPI1_SCK 0x400E80B8U, 0x8U, 0x400E85D0U, 0x0U, 0x400E82FCU +#define IOMUXC_GPIO_EMC_B2_00_LPI2C2_SCL 0x400E80B8U, 0x9U, 0x400E85B4U, 0x0U, 0x400E82FCU +#define IOMUXC_GPIO_EMC_B2_00_GPIO8_IO10 0x400E80B8U, 0xAU, 0, 0, 0x400E82FCU +#define IOMUXC_GPIO_EMC_B2_00_FLEXPWM3_PWM0_A 0x400E80B8U, 0xBU, 0x400E8530U, 0x1U, 0x400E82FCU + +#define IOMUXC_GPIO_EMC_B2_01_SEMC_DATA17 0x400E80BCU, 0x0U, 0, 0, 0x400E8300U +#define IOMUXC_GPIO_EMC_B2_01_USDHC2_CD_B 0x400E80BCU, 0x1U, 0x400E86D0U, 0x0U, 0x400E8300U +#define IOMUXC_GPIO_EMC_B2_01_TMR4_TIMER1 0x400E80BCU, 0x2U, 0x400E8664U, 0x0U, 0x400E8300U +#define IOMUXC_GPIO_EMC_B2_01_LPUART6_RTS_B 0x400E80BCU, 0x3U, 0, 0, 0x400E8300U +#define IOMUXC_GPIO_EMC_B2_01_FLEXSPI2_B_DATA05 0x400E80BCU, 0x4U, 0, 0, 0x400E8300U +#define IOMUXC_GPIO_EMC_B2_01_GPIO_MUX2_IO11 0x400E80BCU, 0x5U, 0, 0, 0x400E8300U +#define IOMUXC_GPIO_EMC_B2_01_XBAR1_INOUT21 0x400E80BCU, 0x6U, 0x400E86DCU, 0x0U, 0x400E8300U +#define IOMUXC_GPIO_EMC_B2_01_ENET_QOS_1588_EVENT1_IN 0x400E80BCU, 0x7U, 0, 0, 0x400E8300U +#define IOMUXC_GPIO_EMC_B2_01_LPSPI1_PCS0 0x400E80BCU, 0x8U, 0x400E85CCU, 0x0U, 0x400E8300U +#define IOMUXC_GPIO_EMC_B2_01_LPI2C2_SDA 0x400E80BCU, 0x9U, 0x400E85B8U, 0x0U, 0x400E8300U +#define IOMUXC_GPIO_EMC_B2_01_GPIO8_IO11 0x400E80BCU, 0xAU, 0, 0, 0x400E8300U +#define IOMUXC_GPIO_EMC_B2_01_FLEXPWM3_PWM0_B 0x400E80BCU, 0xBU, 0x400E8540U, 0x1U, 0x400E8300U + +#define IOMUXC_GPIO_EMC_B2_02_SEMC_DATA18 0x400E80C0U, 0x0U, 0, 0, 0x400E8304U +#define IOMUXC_GPIO_EMC_B2_02_USDHC2_WP 0x400E80C0U, 0x1U, 0x400E86D4U, 0x0U, 0x400E8304U +#define IOMUXC_GPIO_EMC_B2_02_VIDEO_MUX_CSI_DATA23 0x400E80C0U, 0x3U, 0, 0, 0x400E8304U +#define IOMUXC_GPIO_EMC_B2_02_FLEXSPI2_B_DATA04 0x400E80C0U, 0x4U, 0, 0, 0x400E8304U +#define IOMUXC_GPIO_EMC_B2_02_GPIO_MUX2_IO12 0x400E80C0U, 0x5U, 0, 0, 0x400E8304U +#define IOMUXC_GPIO_EMC_B2_02_XBAR1_INOUT22 0x400E80C0U, 0x6U, 0x400E86E0U, 0x0U, 0x400E8304U +#define IOMUXC_GPIO_EMC_B2_02_ENET_QOS_1588_EVENT1_AUX_IN 0x400E80C0U, 0x7U, 0, 0, 0x400E8304U +#define IOMUXC_GPIO_EMC_B2_02_LPSPI1_SOUT 0x400E80C0U, 0x8U, 0x400E85D8U, 0x0U, 0x400E8304U +#define IOMUXC_GPIO_EMC_B2_02_GPIO8_IO12 0x400E80C0U, 0xAU, 0, 0, 0x400E8304U +#define IOMUXC_GPIO_EMC_B2_02_FLEXPWM3_PWM1_A 0x400E80C0U, 0xBU, 0x400E8534U, 0x1U, 0x400E8304U + +#define IOMUXC_GPIO_EMC_B2_03_SEMC_DATA19 0x400E80C4U, 0x0U, 0, 0, 0x400E8308U +#define IOMUXC_GPIO_EMC_B2_03_USDHC2_VSELECT 0x400E80C4U, 0x1U, 0, 0, 0x400E8308U +#define IOMUXC_GPIO_EMC_B2_03_VIDEO_MUX_CSI_DATA22 0x400E80C4U, 0x3U, 0, 0, 0x400E8308U +#define IOMUXC_GPIO_EMC_B2_03_FLEXSPI2_B_DATA03 0x400E80C4U, 0x4U, 0, 0, 0x400E8308U +#define IOMUXC_GPIO_EMC_B2_03_GPIO_MUX2_IO13 0x400E80C4U, 0x5U, 0, 0, 0x400E8308U +#define IOMUXC_GPIO_EMC_B2_03_XBAR1_INOUT23 0x400E80C4U, 0x6U, 0x400E86E4U, 0x0U, 0x400E8308U +#define IOMUXC_GPIO_EMC_B2_03_ENET_1G_TX_DATA03 0x400E80C4U, 0x7U, 0, 0, 0x400E8308U +#define IOMUXC_GPIO_EMC_B2_03_LPSPI1_SIN 0x400E80C4U, 0x8U, 0x400E85D4U, 0x0U, 0x400E8308U +#define IOMUXC_GPIO_EMC_B2_03_GPIO8_IO13 0x400E80C4U, 0xAU, 0, 0, 0x400E8308U +#define IOMUXC_GPIO_EMC_B2_03_FLEXPWM3_PWM1_B 0x400E80C4U, 0xBU, 0x400E8544U, 0x1U, 0x400E8308U + +#define IOMUXC_GPIO_EMC_B2_04_SEMC_DATA20 0x400E80C8U, 0x0U, 0, 0, 0x400E830CU +#define IOMUXC_GPIO_EMC_B2_04_USDHC2_RESET_B 0x400E80C8U, 0x1U, 0, 0, 0x400E830CU +#define IOMUXC_GPIO_EMC_B2_04_SAI2_MCLK 0x400E80C8U, 0x2U, 0, 0, 0x400E830CU +#define IOMUXC_GPIO_EMC_B2_04_VIDEO_MUX_CSI_DATA21 0x400E80C8U, 0x3U, 0, 0, 0x400E830CU +#define IOMUXC_GPIO_EMC_B2_04_FLEXSPI2_B_DATA02 0x400E80C8U, 0x4U, 0, 0, 0x400E830CU +#define IOMUXC_GPIO_EMC_B2_04_GPIO_MUX2_IO14 0x400E80C8U, 0x5U, 0, 0, 0x400E830CU +#define IOMUXC_GPIO_EMC_B2_04_XBAR1_INOUT24 0x400E80C8U, 0x6U, 0x400E86E8U, 0x0U, 0x400E830CU +#define IOMUXC_GPIO_EMC_B2_04_ENET_1G_TX_DATA02 0x400E80C8U, 0x7U, 0, 0, 0x400E830CU +#define IOMUXC_GPIO_EMC_B2_04_LPSPI3_SCK 0x400E80C8U, 0x8U, 0x400E8600U, 0x0U, 0x400E830CU +#define IOMUXC_GPIO_EMC_B2_04_GPIO8_IO14 0x400E80C8U, 0xAU, 0, 0, 0x400E830CU +#define IOMUXC_GPIO_EMC_B2_04_FLEXPWM3_PWM2_A 0x400E80C8U, 0xBU, 0x400E8538U, 0x1U, 0x400E830CU + +#define IOMUXC_GPIO_EMC_B2_05_SEMC_DATA21 0x400E80CCU, 0x0U, 0, 0, 0x400E8310U +#define IOMUXC_GPIO_EMC_B2_05_GPT3_CLK 0x400E80CCU, 0x1U, 0x400E8598U, 0x0U, 0x400E8310U +#define IOMUXC_GPIO_EMC_B2_05_SAI2_RX_SYNC 0x400E80CCU, 0x2U, 0, 0, 0x400E8310U +#define IOMUXC_GPIO_EMC_B2_05_VIDEO_MUX_CSI_DATA20 0x400E80CCU, 0x3U, 0, 0, 0x400E8310U +#define IOMUXC_GPIO_EMC_B2_05_FLEXSPI2_B_DATA01 0x400E80CCU, 0x4U, 0, 0, 0x400E8310U +#define IOMUXC_GPIO_EMC_B2_05_GPIO_MUX2_IO15 0x400E80CCU, 0x5U, 0, 0, 0x400E8310U +#define IOMUXC_GPIO_EMC_B2_05_XBAR1_INOUT25 0x400E80CCU, 0x6U, 0x400E86ECU, 0x0U, 0x400E8310U +#define IOMUXC_GPIO_EMC_B2_05_ENET_1G_RX_CLK 0x400E80CCU, 0x7U, 0x400E84CCU, 0x0U, 0x400E8310U +#define IOMUXC_GPIO_EMC_B2_05_LPSPI3_PCS0 0x400E80CCU, 0x8U, 0x400E85F0U, 0x0U, 0x400E8310U +#define IOMUXC_GPIO_EMC_B2_05_PIT1_TRIGGER0 0x400E80CCU, 0x9U, 0, 0, 0x400E8310U +#define IOMUXC_GPIO_EMC_B2_05_GPIO8_IO15 0x400E80CCU, 0xAU, 0, 0, 0x400E8310U +#define IOMUXC_GPIO_EMC_B2_05_FLEXPWM3_PWM2_B 0x400E80CCU, 0xBU, 0x400E8548U, 0x1U, 0x400E8310U + +#define IOMUXC_GPIO_EMC_B2_06_SEMC_DATA22 0x400E80D0U, 0x0U, 0, 0, 0x400E8314U +#define IOMUXC_GPIO_EMC_B2_06_GPT3_CAPTURE1 0x400E80D0U, 0x1U, 0x400E8590U, 0x0U, 0x400E8314U +#define IOMUXC_GPIO_EMC_B2_06_GPIO8_IO16 0x400E80D0U, 0xAU, 0, 0, 0x400E8314U +#define IOMUXC_GPIO_EMC_B2_06_SAI2_RX_BCLK 0x400E80D0U, 0x2U, 0, 0, 0x400E8314U +#define IOMUXC_GPIO_EMC_B2_06_FLEXPWM3_PWM3_A 0x400E80D0U, 0xBU, 0x400E853CU, 0x1U, 0x400E8314U +#define IOMUXC_GPIO_EMC_B2_06_VIDEO_MUX_CSI_DATA19 0x400E80D0U, 0x3U, 0, 0, 0x400E8314U +#define IOMUXC_GPIO_EMC_B2_06_FLEXSPI2_B_DATA00 0x400E80D0U, 0x4U, 0, 0, 0x400E8314U +#define IOMUXC_GPIO_EMC_B2_06_GPIO_MUX2_IO16 0x400E80D0U, 0x5U, 0, 0, 0x400E8314U +#define IOMUXC_GPIO_EMC_B2_06_XBAR1_INOUT26 0x400E80D0U, 0x6U, 0x400E86F0U, 0x0U, 0x400E8314U +#define IOMUXC_GPIO_EMC_B2_06_ENET_1G_TX_ER 0x400E80D0U, 0x7U, 0, 0, 0x400E8314U +#define IOMUXC_GPIO_EMC_B2_06_LPSPI3_SOUT 0x400E80D0U, 0x8U, 0x400E8608U, 0x0U, 0x400E8314U +#define IOMUXC_GPIO_EMC_B2_06_PIT1_TRIGGER1 0x400E80D0U, 0x9U, 0, 0, 0x400E8314U + +#define IOMUXC_GPIO_EMC_B2_07_SEMC_DATA23 0x400E80D4U, 0x0U, 0, 0, 0x400E8318U +#define IOMUXC_GPIO_EMC_B2_07_GPT3_CAPTURE2 0x400E80D4U, 0x1U, 0x400E8594U, 0x0U, 0x400E8318U +#define IOMUXC_GPIO_EMC_B2_07_SAI2_RX_DATA 0x400E80D4U, 0x2U, 0, 0, 0x400E8318U +#define IOMUXC_GPIO_EMC_B2_07_VIDEO_MUX_CSI_DATA18 0x400E80D4U, 0x3U, 0, 0, 0x400E8318U +#define IOMUXC_GPIO_EMC_B2_07_FLEXSPI2_B_DQS 0x400E80D4U, 0x4U, 0, 0, 0x400E8318U +#define IOMUXC_GPIO_EMC_B2_07_GPIO_MUX2_IO17 0x400E80D4U, 0x5U, 0, 0, 0x400E8318U +#define IOMUXC_GPIO_EMC_B2_07_XBAR1_INOUT27 0x400E80D4U, 0x6U, 0x400E86F4U, 0x0U, 0x400E8318U +#define IOMUXC_GPIO_EMC_B2_07_ENET_1G_RX_DATA03 0x400E80D4U, 0x7U, 0x400E84DCU, 0x0U, 0x400E8318U +#define IOMUXC_GPIO_EMC_B2_07_LPSPI3_SIN 0x400E80D4U, 0x8U, 0x400E8604U, 0x0U, 0x400E8318U +#define IOMUXC_GPIO_EMC_B2_07_PIT1_TRIGGER2 0x400E80D4U, 0x9U, 0, 0, 0x400E8318U +#define IOMUXC_GPIO_EMC_B2_07_GPIO8_IO17 0x400E80D4U, 0xAU, 0, 0, 0x400E8318U +#define IOMUXC_GPIO_EMC_B2_07_FLEXPWM3_PWM3_B 0x400E80D4U, 0xBU, 0x400E854CU, 0x1U, 0x400E8318U + +#define IOMUXC_GPIO_EMC_B2_08_SEMC_DM02 0x400E80D8U, 0x0U, 0, 0, 0x400E831CU +#define IOMUXC_GPIO_EMC_B2_08_GPT3_COMPARE1 0x400E80D8U, 0x1U, 0, 0, 0x400E831CU +#define IOMUXC_GPIO_EMC_B2_08_SAI2_TX_DATA 0x400E80D8U, 0x2U, 0, 0, 0x400E831CU +#define IOMUXC_GPIO_EMC_B2_08_VIDEO_MUX_CSI_DATA17 0x400E80D8U, 0x3U, 0, 0, 0x400E831CU +#define IOMUXC_GPIO_EMC_B2_08_FLEXSPI2_B_SS0_B 0x400E80D8U, 0x4U, 0, 0, 0x400E831CU +#define IOMUXC_GPIO_EMC_B2_08_GPIO_MUX2_IO18 0x400E80D8U, 0x5U, 0, 0, 0x400E831CU +#define IOMUXC_GPIO_EMC_B2_08_XBAR1_INOUT28 0x400E80D8U, 0x6U, 0x400E86F8U, 0x0U, 0x400E831CU +#define IOMUXC_GPIO_EMC_B2_08_ENET_1G_RX_DATA02 0x400E80D8U, 0x7U, 0x400E84D8U, 0x0U, 0x400E831CU +#define IOMUXC_GPIO_EMC_B2_08_LPSPI3_PCS1 0x400E80D8U, 0x8U, 0x400E85F4U, 0x0U, 0x400E831CU +#define IOMUXC_GPIO_EMC_B2_08_PIT1_TRIGGER3 0x400E80D8U, 0x9U, 0, 0, 0x400E831CU +#define IOMUXC_GPIO_EMC_B2_08_GPIO8_IO18 0x400E80D8U, 0xAU, 0, 0, 0x400E831CU + +#define IOMUXC_GPIO_EMC_B2_09_GPIO8_IO19 0x400E80DCU, 0xAU, 0, 0, 0x400E8320U +#define IOMUXC_GPIO_EMC_B2_09_SEMC_DATA24 0x400E80DCU, 0x0U, 0, 0, 0x400E8320U +#define IOMUXC_GPIO_EMC_B2_09_GPT3_COMPARE2 0x400E80DCU, 0x1U, 0, 0, 0x400E8320U +#define IOMUXC_GPIO_EMC_B2_09_SAI2_TX_BCLK 0x400E80DCU, 0x2U, 0, 0, 0x400E8320U +#define IOMUXC_GPIO_EMC_B2_09_VIDEO_MUX_CSI_DATA16 0x400E80DCU, 0x3U, 0, 0, 0x400E8320U +#define IOMUXC_GPIO_EMC_B2_09_FLEXSPI2_B_SCLK 0x400E80DCU, 0x4U, 0, 0, 0x400E8320U +#define IOMUXC_GPIO_EMC_B2_09_GPIO_MUX2_IO19 0x400E80DCU, 0x5U, 0, 0, 0x400E8320U +#define IOMUXC_GPIO_EMC_B2_09_XBAR1_INOUT29 0x400E80DCU, 0x6U, 0x400E86FCU, 0x0U, 0x400E8320U +#define IOMUXC_GPIO_EMC_B2_09_ENET_1G_CRS 0x400E80DCU, 0x7U, 0, 0, 0x400E8320U +#define IOMUXC_GPIO_EMC_B2_09_LPSPI3_PCS2 0x400E80DCU, 0x8U, 0x400E85F8U, 0x0U, 0x400E8320U +#define IOMUXC_GPIO_EMC_B2_09_TMR1_TIMER0 0x400E80DCU, 0x9U, 0x400E863CU, 0x1U, 0x400E8320U + +#define IOMUXC_GPIO_EMC_B2_10_GPIO8_IO20 0x400E80E0U, 0xAU, 0, 0, 0x400E8324U +#define IOMUXC_GPIO_EMC_B2_10_SEMC_DATA25 0x400E80E0U, 0x0U, 0, 0, 0x400E8324U +#define IOMUXC_GPIO_EMC_B2_10_GPT3_COMPARE3 0x400E80E0U, 0x1U, 0, 0, 0x400E8324U +#define IOMUXC_GPIO_EMC_B2_10_SAI2_TX_SYNC 0x400E80E0U, 0x2U, 0, 0, 0x400E8324U +#define IOMUXC_GPIO_EMC_B2_10_VIDEO_MUX_CSI_FIELD 0x400E80E0U, 0x3U, 0, 0, 0x400E8324U +#define IOMUXC_GPIO_EMC_B2_10_FLEXSPI2_A_SCLK 0x400E80E0U, 0x4U, 0x400E858CU, 0x0U, 0x400E8324U +#define IOMUXC_GPIO_EMC_B2_10_GPIO_MUX2_IO20 0x400E80E0U, 0x5U, 0, 0, 0x400E8324U +#define IOMUXC_GPIO_EMC_B2_10_XBAR1_INOUT30 0x400E80E0U, 0x6U, 0x400E8700U, 0x0U, 0x400E8324U +#define IOMUXC_GPIO_EMC_B2_10_ENET_1G_COL 0x400E80E0U, 0x7U, 0, 0, 0x400E8324U +#define IOMUXC_GPIO_EMC_B2_10_LPSPI3_PCS3 0x400E80E0U, 0x8U, 0x400E85FCU, 0x0U, 0x400E8324U +#define IOMUXC_GPIO_EMC_B2_10_TMR1_TIMER1 0x400E80E0U, 0x9U, 0x400E8640U, 0x1U, 0x400E8324U + +#define IOMUXC_GPIO_EMC_B2_11_SEMC_DATA26 0x400E80E4U, 0x0U, 0, 0, 0x400E8328U +#define IOMUXC_GPIO_EMC_B2_11_SPDIF_IN 0x400E80E4U, 0x1U, 0x400E86B4U, 0x0U, 0x400E8328U +#define IOMUXC_GPIO_EMC_B2_11_ENET_1G_TX_DATA00 0x400E80E4U, 0x2U, 0, 0, 0x400E8328U +#define IOMUXC_GPIO_EMC_B2_11_SAI3_RX_SYNC 0x400E80E4U, 0x3U, 0, 0, 0x400E8328U +#define IOMUXC_GPIO_EMC_B2_11_FLEXSPI2_A_SS0_B 0x400E80E4U, 0x4U, 0, 0, 0x400E8328U +#define IOMUXC_GPIO_EMC_B2_11_GPIO_MUX2_IO21 0x400E80E4U, 0x5U, 0, 0, 0x400E8328U +#define IOMUXC_GPIO_EMC_B2_11_XBAR1_INOUT31 0x400E80E4U, 0x6U, 0x400E8704U, 0x0U, 0x400E8328U +#define IOMUXC_GPIO_EMC_B2_11_EMVSIM1_IO 0x400E80E4U, 0x8U, 0x400E869CU, 0x0U, 0x400E8328U +#define IOMUXC_GPIO_EMC_B2_11_TMR1_TIMER2 0x400E80E4U, 0x9U, 0x400E8644U, 0x0U, 0x400E8328U +#define IOMUXC_GPIO_EMC_B2_11_GPIO8_IO21 0x400E80E4U, 0xAU, 0, 0, 0x400E8328U + +#define IOMUXC_GPIO_EMC_B2_12_SEMC_DATA27 0x400E80E8U, 0x0U, 0, 0, 0x400E832CU +#define IOMUXC_GPIO_EMC_B2_12_SPDIF_OUT 0x400E80E8U, 0x1U, 0, 0, 0x400E832CU +#define IOMUXC_GPIO_EMC_B2_12_ENET_1G_TX_DATA01 0x400E80E8U, 0x2U, 0, 0, 0x400E832CU +#define IOMUXC_GPIO_EMC_B2_12_SAI3_RX_BCLK 0x400E80E8U, 0x3U, 0, 0, 0x400E832CU +#define IOMUXC_GPIO_EMC_B2_12_FLEXSPI2_A_DQS 0x400E80E8U, 0x4U, 0, 0, 0x400E832CU +#define IOMUXC_GPIO_EMC_B2_12_GPIO_MUX2_IO22 0x400E80E8U, 0x5U, 0, 0, 0x400E832CU +#define IOMUXC_GPIO_EMC_B2_12_XBAR1_INOUT32 0x400E80E8U, 0x6U, 0x400E8708U, 0x0U, 0x400E832CU +#define IOMUXC_GPIO_EMC_B2_12_EMVSIM1_CLK 0x400E80E8U, 0x8U, 0, 0, 0x400E832CU +#define IOMUXC_GPIO_EMC_B2_12_TMR1_TIMER3 0x400E80E8U, 0x9U, 0, 0, 0x400E832CU +#define IOMUXC_GPIO_EMC_B2_12_GPIO8_IO22 0x400E80E8U, 0xAU, 0, 0, 0x400E832CU + +#define IOMUXC_GPIO_EMC_B2_13_GPIO8_IO23 0x400E80ECU, 0xAU, 0, 0, 0x400E8330U +#define IOMUXC_GPIO_EMC_B2_13_SEMC_DATA28 0x400E80ECU, 0x0U, 0, 0, 0x400E8330U +#define IOMUXC_GPIO_EMC_B2_13_ENET_1G_TX_EN 0x400E80ECU, 0x2U, 0, 0, 0x400E8330U +#define IOMUXC_GPIO_EMC_B2_13_SAI3_RX_DATA 0x400E80ECU, 0x3U, 0, 0, 0x400E8330U +#define IOMUXC_GPIO_EMC_B2_13_FLEXSPI2_A_DATA00 0x400E80ECU, 0x4U, 0x400E857CU, 0x0U, 0x400E8330U +#define IOMUXC_GPIO_EMC_B2_13_GPIO_MUX2_IO23 0x400E80ECU, 0x5U, 0, 0, 0x400E8330U +#define IOMUXC_GPIO_EMC_B2_13_XBAR1_INOUT33 0x400E80ECU, 0x6U, 0x400E870CU, 0x0U, 0x400E8330U +#define IOMUXC_GPIO_EMC_B2_13_EMVSIM1_RST 0x400E80ECU, 0x8U, 0, 0, 0x400E8330U +#define IOMUXC_GPIO_EMC_B2_13_TMR2_TIMER0 0x400E80ECU, 0x9U, 0x400E8648U, 0x1U, 0x400E8330U + +#define IOMUXC_GPIO_EMC_B2_14_SEMC_DATA29 0x400E80F0U, 0x0U, 0, 0, 0x400E8334U +#define IOMUXC_GPIO_EMC_B2_14_ENET_1G_TX_CLK_IO 0x400E80F0U, 0x2U, 0x400E84E8U, 0x0U, 0x400E8334U +#define IOMUXC_GPIO_EMC_B2_14_SAI3_TX_DATA 0x400E80F0U, 0x3U, 0, 0, 0x400E8334U +#define IOMUXC_GPIO_EMC_B2_14_FLEXSPI2_A_DATA01 0x400E80F0U, 0x4U, 0x400E8580U, 0x0U, 0x400E8334U +#define IOMUXC_GPIO_EMC_B2_14_GPIO_MUX2_IO24 0x400E80F0U, 0x5U, 0, 0, 0x400E8334U +#define IOMUXC_GPIO_EMC_B2_14_XBAR1_INOUT34 0x400E80F0U, 0x6U, 0x400E8710U, 0x0U, 0x400E8334U +#define IOMUXC_GPIO_EMC_B2_14_SFA_ipp_do_atx_clk_under_test 0x400E80F0U, 0x7U, 0, 0, 0x400E8334U +#define IOMUXC_GPIO_EMC_B2_14_EMVSIM1_SVEN 0x400E80F0U, 0x8U, 0, 0, 0x400E8334U +#define IOMUXC_GPIO_EMC_B2_14_TMR2_TIMER1 0x400E80F0U, 0x9U, 0x400E864CU, 0x1U, 0x400E8334U +#define IOMUXC_GPIO_EMC_B2_14_GPIO8_IO24 0x400E80F0U, 0xAU, 0, 0, 0x400E8334U + +#define IOMUXC_GPIO_EMC_B2_15_SEMC_DATA30 0x400E80F4U, 0x0U, 0, 0, 0x400E8338U +#define IOMUXC_GPIO_EMC_B2_15_ENET_1G_RX_DATA00 0x400E80F4U, 0x2U, 0x400E84D0U, 0x0U, 0x400E8338U +#define IOMUXC_GPIO_EMC_B2_15_SAI3_TX_BCLK 0x400E80F4U, 0x3U, 0, 0, 0x400E8338U +#define IOMUXC_GPIO_EMC_B2_15_FLEXSPI2_A_DATA02 0x400E80F4U, 0x4U, 0x400E8584U, 0x0U, 0x400E8338U +#define IOMUXC_GPIO_EMC_B2_15_GPIO_MUX2_IO25 0x400E80F4U, 0x5U, 0, 0, 0x400E8338U +#define IOMUXC_GPIO_EMC_B2_15_XBAR1_INOUT35 0x400E80F4U, 0x6U, 0x400E8714U, 0x0U, 0x400E8338U +#define IOMUXC_GPIO_EMC_B2_15_EMVSIM1_PD 0x400E80F4U, 0x8U, 0x400E86A0U, 0x0U, 0x400E8338U +#define IOMUXC_GPIO_EMC_B2_15_TMR2_TIMER2 0x400E80F4U, 0x9U, 0x400E8650U, 0x0U, 0x400E8338U +#define IOMUXC_GPIO_EMC_B2_15_GPIO8_IO25 0x400E80F4U, 0xAU, 0, 0, 0x400E8338U + +#define IOMUXC_GPIO_EMC_B2_16_GPIO8_IO26 0x400E80F8U, 0xAU, 0, 0, 0x400E833CU +#define IOMUXC_GPIO_EMC_B2_16_SEMC_DATA31 0x400E80F8U, 0x0U, 0, 0, 0x400E833CU +#define IOMUXC_GPIO_EMC_B2_16_XBAR1_INOUT14 0x400E80F8U, 0x1U, 0, 0, 0x400E833CU +#define IOMUXC_GPIO_EMC_B2_16_ENET_1G_RX_DATA01 0x400E80F8U, 0x2U, 0x400E84D4U, 0x0U, 0x400E833CU +#define IOMUXC_GPIO_EMC_B2_16_SAI3_TX_SYNC 0x400E80F8U, 0x3U, 0, 0, 0x400E833CU +#define IOMUXC_GPIO_EMC_B2_16_FLEXSPI2_A_DATA03 0x400E80F8U, 0x4U, 0x400E8588U, 0x0U, 0x400E833CU +#define IOMUXC_GPIO_EMC_B2_16_GPIO_MUX2_IO26 0x400E80F8U, 0x5U, 0, 0, 0x400E833CU +#define IOMUXC_GPIO_EMC_B2_16_EMVSIM1_POWER_FAIL 0x400E80F8U, 0x8U, 0x400E86A4U, 0x0U, 0x400E833CU +#define IOMUXC_GPIO_EMC_B2_16_TMR2_TIMER3 0x400E80F8U, 0x9U, 0, 0, 0x400E833CU + +#define IOMUXC_GPIO_EMC_B2_17_SEMC_DM03 0x400E80FCU, 0x0U, 0, 0, 0x400E8340U +#define IOMUXC_GPIO_EMC_B2_17_XBAR1_INOUT15 0x400E80FCU, 0x1U, 0, 0, 0x400E8340U +#define IOMUXC_GPIO_EMC_B2_17_ENET_1G_RX_EN 0x400E80FCU, 0x2U, 0x400E84E0U, 0x0U, 0x400E8340U +#define IOMUXC_GPIO_EMC_B2_17_SAI3_MCLK 0x400E80FCU, 0x3U, 0, 0, 0x400E8340U +#define IOMUXC_GPIO_EMC_B2_17_FLEXSPI2_A_DATA04 0x400E80FCU, 0x4U, 0, 0, 0x400E8340U +#define IOMUXC_GPIO_EMC_B2_17_GPIO_MUX2_IO27 0x400E80FCU, 0x5U, 0, 0, 0x400E8340U +#define IOMUXC_GPIO_EMC_B2_17_WDOG1_ANY 0x400E80FCU, 0x8U, 0, 0, 0x400E8340U +#define IOMUXC_GPIO_EMC_B2_17_TMR3_TIMER0 0x400E80FCU, 0x9U, 0x400E8654U, 0x1U, 0x400E8340U +#define IOMUXC_GPIO_EMC_B2_17_GPIO8_IO27 0x400E80FCU, 0xAU, 0, 0, 0x400E8340U + +#define IOMUXC_GPIO_EMC_B2_18_SEMC_DQS4 0x400E8100U, 0x0U, 0, 0, 0x400E8344U +#define IOMUXC_GPIO_EMC_B2_18_XBAR1_INOUT16 0x400E8100U, 0x1U, 0, 0, 0x400E8344U +#define IOMUXC_GPIO_EMC_B2_18_ENET_1G_RX_ER 0x400E8100U, 0x2U, 0x400E84E4U, 0x0U, 0x400E8344U +#define IOMUXC_GPIO_EMC_B2_18_EWM_OUT_B 0x400E8100U, 0x3U, 0, 0, 0x400E8344U +#define IOMUXC_GPIO_EMC_B2_18_FLEXSPI2_A_DATA05 0x400E8100U, 0x4U, 0, 0, 0x400E8344U +#define IOMUXC_GPIO_EMC_B2_18_GPIO_MUX2_IO28 0x400E8100U, 0x5U, 0, 0, 0x400E8344U +#define IOMUXC_GPIO_EMC_B2_18_FLEXSPI1_A_DQS 0x400E8100U, 0x6U, 0x400E8550U, 0x0U, 0x400E8344U +#define IOMUXC_GPIO_EMC_B2_18_WDOG1_B 0x400E8100U, 0x8U, 0, 0, 0x400E8344U +#define IOMUXC_GPIO_EMC_B2_18_TMR3_TIMER1 0x400E8100U, 0x9U, 0x400E8658U, 0x1U, 0x400E8344U +#define IOMUXC_GPIO_EMC_B2_18_GPIO8_IO28 0x400E8100U, 0xAU, 0, 0, 0x400E8344U + +#define IOMUXC_GPIO_EMC_B2_19_GPIO8_IO29 0x400E8104U, 0xAU, 0, 0, 0x400E8348U +#define IOMUXC_GPIO_EMC_B2_19_SEMC_CLKX00 0x400E8104U, 0x0U, 0, 0, 0x400E8348U +#define IOMUXC_GPIO_EMC_B2_19_ENET_MDC 0x400E8104U, 0x1U, 0, 0, 0x400E8348U +#define IOMUXC_GPIO_EMC_B2_19_ENET_1G_MDC 0x400E8104U, 0x2U, 0, 0, 0x400E8348U +#define IOMUXC_GPIO_EMC_B2_19_ENET_1G_REF_CLK 0x400E8104U, 0x3U, 0x400E84C4U, 0x0U, 0x400E8348U +#define IOMUXC_GPIO_EMC_B2_19_FLEXSPI2_A_DATA06 0x400E8104U, 0x4U, 0, 0, 0x400E8348U +#define IOMUXC_GPIO_EMC_B2_19_GPIO_MUX2_IO29 0x400E8104U, 0x5U, 0, 0, 0x400E8348U +#define IOMUXC_GPIO_EMC_B2_19_ENET_QOS_MDC 0x400E8104U, 0x8U, 0, 0, 0x400E8348U +#define IOMUXC_GPIO_EMC_B2_19_TMR3_TIMER2 0x400E8104U, 0x9U, 0x400E865CU, 0x0U, 0x400E8348U + +#define IOMUXC_GPIO_EMC_B2_20_GPIO8_IO30 0x400E8108U, 0xAU, 0, 0, 0x400E834CU +#define IOMUXC_GPIO_EMC_B2_20_SEMC_CLKX01 0x400E8108U, 0x0U, 0, 0, 0x400E834CU +#define IOMUXC_GPIO_EMC_B2_20_ENET_MDIO 0x400E8108U, 0x1U, 0x400E84ACU, 0x0U, 0x400E834CU +#define IOMUXC_GPIO_EMC_B2_20_ENET_1G_MDIO 0x400E8108U, 0x2U, 0x400E84C8U, 0x1U, 0x400E834CU +#define IOMUXC_GPIO_EMC_B2_20_ENET_QOS_REF_CLK 0x400E8108U, 0x3U, 0x400E84A0U, 0x0U, 0x400E834CU +#define IOMUXC_GPIO_EMC_B2_20_FLEXSPI2_A_DATA07 0x400E8108U, 0x4U, 0, 0, 0x400E834CU +#define IOMUXC_GPIO_EMC_B2_20_GPIO_MUX2_IO30 0x400E8108U, 0x5U, 0, 0, 0x400E834CU +#define IOMUXC_GPIO_EMC_B2_20_ENET_QOS_MDIO 0x400E8108U, 0x8U, 0x400E84ECU, 0x0U, 0x400E834CU +#define IOMUXC_GPIO_EMC_B2_20_TMR3_TIMER3 0x400E8108U, 0x9U, 0, 0, 0x400E834CU + +#define IOMUXC_GPIO_AD_00_GPIO8_IO31 0x400E810CU, 0xAU, 0, 0, 0x400E8350U +#define IOMUXC_GPIO_AD_00_EMVSIM1_IO 0x400E810CU, 0x0U, 0x400E869CU, 0x1U, 0x400E8350U +#define IOMUXC_GPIO_AD_00_FLEXCAN2_TX 0x400E810CU, 0x1U, 0, 0, 0x400E8350U +#define IOMUXC_GPIO_AD_00_ENET_1G_1588_EVENT1_IN 0x400E810CU, 0x2U, 0, 0, 0x400E8350U +#define IOMUXC_GPIO_AD_00_GPT2_CAPTURE1 0x400E810CU, 0x3U, 0, 0, 0x400E8350U +#define IOMUXC_GPIO_AD_00_FLEXPWM1_PWM0_A 0x400E810CU, 0x4U, 0x400E8500U, 0x1U, 0x400E8350U +#define IOMUXC_GPIO_AD_00_GPIO_MUX2_IO31 0x400E810CU, 0x5U, 0, 0, 0x400E8350U +#define IOMUXC_GPIO_AD_00_LPUART7_TXD 0x400E810CU, 0x6U, 0x400E8630U, 0x0U, 0x400E8350U +#define IOMUXC_GPIO_AD_00_FLEXIO2_D00 0x400E810CU, 0x8U, 0, 0, 0x400E8350U +#define IOMUXC_GPIO_AD_00_FLEXSPI2_B_SS1_B 0x400E810CU, 0x9U, 0, 0, 0x400E8350U + +#define IOMUXC_GPIO_AD_01_GPIO9_IO00 0x400E8110U, 0xAU, 0, 0, 0x400E8354U +#define IOMUXC_GPIO_AD_01_EMVSIM1_CLK 0x400E8110U, 0x0U, 0, 0, 0x400E8354U +#define IOMUXC_GPIO_AD_01_FLEXCAN2_RX 0x400E8110U, 0x1U, 0x400E849CU, 0x0U, 0x400E8354U +#define IOMUXC_GPIO_AD_01_ENET_1G_1588_EVENT1_OUT 0x400E8110U, 0x2U, 0, 0, 0x400E8354U +#define IOMUXC_GPIO_AD_01_GPT2_CAPTURE2 0x400E8110U, 0x3U, 0, 0, 0x400E8354U +#define IOMUXC_GPIO_AD_01_FLEXPWM1_PWM0_B 0x400E8110U, 0x4U, 0x400E850CU, 0x1U, 0x400E8354U +#define IOMUXC_GPIO_AD_01_GPIO_MUX3_IO00 0x400E8110U, 0x5U, 0, 0, 0x400E8354U +#define IOMUXC_GPIO_AD_01_LPUART7_RXD 0x400E8110U, 0x6U, 0x400E862CU, 0x0U, 0x400E8354U +#define IOMUXC_GPIO_AD_01_FLEXIO2_D01 0x400E8110U, 0x8U, 0, 0, 0x400E8354U +#define IOMUXC_GPIO_AD_01_FLEXSPI2_A_SS1_B 0x400E8110U, 0x9U, 0, 0, 0x400E8354U + +#define IOMUXC_GPIO_AD_02_GPIO9_IO01 0x400E8114U, 0xAU, 0, 0, 0x400E8358U +#define IOMUXC_GPIO_AD_02_EMVSIM1_RST 0x400E8114U, 0x0U, 0, 0, 0x400E8358U +#define IOMUXC_GPIO_AD_02_LPUART7_CTS_B 0x400E8114U, 0x1U, 0, 0, 0x400E8358U +#define IOMUXC_GPIO_AD_02_ENET_1G_1588_EVENT2_IN 0x400E8114U, 0x2U, 0, 0, 0x400E8358U +#define IOMUXC_GPIO_AD_02_GPT2_COMPARE1 0x400E8114U, 0x3U, 0, 0, 0x400E8358U +#define IOMUXC_GPIO_AD_02_FLEXPWM1_PWM1_A 0x400E8114U, 0x4U, 0x400E8504U, 0x1U, 0x400E8358U +#define IOMUXC_GPIO_AD_02_GPIO_MUX3_IO01 0x400E8114U, 0x5U, 0, 0, 0x400E8358U +#define IOMUXC_GPIO_AD_02_LPUART8_TXD 0x400E8114U, 0x6U, 0x400E8638U, 0x0U, 0x400E8358U +#define IOMUXC_GPIO_AD_02_FLEXIO2_D02 0x400E8114U, 0x8U, 0, 0, 0x400E8358U +#define IOMUXC_GPIO_AD_02_VIDEO_MUX_EXT_DCIC1 0x400E8114U, 0x9U, 0, 0, 0x400E8358U + +#define IOMUXC_GPIO_AD_03_GPIO9_IO02 0x400E8118U, 0xAU, 0, 0, 0x400E835CU +#define IOMUXC_GPIO_AD_03_EMVSIM1_SVEN 0x400E8118U, 0x0U, 0, 0, 0x400E835CU +#define IOMUXC_GPIO_AD_03_LPUART7_RTS_B 0x400E8118U, 0x1U, 0, 0, 0x400E835CU +#define IOMUXC_GPIO_AD_03_ENET_1G_1588_EVENT2_OUT 0x400E8118U, 0x2U, 0, 0, 0x400E835CU +#define IOMUXC_GPIO_AD_03_GPT2_COMPARE2 0x400E8118U, 0x3U, 0, 0, 0x400E835CU +#define IOMUXC_GPIO_AD_03_FLEXPWM1_PWM1_B 0x400E8118U, 0x4U, 0x400E8510U, 0x1U, 0x400E835CU +#define IOMUXC_GPIO_AD_03_GPIO_MUX3_IO02 0x400E8118U, 0x5U, 0, 0, 0x400E835CU +#define IOMUXC_GPIO_AD_03_LPUART8_RXD 0x400E8118U, 0x6U, 0x400E8634U, 0x0U, 0x400E835CU +#define IOMUXC_GPIO_AD_03_FLEXIO2_D03 0x400E8118U, 0x8U, 0, 0, 0x400E835CU +#define IOMUXC_GPIO_AD_03_VIDEO_MUX_EXT_DCIC2 0x400E8118U, 0x9U, 0, 0, 0x400E835CU + +#define IOMUXC_GPIO_AD_04_EMVSIM1_PD 0x400E811CU, 0x0U, 0x400E86A0U, 0x1U, 0x400E8360U +#define IOMUXC_GPIO_AD_04_LPUART8_CTS_B 0x400E811CU, 0x1U, 0, 0, 0x400E8360U +#define IOMUXC_GPIO_AD_04_ENET_1G_1588_EVENT3_IN 0x400E811CU, 0x2U, 0, 0, 0x400E8360U +#define IOMUXC_GPIO_AD_04_GPT2_COMPARE3 0x400E811CU, 0x3U, 0, 0, 0x400E8360U +#define IOMUXC_GPIO_AD_04_FLEXPWM1_PWM2_A 0x400E811CU, 0x4U, 0x400E8508U, 0x1U, 0x400E8360U +#define IOMUXC_GPIO_AD_04_GPIO_MUX3_IO03 0x400E811CU, 0x5U, 0, 0, 0x400E8360U +#define IOMUXC_GPIO_AD_04_WDOG1_B 0x400E811CU, 0x6U, 0, 0, 0x400E8360U +#define IOMUXC_GPIO_AD_04_FLEXIO2_D04 0x400E811CU, 0x8U, 0, 0, 0x400E8360U +#define IOMUXC_GPIO_AD_04_TMR4_TIMER0 0x400E811CU, 0x9U, 0x400E8660U, 0x1U, 0x400E8360U +#define IOMUXC_GPIO_AD_04_GPIO9_IO03 0x400E811CU, 0xAU, 0, 0, 0x400E8360U + +#define IOMUXC_GPIO_AD_05_EMVSIM1_POWER_FAIL 0x400E8120U, 0x0U, 0x400E86A4U, 0x1U, 0x400E8364U +#define IOMUXC_GPIO_AD_05_LPUART8_RTS_B 0x400E8120U, 0x1U, 0, 0, 0x400E8364U +#define IOMUXC_GPIO_AD_05_ENET_1G_1588_EVENT3_OUT 0x400E8120U, 0x2U, 0, 0, 0x400E8364U +#define IOMUXC_GPIO_AD_05_GPT2_CLK 0x400E8120U, 0x3U, 0, 0, 0x400E8364U +#define IOMUXC_GPIO_AD_05_FLEXPWM1_PWM2_B 0x400E8120U, 0x4U, 0x400E8514U, 0x1U, 0x400E8364U +#define IOMUXC_GPIO_AD_05_GPIO_MUX3_IO04 0x400E8120U, 0x5U, 0, 0, 0x400E8364U +#define IOMUXC_GPIO_AD_05_WDOG2_B 0x400E8120U, 0x6U, 0, 0, 0x400E8364U +#define IOMUXC_GPIO_AD_05_FLEXIO2_D05 0x400E8120U, 0x8U, 0, 0, 0x400E8364U +#define IOMUXC_GPIO_AD_05_TMR4_TIMER1 0x400E8120U, 0x9U, 0x400E8664U, 0x1U, 0x400E8364U +#define IOMUXC_GPIO_AD_05_GPIO9_IO04 0x400E8120U, 0xAU, 0, 0, 0x400E8364U + +#define IOMUXC_GPIO_AD_06_USB_OTG2_OC 0x400E8124U, 0x0U, 0x400E86B8U, 0x0U, 0x400E8368U +#define IOMUXC_GPIO_AD_06_FLEXCAN1_TX 0x400E8124U, 0x1U, 0, 0, 0x400E8368U +#define IOMUXC_GPIO_AD_06_EMVSIM2_IO 0x400E8124U, 0x2U, 0x400E86A8U, 0x0U, 0x400E8368U +#define IOMUXC_GPIO_AD_06_GPT3_CAPTURE1 0x400E8124U, 0x3U, 0x400E8590U, 0x1U, 0x400E8368U +#define IOMUXC_GPIO_AD_06_VIDEO_MUX_CSI_DATA15 0x400E8124U, 0x4U, 0, 0, 0x400E8368U +#define IOMUXC_GPIO_AD_06_GPIO_MUX3_IO05 0x400E8124U, 0x5U, 0, 0, 0x400E8368U +#define IOMUXC_GPIO_AD_06_ENET_1588_EVENT1_IN 0x400E8124U, 0x6U, 0, 0, 0x400E8368U +#define IOMUXC_GPIO_AD_06_FLEXIO2_D06 0x400E8124U, 0x8U, 0, 0, 0x400E8368U +#define IOMUXC_GPIO_AD_06_TMR4_TIMER2 0x400E8124U, 0x9U, 0x400E8668U, 0x0U, 0x400E8368U +#define IOMUXC_GPIO_AD_06_GPIO9_IO05 0x400E8124U, 0xAU, 0, 0, 0x400E8368U +#define IOMUXC_GPIO_AD_06_FLEXPWM1_PWM0_X 0x400E8124U, 0xBU, 0, 0, 0x400E8368U + +#define IOMUXC_GPIO_AD_07_USB_OTG2_PWR 0x400E8128U, 0x0U, 0, 0, 0x400E836CU +#define IOMUXC_GPIO_AD_07_FLEXCAN1_RX 0x400E8128U, 0x1U, 0x400E8498U, 0x0U, 0x400E836CU +#define IOMUXC_GPIO_AD_07_EMVSIM2_CLK 0x400E8128U, 0x2U, 0, 0, 0x400E836CU +#define IOMUXC_GPIO_AD_07_GPT3_CAPTURE2 0x400E8128U, 0x3U, 0x400E8594U, 0x1U, 0x400E836CU +#define IOMUXC_GPIO_AD_07_VIDEO_MUX_CSI_DATA14 0x400E8128U, 0x4U, 0, 0, 0x400E836CU +#define IOMUXC_GPIO_AD_07_GPIO_MUX3_IO06 0x400E8128U, 0x5U, 0, 0, 0x400E836CU +#define IOMUXC_GPIO_AD_07_ENET_1588_EVENT1_OUT 0x400E8128U, 0x6U, 0, 0, 0x400E836CU +#define IOMUXC_GPIO_AD_07_FLEXIO2_D07 0x400E8128U, 0x8U, 0, 0, 0x400E836CU +#define IOMUXC_GPIO_AD_07_TMR4_TIMER3 0x400E8128U, 0x9U, 0, 0, 0x400E836CU +#define IOMUXC_GPIO_AD_07_GPIO9_IO06 0x400E8128U, 0xAU, 0, 0, 0x400E836CU +#define IOMUXC_GPIO_AD_07_FLEXPWM1_PWM1_X 0x400E8128U, 0xBU, 0, 0, 0x400E836CU + +#define IOMUXC_GPIO_AD_08_USBPHY2_OTG_ID 0x400E812CU, 0x0U, 0x400E86C4U, 0x0U, 0x400E8370U +#define IOMUXC_GPIO_AD_08_LPI2C1_SCL 0x400E812CU, 0x1U, 0x400E85ACU, 0x0U, 0x400E8370U +#define IOMUXC_GPIO_AD_08_EMVSIM2_RST 0x400E812CU, 0x2U, 0, 0, 0x400E8370U +#define IOMUXC_GPIO_AD_08_GPT3_COMPARE1 0x400E812CU, 0x3U, 0, 0, 0x400E8370U +#define IOMUXC_GPIO_AD_08_VIDEO_MUX_CSI_DATA13 0x400E812CU, 0x4U, 0, 0, 0x400E8370U +#define IOMUXC_GPIO_AD_08_GPIO_MUX3_IO07 0x400E812CU, 0x5U, 0, 0, 0x400E8370U +#define IOMUXC_GPIO_AD_08_ENET_1588_EVENT2_IN 0x400E812CU, 0x6U, 0, 0, 0x400E8370U +#define IOMUXC_GPIO_AD_08_FLEXIO2_D08 0x400E812CU, 0x8U, 0, 0, 0x400E8370U +#define IOMUXC_GPIO_AD_08_GPIO9_IO07 0x400E812CU, 0xAU, 0, 0, 0x400E8370U +#define IOMUXC_GPIO_AD_08_FLEXPWM1_PWM2_X 0x400E812CU, 0xBU, 0, 0, 0x400E8370U + +#define IOMUXC_GPIO_AD_09_USBPHY1_OTG_ID 0x400E8130U, 0x0U, 0x400E86C0U, 0x0U, 0x400E8374U +#define IOMUXC_GPIO_AD_09_LPI2C1_SDA 0x400E8130U, 0x1U, 0x400E85B0U, 0x0U, 0x400E8374U +#define IOMUXC_GPIO_AD_09_EMVSIM2_SVEN 0x400E8130U, 0x2U, 0, 0, 0x400E8374U +#define IOMUXC_GPIO_AD_09_GPT3_COMPARE2 0x400E8130U, 0x3U, 0, 0, 0x400E8374U +#define IOMUXC_GPIO_AD_09_VIDEO_MUX_CSI_DATA12 0x400E8130U, 0x4U, 0, 0, 0x400E8374U +#define IOMUXC_GPIO_AD_09_GPIO_MUX3_IO08 0x400E8130U, 0x5U, 0, 0, 0x400E8374U +#define IOMUXC_GPIO_AD_09_ENET_1588_EVENT2_OUT 0x400E8130U, 0x6U, 0, 0, 0x400E8374U +#define IOMUXC_GPIO_AD_09_FLEXIO2_D09 0x400E8130U, 0x8U, 0, 0, 0x400E8374U +#define IOMUXC_GPIO_AD_09_GPIO9_IO08 0x400E8130U, 0xAU, 0, 0, 0x400E8374U +#define IOMUXC_GPIO_AD_09_FLEXPWM1_PWM3_X 0x400E8130U, 0xBU, 0, 0, 0x400E8374U + +#define IOMUXC_GPIO_AD_10_USB_OTG1_PWR 0x400E8134U, 0x0U, 0, 0, 0x400E8378U +#define IOMUXC_GPIO_AD_10_LPI2C1_SCLS 0x400E8134U, 0x1U, 0, 0, 0x400E8378U +#define IOMUXC_GPIO_AD_10_EMVSIM2_PD 0x400E8134U, 0x2U, 0x400E86ACU, 0x0U, 0x400E8378U +#define IOMUXC_GPIO_AD_10_GPT3_COMPARE3 0x400E8134U, 0x3U, 0, 0, 0x400E8378U +#define IOMUXC_GPIO_AD_10_VIDEO_MUX_CSI_DATA11 0x400E8134U, 0x4U, 0, 0, 0x400E8378U +#define IOMUXC_GPIO_AD_10_GPIO_MUX3_IO09 0x400E8134U, 0x5U, 0, 0, 0x400E8378U +#define IOMUXC_GPIO_AD_10_ENET_1588_EVENT3_IN 0x400E8134U, 0x6U, 0, 0, 0x400E8378U +#define IOMUXC_GPIO_AD_10_FLEXIO2_D10 0x400E8134U, 0x8U, 0, 0, 0x400E8378U +#define IOMUXC_GPIO_AD_10_GPIO9_IO09 0x400E8134U, 0xAU, 0, 0, 0x400E8378U +#define IOMUXC_GPIO_AD_10_FLEXPWM2_PWM0_X 0x400E8134U, 0xBU, 0, 0, 0x400E8378U + +#define IOMUXC_GPIO_AD_11_USB_OTG1_OC 0x400E8138U, 0x0U, 0x400E86BCU, 0x0U, 0x400E837CU +#define IOMUXC_GPIO_AD_11_LPI2C1_SDAS 0x400E8138U, 0x1U, 0, 0, 0x400E837CU +#define IOMUXC_GPIO_AD_11_EMVSIM2_POWER_FAIL 0x400E8138U, 0x2U, 0x400E86B0U, 0x0U, 0x400E837CU +#define IOMUXC_GPIO_AD_11_GPT3_CLK 0x400E8138U, 0x3U, 0x400E8598U, 0x1U, 0x400E837CU +#define IOMUXC_GPIO_AD_11_VIDEO_MUX_CSI_DATA10 0x400E8138U, 0x4U, 0, 0, 0x400E837CU +#define IOMUXC_GPIO_AD_11_GPIO_MUX3_IO10 0x400E8138U, 0x5U, 0, 0, 0x400E837CU +#define IOMUXC_GPIO_AD_11_ENET_1588_EVENT3_OUT 0x400E8138U, 0x6U, 0, 0, 0x400E837CU +#define IOMUXC_GPIO_AD_11_FLEXIO2_D11 0x400E8138U, 0x8U, 0, 0, 0x400E837CU +#define IOMUXC_GPIO_AD_11_GPIO9_IO10 0x400E8138U, 0xAU, 0, 0, 0x400E837CU +#define IOMUXC_GPIO_AD_11_FLEXPWM2_PWM1_X 0x400E8138U, 0xBU, 0, 0, 0x400E837CU + +#define IOMUXC_GPIO_AD_12_SPDIF_LOCK 0x400E813CU, 0x0U, 0, 0, 0x400E8380U +#define IOMUXC_GPIO_AD_12_LPI2C1_HREQ 0x400E813CU, 0x1U, 0, 0, 0x400E8380U +#define IOMUXC_GPIO_AD_12_GPT1_CAPTURE1 0x400E813CU, 0x2U, 0, 0, 0x400E8380U +#define IOMUXC_GPIO_AD_12_FLEXSPI1_B_DATA03 0x400E813CU, 0x3U, 0x400E8570U, 0x0U, 0x400E8380U +#define IOMUXC_GPIO_AD_12_VIDEO_MUX_CSI_PIXCLK 0x400E813CU, 0x4U, 0, 0, 0x400E8380U +#define IOMUXC_GPIO_AD_12_GPIO_MUX3_IO11 0x400E813CU, 0x5U, 0, 0, 0x400E8380U +#define IOMUXC_GPIO_AD_12_ENET_TX_DATA03 0x400E813CU, 0x6U, 0, 0, 0x400E8380U +#define IOMUXC_GPIO_AD_12_FLEXIO2_D12 0x400E813CU, 0x8U, 0, 0, 0x400E8380U +#define IOMUXC_GPIO_AD_12_EWM_OUT_B 0x400E813CU, 0x9U, 0, 0, 0x400E8380U +#define IOMUXC_GPIO_AD_12_GPIO9_IO11 0x400E813CU, 0xAU, 0, 0, 0x400E8380U +#define IOMUXC_GPIO_AD_12_FLEXPWM2_PWM2_X 0x400E813CU, 0xBU, 0, 0, 0x400E8380U + +#define IOMUXC_GPIO_AD_13_SPDIF_SR_CLK 0x400E8140U, 0x0U, 0, 0, 0x400E8384U +#define IOMUXC_GPIO_AD_13_PIT1_TRIGGER0 0x400E8140U, 0x1U, 0, 0, 0x400E8384U +#define IOMUXC_GPIO_AD_13_GPT1_CAPTURE2 0x400E8140U, 0x2U, 0, 0, 0x400E8384U +#define IOMUXC_GPIO_AD_13_FLEXSPI1_B_DATA02 0x400E8140U, 0x3U, 0x400E856CU, 0x0U, 0x400E8384U +#define IOMUXC_GPIO_AD_13_VIDEO_MUX_CSI_MCLK 0x400E8140U, 0x4U, 0, 0, 0x400E8384U +#define IOMUXC_GPIO_AD_13_GPIO_MUX3_IO12 0x400E8140U, 0x5U, 0, 0, 0x400E8384U +#define IOMUXC_GPIO_AD_13_ENET_TX_DATA02 0x400E8140U, 0x6U, 0, 0, 0x400E8384U +#define IOMUXC_GPIO_AD_13_FLEXIO2_D13 0x400E8140U, 0x8U, 0, 0, 0x400E8384U +#define IOMUXC_GPIO_AD_13_REF_CLK_32K 0x400E8140U, 0x9U, 0, 0, 0x400E8384U +#define IOMUXC_GPIO_AD_13_GPIO9_IO12 0x400E8140U, 0xAU, 0, 0, 0x400E8384U +#define IOMUXC_GPIO_AD_13_FLEXPWM2_PWM3_X 0x400E8140U, 0xBU, 0, 0, 0x400E8384U + +#define IOMUXC_GPIO_AD_14_SPDIF_EXT_CLK 0x400E8144U, 0x0U, 0, 0, 0x400E8388U +#define IOMUXC_GPIO_AD_14_REF_CLK_24M 0x400E8144U, 0x1U, 0, 0, 0x400E8388U +#define IOMUXC_GPIO_AD_14_GPT1_COMPARE1 0x400E8144U, 0x2U, 0, 0, 0x400E8388U +#define IOMUXC_GPIO_AD_14_FLEXSPI1_B_DATA01 0x400E8144U, 0x3U, 0x400E8568U, 0x0U, 0x400E8388U +#define IOMUXC_GPIO_AD_14_VIDEO_MUX_CSI_VSYNC 0x400E8144U, 0x4U, 0, 0, 0x400E8388U +#define IOMUXC_GPIO_AD_14_GPIO_MUX3_IO13 0x400E8144U, 0x5U, 0, 0, 0x400E8388U +#define IOMUXC_GPIO_AD_14_ENET_RX_CLK 0x400E8144U, 0x6U, 0, 0, 0x400E8388U +#define IOMUXC_GPIO_AD_14_FLEXIO2_D14 0x400E8144U, 0x8U, 0, 0, 0x400E8388U +#define IOMUXC_GPIO_AD_14_CCM_ENET_REF_CLK_25M 0x400E8144U, 0x9U, 0, 0, 0x400E8388U +#define IOMUXC_GPIO_AD_14_GPIO9_IO13 0x400E8144U, 0xAU, 0, 0, 0x400E8388U +#define IOMUXC_GPIO_AD_14_FLEXPWM3_PWM0_X 0x400E8144U, 0xBU, 0, 0, 0x400E8388U + +#define IOMUXC_GPIO_AD_15_GPIO9_IO14 0x400E8148U, 0xAU, 0, 0, 0x400E838CU +#define IOMUXC_GPIO_AD_15_FLEXPWM3_PWM1_X 0x400E8148U, 0xBU, 0, 0, 0x400E838CU +#define IOMUXC_GPIO_AD_15_SPDIF_IN 0x400E8148U, 0x0U, 0x400E86B4U, 0x1U, 0x400E838CU +#define IOMUXC_GPIO_AD_15_LPUART10_TXD 0x400E8148U, 0x1U, 0x400E8628U, 0x0U, 0x400E838CU +#define IOMUXC_GPIO_AD_15_GPT1_COMPARE2 0x400E8148U, 0x2U, 0, 0, 0x400E838CU +#define IOMUXC_GPIO_AD_15_FLEXSPI1_B_DATA00 0x400E8148U, 0x3U, 0x400E8564U, 0x0U, 0x400E838CU +#define IOMUXC_GPIO_AD_15_VIDEO_MUX_CSI_HSYNC 0x400E8148U, 0x4U, 0, 0, 0x400E838CU +#define IOMUXC_GPIO_AD_15_GPIO_MUX3_IO14 0x400E8148U, 0x5U, 0, 0, 0x400E838CU +#define IOMUXC_GPIO_AD_15_ENET_TX_ER 0x400E8148U, 0x6U, 0, 0, 0x400E838CU +#define IOMUXC_GPIO_AD_15_FLEXIO2_D15 0x400E8148U, 0x8U, 0, 0, 0x400E838CU + +#define IOMUXC_GPIO_AD_16_SPDIF_OUT 0x400E814CU, 0x0U, 0, 0, 0x400E8390U +#define IOMUXC_GPIO_AD_16_LPUART10_RXD 0x400E814CU, 0x1U, 0x400E8624U, 0x0U, 0x400E8390U +#define IOMUXC_GPIO_AD_16_GPT1_COMPARE3 0x400E814CU, 0x2U, 0, 0, 0x400E8390U +#define IOMUXC_GPIO_AD_16_FLEXSPI1_B_SCLK 0x400E814CU, 0x3U, 0x400E8578U, 0x0U, 0x400E8390U +#define IOMUXC_GPIO_AD_16_VIDEO_MUX_CSI_DATA09 0x400E814CU, 0x4U, 0, 0, 0x400E8390U +#define IOMUXC_GPIO_AD_16_GPIO_MUX3_IO15 0x400E814CU, 0x5U, 0, 0, 0x400E8390U +#define IOMUXC_GPIO_AD_16_ENET_RX_DATA03 0x400E814CU, 0x6U, 0, 0, 0x400E8390U +#define IOMUXC_GPIO_AD_16_FLEXIO2_D16 0x400E814CU, 0x8U, 0, 0, 0x400E8390U +#define IOMUXC_GPIO_AD_16_ENET_1G_MDC 0x400E814CU, 0x9U, 0, 0, 0x400E8390U +#define IOMUXC_GPIO_AD_16_GPIO9_IO15 0x400E814CU, 0xAU, 0, 0, 0x400E8390U +#define IOMUXC_GPIO_AD_16_FLEXPWM3_PWM2_X 0x400E814CU, 0xBU, 0, 0, 0x400E8390U + +#define IOMUXC_GPIO_AD_17_SAI1_MCLK 0x400E8150U, 0x0U, 0x400E866CU, 0x0U, 0x400E8394U +#define IOMUXC_GPIO_AD_17_ACMP1_OUT 0x400E8150U, 0x1U, 0, 0, 0x400E8394U +#define IOMUXC_GPIO_AD_17_GPT1_CLK 0x400E8150U, 0x2U, 0, 0, 0x400E8394U +#define IOMUXC_GPIO_AD_17_FLEXSPI1_A_DQS 0x400E8150U, 0x3U, 0x400E8550U, 0x1U, 0x400E8394U +#define IOMUXC_GPIO_AD_17_VIDEO_MUX_CSI_DATA08 0x400E8150U, 0x4U, 0, 0, 0x400E8394U +#define IOMUXC_GPIO_AD_17_GPIO_MUX3_IO16 0x400E8150U, 0x5U, 0, 0, 0x400E8394U +#define IOMUXC_GPIO_AD_17_ENET_RX_DATA02 0x400E8150U, 0x6U, 0, 0, 0x400E8394U +#define IOMUXC_GPIO_AD_17_FLEXIO2_D17 0x400E8150U, 0x8U, 0, 0, 0x400E8394U +#define IOMUXC_GPIO_AD_17_ENET_1G_MDIO 0x400E8150U, 0x9U, 0x400E84C8U, 0x2U, 0x400E8394U +#define IOMUXC_GPIO_AD_17_GPIO9_IO16 0x400E8150U, 0xAU, 0, 0, 0x400E8394U +#define IOMUXC_GPIO_AD_17_FLEXPWM3_PWM3_X 0x400E8150U, 0xBU, 0, 0, 0x400E8394U + +#define IOMUXC_GPIO_AD_18_GPIO9_IO17 0x400E8154U, 0xAU, 0, 0, 0x400E8398U +#define IOMUXC_GPIO_AD_18_FLEXPWM4_PWM0_X 0x400E8154U, 0xBU, 0, 0, 0x400E8398U +#define IOMUXC_GPIO_AD_18_SAI1_RX_SYNC 0x400E8154U, 0x0U, 0x400E8678U, 0x0U, 0x400E8398U +#define IOMUXC_GPIO_AD_18_ACMP2_OUT 0x400E8154U, 0x1U, 0, 0, 0x400E8398U +#define IOMUXC_GPIO_AD_18_LPSPI1_PCS1 0x400E8154U, 0x2U, 0, 0, 0x400E8398U +#define IOMUXC_GPIO_AD_18_FLEXSPI1_A_SS0_B 0x400E8154U, 0x3U, 0, 0, 0x400E8398U +#define IOMUXC_GPIO_AD_18_VIDEO_MUX_CSI_DATA07 0x400E8154U, 0x4U, 0, 0, 0x400E8398U +#define IOMUXC_GPIO_AD_18_GPIO_MUX3_IO17 0x400E8154U, 0x5U, 0, 0, 0x400E8398U +#define IOMUXC_GPIO_AD_18_ENET_CRS 0x400E8154U, 0x6U, 0, 0, 0x400E8398U +#define IOMUXC_GPIO_AD_18_FLEXIO2_D18 0x400E8154U, 0x8U, 0, 0, 0x400E8398U +#define IOMUXC_GPIO_AD_18_LPI2C2_SCL 0x400E8154U, 0x9U, 0x400E85B4U, 0x1U, 0x400E8398U + +#define IOMUXC_GPIO_AD_19_SAI1_RX_BCLK 0x400E8158U, 0x0U, 0x400E8670U, 0x0U, 0x400E839CU +#define IOMUXC_GPIO_AD_19_ACMP3_OUT 0x400E8158U, 0x1U, 0, 0, 0x400E839CU +#define IOMUXC_GPIO_AD_19_LPSPI1_PCS2 0x400E8158U, 0x2U, 0, 0, 0x400E839CU +#define IOMUXC_GPIO_AD_19_FLEXSPI1_A_SCLK 0x400E8158U, 0x3U, 0x400E8574U, 0x0U, 0x400E839CU +#define IOMUXC_GPIO_AD_19_VIDEO_MUX_CSI_DATA06 0x400E8158U, 0x4U, 0, 0, 0x400E839CU +#define IOMUXC_GPIO_AD_19_GPIO_MUX3_IO18 0x400E8158U, 0x5U, 0, 0, 0x400E839CU +#define IOMUXC_GPIO_AD_19_ENET_COL 0x400E8158U, 0x6U, 0, 0, 0x400E839CU +#define IOMUXC_GPIO_AD_19_FLEXIO2_D19 0x400E8158U, 0x8U, 0, 0, 0x400E839CU +#define IOMUXC_GPIO_AD_19_LPI2C2_SDA 0x400E8158U, 0x9U, 0x400E85B8U, 0x1U, 0x400E839CU +#define IOMUXC_GPIO_AD_19_GPIO9_IO18 0x400E8158U, 0xAU, 0, 0, 0x400E839CU +#define IOMUXC_GPIO_AD_19_FLEXPWM4_PWM1_X 0x400E8158U, 0xBU, 0, 0, 0x400E839CU + +#define IOMUXC_GPIO_AD_20_SAI1_RX_DATA00 0x400E815CU, 0x0U, 0x400E8674U, 0x0U, 0x400E83A0U +#define IOMUXC_GPIO_AD_20_ACMP4_OUT 0x400E815CU, 0x1U, 0, 0, 0x400E83A0U +#define IOMUXC_GPIO_AD_20_LPSPI1_PCS3 0x400E815CU, 0x2U, 0, 0, 0x400E83A0U +#define IOMUXC_GPIO_AD_20_FLEXSPI1_A_DATA00 0x400E815CU, 0x3U, 0x400E8554U, 0x0U, 0x400E83A0U +#define IOMUXC_GPIO_AD_20_VIDEO_MUX_CSI_DATA05 0x400E815CU, 0x4U, 0, 0, 0x400E83A0U +#define IOMUXC_GPIO_AD_20_GPIO_MUX3_IO19 0x400E815CU, 0x5U, 0, 0, 0x400E83A0U +#define IOMUXC_GPIO_AD_20_KPP_ROW07 0x400E815CU, 0x6U, 0x400E85A8U, 0x0U, 0x400E83A0U +#define IOMUXC_GPIO_AD_20_FLEXIO2_D20 0x400E815CU, 0x8U, 0, 0, 0x400E83A0U +#define IOMUXC_GPIO_AD_20_ENET_QOS_1588_EVENT2_OUT 0x400E815CU, 0x9U, 0, 0, 0x400E83A0U +#define IOMUXC_GPIO_AD_20_GPIO9_IO19 0x400E815CU, 0xAU, 0, 0, 0x400E83A0U +#define IOMUXC_GPIO_AD_20_FLEXPWM4_PWM2_X 0x400E815CU, 0xBU, 0, 0, 0x400E83A0U + +#define IOMUXC_GPIO_AD_21_SAI1_TX_DATA00 0x400E8160U, 0x0U, 0, 0, 0x400E83A4U +#define IOMUXC_GPIO_AD_21_LPSPI2_PCS1 0x400E8160U, 0x2U, 0x400E85E0U, 0x0U, 0x400E83A4U +#define IOMUXC_GPIO_AD_21_FLEXSPI1_A_DATA01 0x400E8160U, 0x3U, 0x400E8558U, 0x0U, 0x400E83A4U +#define IOMUXC_GPIO_AD_21_VIDEO_MUX_CSI_DATA04 0x400E8160U, 0x4U, 0, 0, 0x400E83A4U +#define IOMUXC_GPIO_AD_21_GPIO_MUX3_IO20 0x400E8160U, 0x5U, 0, 0, 0x400E83A4U +#define IOMUXC_GPIO_AD_21_KPP_COL07 0x400E8160U, 0x6U, 0x400E85A0U, 0x0U, 0x400E83A4U +#define IOMUXC_GPIO_AD_21_FLEXIO2_D21 0x400E8160U, 0x8U, 0, 0, 0x400E83A4U +#define IOMUXC_GPIO_AD_21_ENET_QOS_1588_EVENT2_IN 0x400E8160U, 0x9U, 0, 0, 0x400E83A4U +#define IOMUXC_GPIO_AD_21_GPIO9_IO20 0x400E8160U, 0xAU, 0, 0, 0x400E83A4U +#define IOMUXC_GPIO_AD_21_FLEXPWM4_PWM3_X 0x400E8160U, 0xBU, 0, 0, 0x400E83A4U + +#define IOMUXC_GPIO_AD_22_GPIO9_IO21 0x400E8164U, 0xAU, 0, 0, 0x400E83A8U +#define IOMUXC_GPIO_AD_22_SAI1_TX_BCLK 0x400E8164U, 0x0U, 0x400E867CU, 0x0U, 0x400E83A8U +#define IOMUXC_GPIO_AD_22_LPSPI2_PCS2 0x400E8164U, 0x2U, 0, 0, 0x400E83A8U +#define IOMUXC_GPIO_AD_22_FLEXSPI1_A_DATA02 0x400E8164U, 0x3U, 0x400E855CU, 0x0U, 0x400E83A8U +#define IOMUXC_GPIO_AD_22_VIDEO_MUX_CSI_DATA03 0x400E8164U, 0x4U, 0, 0, 0x400E83A8U +#define IOMUXC_GPIO_AD_22_GPIO_MUX3_IO21 0x400E8164U, 0x5U, 0, 0, 0x400E83A8U +#define IOMUXC_GPIO_AD_22_KPP_ROW06 0x400E8164U, 0x6U, 0x400E85A4U, 0x0U, 0x400E83A8U +#define IOMUXC_GPIO_AD_22_FLEXIO2_D22 0x400E8164U, 0x8U, 0, 0, 0x400E83A8U +#define IOMUXC_GPIO_AD_22_ENET_QOS_1588_EVENT3_OUT 0x400E8164U, 0x9U, 0, 0, 0x400E83A8U + +#define IOMUXC_GPIO_AD_23_SAI1_TX_SYNC 0x400E8168U, 0x0U, 0x400E8680U, 0x0U, 0x400E83ACU +#define IOMUXC_GPIO_AD_23_LPSPI2_PCS3 0x400E8168U, 0x2U, 0, 0, 0x400E83ACU +#define IOMUXC_GPIO_AD_23_FLEXSPI1_A_DATA03 0x400E8168U, 0x3U, 0x400E8560U, 0x0U, 0x400E83ACU +#define IOMUXC_GPIO_AD_23_VIDEO_MUX_CSI_DATA02 0x400E8168U, 0x4U, 0, 0, 0x400E83ACU +#define IOMUXC_GPIO_AD_23_GPIO_MUX3_IO22 0x400E8168U, 0x5U, 0, 0, 0x400E83ACU +#define IOMUXC_GPIO_AD_23_KPP_COL06 0x400E8168U, 0x6U, 0x400E859CU, 0x0U, 0x400E83ACU +#define IOMUXC_GPIO_AD_23_FLEXIO2_D23 0x400E8168U, 0x8U, 0, 0, 0x400E83ACU +#define IOMUXC_GPIO_AD_23_ENET_QOS_1588_EVENT3_IN 0x400E8168U, 0x9U, 0, 0, 0x400E83ACU +#define IOMUXC_GPIO_AD_23_GPIO9_IO22 0x400E8168U, 0xAU, 0, 0, 0x400E83ACU + +#define IOMUXC_GPIO_AD_24_LPUART1_TXD 0x400E816CU, 0x0U, 0x400E8620U, 0x0U, 0x400E83B0U +#define IOMUXC_GPIO_AD_24_LPSPI2_SCK 0x400E816CU, 0x1U, 0x400E85E4U, 0x0U, 0x400E83B0U +#define IOMUXC_GPIO_AD_24_VIDEO_MUX_CSI_DATA00 0x400E816CU, 0x2U, 0, 0, 0x400E83B0U +#define IOMUXC_GPIO_AD_24_ENET_RX_EN 0x400E816CU, 0x3U, 0x400E84B8U, 0x0U, 0x400E83B0U +#define IOMUXC_GPIO_AD_24_FLEXPWM2_PWM0_A 0x400E816CU, 0x4U, 0x400E8518U, 0x1U, 0x400E83B0U +#define IOMUXC_GPIO_AD_24_GPIO_MUX3_IO23 0x400E816CU, 0x5U, 0, 0, 0x400E83B0U +#define IOMUXC_GPIO_AD_24_KPP_ROW05 0x400E816CU, 0x6U, 0, 0, 0x400E83B0U +#define IOMUXC_GPIO_AD_24_FLEXIO2_D24 0x400E816CU, 0x8U, 0, 0, 0x400E83B0U +#define IOMUXC_GPIO_AD_24_LPI2C4_SCL 0x400E816CU, 0x9U, 0x400E85C4U, 0x0U, 0x400E83B0U +#define IOMUXC_GPIO_AD_24_GPIO9_IO23 0x400E816CU, 0xAU, 0, 0, 0x400E83B0U + +#define IOMUXC_GPIO_AD_25_GPIO9_IO24 0x400E8170U, 0xAU, 0, 0, 0x400E83B4U +#define IOMUXC_GPIO_AD_25_LPUART1_RXD 0x400E8170U, 0x0U, 0x400E861CU, 0x0U, 0x400E83B4U +#define IOMUXC_GPIO_AD_25_LPSPI2_PCS0 0x400E8170U, 0x1U, 0x400E85DCU, 0x0U, 0x400E83B4U +#define IOMUXC_GPIO_AD_25_VIDEO_MUX_CSI_DATA01 0x400E8170U, 0x2U, 0, 0, 0x400E83B4U +#define IOMUXC_GPIO_AD_25_ENET_RX_ER 0x400E8170U, 0x3U, 0x400E84BCU, 0x0U, 0x400E83B4U +#define IOMUXC_GPIO_AD_25_FLEXPWM2_PWM0_B 0x400E8170U, 0x4U, 0x400E8524U, 0x1U, 0x400E83B4U +#define IOMUXC_GPIO_AD_25_GPIO_MUX3_IO24 0x400E8170U, 0x5U, 0, 0, 0x400E83B4U +#define IOMUXC_GPIO_AD_25_KPP_COL05 0x400E8170U, 0x6U, 0, 0, 0x400E83B4U +#define IOMUXC_GPIO_AD_25_FLEXIO2_D25 0x400E8170U, 0x8U, 0, 0, 0x400E83B4U +#define IOMUXC_GPIO_AD_25_LPI2C4_SDA 0x400E8170U, 0x9U, 0x400E85C8U, 0x0U, 0x400E83B4U + +#define IOMUXC_GPIO_AD_26_LPUART1_CTS_B 0x400E8174U, 0x0U, 0, 0, 0x400E83B8U +#define IOMUXC_GPIO_AD_26_LPSPI2_SOUT 0x400E8174U, 0x1U, 0x400E85ECU, 0x0U, 0x400E83B8U +#define IOMUXC_GPIO_AD_26_SEMC_CSX01 0x400E8174U, 0x2U, 0, 0, 0x400E83B8U +#define IOMUXC_GPIO_AD_26_ENET_RX_DATA00 0x400E8174U, 0x3U, 0x400E84B0U, 0x0U, 0x400E83B8U +#define IOMUXC_GPIO_AD_26_FLEXPWM2_PWM1_A 0x400E8174U, 0x4U, 0x400E851CU, 0x1U, 0x400E83B8U +#define IOMUXC_GPIO_AD_26_GPIO_MUX3_IO25 0x400E8174U, 0x5U, 0, 0, 0x400E83B8U +#define IOMUXC_GPIO_AD_26_KPP_ROW04 0x400E8174U, 0x6U, 0, 0, 0x400E83B8U +#define IOMUXC_GPIO_AD_26_FLEXIO2_D26 0x400E8174U, 0x8U, 0, 0, 0x400E83B8U +#define IOMUXC_GPIO_AD_26_ENET_QOS_MDC 0x400E8174U, 0x9U, 0, 0, 0x400E83B8U +#define IOMUXC_GPIO_AD_26_GPIO9_IO25 0x400E8174U, 0xAU, 0, 0, 0x400E83B8U +#define IOMUXC_GPIO_AD_26_USDHC2_CD_B 0x400E8174U, 0xBU, 0x400E86D0U, 0x1U, 0x400E83B8U + +#define IOMUXC_GPIO_AD_27_LPUART1_RTS_B 0x400E8178U, 0x0U, 0, 0, 0x400E83BCU +#define IOMUXC_GPIO_AD_27_LPSPI2_SIN 0x400E8178U, 0x1U, 0x400E85E8U, 0x0U, 0x400E83BCU +#define IOMUXC_GPIO_AD_27_SEMC_CSX02 0x400E8178U, 0x2U, 0, 0, 0x400E83BCU +#define IOMUXC_GPIO_AD_27_ENET_RX_DATA01 0x400E8178U, 0x3U, 0x400E84B4U, 0x0U, 0x400E83BCU +#define IOMUXC_GPIO_AD_27_FLEXPWM2_PWM1_B 0x400E8178U, 0x4U, 0x400E8528U, 0x1U, 0x400E83BCU +#define IOMUXC_GPIO_AD_27_GPIO_MUX3_IO26 0x400E8178U, 0x5U, 0, 0, 0x400E83BCU +#define IOMUXC_GPIO_AD_27_KPP_COL04 0x400E8178U, 0x6U, 0, 0, 0x400E83BCU +#define IOMUXC_GPIO_AD_27_FLEXIO2_D27 0x400E8178U, 0x8U, 0, 0, 0x400E83BCU +#define IOMUXC_GPIO_AD_27_ENET_QOS_MDIO 0x400E8178U, 0x9U, 0x400E84ECU, 0x1U, 0x400E83BCU +#define IOMUXC_GPIO_AD_27_GPIO9_IO26 0x400E8178U, 0xAU, 0, 0, 0x400E83BCU +#define IOMUXC_GPIO_AD_27_USDHC2_WP 0x400E8178U, 0xBU, 0x400E86D4U, 0x1U, 0x400E83BCU + +#define IOMUXC_GPIO_AD_28_GPIO9_IO27 0x400E817CU, 0xAU, 0, 0, 0x400E83C0U +#define IOMUXC_GPIO_AD_28_USDHC2_VSELECT 0x400E817CU, 0xBU, 0, 0, 0x400E83C0U +#define IOMUXC_GPIO_AD_28_LPSPI1_SCK 0x400E817CU, 0x0U, 0x400E85D0U, 0x1U, 0x400E83C0U +#define IOMUXC_GPIO_AD_28_LPUART5_TXD 0x400E817CU, 0x1U, 0, 0, 0x400E83C0U +#define IOMUXC_GPIO_AD_28_SEMC_CSX03 0x400E817CU, 0x2U, 0, 0, 0x400E83C0U +#define IOMUXC_GPIO_AD_28_ENET_TX_EN 0x400E817CU, 0x3U, 0, 0, 0x400E83C0U +#define IOMUXC_GPIO_AD_28_FLEXPWM2_PWM2_A 0x400E817CU, 0x4U, 0x400E8520U, 0x1U, 0x400E83C0U +#define IOMUXC_GPIO_AD_28_GPIO_MUX3_IO27 0x400E817CU, 0x5U, 0, 0, 0x400E83C0U +#define IOMUXC_GPIO_AD_28_KPP_ROW03 0x400E817CU, 0x6U, 0, 0, 0x400E83C0U +#define IOMUXC_GPIO_AD_28_FLEXIO2_D28 0x400E817CU, 0x8U, 0, 0, 0x400E83C0U +#define IOMUXC_GPIO_AD_28_VIDEO_MUX_EXT_DCIC1 0x400E817CU, 0x9U, 0, 0, 0x400E83C0U + +#define IOMUXC_GPIO_AD_29_LPSPI1_PCS0 0x400E8180U, 0x0U, 0x400E85CCU, 0x1U, 0x400E83C4U +#define IOMUXC_GPIO_AD_29_LPUART5_RXD 0x400E8180U, 0x1U, 0, 0, 0x400E83C4U +#define IOMUXC_GPIO_AD_29_ENET_REF_CLK 0x400E8180U, 0x2U, 0x400E84A8U, 0x0U, 0x400E83C4U +#define IOMUXC_GPIO_AD_29_ENET_TX_CLK 0x400E8180U, 0x3U, 0x400E84C0U, 0x0U, 0x400E83C4U +#define IOMUXC_GPIO_AD_29_FLEXPWM2_PWM2_B 0x400E8180U, 0x4U, 0x400E852CU, 0x1U, 0x400E83C4U +#define IOMUXC_GPIO_AD_29_GPIO_MUX3_IO28 0x400E8180U, 0x5U, 0, 0, 0x400E83C4U +#define IOMUXC_GPIO_AD_29_KPP_COL03 0x400E8180U, 0x6U, 0, 0, 0x400E83C4U +#define IOMUXC_GPIO_AD_29_FLEXIO2_D29 0x400E8180U, 0x8U, 0, 0, 0x400E83C4U +#define IOMUXC_GPIO_AD_29_VIDEO_MUX_EXT_DCIC2 0x400E8180U, 0x9U, 0, 0, 0x400E83C4U +#define IOMUXC_GPIO_AD_29_GPIO9_IO28 0x400E8180U, 0xAU, 0, 0, 0x400E83C4U +#define IOMUXC_GPIO_AD_29_USDHC2_RESET_B 0x400E8180U, 0xBU, 0, 0, 0x400E83C4U + +#define IOMUXC_GPIO_AD_30_LPSPI1_SOUT 0x400E8184U, 0x0U, 0x400E85D8U, 0x1U, 0x400E83C8U +#define IOMUXC_GPIO_AD_30_USB_OTG2_OC 0x400E8184U, 0x1U, 0x400E86B8U, 0x1U, 0x400E83C8U +#define IOMUXC_GPIO_AD_30_FLEXCAN2_TX 0x400E8184U, 0x2U, 0, 0, 0x400E83C8U +#define IOMUXC_GPIO_AD_30_ENET_TX_DATA00 0x400E8184U, 0x3U, 0, 0, 0x400E83C8U +#define IOMUXC_GPIO_AD_30_LPUART3_TXD 0x400E8184U, 0x4U, 0, 0, 0x400E83C8U +#define IOMUXC_GPIO_AD_30_GPIO_MUX3_IO29 0x400E8184U, 0x5U, 0, 0, 0x400E83C8U +#define IOMUXC_GPIO_AD_30_KPP_ROW02 0x400E8184U, 0x6U, 0, 0, 0x400E83C8U +#define IOMUXC_GPIO_AD_30_FLEXIO2_D30 0x400E8184U, 0x8U, 0, 0, 0x400E83C8U +#define IOMUXC_GPIO_AD_30_WDOG2_RESET_B_DEB 0x400E8184U, 0x9U, 0, 0, 0x400E83C8U +#define IOMUXC_GPIO_AD_30_GPIO9_IO29 0x400E8184U, 0xAU, 0, 0, 0x400E83C8U + +#define IOMUXC_GPIO_AD_31_LPSPI1_SIN 0x400E8188U, 0x0U, 0x400E85D4U, 0x1U, 0x400E83CCU +#define IOMUXC_GPIO_AD_31_USB_OTG2_PWR 0x400E8188U, 0x1U, 0, 0, 0x400E83CCU +#define IOMUXC_GPIO_AD_31_FLEXCAN2_RX 0x400E8188U, 0x2U, 0x400E849CU, 0x1U, 0x400E83CCU +#define IOMUXC_GPIO_AD_31_ENET_TX_DATA01 0x400E8188U, 0x3U, 0, 0, 0x400E83CCU +#define IOMUXC_GPIO_AD_31_LPUART3_RXD 0x400E8188U, 0x4U, 0, 0, 0x400E83CCU +#define IOMUXC_GPIO_AD_31_GPIO_MUX3_IO30 0x400E8188U, 0x5U, 0, 0, 0x400E83CCU +#define IOMUXC_GPIO_AD_31_KPP_COL02 0x400E8188U, 0x6U, 0, 0, 0x400E83CCU +#define IOMUXC_GPIO_AD_31_FLEXIO2_D31 0x400E8188U, 0x8U, 0, 0, 0x400E83CCU +#define IOMUXC_GPIO_AD_31_WDOG1_RESET_B_DEB 0x400E8188U, 0x9U, 0, 0, 0x400E83CCU +#define IOMUXC_GPIO_AD_31_GPIO9_IO30 0x400E8188U, 0xAU, 0, 0, 0x400E83CCU + +#define IOMUXC_GPIO_AD_32_GPIO9_IO31 0x400E818CU, 0xAU, 0, 0, 0x400E83D0U +#define IOMUXC_GPIO_AD_32_LPI2C1_SCL 0x400E818CU, 0x0U, 0x400E85ACU, 0x1U, 0x400E83D0U +#define IOMUXC_GPIO_AD_32_USBPHY2_OTG_ID 0x400E818CU, 0x1U, 0x400E86C4U, 0x1U, 0x400E83D0U +#define IOMUXC_GPIO_AD_32_PGMC_PMIC_RDY 0x400E818CU, 0x2U, 0, 0, 0x400E83D0U +#define IOMUXC_GPIO_AD_32_ENET_MDC 0x400E818CU, 0x3U, 0, 0, 0x400E83D0U +#define IOMUXC_GPIO_AD_32_USDHC1_CD_B 0x400E818CU, 0x4U, 0x400E86C8U, 0x0U, 0x400E83D0U +#define IOMUXC_GPIO_AD_32_GPIO_MUX3_IO31 0x400E818CU, 0x5U, 0, 0, 0x400E83D0U +#define IOMUXC_GPIO_AD_32_KPP_ROW01 0x400E818CU, 0x6U, 0, 0, 0x400E83D0U +#define IOMUXC_GPIO_AD_32_LPUART10_TXD 0x400E818CU, 0x8U, 0x400E8628U, 0x1U, 0x400E83D0U +#define IOMUXC_GPIO_AD_32_ENET_1G_MDC 0x400E818CU, 0x9U, 0, 0, 0x400E83D0U + +#define IOMUXC_GPIO_AD_33_LPI2C1_SDA 0x400E8190U, 0x0U, 0x400E85B0U, 0x1U, 0x400E83D4U +#define IOMUXC_GPIO_AD_33_USBPHY1_OTG_ID 0x400E8190U, 0x1U, 0x400E86C0U, 0x1U, 0x400E83D4U +#define IOMUXC_GPIO_AD_33_XBAR1_INOUT17 0x400E8190U, 0x2U, 0, 0, 0x400E83D4U +#define IOMUXC_GPIO_AD_33_ENET_MDIO 0x400E8190U, 0x3U, 0x400E84ACU, 0x1U, 0x400E83D4U +#define IOMUXC_GPIO_AD_33_USDHC1_WP 0x400E8190U, 0x4U, 0x400E86CCU, 0x0U, 0x400E83D4U +#define IOMUXC_GPIO_AD_33_GPIO_MUX4_IO00 0x400E8190U, 0x5U, 0, 0, 0x400E83D4U +#define IOMUXC_GPIO_AD_33_KPP_COL01 0x400E8190U, 0x6U, 0, 0, 0x400E83D4U +#define IOMUXC_GPIO_AD_33_LPUART10_RXD 0x400E8190U, 0x8U, 0x400E8624U, 0x1U, 0x400E83D4U +#define IOMUXC_GPIO_AD_33_ENET_1G_MDIO 0x400E8190U, 0x9U, 0x400E84C8U, 0x3U, 0x400E83D4U +#define IOMUXC_GPIO_AD_33_GPIO10_IO00 0x400E8190U, 0xAU, 0, 0, 0x400E83D4U + +#define IOMUXC_GPIO_AD_34_ENET_1G_1588_EVENT0_IN 0x400E8194U, 0x0U, 0, 0, 0x400E83D8U +#define IOMUXC_GPIO_AD_34_USB_OTG1_PWR 0x400E8194U, 0x1U, 0, 0, 0x400E83D8U +#define IOMUXC_GPIO_AD_34_XBAR1_INOUT18 0x400E8194U, 0x2U, 0, 0, 0x400E83D8U +#define IOMUXC_GPIO_AD_34_ENET_1588_EVENT0_IN 0x400E8194U, 0x3U, 0, 0, 0x400E83D8U +#define IOMUXC_GPIO_AD_34_USDHC1_VSELECT 0x400E8194U, 0x4U, 0, 0, 0x400E83D8U +#define IOMUXC_GPIO_AD_34_GPIO_MUX4_IO01 0x400E8194U, 0x5U, 0, 0, 0x400E83D8U +#define IOMUXC_GPIO_AD_34_KPP_ROW00 0x400E8194U, 0x6U, 0, 0, 0x400E83D8U +#define IOMUXC_GPIO_AD_34_LPUART10_CTS_B 0x400E8194U, 0x8U, 0, 0, 0x400E83D8U +#define IOMUXC_GPIO_AD_34_WDOG1_ANY 0x400E8194U, 0x9U, 0, 0, 0x400E83D8U +#define IOMUXC_GPIO_AD_34_GPIO10_IO01 0x400E8194U, 0xAU, 0, 0, 0x400E83D8U + +#define IOMUXC_GPIO_AD_35_GPIO10_IO02 0x400E8198U, 0xAU, 0, 0, 0x400E83DCU +#define IOMUXC_GPIO_AD_35_ENET_1G_1588_EVENT0_OUT 0x400E8198U, 0x0U, 0, 0, 0x400E83DCU +#define IOMUXC_GPIO_AD_35_USB_OTG1_OC 0x400E8198U, 0x1U, 0x400E86BCU, 0x1U, 0x400E83DCU +#define IOMUXC_GPIO_AD_35_XBAR1_INOUT19 0x400E8198U, 0x2U, 0, 0, 0x400E83DCU +#define IOMUXC_GPIO_AD_35_ENET_1588_EVENT0_OUT 0x400E8198U, 0x3U, 0, 0, 0x400E83DCU +#define IOMUXC_GPIO_AD_35_USDHC1_RESET_B 0x400E8198U, 0x4U, 0, 0, 0x400E83DCU +#define IOMUXC_GPIO_AD_35_GPIO_MUX4_IO02 0x400E8198U, 0x5U, 0, 0, 0x400E83DCU +#define IOMUXC_GPIO_AD_35_KPP_COL00 0x400E8198U, 0x6U, 0, 0, 0x400E83DCU +#define IOMUXC_GPIO_AD_35_LPUART10_RTS_B 0x400E8198U, 0x8U, 0, 0, 0x400E83DCU +#define IOMUXC_GPIO_AD_35_FLEXSPI1_B_SS1_B 0x400E8198U, 0x9U, 0, 0, 0x400E83DCU + +#define IOMUXC_GPIO_SD_B1_00_USDHC1_CMD 0x400E819CU, 0x0U, 0, 0, 0x400E83E0U +#define IOMUXC_GPIO_SD_B1_00_XBAR1_INOUT20 0x400E819CU, 0x2U, 0x400E86D8U, 0x1U, 0x400E83E0U +#define IOMUXC_GPIO_SD_B1_00_GPT4_CAPTURE1 0x400E819CU, 0x3U, 0, 0, 0x400E83E0U +#define IOMUXC_GPIO_SD_B1_00_GPIO_MUX4_IO03 0x400E819CU, 0x5U, 0, 0, 0x400E83E0U +#define IOMUXC_GPIO_SD_B1_00_FLEXSPI2_A_SS0_B 0x400E819CU, 0x6U, 0, 0, 0x400E83E0U +#define IOMUXC_GPIO_SD_B1_00_KPP_ROW07 0x400E819CU, 0x8U, 0x400E85A8U, 0x1U, 0x400E83E0U +#define IOMUXC_GPIO_SD_B1_00_GPIO10_IO03 0x400E819CU, 0xAU, 0, 0, 0x400E83E0U + +#define IOMUXC_GPIO_SD_B1_01_USDHC1_CLK 0x400E81A0U, 0x0U, 0, 0, 0x400E83E4U +#define IOMUXC_GPIO_SD_B1_01_XBAR1_INOUT21 0x400E81A0U, 0x2U, 0x400E86DCU, 0x1U, 0x400E83E4U +#define IOMUXC_GPIO_SD_B1_01_GPT4_CAPTURE2 0x400E81A0U, 0x3U, 0, 0, 0x400E83E4U +#define IOMUXC_GPIO_SD_B1_01_GPIO_MUX4_IO04 0x400E81A0U, 0x5U, 0, 0, 0x400E83E4U +#define IOMUXC_GPIO_SD_B1_01_FLEXSPI2_A_SCLK 0x400E81A0U, 0x6U, 0x400E858CU, 0x1U, 0x400E83E4U +#define IOMUXC_GPIO_SD_B1_01_KPP_COL07 0x400E81A0U, 0x8U, 0x400E85A0U, 0x1U, 0x400E83E4U +#define IOMUXC_GPIO_SD_B1_01_GPIO10_IO04 0x400E81A0U, 0xAU, 0, 0, 0x400E83E4U + +#define IOMUXC_GPIO_SD_B1_02_GPIO10_IO05 0x400E81A4U, 0xAU, 0, 0, 0x400E83E8U +#define IOMUXC_GPIO_SD_B1_02_USDHC1_DATA0 0x400E81A4U, 0x0U, 0, 0, 0x400E83E8U +#define IOMUXC_GPIO_SD_B1_02_XBAR1_INOUT22 0x400E81A4U, 0x2U, 0x400E86E0U, 0x1U, 0x400E83E8U +#define IOMUXC_GPIO_SD_B1_02_GPT4_COMPARE1 0x400E81A4U, 0x3U, 0, 0, 0x400E83E8U +#define IOMUXC_GPIO_SD_B1_02_GPIO_MUX4_IO05 0x400E81A4U, 0x5U, 0, 0, 0x400E83E8U +#define IOMUXC_GPIO_SD_B1_02_FLEXSPI2_A_DATA00 0x400E81A4U, 0x6U, 0x400E857CU, 0x1U, 0x400E83E8U +#define IOMUXC_GPIO_SD_B1_02_KPP_ROW06 0x400E81A4U, 0x8U, 0x400E85A4U, 0x1U, 0x400E83E8U +#define IOMUXC_GPIO_SD_B1_02_FLEXSPI1_A_SS1_B 0x400E81A4U, 0x9U, 0, 0, 0x400E83E8U + +#define IOMUXC_GPIO_SD_B1_03_USDHC1_DATA1 0x400E81A8U, 0x0U, 0, 0, 0x400E83ECU +#define IOMUXC_GPIO_SD_B1_03_XBAR1_INOUT23 0x400E81A8U, 0x2U, 0x400E86E4U, 0x1U, 0x400E83ECU +#define IOMUXC_GPIO_SD_B1_03_GPT4_COMPARE2 0x400E81A8U, 0x3U, 0, 0, 0x400E83ECU +#define IOMUXC_GPIO_SD_B1_03_GPIO_MUX4_IO06 0x400E81A8U, 0x5U, 0, 0, 0x400E83ECU +#define IOMUXC_GPIO_SD_B1_03_FLEXSPI2_A_DATA01 0x400E81A8U, 0x6U, 0x400E8580U, 0x1U, 0x400E83ECU +#define IOMUXC_GPIO_SD_B1_03_KPP_COL06 0x400E81A8U, 0x8U, 0x400E859CU, 0x1U, 0x400E83ECU +#define IOMUXC_GPIO_SD_B1_03_FLEXSPI1_B_SS1_B 0x400E81A8U, 0x9U, 0, 0, 0x400E83ECU +#define IOMUXC_GPIO_SD_B1_03_GPIO10_IO06 0x400E81A8U, 0xAU, 0, 0, 0x400E83ECU + +#define IOMUXC_GPIO_SD_B1_04_USDHC1_DATA2 0x400E81ACU, 0x0U, 0, 0, 0x400E83F0U +#define IOMUXC_GPIO_SD_B1_04_XBAR1_INOUT24 0x400E81ACU, 0x2U, 0x400E86E8U, 0x1U, 0x400E83F0U +#define IOMUXC_GPIO_SD_B1_04_GPT4_COMPARE3 0x400E81ACU, 0x3U, 0, 0, 0x400E83F0U +#define IOMUXC_GPIO_SD_B1_04_GPIO_MUX4_IO07 0x400E81ACU, 0x5U, 0, 0, 0x400E83F0U +#define IOMUXC_GPIO_SD_B1_04_FLEXSPI2_A_DATA02 0x400E81ACU, 0x6U, 0x400E8584U, 0x1U, 0x400E83F0U +#define IOMUXC_GPIO_SD_B1_04_FLEXSPI1_B_SS0_B 0x400E81ACU, 0x8U, 0, 0, 0x400E83F0U +#define IOMUXC_GPIO_SD_B1_04_ENET_QOS_1588_EVENT2_AUX_IN 0x400E81ACU, 0x9U, 0, 0, 0x400E83F0U +#define IOMUXC_GPIO_SD_B1_04_GPIO10_IO07 0x400E81ACU, 0xAU, 0, 0, 0x400E83F0U + +#define IOMUXC_GPIO_SD_B1_05_GPIO10_IO08 0x400E81B0U, 0xAU, 0, 0, 0x400E83F4U +#define IOMUXC_GPIO_SD_B1_05_USDHC1_DATA3 0x400E81B0U, 0x0U, 0, 0, 0x400E83F4U +#define IOMUXC_GPIO_SD_B1_05_XBAR1_INOUT25 0x400E81B0U, 0x2U, 0x400E86ECU, 0x1U, 0x400E83F4U +#define IOMUXC_GPIO_SD_B1_05_GPT4_CLK 0x400E81B0U, 0x3U, 0, 0, 0x400E83F4U +#define IOMUXC_GPIO_SD_B1_05_GPIO_MUX4_IO08 0x400E81B0U, 0x5U, 0, 0, 0x400E83F4U +#define IOMUXC_GPIO_SD_B1_05_FLEXSPI2_A_DATA03 0x400E81B0U, 0x6U, 0x400E8588U, 0x1U, 0x400E83F4U +#define IOMUXC_GPIO_SD_B1_05_FLEXSPI1_B_DQS 0x400E81B0U, 0x8U, 0, 0, 0x400E83F4U +#define IOMUXC_GPIO_SD_B1_05_ENET_QOS_1588_EVENT3_AUX_IN 0x400E81B0U, 0x9U, 0, 0, 0x400E83F4U + +#define IOMUXC_GPIO_SD_B2_00_GPIO10_IO09 0x400E81B4U, 0xAU, 0, 0, 0x400E83F8U +#define IOMUXC_GPIO_SD_B2_00_USDHC2_DATA3 0x400E81B4U, 0x0U, 0, 0, 0x400E83F8U +#define IOMUXC_GPIO_SD_B2_00_FLEXSPI1_B_DATA03 0x400E81B4U, 0x1U, 0x400E8570U, 0x1U, 0x400E83F8U +#define IOMUXC_GPIO_SD_B2_00_ENET_1G_RX_EN 0x400E81B4U, 0x2U, 0x400E84E0U, 0x1U, 0x400E83F8U +#define IOMUXC_GPIO_SD_B2_00_LPUART9_TXD 0x400E81B4U, 0x3U, 0, 0, 0x400E83F8U +#define IOMUXC_GPIO_SD_B2_00_LPSPI4_SCK 0x400E81B4U, 0x4U, 0x400E8610U, 0x0U, 0x400E83F8U +#define IOMUXC_GPIO_SD_B2_00_GPIO_MUX4_IO09 0x400E81B4U, 0x5U, 0, 0, 0x400E83F8U + +#define IOMUXC_GPIO_SD_B2_01_USDHC2_DATA2 0x400E81B8U, 0x0U, 0, 0, 0x400E83FCU +#define IOMUXC_GPIO_SD_B2_01_FLEXSPI1_B_DATA02 0x400E81B8U, 0x1U, 0x400E856CU, 0x1U, 0x400E83FCU +#define IOMUXC_GPIO_SD_B2_01_ENET_1G_RX_CLK 0x400E81B8U, 0x2U, 0x400E84CCU, 0x1U, 0x400E83FCU +#define IOMUXC_GPIO_SD_B2_01_LPUART9_RXD 0x400E81B8U, 0x3U, 0, 0, 0x400E83FCU +#define IOMUXC_GPIO_SD_B2_01_LPSPI4_PCS0 0x400E81B8U, 0x4U, 0x400E860CU, 0x0U, 0x400E83FCU +#define IOMUXC_GPIO_SD_B2_01_GPIO_MUX4_IO10 0x400E81B8U, 0x5U, 0, 0, 0x400E83FCU +#define IOMUXC_GPIO_SD_B2_01_GPIO10_IO10 0x400E81B8U, 0xAU, 0, 0, 0x400E83FCU + +#define IOMUXC_GPIO_SD_B2_02_GPIO10_IO11 0x400E81BCU, 0xAU, 0, 0, 0x400E8400U +#define IOMUXC_GPIO_SD_B2_02_USDHC2_DATA1 0x400E81BCU, 0x0U, 0, 0, 0x400E8400U +#define IOMUXC_GPIO_SD_B2_02_FLEXSPI1_B_DATA01 0x400E81BCU, 0x1U, 0x400E8568U, 0x1U, 0x400E8400U +#define IOMUXC_GPIO_SD_B2_02_ENET_1G_RX_DATA00 0x400E81BCU, 0x2U, 0x400E84D0U, 0x1U, 0x400E8400U +#define IOMUXC_GPIO_SD_B2_02_LPUART9_CTS_B 0x400E81BCU, 0x3U, 0, 0, 0x400E8400U +#define IOMUXC_GPIO_SD_B2_02_LPSPI4_SOUT 0x400E81BCU, 0x4U, 0x400E8618U, 0x0U, 0x400E8400U +#define IOMUXC_GPIO_SD_B2_02_GPIO_MUX4_IO11 0x400E81BCU, 0x5U, 0, 0, 0x400E8400U + +#define IOMUXC_GPIO_SD_B2_03_GPIO10_IO12 0x400E81C0U, 0xAU, 0, 0, 0x400E8404U +#define IOMUXC_GPIO_SD_B2_03_USDHC2_DATA0 0x400E81C0U, 0x0U, 0, 0, 0x400E8404U +#define IOMUXC_GPIO_SD_B2_03_FLEXSPI1_B_DATA00 0x400E81C0U, 0x1U, 0x400E8564U, 0x1U, 0x400E8404U +#define IOMUXC_GPIO_SD_B2_03_ENET_1G_RX_DATA01 0x400E81C0U, 0x2U, 0x400E84D4U, 0x1U, 0x400E8404U +#define IOMUXC_GPIO_SD_B2_03_LPUART9_RTS_B 0x400E81C0U, 0x3U, 0, 0, 0x400E8404U +#define IOMUXC_GPIO_SD_B2_03_LPSPI4_SIN 0x400E81C0U, 0x4U, 0x400E8614U, 0x0U, 0x400E8404U +#define IOMUXC_GPIO_SD_B2_03_GPIO_MUX4_IO12 0x400E81C0U, 0x5U, 0, 0, 0x400E8404U + +#define IOMUXC_GPIO_SD_B2_04_USDHC2_CLK 0x400E81C4U, 0x0U, 0, 0, 0x400E8408U +#define IOMUXC_GPIO_SD_B2_04_FLEXSPI1_B_SCLK 0x400E81C4U, 0x1U, 0x400E8578U, 0x1U, 0x400E8408U +#define IOMUXC_GPIO_SD_B2_04_ENET_1G_RX_DATA02 0x400E81C4U, 0x2U, 0x400E84D8U, 0x1U, 0x400E8408U +#define IOMUXC_GPIO_SD_B2_04_FLEXSPI1_A_SS1_B 0x400E81C4U, 0x3U, 0, 0, 0x400E8408U +#define IOMUXC_GPIO_SD_B2_04_LPSPI4_PCS1 0x400E81C4U, 0x4U, 0, 0, 0x400E8408U +#define IOMUXC_GPIO_SD_B2_04_GPIO_MUX4_IO13 0x400E81C4U, 0x5U, 0, 0, 0x400E8408U +#define IOMUXC_GPIO_SD_B2_04_GPIO10_IO13 0x400E81C4U, 0xAU, 0, 0, 0x400E8408U + +#define IOMUXC_GPIO_SD_B2_05_GPIO10_IO14 0x400E81C8U, 0xAU, 0, 0, 0x400E840CU +#define IOMUXC_GPIO_SD_B2_05_USDHC2_CMD 0x400E81C8U, 0x0U, 0, 0, 0x400E840CU +#define IOMUXC_GPIO_SD_B2_05_FLEXSPI1_A_DQS 0x400E81C8U, 0x1U, 0x400E8550U, 0x2U, 0x400E840CU +#define IOMUXC_GPIO_SD_B2_05_ENET_1G_RX_DATA03 0x400E81C8U, 0x2U, 0x400E84DCU, 0x1U, 0x400E840CU +#define IOMUXC_GPIO_SD_B2_05_FLEXSPI1_B_SS0_B 0x400E81C8U, 0x3U, 0, 0, 0x400E840CU +#define IOMUXC_GPIO_SD_B2_05_LPSPI4_PCS2 0x400E81C8U, 0x4U, 0, 0, 0x400E840CU +#define IOMUXC_GPIO_SD_B2_05_GPIO_MUX4_IO14 0x400E81C8U, 0x5U, 0, 0, 0x400E840CU + +#define IOMUXC_GPIO_SD_B2_06_GPIO10_IO15 0x400E81CCU, 0xAU, 0, 0, 0x400E8410U +#define IOMUXC_GPIO_SD_B2_06_USDHC2_RESET_B 0x400E81CCU, 0x0U, 0, 0, 0x400E8410U +#define IOMUXC_GPIO_SD_B2_06_FLEXSPI1_A_SS0_B 0x400E81CCU, 0x1U, 0, 0, 0x400E8410U +#define IOMUXC_GPIO_SD_B2_06_ENET_1G_TX_DATA03 0x400E81CCU, 0x2U, 0, 0, 0x400E8410U +#define IOMUXC_GPIO_SD_B2_06_LPSPI4_PCS3 0x400E81CCU, 0x3U, 0, 0, 0x400E8410U +#define IOMUXC_GPIO_SD_B2_06_GPT6_CAPTURE1 0x400E81CCU, 0x4U, 0, 0, 0x400E8410U +#define IOMUXC_GPIO_SD_B2_06_GPIO_MUX4_IO15 0x400E81CCU, 0x5U, 0, 0, 0x400E8410U + +#define IOMUXC_GPIO_SD_B2_07_USDHC2_STROBE 0x400E81D0U, 0x0U, 0, 0, 0x400E8414U +#define IOMUXC_GPIO_SD_B2_07_FLEXSPI1_A_SCLK 0x400E81D0U, 0x1U, 0x400E8574U, 0x1U, 0x400E8414U +#define IOMUXC_GPIO_SD_B2_07_ENET_1G_TX_DATA02 0x400E81D0U, 0x2U, 0, 0, 0x400E8414U +#define IOMUXC_GPIO_SD_B2_07_LPUART3_CTS_B 0x400E81D0U, 0x3U, 0, 0, 0x400E8414U +#define IOMUXC_GPIO_SD_B2_07_GPT6_CAPTURE2 0x400E81D0U, 0x4U, 0, 0, 0x400E8414U +#define IOMUXC_GPIO_SD_B2_07_GPIO_MUX4_IO16 0x400E81D0U, 0x5U, 0, 0, 0x400E8414U +#define IOMUXC_GPIO_SD_B2_07_LPSPI2_SCK 0x400E81D0U, 0x6U, 0x400E85E4U, 0x1U, 0x400E8414U +#define IOMUXC_GPIO_SD_B2_07_ENET_TX_ER 0x400E81D0U, 0x8U, 0, 0, 0x400E8414U +#define IOMUXC_GPIO_SD_B2_07_ENET_QOS_REF_CLK 0x400E81D0U, 0x9U, 0x400E84A0U, 0x1U, 0x400E8414U +#define IOMUXC_GPIO_SD_B2_07_GPIO10_IO16 0x400E81D0U, 0xAU, 0, 0, 0x400E8414U + +#define IOMUXC_GPIO_SD_B2_08_GPIO10_IO17 0x400E81D4U, 0xAU, 0, 0, 0x400E8418U +#define IOMUXC_GPIO_SD_B2_08_USDHC2_DATA4 0x400E81D4U, 0x0U, 0, 0, 0x400E8418U +#define IOMUXC_GPIO_SD_B2_08_FLEXSPI1_A_DATA00 0x400E81D4U, 0x1U, 0x400E8554U, 0x1U, 0x400E8418U +#define IOMUXC_GPIO_SD_B2_08_ENET_1G_TX_DATA01 0x400E81D4U, 0x2U, 0, 0, 0x400E8418U +#define IOMUXC_GPIO_SD_B2_08_LPUART3_RTS_B 0x400E81D4U, 0x3U, 0, 0, 0x400E8418U +#define IOMUXC_GPIO_SD_B2_08_GPT6_COMPARE1 0x400E81D4U, 0x4U, 0, 0, 0x400E8418U +#define IOMUXC_GPIO_SD_B2_08_GPIO_MUX4_IO17 0x400E81D4U, 0x5U, 0, 0, 0x400E8418U +#define IOMUXC_GPIO_SD_B2_08_LPSPI2_PCS0 0x400E81D4U, 0x6U, 0x400E85DCU, 0x1U, 0x400E8418U + +#define IOMUXC_GPIO_SD_B2_09_GPIO10_IO18 0x400E81D8U, 0xAU, 0, 0, 0x400E841CU +#define IOMUXC_GPIO_SD_B2_09_USDHC2_DATA5 0x400E81D8U, 0x0U, 0, 0, 0x400E841CU +#define IOMUXC_GPIO_SD_B2_09_FLEXSPI1_A_DATA01 0x400E81D8U, 0x1U, 0x400E8558U, 0x1U, 0x400E841CU +#define IOMUXC_GPIO_SD_B2_09_ENET_1G_TX_DATA00 0x400E81D8U, 0x2U, 0, 0, 0x400E841CU +#define IOMUXC_GPIO_SD_B2_09_LPUART5_CTS_B 0x400E81D8U, 0x3U, 0, 0, 0x400E841CU +#define IOMUXC_GPIO_SD_B2_09_GPT6_COMPARE2 0x400E81D8U, 0x4U, 0, 0, 0x400E841CU +#define IOMUXC_GPIO_SD_B2_09_GPIO_MUX4_IO18 0x400E81D8U, 0x5U, 0, 0, 0x400E841CU +#define IOMUXC_GPIO_SD_B2_09_LPSPI2_SOUT 0x400E81D8U, 0x6U, 0x400E85ECU, 0x1U, 0x400E841CU + +#define IOMUXC_GPIO_SD_B2_10_GPIO10_IO19 0x400E81DCU, 0xAU, 0, 0, 0x400E8420U +#define IOMUXC_GPIO_SD_B2_10_USDHC2_DATA6 0x400E81DCU, 0x0U, 0, 0, 0x400E8420U +#define IOMUXC_GPIO_SD_B2_10_FLEXSPI1_A_DATA02 0x400E81DCU, 0x1U, 0x400E855CU, 0x1U, 0x400E8420U +#define IOMUXC_GPIO_SD_B2_10_ENET_1G_TX_EN 0x400E81DCU, 0x2U, 0, 0, 0x400E8420U +#define IOMUXC_GPIO_SD_B2_10_LPUART5_RTS_B 0x400E81DCU, 0x3U, 0, 0, 0x400E8420U +#define IOMUXC_GPIO_SD_B2_10_GPT6_COMPARE3 0x400E81DCU, 0x4U, 0, 0, 0x400E8420U +#define IOMUXC_GPIO_SD_B2_10_GPIO_MUX4_IO19 0x400E81DCU, 0x5U, 0, 0, 0x400E8420U +#define IOMUXC_GPIO_SD_B2_10_LPSPI2_SIN 0x400E81DCU, 0x6U, 0x400E85E8U, 0x1U, 0x400E8420U + +#define IOMUXC_GPIO_SD_B2_11_USDHC2_DATA7 0x400E81E0U, 0x0U, 0, 0, 0x400E8424U +#define IOMUXC_GPIO_SD_B2_11_FLEXSPI1_A_DATA03 0x400E81E0U, 0x1U, 0x400E8560U, 0x1U, 0x400E8424U +#define IOMUXC_GPIO_SD_B2_11_ENET_1G_TX_CLK_IO 0x400E81E0U, 0x2U, 0x400E84E8U, 0x1U, 0x400E8424U +#define IOMUXC_GPIO_SD_B2_11_ENET_1G_REF_CLK 0x400E81E0U, 0x3U, 0x400E84C4U, 0x1U, 0x400E8424U +#define IOMUXC_GPIO_SD_B2_11_GPT6_CLK 0x400E81E0U, 0x4U, 0, 0, 0x400E8424U +#define IOMUXC_GPIO_SD_B2_11_GPIO_MUX4_IO20 0x400E81E0U, 0x5U, 0, 0, 0x400E8424U +#define IOMUXC_GPIO_SD_B2_11_LPSPI2_PCS1 0x400E81E0U, 0x6U, 0x400E85E0U, 0x1U, 0x400E8424U +#define IOMUXC_GPIO_SD_B2_11_GPIO10_IO20 0x400E81E0U, 0xAU, 0, 0, 0x400E8424U + +#define IOMUXC_GPIO_DISP_B1_00_VIDEO_MUX_LCDIF_CLK 0x400E81E4U, 0x0U, 0, 0, 0x400E8428U +#define IOMUXC_GPIO_DISP_B1_00_ENET_1G_RX_EN 0x400E81E4U, 0x1U, 0x400E84E0U, 0x2U, 0x400E8428U +#define IOMUXC_GPIO_DISP_B1_00_TMR1_TIMER0 0x400E81E4U, 0x3U, 0x400E863CU, 0x2U, 0x400E8428U +#define IOMUXC_GPIO_DISP_B1_00_XBAR1_INOUT26 0x400E81E4U, 0x4U, 0x400E86F0U, 0x1U, 0x400E8428U +#define IOMUXC_GPIO_DISP_B1_00_GPIO_MUX4_IO21 0x400E81E4U, 0x5U, 0, 0, 0x400E8428U +#define IOMUXC_GPIO_DISP_B1_00_ENET_QOS_RX_EN 0x400E81E4U, 0x8U, 0x400E84F8U, 0x0U, 0x400E8428U +#define IOMUXC_GPIO_DISP_B1_00_GPIO10_IO21 0x400E81E4U, 0xAU, 0, 0, 0x400E8428U + +#define IOMUXC_GPIO_DISP_B1_01_VIDEO_MUX_LCDIF_ENABLE 0x400E81E8U, 0x0U, 0, 0, 0x400E842CU +#define IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_CLK 0x400E81E8U, 0x1U, 0x400E84CCU, 0x2U, 0x400E842CU +#define IOMUXC_GPIO_DISP_B1_01_ENET_1G_RX_ER 0x400E81E8U, 0x2U, 0x400E84E4U, 0x1U, 0x400E842CU +#define IOMUXC_GPIO_DISP_B1_01_TMR1_TIMER1 0x400E81E8U, 0x3U, 0x400E8640U, 0x2U, 0x400E842CU +#define IOMUXC_GPIO_DISP_B1_01_XBAR1_INOUT27 0x400E81E8U, 0x4U, 0x400E86F4U, 0x1U, 0x400E842CU +#define IOMUXC_GPIO_DISP_B1_01_GPIO_MUX4_IO22 0x400E81E8U, 0x5U, 0, 0, 0x400E842CU +#define IOMUXC_GPIO_DISP_B1_01_ENET_QOS_RX_CLK 0x400E81E8U, 0x8U, 0, 0, 0x400E842CU +#define IOMUXC_GPIO_DISP_B1_01_ENET_QOS_RX_ER 0x400E81E8U, 0x9U, 0x400E84FCU, 0x0U, 0x400E842CU +#define IOMUXC_GPIO_DISP_B1_01_GPIO10_IO22 0x400E81E8U, 0xAU, 0, 0, 0x400E842CU + +#define IOMUXC_GPIO_DISP_B1_02_GPIO10_IO23 0x400E81ECU, 0xAU, 0, 0, 0x400E8430U +#define IOMUXC_GPIO_DISP_B1_02_VIDEO_MUX_LCDIF_HSYNC 0x400E81ECU, 0x0U, 0, 0, 0x400E8430U +#define IOMUXC_GPIO_DISP_B1_02_ENET_1G_RX_DATA00 0x400E81ECU, 0x1U, 0x400E84D0U, 0x2U, 0x400E8430U +#define IOMUXC_GPIO_DISP_B1_02_LPI2C3_SCL 0x400E81ECU, 0x2U, 0x400E85BCU, 0x0U, 0x400E8430U +#define IOMUXC_GPIO_DISP_B1_02_TMR1_TIMER2 0x400E81ECU, 0x3U, 0x400E8644U, 0x1U, 0x400E8430U +#define IOMUXC_GPIO_DISP_B1_02_XBAR1_INOUT28 0x400E81ECU, 0x4U, 0x400E86F8U, 0x1U, 0x400E8430U +#define IOMUXC_GPIO_DISP_B1_02_GPIO_MUX4_IO23 0x400E81ECU, 0x5U, 0, 0, 0x400E8430U +#define IOMUXC_GPIO_DISP_B1_02_ENET_QOS_RX_DATA00 0x400E81ECU, 0x8U, 0x400E84F0U, 0x0U, 0x400E8430U +#define IOMUXC_GPIO_DISP_B1_02_LPUART1_TXD 0x400E81ECU, 0x9U, 0x400E8620U, 0x1U, 0x400E8430U + +#define IOMUXC_GPIO_DISP_B1_03_VIDEO_MUX_LCDIF_VSYNC 0x400E81F0U, 0x0U, 0, 0, 0x400E8434U +#define IOMUXC_GPIO_DISP_B1_03_ENET_1G_RX_DATA01 0x400E81F0U, 0x1U, 0x400E84D4U, 0x2U, 0x400E8434U +#define IOMUXC_GPIO_DISP_B1_03_LPI2C3_SDA 0x400E81F0U, 0x2U, 0x400E85C0U, 0x0U, 0x400E8434U +#define IOMUXC_GPIO_DISP_B1_03_TMR2_TIMER0 0x400E81F0U, 0x3U, 0x400E8648U, 0x2U, 0x400E8434U +#define IOMUXC_GPIO_DISP_B1_03_XBAR1_INOUT29 0x400E81F0U, 0x4U, 0x400E86FCU, 0x1U, 0x400E8434U +#define IOMUXC_GPIO_DISP_B1_03_GPIO_MUX4_IO24 0x400E81F0U, 0x5U, 0, 0, 0x400E8434U +#define IOMUXC_GPIO_DISP_B1_03_ENET_QOS_RX_DATA01 0x400E81F0U, 0x8U, 0x400E84F4U, 0x0U, 0x400E8434U +#define IOMUXC_GPIO_DISP_B1_03_LPUART1_RXD 0x400E81F0U, 0x9U, 0x400E861CU, 0x1U, 0x400E8434U +#define IOMUXC_GPIO_DISP_B1_03_GPIO10_IO24 0x400E81F0U, 0xAU, 0, 0, 0x400E8434U + +#define IOMUXC_GPIO_DISP_B1_04_VIDEO_MUX_LCDIF_DATA00 0x400E81F4U, 0x0U, 0, 0, 0x400E8438U +#define IOMUXC_GPIO_DISP_B1_04_ENET_1G_RX_DATA02 0x400E81F4U, 0x1U, 0x400E84D8U, 0x2U, 0x400E8438U +#define IOMUXC_GPIO_DISP_B1_04_LPUART4_RXD 0x400E81F4U, 0x2U, 0, 0, 0x400E8438U +#define IOMUXC_GPIO_DISP_B1_04_TMR2_TIMER1 0x400E81F4U, 0x3U, 0x400E864CU, 0x2U, 0x400E8438U +#define IOMUXC_GPIO_DISP_B1_04_XBAR1_INOUT30 0x400E81F4U, 0x4U, 0x400E8700U, 0x1U, 0x400E8438U +#define IOMUXC_GPIO_DISP_B1_04_GPIO_MUX4_IO25 0x400E81F4U, 0x5U, 0, 0, 0x400E8438U +#define IOMUXC_GPIO_DISP_B1_04_ENET_QOS_RX_DATA02 0x400E81F4U, 0x8U, 0, 0, 0x400E8438U +#define IOMUXC_GPIO_DISP_B1_04_LPSPI3_SCK 0x400E81F4U, 0x9U, 0x400E8600U, 0x1U, 0x400E8438U +#define IOMUXC_GPIO_DISP_B1_04_GPIO10_IO25 0x400E81F4U, 0xAU, 0, 0, 0x400E8438U + +#define IOMUXC_GPIO_DISP_B1_05_GPIO10_IO26 0x400E81F8U, 0xAU, 0, 0, 0x400E843CU +#define IOMUXC_GPIO_DISP_B1_05_VIDEO_MUX_LCDIF_DATA01 0x400E81F8U, 0x0U, 0, 0, 0x400E843CU +#define IOMUXC_GPIO_DISP_B1_05_ENET_1G_RX_DATA03 0x400E81F8U, 0x1U, 0x400E84DCU, 0x2U, 0x400E843CU +#define IOMUXC_GPIO_DISP_B1_05_LPUART4_CTS_B 0x400E81F8U, 0x2U, 0, 0, 0x400E843CU +#define IOMUXC_GPIO_DISP_B1_05_TMR2_TIMER2 0x400E81F8U, 0x3U, 0x400E8650U, 0x1U, 0x400E843CU +#define IOMUXC_GPIO_DISP_B1_05_XBAR1_INOUT31 0x400E81F8U, 0x4U, 0x400E8704U, 0x1U, 0x400E843CU +#define IOMUXC_GPIO_DISP_B1_05_GPIO_MUX4_IO26 0x400E81F8U, 0x5U, 0, 0, 0x400E843CU +#define IOMUXC_GPIO_DISP_B1_05_ENET_QOS_RX_DATA03 0x400E81F8U, 0x8U, 0, 0, 0x400E843CU +#define IOMUXC_GPIO_DISP_B1_05_LPSPI3_SIN 0x400E81F8U, 0x9U, 0x400E8604U, 0x1U, 0x400E843CU + +#define IOMUXC_GPIO_DISP_B1_06_VIDEO_MUX_LCDIF_DATA02 0x400E81FCU, 0x0U, 0, 0, 0x400E8440U +#define IOMUXC_GPIO_DISP_B1_06_ENET_1G_TX_DATA03 0x400E81FCU, 0x1U, 0, 0, 0x400E8440U +#define IOMUXC_GPIO_DISP_B1_06_LPUART4_TXD 0x400E81FCU, 0x2U, 0, 0, 0x400E8440U +#define IOMUXC_GPIO_DISP_B1_06_TMR3_TIMER0 0x400E81FCU, 0x3U, 0x400E8654U, 0x2U, 0x400E8440U +#define IOMUXC_GPIO_DISP_B1_06_XBAR1_INOUT32 0x400E81FCU, 0x4U, 0x400E8708U, 0x1U, 0x400E8440U +#define IOMUXC_GPIO_DISP_B1_06_GPIO_MUX4_IO27 0x400E81FCU, 0x5U, 0, 0, 0x400E8440U +#define IOMUXC_GPIO_DISP_B1_06_SRC_BT_CFG00 0x400E81FCU, 0x6U, 0, 0, 0x400E8440U +#define IOMUXC_GPIO_DISP_B1_06_ENET_QOS_TX_DATA03 0x400E81FCU, 0x8U, 0, 0, 0x400E8440U +#define IOMUXC_GPIO_DISP_B1_06_LPSPI3_SOUT 0x400E81FCU, 0x9U, 0x400E8608U, 0x1U, 0x400E8440U +#define IOMUXC_GPIO_DISP_B1_06_GPIO10_IO27 0x400E81FCU, 0xAU, 0, 0, 0x400E8440U + +#define IOMUXC_GPIO_DISP_B1_07_VIDEO_MUX_LCDIF_DATA03 0x400E8200U, 0x0U, 0, 0, 0x400E8444U +#define IOMUXC_GPIO_DISP_B1_07_ENET_1G_TX_DATA02 0x400E8200U, 0x1U, 0, 0, 0x400E8444U +#define IOMUXC_GPIO_DISP_B1_07_LPUART4_RTS_B 0x400E8200U, 0x2U, 0, 0, 0x400E8444U +#define IOMUXC_GPIO_DISP_B1_07_TMR3_TIMER1 0x400E8200U, 0x3U, 0x400E8658U, 0x2U, 0x400E8444U +#define IOMUXC_GPIO_DISP_B1_07_XBAR1_INOUT33 0x400E8200U, 0x4U, 0x400E870CU, 0x1U, 0x400E8444U +#define IOMUXC_GPIO_DISP_B1_07_GPIO_MUX4_IO28 0x400E8200U, 0x5U, 0, 0, 0x400E8444U +#define IOMUXC_GPIO_DISP_B1_07_SRC_BT_CFG01 0x400E8200U, 0x6U, 0, 0, 0x400E8444U +#define IOMUXC_GPIO_DISP_B1_07_ENET_QOS_TX_DATA02 0x400E8200U, 0x8U, 0, 0, 0x400E8444U +#define IOMUXC_GPIO_DISP_B1_07_LPSPI3_PCS0 0x400E8200U, 0x9U, 0x400E85F0U, 0x1U, 0x400E8444U +#define IOMUXC_GPIO_DISP_B1_07_GPIO10_IO28 0x400E8200U, 0xAU, 0, 0, 0x400E8444U + +#define IOMUXC_GPIO_DISP_B1_08_GPIO10_IO29 0x400E8204U, 0xAU, 0, 0, 0x400E8448U +#define IOMUXC_GPIO_DISP_B1_08_VIDEO_MUX_LCDIF_DATA04 0x400E8204U, 0x0U, 0, 0, 0x400E8448U +#define IOMUXC_GPIO_DISP_B1_08_ENET_1G_TX_DATA01 0x400E8204U, 0x1U, 0, 0, 0x400E8448U +#define IOMUXC_GPIO_DISP_B1_08_USDHC1_CD_B 0x400E8204U, 0x2U, 0x400E86C8U, 0x1U, 0x400E8448U +#define IOMUXC_GPIO_DISP_B1_08_TMR3_TIMER2 0x400E8204U, 0x3U, 0x400E865CU, 0x1U, 0x400E8448U +#define IOMUXC_GPIO_DISP_B1_08_XBAR1_INOUT34 0x400E8204U, 0x4U, 0x400E8710U, 0x1U, 0x400E8448U +#define IOMUXC_GPIO_DISP_B1_08_GPIO_MUX4_IO29 0x400E8204U, 0x5U, 0, 0, 0x400E8448U +#define IOMUXC_GPIO_DISP_B1_08_SRC_BT_CFG02 0x400E8204U, 0x6U, 0, 0, 0x400E8448U +#define IOMUXC_GPIO_DISP_B1_08_ENET_QOS_TX_DATA01 0x400E8204U, 0x8U, 0, 0, 0x400E8448U +#define IOMUXC_GPIO_DISP_B1_08_LPSPI3_PCS1 0x400E8204U, 0x9U, 0x400E85F4U, 0x1U, 0x400E8448U + +#define IOMUXC_GPIO_DISP_B1_09_VIDEO_MUX_LCDIF_DATA05 0x400E8208U, 0x0U, 0, 0, 0x400E844CU +#define IOMUXC_GPIO_DISP_B1_09_ENET_1G_TX_DATA00 0x400E8208U, 0x1U, 0, 0, 0x400E844CU +#define IOMUXC_GPIO_DISP_B1_09_USDHC1_WP 0x400E8208U, 0x2U, 0x400E86CCU, 0x1U, 0x400E844CU +#define IOMUXC_GPIO_DISP_B1_09_TMR4_TIMER0 0x400E8208U, 0x3U, 0x400E8660U, 0x2U, 0x400E844CU +#define IOMUXC_GPIO_DISP_B1_09_XBAR1_INOUT35 0x400E8208U, 0x4U, 0x400E8714U, 0x1U, 0x400E844CU +#define IOMUXC_GPIO_DISP_B1_09_GPIO_MUX4_IO30 0x400E8208U, 0x5U, 0, 0, 0x400E844CU +#define IOMUXC_GPIO_DISP_B1_09_SRC_BT_CFG03 0x400E8208U, 0x6U, 0, 0, 0x400E844CU +#define IOMUXC_GPIO_DISP_B1_09_ENET_QOS_TX_DATA00 0x400E8208U, 0x8U, 0, 0, 0x400E844CU +#define IOMUXC_GPIO_DISP_B1_09_LPSPI3_PCS2 0x400E8208U, 0x9U, 0x400E85F8U, 0x1U, 0x400E844CU +#define IOMUXC_GPIO_DISP_B1_09_GPIO10_IO30 0x400E8208U, 0xAU, 0, 0, 0x400E844CU + +#define IOMUXC_GPIO_DISP_B1_10_VIDEO_MUX_LCDIF_DATA06 0x400E820CU, 0x0U, 0, 0, 0x400E8450U +#define IOMUXC_GPIO_DISP_B1_10_ENET_1G_TX_EN 0x400E820CU, 0x1U, 0, 0, 0x400E8450U +#define IOMUXC_GPIO_DISP_B1_10_USDHC1_RESET_B 0x400E820CU, 0x2U, 0, 0, 0x400E8450U +#define IOMUXC_GPIO_DISP_B1_10_TMR4_TIMER1 0x400E820CU, 0x3U, 0x400E8664U, 0x2U, 0x400E8450U +#define IOMUXC_GPIO_DISP_B1_10_XBAR1_INOUT36 0x400E820CU, 0x4U, 0, 0, 0x400E8450U +#define IOMUXC_GPIO_DISP_B1_10_GPIO_MUX4_IO31 0x400E820CU, 0x5U, 0, 0, 0x400E8450U +#define IOMUXC_GPIO_DISP_B1_10_SRC_BT_CFG04 0x400E820CU, 0x6U, 0, 0, 0x400E8450U +#define IOMUXC_GPIO_DISP_B1_10_ENET_QOS_TX_EN 0x400E820CU, 0x8U, 0, 0, 0x400E8450U +#define IOMUXC_GPIO_DISP_B1_10_LPSPI3_PCS3 0x400E820CU, 0x9U, 0x400E85FCU, 0x1U, 0x400E8450U +#define IOMUXC_GPIO_DISP_B1_10_GPIO10_IO31 0x400E820CU, 0xAU, 0, 0, 0x400E8450U + +#define IOMUXC_GPIO_DISP_B1_11_VIDEO_MUX_LCDIF_DATA07 0x400E8210U, 0x0U, 0, 0, 0x400E8454U +#define IOMUXC_GPIO_DISP_B1_11_ENET_1G_TX_CLK_IO 0x400E8210U, 0x1U, 0x400E84E8U, 0x2U, 0x400E8454U +#define IOMUXC_GPIO_DISP_B1_11_ENET_1G_REF_CLK 0x400E8210U, 0x2U, 0x400E84C4U, 0x2U, 0x400E8454U +#define IOMUXC_GPIO_DISP_B1_11_TMR4_TIMER2 0x400E8210U, 0x3U, 0x400E8668U, 0x1U, 0x400E8454U +#define IOMUXC_GPIO_DISP_B1_11_XBAR1_INOUT37 0x400E8210U, 0x4U, 0, 0, 0x400E8454U +#define IOMUXC_GPIO_DISP_B1_11_GPIO_MUX5_IO00 0x400E8210U, 0x5U, 0, 0, 0x400E8454U +#define IOMUXC_GPIO_DISP_B1_11_SRC_BT_CFG05 0x400E8210U, 0x6U, 0, 0, 0x400E8454U +#define IOMUXC_GPIO_DISP_B1_11_ENET_QOS_TX_CLK 0x400E8210U, 0x8U, 0x400E84A4U, 0x0U, 0x400E8454U +#define IOMUXC_GPIO_DISP_B1_11_ENET_QOS_REF_CLK 0x400E8210U, 0x9U, 0x400E84A0U, 0x2U, 0x400E8454U +#define IOMUXC_GPIO_DISP_B1_11_GPIO11_IO00 0x400E8210U, 0xAU, 0, 0, 0x400E8454U + +#define IOMUXC_GPIO_DISP_B2_00_GPIO11_IO01 0x400E8214U, 0xAU, 0, 0, 0x400E8458U +#define IOMUXC_GPIO_DISP_B2_00_VIDEO_MUX_LCDIF_DATA08 0x400E8214U, 0x0U, 0, 0, 0x400E8458U +#define IOMUXC_GPIO_DISP_B2_00_WDOG1_B 0x400E8214U, 0x1U, 0, 0, 0x400E8458U +#define IOMUXC_GPIO_DISP_B2_00_MQS_RIGHT 0x400E8214U, 0x2U, 0, 0, 0x400E8458U +#define IOMUXC_GPIO_DISP_B2_00_ENET_1G_TX_ER 0x400E8214U, 0x3U, 0, 0, 0x400E8458U +#define IOMUXC_GPIO_DISP_B2_00_SAI1_TX_DATA03 0x400E8214U, 0x4U, 0, 0, 0x400E8458U +#define IOMUXC_GPIO_DISP_B2_00_GPIO_MUX5_IO01 0x400E8214U, 0x5U, 0, 0, 0x400E8458U +#define IOMUXC_GPIO_DISP_B2_00_SRC_BT_CFG06 0x400E8214U, 0x6U, 0, 0, 0x400E8458U +#define IOMUXC_GPIO_DISP_B2_00_ENET_QOS_TX_ER 0x400E8214U, 0x8U, 0, 0, 0x400E8458U + +#define IOMUXC_GPIO_DISP_B2_01_VIDEO_MUX_LCDIF_DATA09 0x400E8218U, 0x0U, 0, 0, 0x400E845CU +#define IOMUXC_GPIO_DISP_B2_01_USDHC1_VSELECT 0x400E8218U, 0x1U, 0, 0, 0x400E845CU +#define IOMUXC_GPIO_DISP_B2_01_MQS_LEFT 0x400E8218U, 0x2U, 0, 0, 0x400E845CU +#define IOMUXC_GPIO_DISP_B2_01_WDOG2_B 0x400E8218U, 0x3U, 0, 0, 0x400E845CU +#define IOMUXC_GPIO_DISP_B2_01_SAI1_TX_DATA02 0x400E8218U, 0x4U, 0, 0, 0x400E845CU +#define IOMUXC_GPIO_DISP_B2_01_GPIO_MUX5_IO02 0x400E8218U, 0x5U, 0, 0, 0x400E845CU +#define IOMUXC_GPIO_DISP_B2_01_SRC_BT_CFG07 0x400E8218U, 0x6U, 0, 0, 0x400E845CU +#define IOMUXC_GPIO_DISP_B2_01_EWM_OUT_B 0x400E8218U, 0x8U, 0, 0, 0x400E845CU +#define IOMUXC_GPIO_DISP_B2_01_CCM_ENET_REF_CLK_25M 0x400E8218U, 0x9U, 0, 0, 0x400E845CU +#define IOMUXC_GPIO_DISP_B2_01_GPIO11_IO02 0x400E8218U, 0xAU, 0, 0, 0x400E845CU + +#define IOMUXC_GPIO_DISP_B2_02_GPIO11_IO03 0x400E821CU, 0xAU, 0, 0, 0x400E8460U +#define IOMUXC_GPIO_DISP_B2_02_VIDEO_MUX_LCDIF_DATA10 0x400E821CU, 0x0U, 0, 0, 0x400E8460U +#define IOMUXC_GPIO_DISP_B2_02_ENET_TX_DATA00 0x400E821CU, 0x1U, 0, 0, 0x400E8460U +#define IOMUXC_GPIO_DISP_B2_02_PIT1_TRIGGER3 0x400E821CU, 0x2U, 0, 0, 0x400E8460U +#define IOMUXC_GPIO_DISP_B2_02_ARM_TRACE00 0x400E821CU, 0x3U, 0, 0, 0x400E8460U +#define IOMUXC_GPIO_DISP_B2_02_SAI1_TX_DATA01 0x400E821CU, 0x4U, 0, 0, 0x400E8460U +#define IOMUXC_GPIO_DISP_B2_02_GPIO_MUX5_IO03 0x400E821CU, 0x5U, 0, 0, 0x400E8460U +#define IOMUXC_GPIO_DISP_B2_02_SRC_BT_CFG08 0x400E821CU, 0x6U, 0, 0, 0x400E8460U +#define IOMUXC_GPIO_DISP_B2_02_ENET_QOS_TX_DATA00 0x400E821CU, 0x8U, 0, 0, 0x400E8460U + +#define IOMUXC_GPIO_DISP_B2_03_GPIO11_IO04 0x400E8220U, 0xAU, 0, 0, 0x400E8464U +#define IOMUXC_GPIO_DISP_B2_03_VIDEO_MUX_LCDIF_DATA11 0x400E8220U, 0x0U, 0, 0, 0x400E8464U +#define IOMUXC_GPIO_DISP_B2_03_ENET_TX_DATA01 0x400E8220U, 0x1U, 0, 0, 0x400E8464U +#define IOMUXC_GPIO_DISP_B2_03_PIT1_TRIGGER2 0x400E8220U, 0x2U, 0, 0, 0x400E8464U +#define IOMUXC_GPIO_DISP_B2_03_ARM_TRACE01 0x400E8220U, 0x3U, 0, 0, 0x400E8464U +#define IOMUXC_GPIO_DISP_B2_03_SAI1_MCLK 0x400E8220U, 0x4U, 0x400E866CU, 0x1U, 0x400E8464U +#define IOMUXC_GPIO_DISP_B2_03_GPIO_MUX5_IO04 0x400E8220U, 0x5U, 0, 0, 0x400E8464U +#define IOMUXC_GPIO_DISP_B2_03_SRC_BT_CFG09 0x400E8220U, 0x6U, 0, 0, 0x400E8464U +#define IOMUXC_GPIO_DISP_B2_03_ENET_QOS_TX_DATA01 0x400E8220U, 0x8U, 0, 0, 0x400E8464U + +#define IOMUXC_GPIO_DISP_B2_04_VIDEO_MUX_LCDIF_DATA12 0x400E8224U, 0x0U, 0, 0, 0x400E8468U +#define IOMUXC_GPIO_DISP_B2_04_ENET_TX_EN 0x400E8224U, 0x1U, 0, 0, 0x400E8468U +#define IOMUXC_GPIO_DISP_B2_04_PIT1_TRIGGER1 0x400E8224U, 0x2U, 0, 0, 0x400E8468U +#define IOMUXC_GPIO_DISP_B2_04_ARM_TRACE02 0x400E8224U, 0x3U, 0, 0, 0x400E8468U +#define IOMUXC_GPIO_DISP_B2_04_SAI1_RX_SYNC 0x400E8224U, 0x4U, 0x400E8678U, 0x1U, 0x400E8468U +#define IOMUXC_GPIO_DISP_B2_04_GPIO_MUX5_IO05 0x400E8224U, 0x5U, 0, 0, 0x400E8468U +#define IOMUXC_GPIO_DISP_B2_04_SRC_BT_CFG10 0x400E8224U, 0x6U, 0, 0, 0x400E8468U +#define IOMUXC_GPIO_DISP_B2_04_ENET_QOS_TX_EN 0x400E8224U, 0x8U, 0, 0, 0x400E8468U +#define IOMUXC_GPIO_DISP_B2_04_GPIO11_IO05 0x400E8224U, 0xAU, 0, 0, 0x400E8468U + +#define IOMUXC_GPIO_DISP_B2_05_GPIO11_IO06 0x400E8228U, 0xAU, 0, 0, 0x400E846CU +#define IOMUXC_GPIO_DISP_B2_05_VIDEO_MUX_LCDIF_DATA13 0x400E8228U, 0x0U, 0, 0, 0x400E846CU +#define IOMUXC_GPIO_DISP_B2_05_ENET_TX_CLK 0x400E8228U, 0x1U, 0x400E84C0U, 0x1U, 0x400E846CU +#define IOMUXC_GPIO_DISP_B2_05_ENET_REF_CLK 0x400E8228U, 0x2U, 0x400E84A8U, 0x1U, 0x400E846CU +#define IOMUXC_GPIO_DISP_B2_05_ARM_TRACE03 0x400E8228U, 0x3U, 0, 0, 0x400E846CU +#define IOMUXC_GPIO_DISP_B2_05_SAI1_RX_BCLK 0x400E8228U, 0x4U, 0x400E8670U, 0x1U, 0x400E846CU +#define IOMUXC_GPIO_DISP_B2_05_GPIO_MUX5_IO06 0x400E8228U, 0x5U, 0, 0, 0x400E846CU +#define IOMUXC_GPIO_DISP_B2_05_SRC_BT_CFG11 0x400E8228U, 0x6U, 0, 0, 0x400E846CU +#define IOMUXC_GPIO_DISP_B2_05_ENET_QOS_TX_CLK 0x400E8228U, 0x8U, 0x400E84A4U, 0x1U, 0x400E846CU + +#define IOMUXC_GPIO_DISP_B2_06_GPIO11_IO07 0x400E822CU, 0xAU, 0, 0, 0x400E8470U +#define IOMUXC_GPIO_DISP_B2_06_VIDEO_MUX_LCDIF_DATA14 0x400E822CU, 0x0U, 0, 0, 0x400E8470U +#define IOMUXC_GPIO_DISP_B2_06_ENET_RX_DATA00 0x400E822CU, 0x1U, 0x400E84B0U, 0x1U, 0x400E8470U +#define IOMUXC_GPIO_DISP_B2_06_LPUART7_TXD 0x400E822CU, 0x2U, 0x400E8630U, 0x1U, 0x400E8470U +#define IOMUXC_GPIO_DISP_B2_06_ARM_TRACE_CLK 0x400E822CU, 0x3U, 0, 0, 0x400E8470U +#define IOMUXC_GPIO_DISP_B2_06_SAI1_RX_DATA00 0x400E822CU, 0x4U, 0x400E8674U, 0x1U, 0x400E8470U +#define IOMUXC_GPIO_DISP_B2_06_GPIO_MUX5_IO07 0x400E822CU, 0x5U, 0, 0, 0x400E8470U +#define IOMUXC_GPIO_DISP_B2_06_ENET_QOS_RX_DATA00 0x400E822CU, 0x8U, 0x400E84F0U, 0x1U, 0x400E8470U + +#define IOMUXC_GPIO_DISP_B2_07_VIDEO_MUX_LCDIF_DATA15 0x400E8230U, 0x0U, 0, 0, 0x400E8474U +#define IOMUXC_GPIO_DISP_B2_07_ENET_RX_DATA01 0x400E8230U, 0x1U, 0x400E84B4U, 0x1U, 0x400E8474U +#define IOMUXC_GPIO_DISP_B2_07_LPUART7_RXD 0x400E8230U, 0x2U, 0x400E862CU, 0x1U, 0x400E8474U +#define IOMUXC_GPIO_DISP_B2_07_ARM_TRACE_SWO 0x400E8230U, 0x3U, 0, 0, 0x400E8474U +#define IOMUXC_GPIO_DISP_B2_07_SAI1_TX_DATA00 0x400E8230U, 0x4U, 0, 0, 0x400E8474U +#define IOMUXC_GPIO_DISP_B2_07_GPIO_MUX5_IO08 0x400E8230U, 0x5U, 0, 0, 0x400E8474U +#define IOMUXC_GPIO_DISP_B2_07_ENET_QOS_RX_DATA01 0x400E8230U, 0x8U, 0x400E84F4U, 0x1U, 0x400E8474U +#define IOMUXC_GPIO_DISP_B2_07_GPIO11_IO08 0x400E8230U, 0xAU, 0, 0, 0x400E8474U + +#define IOMUXC_GPIO_DISP_B2_08_GPIO11_IO09 0x400E8234U, 0xAU, 0, 0, 0x400E8478U +#define IOMUXC_GPIO_DISP_B2_08_VIDEO_MUX_LCDIF_DATA16 0x400E8234U, 0x0U, 0, 0, 0x400E8478U +#define IOMUXC_GPIO_DISP_B2_08_ENET_RX_EN 0x400E8234U, 0x1U, 0x400E84B8U, 0x1U, 0x400E8478U +#define IOMUXC_GPIO_DISP_B2_08_LPUART8_TXD 0x400E8234U, 0x2U, 0x400E8638U, 0x1U, 0x400E8478U +#define IOMUXC_GPIO_DISP_B2_08_ARM_CM7_EVENTO 0x400E8234U, 0x3U, 0, 0, 0x400E8478U +#define IOMUXC_GPIO_DISP_B2_08_SAI1_TX_BCLK 0x400E8234U, 0x4U, 0x400E867CU, 0x1U, 0x400E8478U +#define IOMUXC_GPIO_DISP_B2_08_GPIO_MUX5_IO09 0x400E8234U, 0x5U, 0, 0, 0x400E8478U +#define IOMUXC_GPIO_DISP_B2_08_ENET_QOS_RX_EN 0x400E8234U, 0x8U, 0x400E84F8U, 0x1U, 0x400E8478U +#define IOMUXC_GPIO_DISP_B2_08_LPUART1_TXD 0x400E8234U, 0x9U, 0x400E8620U, 0x2U, 0x400E8478U + +#define IOMUXC_GPIO_DISP_B2_09_GPIO11_IO10 0x400E8238U, 0xAU, 0, 0, 0x400E847CU +#define IOMUXC_GPIO_DISP_B2_09_VIDEO_MUX_LCDIF_DATA17 0x400E8238U, 0x0U, 0, 0, 0x400E847CU +#define IOMUXC_GPIO_DISP_B2_09_ENET_RX_ER 0x400E8238U, 0x1U, 0x400E84BCU, 0x1U, 0x400E847CU +#define IOMUXC_GPIO_DISP_B2_09_LPUART8_RXD 0x400E8238U, 0x2U, 0x400E8634U, 0x1U, 0x400E847CU +#define IOMUXC_GPIO_DISP_B2_09_ARM_CM7_EVENTI 0x400E8238U, 0x3U, 0, 0, 0x400E847CU +#define IOMUXC_GPIO_DISP_B2_09_SAI1_TX_SYNC 0x400E8238U, 0x4U, 0x400E8680U, 0x1U, 0x400E847CU +#define IOMUXC_GPIO_DISP_B2_09_GPIO_MUX5_IO10 0x400E8238U, 0x5U, 0, 0, 0x400E847CU +#define IOMUXC_GPIO_DISP_B2_09_ENET_QOS_RX_ER 0x400E8238U, 0x8U, 0x400E84FCU, 0x1U, 0x400E847CU +#define IOMUXC_GPIO_DISP_B2_09_LPUART1_RXD 0x400E8238U, 0x9U, 0x400E861CU, 0x2U, 0x400E847CU + +#define IOMUXC_GPIO_DISP_B2_10_GPIO11_IO11 0x400E823CU, 0xAU, 0, 0, 0x400E8480U +#define IOMUXC_GPIO_DISP_B2_10_VIDEO_MUX_LCDIF_DATA18 0x400E823CU, 0x0U, 0, 0, 0x400E8480U +#define IOMUXC_GPIO_DISP_B2_10_EMVSIM2_IO 0x400E823CU, 0x1U, 0x400E86A8U, 0x1U, 0x400E8480U +#define IOMUXC_GPIO_DISP_B2_10_LPUART2_TXD 0x400E823CU, 0x2U, 0, 0, 0x400E8480U +#define IOMUXC_GPIO_DISP_B2_10_WDOG2_RESET_B_DEB 0x400E823CU, 0x3U, 0, 0, 0x400E8480U +#define IOMUXC_GPIO_DISP_B2_10_XBAR1_INOUT38 0x400E823CU, 0x4U, 0, 0, 0x400E8480U +#define IOMUXC_GPIO_DISP_B2_10_GPIO_MUX5_IO11 0x400E823CU, 0x5U, 0, 0, 0x400E8480U +#define IOMUXC_GPIO_DISP_B2_10_LPI2C3_SCL 0x400E823CU, 0x6U, 0x400E85BCU, 0x1U, 0x400E8480U +#define IOMUXC_GPIO_DISP_B2_10_ENET_QOS_RX_ER 0x400E823CU, 0x8U, 0x400E84FCU, 0x2U, 0x400E8480U +#define IOMUXC_GPIO_DISP_B2_10_SPDIF_IN 0x400E823CU, 0x9U, 0x400E86B4U, 0x2U, 0x400E8480U + +#define IOMUXC_GPIO_DISP_B2_11_VIDEO_MUX_LCDIF_DATA19 0x400E8240U, 0x0U, 0, 0, 0x400E8484U +#define IOMUXC_GPIO_DISP_B2_11_EMVSIM2_CLK 0x400E8240U, 0x1U, 0, 0, 0x400E8484U +#define IOMUXC_GPIO_DISP_B2_11_LPUART2_RXD 0x400E8240U, 0x2U, 0, 0, 0x400E8484U +#define IOMUXC_GPIO_DISP_B2_11_WDOG1_RESET_B_DEB 0x400E8240U, 0x3U, 0, 0, 0x400E8484U +#define IOMUXC_GPIO_DISP_B2_11_XBAR1_INOUT39 0x400E8240U, 0x4U, 0, 0, 0x400E8484U +#define IOMUXC_GPIO_DISP_B2_11_GPIO_MUX5_IO12 0x400E8240U, 0x5U, 0, 0, 0x400E8484U +#define IOMUXC_GPIO_DISP_B2_11_LPI2C3_SDA 0x400E8240U, 0x6U, 0x400E85C0U, 0x1U, 0x400E8484U +#define IOMUXC_GPIO_DISP_B2_11_ENET_QOS_CRS 0x400E8240U, 0x8U, 0, 0, 0x400E8484U +#define IOMUXC_GPIO_DISP_B2_11_SPDIF_OUT 0x400E8240U, 0x9U, 0, 0, 0x400E8484U +#define IOMUXC_GPIO_DISP_B2_11_GPIO11_IO12 0x400E8240U, 0xAU, 0, 0, 0x400E8484U + +#define IOMUXC_GPIO_DISP_B2_12_GPIO11_IO13 0x400E8244U, 0xAU, 0, 0, 0x400E8488U +#define IOMUXC_GPIO_DISP_B2_12_VIDEO_MUX_LCDIF_DATA20 0x400E8244U, 0x0U, 0, 0, 0x400E8488U +#define IOMUXC_GPIO_DISP_B2_12_EMVSIM2_RST 0x400E8244U, 0x1U, 0, 0, 0x400E8488U +#define IOMUXC_GPIO_DISP_B2_12_FLEXCAN1_TX 0x400E8244U, 0x2U, 0, 0, 0x400E8488U +#define IOMUXC_GPIO_DISP_B2_12_LPUART2_CTS_B 0x400E8244U, 0x3U, 0, 0, 0x400E8488U +#define IOMUXC_GPIO_DISP_B2_12_XBAR1_INOUT40 0x400E8244U, 0x4U, 0, 0, 0x400E8488U +#define IOMUXC_GPIO_DISP_B2_12_GPIO_MUX5_IO13 0x400E8244U, 0x5U, 0, 0, 0x400E8488U +#define IOMUXC_GPIO_DISP_B2_12_LPI2C4_SCL 0x400E8244U, 0x6U, 0x400E85C4U, 0x1U, 0x400E8488U +#define IOMUXC_GPIO_DISP_B2_12_ENET_QOS_COL 0x400E8244U, 0x8U, 0, 0, 0x400E8488U +#define IOMUXC_GPIO_DISP_B2_12_LPSPI4_SCK 0x400E8244U, 0x9U, 0x400E8610U, 0x1U, 0x400E8488U + +#define IOMUXC_GPIO_DISP_B2_13_GPIO11_IO14 0x400E8248U, 0xAU, 0, 0, 0x400E848CU +#define IOMUXC_GPIO_DISP_B2_13_VIDEO_MUX_LCDIF_DATA21 0x400E8248U, 0x0U, 0, 0, 0x400E848CU +#define IOMUXC_GPIO_DISP_B2_13_EMVSIM2_SVEN 0x400E8248U, 0x1U, 0, 0, 0x400E848CU +#define IOMUXC_GPIO_DISP_B2_13_FLEXCAN1_RX 0x400E8248U, 0x2U, 0x400E8498U, 0x1U, 0x400E848CU +#define IOMUXC_GPIO_DISP_B2_13_LPUART2_RTS_B 0x400E8248U, 0x3U, 0, 0, 0x400E848CU +#define IOMUXC_GPIO_DISP_B2_13_ENET_REF_CLK 0x400E8248U, 0x4U, 0x400E84A8U, 0x2U, 0x400E848CU +#define IOMUXC_GPIO_DISP_B2_13_GPIO_MUX5_IO14 0x400E8248U, 0x5U, 0, 0, 0x400E848CU +#define IOMUXC_GPIO_DISP_B2_13_LPI2C4_SDA 0x400E8248U, 0x6U, 0x400E85C8U, 0x1U, 0x400E848CU +#define IOMUXC_GPIO_DISP_B2_13_ENET_QOS_1588_EVENT0_OUT 0x400E8248U, 0x8U, 0, 0, 0x400E848CU +#define IOMUXC_GPIO_DISP_B2_13_LPSPI4_SIN 0x400E8248U, 0x9U, 0x400E8614U, 0x1U, 0x400E848CU + +#define IOMUXC_GPIO_DISP_B2_14_GPIO_MUX5_IO15 0x400E824CU, 0x5U, 0, 0, 0x400E8490U +#define IOMUXC_GPIO_DISP_B2_14_FLEXCAN1_TX 0x400E824CU, 0x6U, 0, 0, 0x400E8490U +#define IOMUXC_GPIO_DISP_B2_14_ENET_QOS_1588_EVENT0_IN 0x400E824CU, 0x8U, 0, 0, 0x400E8490U +#define IOMUXC_GPIO_DISP_B2_14_LPSPI4_SOUT 0x400E824CU, 0x9U, 0x400E8618U, 0x1U, 0x400E8490U +#define IOMUXC_GPIO_DISP_B2_14_GPIO11_IO15 0x400E824CU, 0xAU, 0, 0, 0x400E8490U +#define IOMUXC_GPIO_DISP_B2_14_VIDEO_MUX_LCDIF_DATA22 0x400E824CU, 0x0U, 0, 0, 0x400E8490U +#define IOMUXC_GPIO_DISP_B2_14_EMVSIM2_PD 0x400E824CU, 0x1U, 0x400E86ACU, 0x1U, 0x400E8490U +#define IOMUXC_GPIO_DISP_B2_14_WDOG2_B 0x400E824CU, 0x2U, 0, 0, 0x400E8490U +#define IOMUXC_GPIO_DISP_B2_14_VIDEO_MUX_EXT_DCIC1 0x400E824CU, 0x3U, 0, 0, 0x400E8490U +#define IOMUXC_GPIO_DISP_B2_14_ENET_1G_REF_CLK 0x400E824CU, 0x4U, 0x400E84C4U, 0x3U, 0x400E8490U + +#define IOMUXC_GPIO_DISP_B2_15_VIDEO_MUX_LCDIF_DATA23 0x400E8250U, 0x0U, 0, 0, 0x400E8494U +#define IOMUXC_GPIO_DISP_B2_15_EMVSIM2_POWER_FAIL 0x400E8250U, 0x1U, 0x400E86B0U, 0x1U, 0x400E8494U +#define IOMUXC_GPIO_DISP_B2_15_WDOG1_B 0x400E8250U, 0x2U, 0, 0, 0x400E8494U +#define IOMUXC_GPIO_DISP_B2_15_VIDEO_MUX_EXT_DCIC2 0x400E8250U, 0x3U, 0, 0, 0x400E8494U +#define IOMUXC_GPIO_DISP_B2_15_PIT1_TRIGGER0 0x400E8250U, 0x4U, 0, 0, 0x400E8494U +#define IOMUXC_GPIO_DISP_B2_15_GPIO_MUX5_IO16 0x400E8250U, 0x5U, 0, 0, 0x400E8494U +#define IOMUXC_GPIO_DISP_B2_15_FLEXCAN1_RX 0x400E8250U, 0x6U, 0x400E8498U, 0x2U, 0x400E8494U +#define IOMUXC_GPIO_DISP_B2_15_ENET_QOS_1588_EVENT0_AUX_IN 0x400E8250U, 0x8U, 0, 0, 0x400E8494U +#define IOMUXC_GPIO_DISP_B2_15_LPSPI4_PCS0 0x400E8250U, 0x9U, 0x400E860CU, 0x1U, 0x400E8494U +#define IOMUXC_GPIO_DISP_B2_15_GPIO11_IO16 0x400E8250U, 0xAU, 0, 0, 0x400E8494U + +/*@}*/ + +#define IOMUXC_GPR_SAIMCLK_LOWBITMASK (0x7U) +#define IOMUXC_GPR_SAIMCLK_HIGHBITMASK (0x3U) + +typedef enum _iomuxc_gpr_saimclk +{ + kIOMUXC_GPR_SAI1MClk1Sel = IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_SHIFT, + kIOMUXC_GPR_SAI1MClk2Sel = IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_SHIFT, + kIOMUXC_GPR_SAI1MClk3Sel = IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_SHIFT, + kIOMUXC_GPR_SAI2MClk3Sel = IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT + 8U, + kIOMUXC_GPR_SAI3MClk3Sel = IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_SHIFT + 10U, +} iomuxc_gpr_saimclk_t; + +typedef enum _iomuxc_mqs_pwm_oversample_rate +{ + kIOMUXC_MqsPwmOverSampleRate32 = 0, /* MQS PWM over sampling rate 32. */ + kIOMUXC_MqsPwmOverSampleRate64 = 1 /* MQS PWM over sampling rate 64. */ +} iomuxc_mqs_pwm_oversample_rate_t; + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus */ + +/*! @name Configuration */ +/*@{*/ + +/*! + * @brief Sets the IOMUXC pin mux mode. + * @note The first five parameters can be filled with the pin function ID macros. + * + * This is an example to set the PTA6 as the lpuart0_tx: + * @code + * IOMUXC_SetPinMux(IOMUXC_PTA6_LPUART0_TX, 0); + * @endcode + * + * This is an example to set the PTA0 as GPIOA0: + * @code + * IOMUXC_SetPinMux(IOMUXC_PTA0_GPIOA0, 0); + * @endcode + * + * @param muxRegister The pin mux register. + * @param muxMode The pin mux mode. + * @param inputRegister The select input register. + * @param inputDaisy The input daisy. + * @param configRegister The config register. + * @param inputOnfield Software input on field. + */ +static inline void IOMUXC_SetPinMux(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t inputOnfield) +{ + *((volatile uint32_t *)muxRegister) = + IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); + + if (inputRegister != 0UL) + { + *((volatile uint32_t *)inputRegister) = inputDaisy; + } +} + +/*! + * @brief Sets the IOMUXC pin configuration. + * @note The previous five parameters can be filled with the pin function ID macros. + * + * This is an example to set pin configuration for IOMUXC_PTA3_LPI2C0_SCLS: + * @code + * IOMUXC_SetPinConfig(IOMUXC_PTA3_LPI2C0_SCLS,IOMUXC_SW_PAD_CTL_PAD_PUS_MASK|IOMUXC_SW_PAD_CTL_PAD_PUS(2U)) + * @endcode + * + * @param muxRegister The pin mux register. + * @param muxMode The pin mux mode. + * @param inputRegister The select input register. + * @param inputDaisy The input daisy. + * @param configRegister The config register. + * @param configValue The pin config value. + */ +static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, + uint32_t muxMode, + uint32_t inputRegister, + uint32_t inputDaisy, + uint32_t configRegister, + uint32_t configValue) +{ + if (configRegister != 0UL) + { + *((volatile uint32_t *)configRegister) = configValue; + } +} + +/*! + * @brief Sets IOMUXC general configuration for SAI MCLK selection. + * + * @param base The IOMUXC GPR base address. + * @param mclk The SAI MCLK. + * @param clkSrc The clock source. Take refer to register setting details for the clock source in RM. + */ +static inline void IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR_Type *base, iomuxc_gpr_saimclk_t mclk, uint8_t clkSrc) +{ + uint32_t gpr; + + if (mclk > kIOMUXC_GPR_SAI2MClk3Sel) + { + gpr = base->GPR2 & ~(IOMUXC_GPR_SAIMCLK_HIGHBITMASK); + base->GPR2 = ((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) | gpr; + } + else if (mclk > kIOMUXC_GPR_SAI1MClk3Sel) + { + gpr = base->GPR1 & ~(IOMUXC_GPR_SAIMCLK_HIGHBITMASK); + base->GPR1 = ((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) | gpr; + } + else if (mclk > kIOMUXC_GPR_SAI1MClk2Sel) + { + gpr = base->GPR0 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_HIGHBITMASK << (uint32_t)mclk); + base->GPR0 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << (uint32_t)mclk) | gpr; + } + else + { + gpr = base->GPR0 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_LOWBITMASK << (uint32_t)mclk); + base->GPR0 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << (uint32_t)mclk) | gpr; + } +} + +/*! + * @brief Enters or exit MQS software reset. + * + * @param base The IOMUXC GPR base address. + * @param enable Enter or exit MQS software reset. + */ +static inline void IOMUXC_MQSEnterSoftwareReset(IOMUXC_GPR_Type *base, bool enable) +{ + if (enable) + { + base->GPR3 |= IOMUXC_GPR_GPR3_MQS_SW_RST_MASK; + } + else + { + base->GPR3 &= ~IOMUXC_GPR_GPR3_MQS_SW_RST_MASK; + } +} + +/*! + * @brief Enables or disables MQS. + * + * @param base The IOMUXC GPR base address. + * @param enable Enable or disable the MQS. + */ +static inline void IOMUXC_MQSEnable(IOMUXC_GPR_Type *base, bool enable) +{ + if (enable) + { + base->GPR3 |= IOMUXC_GPR_GPR3_MQS_EN_MASK; + } + else + { + base->GPR3 &= ~IOMUXC_GPR_GPR3_MQS_EN_MASK; + } +} + +/*! + * @brief Configure MQS PWM oversampling rate compared with mclk and divider ratio control for mclk from hmclk. + * + * @param base The IOMUXC GPR base address. + * @param rate The MQS PWM oversampling rate, refer to "iomuxc_mqs_pwm_oversample_rate_t". + * @param divider The divider ratio control for mclk from hmclk. mclk freq = 1 /(divider + 1) * hmclk freq. + */ + +static inline void IOMUXC_MQSConfig(IOMUXC_GPR_Type *base, iomuxc_mqs_pwm_oversample_rate_t rate, uint8_t divider) +{ + uint32_t gpr = base->GPR3 & ~(IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_MASK | IOMUXC_GPR_GPR3_MQS_CLK_DIV_MASK); + + base->GPR3 = gpr | IOMUXC_GPR_GPR3_MQS_OVERSAMPLE(rate) | IOMUXC_GPR_GPR3_MQS_CLK_DIV(divider); +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif /*_cplusplus */ + +/*! @}*/ + +#endif /* _FSL_IOMUXC_H_ */ diff --git a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_memory.h b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_memory.h new file mode 100644 index 0000000000..a325513859 --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_memory.h @@ -0,0 +1,89 @@ +/* + * Copyright 2021 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_MEMORY_H_ +#define _FSL_MEMORY_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.memory" +#endif +/* The CM4 subsystem local TCM start address, refer to Reference Manual for detailed information */ +#define FSL_MEM_M4_TCM_BEGIN 0x1FFE0000U +/* The CM4 subsystem local TCM end address, refer to Reference Manual for detailed information */ +#define FSL_MEM_M4_TCM_END 0x2001FFFFU + +#define FSL_MEM_M4_TCM_OFFSET 0x220000U + +typedef enum _mem_direction +{ + kMEMORY_Local2DMA = 0, + kMEMORY_DMA2Local, +} mem_direction_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif +/*! + * @brief Convert the memory map address. + * + * This function convert the address between system mapped address and native mapped address. + * There maybe offset between subsystem native address and system address for some memory, + * this funciton convert the address to different memory map. + * @param addr address need to be converted. + * @param direction convert direction. + * @return the converted address + */ +static inline uint32_t MEMORY_ConvertMemoryMapAddress(uint32_t addr, mem_direction_t direction) +{ + uint32_t dest; + + switch (direction) + { + case kMEMORY_Local2DMA: + { + if ((addr >= FSL_MEM_M4_TCM_BEGIN) && (addr <= FSL_MEM_M4_TCM_END)) + { + dest = addr + FSL_MEM_M4_TCM_OFFSET; + } + else + { + dest = addr; + } + break; + } + case kMEMORY_DMA2Local: + { + if ((addr >= (FSL_MEM_M4_TCM_BEGIN + FSL_MEM_M4_TCM_OFFSET)) && + (addr <= (FSL_MEM_M4_TCM_END + FSL_MEM_M4_TCM_OFFSET))) + { + dest = addr - FSL_MEM_M4_TCM_OFFSET; + } + else + { + dest = addr; + } + break; + } + default: + dest = addr; + break; + } + + return dest; +} +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _FSL_MEMORY_H_ */ diff --git a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_nic301.h b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_nic301.h new file mode 100644 index 0000000000..cbdb107d07 --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_nic301.h @@ -0,0 +1,293 @@ +/* + * Copyright 2020-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_NIC301_H_ +#define _FSL_NIC301_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup nic301 + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.nic301" +#endif + +/*! @name Driver version */ +/*@{*/ +/*! @brief NIC301 driver version 2.0.1. */ +#define FSL_NIC301_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U)) +/*@}*/ + +#define GPV0_BASE (0x41000000UL) +#define GPV1_BASE (0x41100000UL) +#define GPV4_BASE (0x41400000UL) + +#define NIC_FN_MOD_AHB_OFFSET (0x028UL) +#define NIC_WR_TIDEMARK_OFFSET (0x040UL) +#define NIC_READ_QOS_OFFSET (0x100UL) +#define NIC_WRITE_QOS_OFFSET (0x104UL) +#define NIC_FN_MOD_OFFSET (0x108UL) + +#define NIC_GC355_BASE (GPV0_BASE + 0x42000) +#define NIC_PXP_BASE (GPV0_BASE + 0x43000) +#define NIC_LCDIF_BASE (GPV0_BASE + 0x44000) +#define NIC_LCDIFV2_BASE (GPV0_BASE + 0x45000) +#define NIC_CSI_BASE (GPV0_BASE + 0x46000) + +#define NIC_CAAM_BASE (GPV1_BASE + 0x42000) +#define NIC_ENET1G_RX_BASE (GPV1_BASE + 0x43000) +#define NIC_ENET1G_TX_BASE (GPV1_BASE + 0x44000) +#define NIC_ENET_BASE (GPV1_BASE + 0x45000) +#define NIC_USBO2_BASE (GPV1_BASE + 0x46000) +#define NIC_USDHC1_BASE (GPV1_BASE + 0x47000) +#define NIC_USDHC2_BASE (GPV1_BASE + 0x48000) +#define NIC_ENET_QOS_BASE (GPV1_BASE + 0x4A000) + +#define NIC_CM7_BASE (GPV4_BASE + 0x42000) +#define NIC_LPSRMIX_M_BASE (GPV4_BASE + 0x46000) +#define NIC_DMA_BASE (GPV4_BASE + 0x47000) +#define NIC_IEE_BASE (GPV4_BASE + 0x48000) + +#define NIC_QOS_MASK (0xF) +#define NIC_WR_TIDEMARK_MASK (0xF) +#define NIC_FN_MOD_AHB_MASK (0x7) +#define NIC_FN_MOD_MASK (0x1) + +typedef enum _nic_reg +{ + /* read_qos */ + kNIC_REG_READ_QOS_GC355 = NIC_GC355_BASE + NIC_READ_QOS_OFFSET, + kNIC_REG_READ_QOS_PXP = NIC_PXP_BASE + NIC_READ_QOS_OFFSET, + kNIC_REG_READ_QOS_LCDIF = NIC_LCDIF_BASE + NIC_READ_QOS_OFFSET, + kNIC_REG_READ_QOS_LCDIFV2 = NIC_LCDIFV2_BASE + NIC_READ_QOS_OFFSET, + kNIC_REG_READ_QOS_CSI = NIC_CSI_BASE + NIC_READ_QOS_OFFSET, + kNIC_REG_READ_QOS_CAAM = NIC_CAAM_BASE + NIC_READ_QOS_OFFSET, + kNIC_REG_READ_QOS_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_READ_QOS_OFFSET, + kNIC_REG_READ_QOS_ENET1G_TX = NIC_ENET1G_TX_BASE + NIC_READ_QOS_OFFSET, + kNIC_REG_READ_QOS_ENET = NIC_ENET_BASE + NIC_READ_QOS_OFFSET, + kNIC_REG_READ_QOS_USBO2 = NIC_USBO2_BASE + NIC_READ_QOS_OFFSET, + kNIC_REG_READ_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_READ_QOS_OFFSET, + kNIC_REG_READ_QOS_USDHC2 = NIC_USDHC2_BASE + NIC_READ_QOS_OFFSET, + kNIC_REG_READ_QOS_ENET_QOS = NIC_ENET_QOS_BASE + NIC_READ_QOS_OFFSET, + kNIC_REG_READ_QOS_CM7 = NIC_CM7_BASE + NIC_READ_QOS_OFFSET, + kNIC_REG_READ_QOS_DMA = NIC_DMA_BASE + NIC_READ_QOS_OFFSET, + kNIC_REG_READ_QOS_IEE = NIC_IEE_BASE + NIC_READ_QOS_OFFSET, + + /* write_qos */ + kNIC_REG_WRITE_QOS_GC355 = NIC_GC355_BASE + NIC_WRITE_QOS_OFFSET, + kNIC_REG_WRITE_QOS_PXP = NIC_PXP_BASE + NIC_WRITE_QOS_OFFSET, + kNIC_REG_WRITE_QOS_LCDIF = NIC_LCDIF_BASE + NIC_WRITE_QOS_OFFSET, + kNIC_REG_WRITE_QOS_LCDIFV2 = NIC_LCDIFV2_BASE + NIC_WRITE_QOS_OFFSET, + kNIC_REG_WRITE_QOS_CSI = NIC_CSI_BASE + NIC_WRITE_QOS_OFFSET, + kNIC_REG_WRITE_QOS_CAAM = NIC_CAAM_BASE + NIC_WRITE_QOS_OFFSET, + kNIC_REG_WRITE_QOS_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_WRITE_QOS_OFFSET, + kNIC_REG_WRITE_QOS_ENET1G_TX = NIC_ENET1G_TX_BASE + NIC_WRITE_QOS_OFFSET, + kNIC_REG_WRITE_QOS_ENET = NIC_ENET_BASE + NIC_WRITE_QOS_OFFSET, + kNIC_REG_WRITE_QOS_USBO2 = NIC_USBO2_BASE + NIC_WRITE_QOS_OFFSET, + kNIC_REG_WRITE_QOS_USDHC1 = NIC_USDHC1_BASE + NIC_WRITE_QOS_OFFSET, + kNIC_REG_WRITE_QOS_USDHC2 = NIC_USDHC2_BASE + NIC_WRITE_QOS_OFFSET, + kNIC_REG_WRITE_QOS_ENET_QOS = NIC_ENET_QOS_BASE + NIC_WRITE_QOS_OFFSET, + kNIC_REG_WRITE_QOS_CM7 = NIC_CM7_BASE + NIC_WRITE_QOS_OFFSET, + kNIC_REG_WRITE_QOS_DMA = NIC_DMA_BASE + NIC_WRITE_QOS_OFFSET, + kNIC_REG_WRITE_QOS_IEE = NIC_IEE_BASE + NIC_WRITE_QOS_OFFSET, + + /* fn_mod */ + kNIC_REG_FN_MOD_GC355 = NIC_GC355_BASE + NIC_FN_MOD_OFFSET, + kNIC_REG_FN_MOD_PXP = NIC_PXP_BASE + NIC_FN_MOD_OFFSET, + kNIC_REG_FN_MOD_LCDIF = NIC_LCDIF_BASE + NIC_FN_MOD_OFFSET, + kNIC_REG_FN_MOD_LCDIFV2 = NIC_LCDIFV2_BASE + NIC_FN_MOD_OFFSET, + kNIC_REG_FN_MOD_CSI = NIC_CSI_BASE + NIC_FN_MOD_OFFSET, + kNIC_REG_FN_MOD_CAAM = NIC_CAAM_BASE + NIC_FN_MOD_OFFSET, + kNIC_REG_FN_MOD_ENET1G_RX = NIC_ENET1G_RX_BASE + NIC_FN_MOD_OFFSET, + kNIC_REG_FN_MOD_ENET1G_TX = NIC_ENET1G_TX_BASE + NIC_FN_MOD_OFFSET, + kNIC_REG_FN_MOD_ENET = NIC_ENET_BASE + NIC_FN_MOD_OFFSET, + kNIC_REG_FN_MOD_USBO2 = NIC_USBO2_BASE + NIC_FN_MOD_OFFSET, + kNIC_REG_FN_MOD_USDHC1 = NIC_USDHC1_BASE + NIC_FN_MOD_OFFSET, + kNIC_REG_FN_MOD_USDHC2 = NIC_USDHC2_BASE + NIC_FN_MOD_OFFSET, + kNIC_REG_FN_MOD_ENET_QOS = NIC_ENET_QOS_BASE + NIC_FN_MOD_OFFSET, + kNIC_REG_FN_MOD_CM7 = NIC_CM7_BASE + NIC_FN_MOD_OFFSET, + kNIC_REG_FN_MOD_DMA = NIC_DMA_BASE + NIC_FN_MOD_OFFSET, + kNIC_REG_FN_MOD_IEE = NIC_IEE_BASE + NIC_FN_MOD_OFFSET, + + /* fn_mod_ahb */ + kNIC_REG_FN_MOD_AHB_ENET = NIC_ENET_BASE + NIC_FN_MOD_AHB_OFFSET, + kNIC_REG_FN_MOD_AHB_DMA = NIC_DMA_BASE + NIC_FN_MOD_AHB_OFFSET, + + /* wr_tidemark */ + kNIC_REG_WR_TIDEMARK_LPSRMIX_M = NIC_LPSRMIX_M_BASE + NIC_WR_TIDEMARK_OFFSET, +} nic_reg_t; + +/* fn_mod_ahb */ +typedef enum _nic_fn_mod_ahb +{ + kNIC_FN_MOD_AHB_RD_INCR_OVERRIDE = 0, + kNIC_FN_MOD_AHB_WR_INCR_OVERRIDE, + kNIC_FN_MOD_AHB_LOCK_OVERRIDE, +} nic_fn_mod_ahb_t; + +/* fn_mod */ +typedef enum _nic_fn_mod +{ + kNIC_FN_MOD_ReadIssue = 0, + kNIC_FN_MOD_WriteIssue, +} nic_fn_mod_t; + +/* read_qos/write_qos */ +typedef enum _nic_qos +{ + kNIC_QOS_0 = 0, + kNIC_QOS_1, + kNIC_QOS_2, + kNIC_QOS_3, + kNIC_QOS_4, + kNIC_QOS_5, + kNIC_QOS_6, + kNIC_QOS_7, + kNIC_QOS_8, + kNIC_QOS_9, + kNIC_QOS_10, + kNIC_QOS_11, + kNIC_QOS_12, + kNIC_QOS_13, + kNIC_QOS_14, + kNIC_QOS_15, +} nic_qos_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @brief Set read_qos Value + * + * @param base Base address of GPV address + * @param value Target value (0 - 15) + */ +static inline void NIC_SetReadQos(nic_reg_t base, nic_qos_t value) +{ + *(volatile uint32_t *)(base) = (value & NIC_QOS_MASK); + __DSB(); +} + +/*! + * @brief Get read_qos Value + * + * @param base Base address of GPV address + * @return Current value configured + */ +static inline nic_qos_t NIC_GetReadQos(nic_reg_t base) +{ + return (nic_qos_t)((*(volatile uint32_t *)(base)) & NIC_QOS_MASK); +} + +/*! + * @brief Set write_qos Value + * + * @param base Base address of GPV address + * @param value Target value (0 - 15) + */ +static void inline NIC_SetWriteQos(nic_reg_t base, nic_qos_t value) +{ + *(volatile uint32_t *)(base) = (value & NIC_QOS_MASK); + __DSB(); +} + +/*! + * @brief Get write_qos Value + * + * @param base Base address of GPV address + * @return Current value configured + */ +static inline nic_qos_t NIC_GetWriteQos(nic_reg_t base) +{ + return (nic_qos_t)((*(volatile uint32_t *)(base)) & NIC_QOS_MASK); +} + +/*! + * @brief Set fn_mod_ahb Value + * + * @param base Base address of GPV address + * @param value Target value + */ +static inline void NIC_SetFnModAhb(nic_reg_t base, nic_fn_mod_ahb_t v) +{ + *(volatile uint32_t *)(base) = v; + __DSB(); +} + +/*! + * @brief Get fn_mod_ahb Value + * + * @param base Base address of GPV address + * @return Current value configured + */ +static inline nic_fn_mod_ahb_t NIC_GetFnModAhb(nic_reg_t base) +{ + return (nic_fn_mod_ahb_t)((*(volatile uint32_t *)(base)) & NIC_FN_MOD_AHB_MASK); +} + +/*! + * @brief Set wr_tidemark Value + * + * @param base Base address of GPV address + * @param value Target value (0 - 15) + */ +static inline void NIC_SetWrTideMark(nic_reg_t base, uint8_t value) +{ + *(volatile uint32_t *)(base) = (value & NIC_WR_TIDEMARK_MASK); + __DSB(); +} + +/*! + * @brief Get wr_tidemark Value + * + * @param base Base address of GPV address + * @return Current value configured + */ +static inline uint8_t NIC_GetWrTideMark(nic_reg_t base) +{ + return (uint8_t)((*(volatile uint32_t *)(base)) & NIC_WR_TIDEMARK_MASK); +} + +/*! + * @brief Set fn_mod Value + * + * @param base Base address of GPV address + * @param value Target value + */ +static inline void NIC_SetFnMod(nic_reg_t base, nic_fn_mod_t value) +{ + *(volatile uint32_t *)(base) = value; + __DSB(); +} + +/*! + * @brief Get fn_mod Value + * + * @param base Base address of GPV address + * @return Current value configured + */ +static inline nic_fn_mod_t NIC_GetFnMod(nic_reg_t base) +{ + return (nic_fn_mod_t)((*(volatile uint32_t *)(base)) & NIC_FN_MOD_MASK); +} + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +#endif /* _FSL_NIC301_H_ */ diff --git a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_pgmc.c b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_pgmc.c new file mode 100644 index 0000000000..03488ee4b1 --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_pgmc.c @@ -0,0 +1,461 @@ +/* + * Copyright 2019-2021, NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_pgmc.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.pgmc" +#endif + +/*! + * @brief The structure of MIF signal. + */ +typedef struct +{ + __IO uint32_t SIGNAL; /*!< MIF MLPL control of each signal. */ + __IO uint32_t DELAY; /*!< MIF Delay of each signal */ + uint32_t RESERVED[2]; +} PGMC_MIF_SIGNAL_Type; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Makes the BPC module controlled by the target CPU power mode(Such as Wait mode). + * + * This function makes the module controlled by four typical CPU power modes, It also configs the resource domain and + * set memory low power level. + * + * param base PGMC basic power controller base address. + * param mode Target CPU power mode. + * param option The pointer of @ref pgmc_bpc_cpu_power_mode_option_t structure. + */ +void PGMC_BPC_ControlPowerDomainByCpuPowerMode(PGMC_BPC_Type *base, + pgmc_cpu_mode_t mode, + const pgmc_bpc_cpu_power_mode_option_t *option) +{ + assert(option != NULL); + + uint32_t tmp32 = base->BPC_SSAR_SAVE_CTRL; + + base->BPC_MODE = PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN(option->assignDomain) | + PGMC_BPC_BPC_MODE_CTRL_MODE(kPGMC_ControlledByCpuPowerMode); + switch (mode) + { + case kPGMC_RunMode: + tmp32 |= PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_MASK; + break; + case kPGMC_WaitMode: + if (option->powerOff) + { + base->BPC_POWER_CTRL |= PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_MASK; + } + tmp32 |= PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_MASK; + break; + case kPGMC_StopMode: + if (option->powerOff) + { + base->BPC_POWER_CTRL |= PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_MASK; + } + tmp32 |= PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_MASK; + break; + case kPGMC_SuspendMode: + if (option->powerOff) + { + base->BPC_POWER_CTRL |= PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK; + } + tmp32 |= PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_MASK; + break; + default: + assert(false); + break; + } + + if (option->stateSave) + { + base->BPC_SSAR_SAVE_CTRL = tmp32; + } +} + +/*! + * brief Makes the BPC module controlled by the target set points. + * + * This function makes the module controlled by specific set point, It also supports set memory lowe power level. + * + * note When setting more than one set point, use "|" between the map values in @ref _pgmc_setpoint_map. + * + * param base PGMC basic power controller base address. + * param setPointMap Should be the OR'ed value of @ref _pgmc_setpoint_map. + * param option The pointer of @ref pgmc_bpc_setpoint_mode_option_t structure. + */ +void PGMC_BPC_ControlPowerDomainBySetPointMode(PGMC_BPC_Type *base, + uint32_t setPointMap, + const pgmc_bpc_setpoint_mode_option_t *option) +{ + assert(option != NULL); + + setPointMap &= 0xFFFFU; + + base->BPC_MODE = PGMC_BPC_BPC_MODE_CTRL_MODE(kPGMC_ControlledBySetPoint); + if (option->powerOff) + { + base->BPC_POWER_CTRL |= PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP(setPointMap); + } + + if (option->stateSave) + { + base->BPC_SSAR_SAVE_CTRL = PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP(setPointMap); + } +} + +/*! + * brief Controls the selected power domain by software mode. + * + * note The function is used to control power domain when the CPU is in RUN mode. + * + * param base PGMC basic power controller base address. + * param powerOff Power On/Off power domain in software mode. + * - \b true Power off the power domain in software mode. + * - \b false Power on the power domain in software mode. + */ +void PGMC_BPC_ControlPowerDomainBySoftwareMode(PGMC_BPC_Type *base, bool powerOff) +{ + if (powerOff) + { + base->BPC_POWER_CTRL |= (PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_MASK | PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_MASK); + } + else + { + base->BPC_POWER_CTRL |= (PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_MASK | PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_MASK); + } +} + +/*! + * brief Powers off the CPC core module by the target CPU power mode(Such as Wait mode). + * + * param base CPC CORE module base address. + * param mode Target CPU power mode. + */ +void PGMC_CPC_CORE_PowerOffByCpuPowerMode(PGMC_CPC_Type *base, pgmc_cpu_mode_t mode) +{ + base->CPC_CORE_MODE = PGMC_CPC_CPC_CORE_MODE_CTRL_MODE(kPGMC_ControlledByCpuPowerMode); + switch (mode) + { + case kPGMC_RunMode: + break; + case kPGMC_WaitMode: + base->CPC_CORE_POWER_CTRL |= PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_MASK; + break; + case kPGMC_StopMode: + base->CPC_CORE_POWER_CTRL |= PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_MASK; + break; + case kPGMC_SuspendMode: + base->CPC_CORE_POWER_CTRL |= PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK; + break; + default: + assert(false); + break; + } +} + +/*! + * brief Makes the CPC CACHE module controlled by the target CPU power mode(Such as Wait mode). + * + * This function makes the module controlled by four typical CPU power modes, it also can set memory low power level. + * + * param base CPC CACHE module base address. + * param mode Target CPU power mode. + * param memoryLowPowerLevel Memory low power level. + */ +void PGMC_CPC_CACHE_ControlByCpuPowerMode(PGMC_CPC_Type *base, + pgmc_cpu_mode_t mode, + pgmc_memory_low_power_level_t memoryLowPowerLevel) +{ + uint32_t temp32; + + base->CPC_CACHE_MODE = PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE(kPGMC_ControlledByCpuPowerMode); + temp32 = base->CPC_CACHE_CM_CTRL; + switch (mode) + { + case kPGMC_RunMode: + temp32 &= ~PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_MASK; + base->CPC_CACHE_CM_CTRL = temp32 | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN(memoryLowPowerLevel); + break; + case kPGMC_WaitMode: + temp32 &= ~PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_MASK; + base->CPC_CACHE_CM_CTRL = temp32 | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT(memoryLowPowerLevel); + break; + case kPGMC_StopMode: + temp32 &= ~PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_MASK; + base->CPC_CACHE_CM_CTRL = temp32 | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP(memoryLowPowerLevel); + break; + case kPGMC_SuspendMode: + temp32 &= ~PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_MASK; + base->CPC_CACHE_CM_CTRL = temp32 | PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND(memoryLowPowerLevel); + break; + default: + assert(false); + break; + } +} + +/*! + * brief Makes the CPC CACHE module controlled by the target set points. + * + * This function makes the module controlled by specific set point, It also supports set memory lowe power level. + * + * note When setting more than one set point, use "|" between the map values in @ref _pgmc_setpoint_map. + * + * param base CPC CACHE module base address. + * param setPointMap Should be the OR'ed value of @ref _pgmc_setpoint_map. + * param memoryLowPowerLevel Memory low power level. + */ +void PGMC_CPC_CACHE_ControlBySetPointMode(PGMC_CPC_Type *base, + uint32_t setPointMap, + pgmc_memory_low_power_level_t memoryLowPowerLevel) +{ + uint32_t setPointIndex = 0UL; + uint32_t tmp32 = 0UL; + uint32_t regIndex = 0UL; + volatile uint32_t *ptrMemSpCtrlReg = NULL; + + setPointMap &= 0xFFFFU; + + base->CPC_CACHE_MODE = PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE(kPGMC_ControlledBySetPoint); + + ptrMemSpCtrlReg = &(base->CPC_CACHE_SP_CTRL_0); + for (regIndex = 0UL; regIndex < 2UL; regIndex++) + { + ptrMemSpCtrlReg += regIndex; + tmp32 = *ptrMemSpCtrlReg; + for (setPointIndex = 0UL; setPointIndex < 8UL; setPointIndex++) + { + if (0UL != (setPointMap & (1UL << ((regIndex * 8UL) + setPointIndex)))) + { + tmp32 &= ~((uint32_t)PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_MASK << (setPointIndex * 4U)); + tmp32 |= ((uint32_t)memoryLowPowerLevel << (setPointIndex * 4U)); + } + } + *ptrMemSpCtrlReg = tmp32; + } +} + +/*! + * brief Requests CPC cache module's memory low power level change by software mode. + * + * note If request memory low power level change, must wait the MLPL transition complete. + * + * param base CPC LMEM module base address. + */ +void PGMC_CPC_CACHE_TriggerMLPLSoftwareChange(PGMC_CPC_Type *base) +{ + base->CPC_CACHE_CM_CTRL |= PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_MASK; + + /* If request software change, check the MLPL transition status. */ + while (0UL != ((base->CPC_CACHE_CM_CTRL) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_MASK)) + { + } +} + +/*! + * brief Makes the CPC LMEM module controlled by the target CPU power mode(Such as Wait mode). + * + * This function makes the module controlled by four typical CPU power modes, it also can set memory low power level. + * + * param base CPC LMEM module base address. + * param mode Target CPU power mode. + * param memoryLowPowerLevel Memory low power level. + */ +void PGMC_CPC_LMEM_ControlByCpuPowerMode(PGMC_CPC_Type *base, + pgmc_cpu_mode_t mode, + pgmc_memory_low_power_level_t memoryLowPowerLevel) +{ + uint32_t temp32; + + base->CPC_LMEM_MODE = PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE(kPGMC_ControlledByCpuPowerMode); + + temp32 = base->CPC_LMEM_CM_CTRL; + switch (mode) + { + case kPGMC_RunMode: + temp32 &= ~PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_MASK; + base->CPC_LMEM_CM_CTRL = temp32 | PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN(memoryLowPowerLevel); + break; + case kPGMC_WaitMode: + temp32 &= ~PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_MASK; + base->CPC_LMEM_CM_CTRL = temp32 | PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT(memoryLowPowerLevel); + break; + case kPGMC_StopMode: + temp32 &= ~PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_MASK; + base->CPC_LMEM_CM_CTRL = temp32 | PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP(memoryLowPowerLevel); + break; + case kPGMC_SuspendMode: + temp32 &= ~PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_MASK; + base->CPC_LMEM_CM_CTRL = temp32 | PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND(memoryLowPowerLevel); + break; + default: + assert(false); + break; + } +} + +/*! + * brief Makes the CPC LMEM module controlled by the target set points. + * + * This function makes the module controlled by specific set point, It also supports set memory lowe power level. + * + * note When setting more than one set point, use "|" between the map values in @ref _pgmc_setpoint_map. + * + * param base CPC LMEM module base address. + * param setPointMap Should be the OR'ed value of @ref _pgmc_setpoint_map. + * param memoryLowPowerLevel Memory low power level. + */ +void PGMC_CPC_LMEM_ControlBySetPointMode(PGMC_CPC_Type *base, + uint32_t setPointMap, + pgmc_memory_low_power_level_t memoryLowPowerLevel) +{ + uint32_t setPointIndex = 0UL; + uint32_t tmp32 = 0UL; + uint32_t regIndex = 0UL; + volatile uint32_t *ptrMemSpCtrlReg = NULL; + + setPointMap &= 0xFFFFU; + + base->CPC_LMEM_MODE = PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE(kPGMC_ControlledBySetPoint); + + ptrMemSpCtrlReg = &(base->CPC_LMEM_SP_CTRL_0); + for (regIndex = 0UL; regIndex < 2UL; regIndex++) + { + ptrMemSpCtrlReg += regIndex; + tmp32 = *ptrMemSpCtrlReg; + for (setPointIndex = 0UL; setPointIndex < 8UL; setPointIndex++) + { + if (0UL != (setPointMap & (1UL << ((regIndex * 8UL) + setPointIndex)))) + { + tmp32 &= ~((uint32_t)PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_MASK << (setPointIndex * 4U)); + tmp32 |= ((uint32_t)memoryLowPowerLevel << (setPointIndex * 4U)); + } + } + *ptrMemSpCtrlReg = tmp32; + } +} + +/*! + * brief Requests CPC LMEM module's memory low power level change in software mode. + * + * note If request memory low power level change, must wait the MLPL transition complete. + * + * param base CPC LMEM module base address. + */ +void PGMC_CPC_LMEM_TriggerMLPLSoftwareChange(PGMC_CPC_Type *base) +{ + base->CPC_LMEM_CM_CTRL |= PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_MASK; + + /* If request software change, check the MLPL transition status. */ + while (0UL != ((base->CPC_LMEM_CM_CTRL) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_MASK)) + { + } +} + +/*! + * brief Sets the behaviour of each signal(Such as Sleep signal) in MIF. + * + * note To control the memory low power operation, this function must be invoked after selecting the + * memory low power level. + * Use case: + * code + * PGMC_BPC_ControlPowerDomainByCpuPowerMode(PGMC_BPC0_BASE, kPGMC_WaitMode, kPGMC_CM7Core, + * kPGMC_MLPLSleep, false); + * PGMC_MIF_SetSignalBehaviour(PGMC_BPC0_MIF_BASE, kPGMC_MLPLSleep, kPGMC_AssertSleepSignal); + * endcode + * + * param base PGMC MIF peripheral base address. + * param memoryLevel The selected memory low power level. For details please refer to @ref + * pgmc_memory_low_power_level_t. + * param mask The mask of MIF signal behaviour. Should be the OR'ed value of @ref _pgmc_mif_signal_behaviour + */ +void PGMC_MIF_SetSignalBehaviour(PGMC_MIF_Type *base, pgmc_memory_low_power_level_t memoryLevel, uint32_t mask) +{ + uint8_t signalIndex = 0U; + uint32_t temp32 = 0U; + PGMC_MIF_SIGNAL_Type *MIF_SIG = (PGMC_MIF_SIGNAL_Type *)(uint32_t)(&(base->MIF_MLPL_SLEEP)); + + for (signalIndex = 0U; signalIndex < 11U; signalIndex++) + { + temp32 = MIF_SIG[signalIndex].SIGNAL; + temp32 &= ~(1UL << (uint32_t)memoryLevel); + temp32 |= ((uint32_t)(mask & (1UL << signalIndex)) << (uint32_t)memoryLevel); + MIF_SIG[signalIndex].SIGNAL = temp32; + } +} + +/*! + * brief Makes the PMIC module controlled by the target CPU power mode(Such as Wait mode). + * + * param base PMIC module base address. + * param mode Target CPU power mode. + */ +void PGMC_PPC_ControlByCpuPowerMode(PGMC_PPC_Type *base, pgmc_cpu_mode_t mode) +{ + base->PPC_MODE = PGMC_PPC_PPC_MODE_CTRL_MODE(kPGMC_ControlledByCpuPowerMode); + switch (mode) + { + case kPGMC_RunMode: + break; + case kPGMC_WaitMode: + base->PPC_STBY_CM_CTRL |= PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_WAIT_MASK; + break; + case kPGMC_StopMode: + base->PPC_STBY_CM_CTRL |= PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_STOP_MASK; + break; + case kPGMC_SuspendMode: + base->PPC_STBY_CM_CTRL |= PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_SUSPEND_MASK; + break; + default: + assert(false); + break; + } +} + +/*! + * brief Makes the PMIC module controlled by the target set points. + * + * This function makes the module controlled by specific set point, It also supports PMIC standby on. + * + * note When setting more than one set point, use "|" between the map values in @ref _pgmc_setpoint_map. + * + * param base PMIC module base address. + * param setPointMap Should be the OR'ed value of @ref _pgmc_setpoint_map. + * param enableStandby true: PMIC standby on when system enters set point number and system is in standby mode. + * false: PMIC standby on when system enters set point number + */ +void PGMC_PPC_ControlBySetPointMode(PGMC_PPC_Type *base, uint32_t setPointMap, bool enableStandby) +{ + setPointMap &= 0xFFFFU; + + base->PPC_MODE = PGMC_PPC_PPC_MODE_CTRL_MODE(kPGMC_ControlledBySetPoint); + + if (enableStandby) + { + base->PPC_STBY_SP_CTRL = (setPointMap << PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_SLEEP_SHIFT); + } + else + { + base->PPC_STBY_SP_CTRL = setPointMap; + } +} diff --git a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_pgmc.h b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_pgmc.h new file mode 100644 index 0000000000..47fb2f8d42 --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_pgmc.h @@ -0,0 +1,783 @@ +/* + * Copyright 2019-2021, NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_PGMC_H_ +#define _FSL_PGMC_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup PGMC + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief PGMC driver version 2.1.1. */ +#define FSL_PGMC_RIVER_VERSION (MAKE_VERSION(2, 1, 1)) +/*@}*/ + +/*! @brief The enumeration of setpoint. + * @anchor _pgmc_setpoint_map + */ +enum +{ + kPGMC_SetPoint0 = 1UL << 0UL, /*!< The mask of set point0. */ + kPGMC_SetPoint1 = 1UL << 1UL, /*!< The mask of set point1. */ + kPGMC_SetPoint2 = 1UL << 2UL, /*!< The mask of set point2. */ + kPGMC_SetPoint3 = 1UL << 3UL, /*!< The mask of set point3. */ + kPGMC_SetPoint4 = 1UL << 4UL, /*!< The mask of set point4. */ + kPGMC_SetPoint5 = 1UL << 5UL, /*!< The mask of set point5. */ + kPGMC_SetPoint6 = 1UL << 6UL, /*!< The mask of set point6. */ + kPGMC_SetPoint7 = 1UL << 7UL, /*!< The mask of set point7. */ + kPGMC_SetPoint8 = 1UL << 8UL, /*!< The mask of set point8. */ + kPGMC_SetPoint9 = 1UL << 9UL, /*!< The mask of set point9. */ + kPGMC_SetPoint10 = 1UL << 10UL, /*!< The mask of set point10. */ + kPGMC_SetPoint11 = 1UL << 11UL, /*!< The mask of set point11. */ + kPGMC_SetPoint12 = 1UL << 12UL, /*!< The mask of set point12. */ + kPGMC_SetPoint13 = 1UL << 13UL, /*!< The mask of set point13. */ + kPGMC_SetPoint14 = 1UL << 14UL, /*!< The mask of set point14. */ + kPGMC_SetPoint15 = 1UL << 15UL, /*!< The mask of set point15. */ +}; + +/*! + * @brief The enumeration of MIF signal behaviour(Such as Sleep Signal, Standby Signal, and so on). + */ +enum _pgmc_mif_signal_behaviour +{ + kPGMC_AssertSleepSignal = 1U << 0U, /*!< Assert Sleep signal. */ + kPGMC_AssertInputGateSignal = 1U << 1U, /*!< Assert InputGate signal. */ + kPGMC_AssetLowSpeedSignal = 1U << 2U, /*!< Assert LowSpeed signal. */ + kPGMC_AssertHighSpeedSignal = 1U << 3U, /*!< Assert HighSpeed signal. */ + kPGMC_AssertStandbySignal = 1U << 4U, /*!< Assert Standby signal. */ + kPGMC_AssertArrayPowerDownSignal = 1U << 5U, /*!< Assert ArrayPowerDown signal. */ + kPGMC_AssertPeripheralPowerDownSignal = 1U << 6U, /*!< Assert PeripheralPowerDown signal. */ + kPGMC_AssertInitnSignal = 1U << 7U, /*!< Assert Initn signal. */ + kPGMC_AssertSwitch1OffSignal = 1U << 8U, /*!< Assert Switch1Off signal. */ + kPGMC_AssertSwitch2OffSignal = 1U << 9U, /*!< Assert Switch2Off signal. */ + kPGMC_AssertIsoSignal = 1U << 10U, /*!< Assert Iso_en signal. */ +}; + +/*! + * @brief PGMC BPC assign domain enumeration. + */ +typedef enum _pgmc_bpc_assign_domain +{ + kPGMC_CM7Core = 0U, /*!< CM7 Core domain. */ + kPGMC_CM4Core = 1U /*!< CM4 Core domain. */ +} pgmc_bpc_assign_domain_t; + +/*! @brief CPU mode. */ +typedef enum _pgmc_cpu_mode +{ + kPGMC_RunMode = 0x0UL, /*!< RUN mode. */ + kPGMC_WaitMode = 0x1UL, /*!< WAIT mode. */ + kPGMC_StopMode = 0x2UL, /*!< STOP mode. */ + kPGMC_SuspendMode = 0x3UL, /*!< SUSPEND mode. */ +} pgmc_cpu_mode_t; + +/*! @brief PGMC control modes. */ +typedef enum _pgmc_control_mode +{ + kPGMC_DisableLowPowerControl = 0UL, + kPGMC_ControlledByCpuPowerMode = 1UL, + kPGMC_ControlledBySetPoint = 2UL, +} pgmc_control_mode_t; + +/*! + * @brief The enumeration of memory low power level. + */ +typedef enum _pgmc_memory_low_power_level +{ + kPGMC_MLPLHighSpeed = 1U, /*!< Memory low power level: High speed. */ + kPGMC_MLPLNormal = 3U, /*!< Memory low power level: Normal. */ + kPGMC_MLPLLowSpeed = 4U, /*!< Memory low power level: Low Speed. */ + kPGMC_MLPLInputGating = 5U, /*!< Memory low power level: Input Gating. */ + kPGMC_MLPLStandby = 6U, /*!< Memory low power level: Standby. */ + kPGMC_MLPLSleep = 8U, /*!< Memory low power level: Sleep. */ + kPGMC_MLPLArrOnPerOff = 9U, /*!< Memory low power level: Arr on per off. */ + kPGMC_MLPLArrOffPerOn = 10U, /*!< Memory low power level: Arr off per on. */ + kPGMC_MLPLArrOffPerOff = 11U, /*!< Memory low power level: Arr off per off. */ + kPGMC_MLPLSw2 = 13U, /*!< Memory low power level: SW2. */ + kPGMC_MLPLSw2PerOff = 14U, /*!< Memory low power level: SW2 Per off. */ + kPGMC_MLPLSw1PerOff = 15U, /*!< Memory low power level: SW1 Per off. */ +} pgmc_memory_low_power_level_t; + +/*! + * @brief The enumeration of MIF signal. + */ +typedef enum _pgmc_mif_signal +{ + kPGMC_SleepSignal = 0U, /*!< MIF Sleep signal. */ + kPGMC_InputGateSignal = 1U, /*!< MIF InputGate signal. */ + kPGMC_LowSpeedSignal = 2U, /*!< MIF LowSpeed signal. */ + kPGMC_HighSpeedSignal = 3U, /*!< MIF HighSpeed signal. */ + kPGMC_StandbySignal = 4U, /*!< MIF Standby signal. */ + kPGMC_ArrayPowerDownSignal = 5U, /*!< MIF ArrayPowerDown signal. */ + kPGMC_PeripheralPowerDownSignal = 6U, /*!< MIF PeripheralPowerDown signal. */ + kPGMC_InitnSignal = 7U, /*!< MIF Initn signal. */ + kPGMC_Switch1OffSignal = 8U, /*!< MIF Switch1Off signal. */ + kPGMC_Switch2OffSignal = 9U, /*!< MIF Switch2Off signal. */ + kPGMC_IsoSignal = 10U, /*!< MIF Iso_en signal. */ +} pgmc_mif_signal_t; + +/*! + * @brief The control option of the power domain controlled by CPU power mode. + */ +typedef struct _pgmc_bpc_cpu_power_mode_option +{ + pgmc_bpc_assign_domain_t assignDomain; /*!< Domain assignment of the BPC. The power mode of the selected core domain + will control the selected power domain. */ + bool stateSave; /*!< Request save the state of power domain before entering target power mode. + - \b true Save data when domain enter the selected mode. + - \b false Do not save data when domain enter the selected mode. */ + bool powerOff; /*!< Request power off the power domain. + - \b true Power off the power domain when enter the selected mode. + - \b false Do not power off the power domain when enter the selected mode. */ +} pgmc_bpc_cpu_power_mode_option_t; + +/*! + * @brief The control option of the power domain controlled by setpoint mode. + */ +typedef struct _pgmc_bpc_setpoint_mode_option +{ + bool stateSave; /*!< Request save the state of power domain before entering target setpoint. + - \b true Save data when domain enter the selected setpoint. + - \b false Do not save data when domain enter the selected setpoint. */ + bool powerOff; /*!< Request power off the power domain. + - \b true Power off the power domain when enter the selected setpoint. + - \b false Do not power off the power domain when enter the selected setpoint. */ +} pgmc_bpc_setpoint_mode_option_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Basic Power Controller Related Interfaces + * @{ + */ + +/*! + * @brief Makes the BPC module controlled by the target CPU power mode, such as Wait mode. + * + * This function makes the module controlled by four typical CPU power modes, It also configs the resource domain and + * set memory low power level. + * + * @param base PGMC basic power controller base address. + * @param mode Target CPU power mode. + * @param option The pointer of @ref pgmc_bpc_cpu_power_mode_option_t structure. + */ +void PGMC_BPC_ControlPowerDomainByCpuPowerMode(PGMC_BPC_Type *base, + pgmc_cpu_mode_t mode, + const pgmc_bpc_cpu_power_mode_option_t *option); + +/*! + * @brief Makes the BPC module controlled by the target set points. + * + * This function makes the module controlled by specific set point, It also supports set memory lowe power level. + * + * @note When setting more than one set point, use "|" between the map values in @ref _pgmc_setpoint_map. + * + * @param base PGMC basic power controller base address. + * @param setPointMap Should be the OR'ed value of @ref _pgmc_setpoint_map. + * @param option The pointer of @ref pgmc_bpc_setpoint_mode_option_t structure. + */ +void PGMC_BPC_ControlPowerDomainBySetPointMode(PGMC_BPC_Type *base, + uint32_t setPointMap, + const pgmc_bpc_setpoint_mode_option_t *option); + +/*! + * @brief Controls the selected power domain by software mode. + * + * @note The function is used to control power domain when the CPU is in RUN mode. + * + * @param base PGMC basic power controller base address. + * @param powerOff Power On/Off power domain in software mode. + * - \b true Power off the power domain in software mode. + * - \b false Power on the power domain in software mode. + */ +void PGMC_BPC_ControlPowerDomainBySoftwareMode(PGMC_BPC_Type *base, bool powerOff); + +/*! + * @brief Disables low power mode control. + * + * @param base PGMC basic power controller base address. + */ +static inline void PGMC_BPC_DisableLowPower(PGMC_BPC_Type *base) +{ + base->BPC_MODE = PGMC_BPC_BPC_MODE_CTRL_MODE(kPGMC_DisableLowPowerControl); +} + +/*! + * @brief Requests power domain state restore at run mode. + * + * @param base PGMC basic power controller base address. + */ +static inline void PGMC_BPC_RequestStateRestoreAtRunMode(PGMC_BPC_Type *base) +{ + base->BPC_SSAR_RESTORE_CTRL |= PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_MASK; +} + +/*! + * @brief Requests power domain state restore when enters the selected set points. + * + * @note When setting more than one set point, use "|" between the map values in @ref _pgmc_setpoint_map. + * @param base PGMC basic power controller base address. + * @param setPointMap Should be the OR'ed value of @ref _pgmc_setpoint_map. + */ +static inline void PGMC_BPC_RequestStateRestoreAtSetPoint(PGMC_BPC_Type *base, uint32_t setPointMap) +{ + base->BPC_SSAR_RESTORE_CTRL |= PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP(setPointMap & 0xFFFFU); +} + +/*! + * @brief Allows user mode access or not for the BPC module. + * + * @note If locked access related settings, the setting via this function is useless. + * + * @param base PGMC basic power controller base address. + * @param enable Used to control whether allow user mode access. + * - \b true Allow both privilege and user mode to access CPU mode control registers. + * - \b false Allow only privilege mode to access CPU mode control registers. + */ +static inline void PGMC_BPC_AllowUserModeAccess(PGMC_BPC_Type *base, bool enable) +{ + if (enable) + { + base->BPC_AUTHEN_CTRL |= PGMC_BPC_BPC_AUTHEN_CTRL_USER_MASK; + } + else + { + base->BPC_AUTHEN_CTRL &= ~PGMC_BPC_BPC_AUTHEN_CTRL_USER_MASK; + } +} + +/*! + * @brief Allows non-secure mode access or not for the BPC module. + * + * @note If locked access related settings, the setting via this function is useless. + * + * @param base PGMC basic power controller base address. + * @param enable Used to control whether allow non-secure mode to access CPU mode control registers. + * - \b true Allow both secure and non-secure mode to access CPU mode control registers. + * - \b false Allow only secure mode to access CPU mode control registers. + */ +static inline void PGMC_BPC_AllowNonSecureModeAccess(PGMC_BPC_Type *base, bool enable) +{ + if (enable) + { + base->BPC_AUTHEN_CTRL |= PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_MASK; + } + else + { + base->BPC_AUTHEN_CTRL &= ~PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_MASK; + } +} + +/*! + * @brief Locks access related settings for the BPC module, including Secure access setting and user access setting. + * + * @note This function used to lock access related settings. After locked the related bit field + * can not be written unless POR. + * + * @param base PGMC basic power controller base address. + */ +static inline void PGMC_BPC_LockAccessSetting(PGMC_BPC_Type *base) +{ + base->BPC_AUTHEN_CTRL |= PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_MASK; +} + +/*! + * @brief Sets the corrsponding domain ID that can access CPU mode control registers for the BPC module. + * + * @note If locked the domain ID white list, the setting via this function is useless. + * + * @param base PGMC basic power controller base address. + * @param domainId Should be the OR'ed value of @ref pgmc_bpc_assign_domain_t. + */ +static inline void PGMC_BPC_SetDomainIdWhiteList(PGMC_BPC_Type *base, uint8_t domainId) +{ + base->BPC_AUTHEN_CTRL = (base->BPC_AUTHEN_CTRL & (~PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_MASK)) | + PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST(domainId); +} + +/*! + * @brief Locks the value of Domain ID white list for the BPC module. + * + * @note After locked the domain ID white list can not be written again unless POR. + * + * @param base PGMC basic power controller base address. + */ +static inline void PGMC_BPC_LockDomainIDWhiteList(PGMC_BPC_Type *base) +{ + base->BPC_AUTHEN_CTRL |= PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_MASK; +} + +/*! + * @brief Locks low power configuration fields for the BPC module. + * + * @note After locked the low power configurations fields can not be updated unless POR. + * + * @param base PGMC basic power controller base address. + */ +static inline void PGMC_BPC_LockLowPowerConfigurationFields(PGMC_BPC_Type *base) +{ + base->BPC_AUTHEN_CTRL |= PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_MASK; +} + +/*! + * @} + */ + +/*! + * @name CPU Power Controller Related Interfaces + * @{ + */ + +/*! + * @brief Powers off the CPC core module by the target CPU power mode, such as Wait mode. + * + * @param base CPC CORE module base address. + * @param mode Target CPU power mode. + */ +void PGMC_CPC_CORE_PowerOffByCpuPowerMode(PGMC_CPC_Type *base, pgmc_cpu_mode_t mode); + +/*! + * @brief Powers off/on the CPC core module by the software. + * + * @param base CPC CORE module base address. + * @param powerOff Used to power off/on the CPC core module. + * - \b true Power off the CPC core module. + * - \b false Power on the CPC core module. + */ +static inline void PGMC_CPC_CORE_PowerOffBySoftwareMode(PGMC_CPC_Type *base, bool powerOff) +{ + if (powerOff) + { + base->CPC_CORE_POWER_CTRL |= + (PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_MASK | PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_MASK); + } + else + { + base->CPC_CORE_POWER_CTRL |= + (PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_MASK | PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_MASK); + } +} + +/*! + * @brief Disables low power mode control, the CPU core will not be affected by any low power modes. + * + * @param base CPC CORE module base address. + */ +static inline void PGMC_CPC_CORE_DisableLowPower(PGMC_CPC_Type *base) +{ + base->CPC_CORE_MODE = PGMC_CPC_CPC_CORE_MODE_CTRL_MODE(kPGMC_DisableLowPowerControl); +} + +/*! + * @brief Makes the CPC CACHE module controlled by the target CPU power mode, such as Wait mode. + * + * This function makes the module controlled by four typical CPU power modes, it also can set memory low power level. + * + * @param base CPC CACHE module base address. + * @param mode Target CPU power mode. + * @param memoryLowPowerLevel Memory low power level. + */ +void PGMC_CPC_CACHE_ControlByCpuPowerMode(PGMC_CPC_Type *base, + pgmc_cpu_mode_t mode, + pgmc_memory_low_power_level_t memoryLowPowerLevel); + +/*! + * @brief Makes the CPC CACHE module controlled by the target set points. + * + * This function makes the module controlled by specific set point, It also supports set memory lowe power level. + * + * @note When setting more than one set point, use "|" between the map values in @ref _pgmc_setpoint_map. + * + * @param base CPC CACHE module base address. + * @param setPointMap Should be the OR'ed value of @ref _pgmc_setpoint_map. + * @param memoryLowPowerLevel Memory low power level. + */ +void PGMC_CPC_CACHE_ControlBySetPointMode(PGMC_CPC_Type *base, + uint32_t setPointMap, + pgmc_memory_low_power_level_t memoryLowPowerLevel); + +/*! + * @brief Disables low power mode control, so the cache will not be affected by any low power modes. + * + * @param base CPC CACHE module base address. + */ +static inline void PGMC_CPC_CACHE_DisableLowPower(PGMC_CPC_Type *base) +{ + base->CPC_CACHE_MODE = PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE(kPGMC_DisableLowPowerControl); +} + +/*! + * @brief Requests CPC cache module's memory low power level change by software mode. + * + * @note If request memory low power level change, must wait the MLPL transition complete. + * + * @param base CPC LMEM module base address. + */ +void PGMC_CPC_CACHE_TriggerMLPLSoftwareChange(PGMC_CPC_Type *base); + +/*! + * @brief Makes the CPC LMEM module controlled by the target CPU power mode, such as Wait mode. + * + * This function makes the module controlled by four typical CPU power modes, it also can set memory low power level. + * + * @param base CPC LMEM module base address. + * @param mode Target CPU power mode. + * @param memoryLowPowerLevel Memory low power level. + */ +void PGMC_CPC_LMEM_ControlByCpuPowerMode(PGMC_CPC_Type *base, + pgmc_cpu_mode_t mode, + pgmc_memory_low_power_level_t memoryLowPowerLevel); + +/*! + * @brief Makes the CPC LMEM module controlled by the target set points. + * + * This function makes the module controlled by specific set point, It also supports set memory lowe power level. + * + * @note When setting more than one set point, use "|" between the map values in @ref _pgmc_setpoint_map. + * + * @param base CPC LMEM module base address. + * @param setPointMap Should be the OR'ed value of @ref _pgmc_setpoint_map. + * @param memoryLowPowerLevel Memory low power level. + */ +void PGMC_CPC_LMEM_ControlBySetPointMode(PGMC_CPC_Type *base, + uint32_t setPointMap, + pgmc_memory_low_power_level_t memoryLowPowerLevel); + +/*! + * @brief Disables low power mode control, so that the CPC LMEM will not be affected by any low power modes. + * + * @param base CPC LMEM module base address. + */ +static inline void PGMC_CPC_LMEM_DisableLowPower(PGMC_CPC_Type *base) +{ + base->CPC_LMEM_MODE = PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE(kPGMC_DisableLowPowerControl); +} + +/*! + * @brief Requests CPC LMEM module's memory low power level change in software mode. + * + * @note If request memory low power level change, must wait the MLPL transition complete. + * + * @param base CPC LMEM module base address. + */ +void PGMC_CPC_LMEM_TriggerMLPLSoftwareChange(PGMC_CPC_Type *base); + +/*! + * @brief Allows user mode access or not for the CPC module. + * + * @note If locked access related settings, the setting via this function is useless. + * + * @param base CPC LMEM module base address. + * @param enable Used to control whether allow user mode access. + * - \b true Allow both privilege and user mode to access CPU mode control registers. + * - \b false Allow only privilege mode to access CPU mode control registers. + */ +static inline void PGMC_CPC_AllowUserModeAccess(PGMC_CPC_Type *base, bool enable) +{ + if (enable) + { + base->CPC_AUTHEN_CTRL |= PGMC_CPC_CPC_AUTHEN_CTRL_USER_MASK; + } + else + { + base->CPC_AUTHEN_CTRL &= ~PGMC_CPC_CPC_AUTHEN_CTRL_USER_MASK; + } +} + +/*! + * @brief Allows non-secure mode access or not for the CPC module. + * + * @note If locked access related settings, the setting via this function is useless. + * + * @param base CPC LMEM module base address. + * @param enable Used to control whether allow non-secure mode to access CPU mode control registers. + * - \b true Allow both secure and non-secure mode to access CPU mode control registers. + * - \b false Allow only secure mode to access CPU mode control registers. + */ +static inline void PGMC_CPC_AllowNonSecureModeAccess(PGMC_CPC_Type *base, bool enable) +{ + if (enable) + { + base->CPC_AUTHEN_CTRL |= PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_MASK; + } + else + { + base->CPC_AUTHEN_CTRL &= ~PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_MASK; + } +} + +/*! + * @brief Locks access related settings, including secure access setting and user access setting, for the CPC module. + * + * @note This function used to lock access related settings. After locked the related bit field + * can not be written unless POR. + * + * @param base CPC LMEM module base address. + */ +static inline void PGMC_CPC_LockAccessSetting(PGMC_CPC_Type *base) +{ + base->CPC_AUTHEN_CTRL |= PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_MASK; +} + +/*! + * @brief Sets the corrsponding domain ID that can access CPU mode control registers for the CPC module. + * + * @note If the domain ID whitelist is locked, the setting via this function is useless. + * + * @param base CPC LMEM module base address. + * @param domainId Should be the OR'ed value of @ref pgmc_bpc_assign_domain_t. + */ +static inline void PGMC_CPC_SetDomainIdWhiteList(PGMC_CPC_Type *base, uint8_t domainId) +{ + base->CPC_AUTHEN_CTRL = (base->CPC_AUTHEN_CTRL & (~PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_MASK)) | + PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST(domainId); +} + +/*! + * @brief Locks the value of Domain ID white list for CPC module. + * + * @note After locked the domain ID white list can not be written again unless POR. + * + * @param base CPC LMEM module base address. + */ +static inline void PGMC_CPC_LockDomainIDWhiteList(PGMC_CPC_Type *base) +{ + base->CPC_AUTHEN_CTRL |= PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_MASK; +} + +/*! + * @brief Locks CPC realted low power configuration fields for CPC module. + * + * @note After locked the low power configurations fields can not be updated unless POR. + * + * @param base CPC LMEM module base address. + */ +static inline void PGMC_CPC_LockLowPowerConfigurationFields(PGMC_CPC_Type *base) +{ + base->CPC_AUTHEN_CTRL |= PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_MASK; +} + +/*! + * @} + */ + +/*! + * @name MIF Module Related APIs + * @{ + */ + +/*! + * @brief Sets the behaviour of each signal in MIF, such as Sleep signal. + * + * @note To control the memory low power operation, this function must be invoked after selecting the + * memory low power level. + * Use case: + * @code + * PGMC_BPC_ControlPowerDomainByCpuPowerMode(PGMC_BPC0_BASE, kPGMC_WaitMode, kPGMC_CM7Core, + * kPGMC_MLPLSleep, false); + * PGMC_MIF_SetSignalBehaviour(PGMC_BPC0_MIF_BASE, kPGMC_MLPLSleep, kPGMC_AssertSleepSignal); + * @endcode + * + * @param base PGMC MIF peripheral base address. + * @param memoryLevel The selected memory low power level. For details please refer to @ref + * pgmc_memory_low_power_level_t. + * @param mask The mask of MIF signal behaviour. Should be the OR'ed value of @ref _pgmc_mif_signal_behaviour + */ +void PGMC_MIF_SetSignalBehaviour(PGMC_MIF_Type *base, pgmc_memory_low_power_level_t memoryLevel, uint32_t mask); + +/*! + * @brief Locks MIF realted low power configuration fields for MIF module. + * + * @note After locked the low power configurations fields can not be updated unless POR. + * + * @param base PGMC MIF peripheral base address. + */ +static inline void PGMC_MIF_LockLowPowerConfigurationFields(PGMC_MIF_Type *base) +{ + base->MIF_AUTHEN_CTRL |= PGMC_MIF_MIF_AUTHEN_CTRL_LOCK_CFG_MASK; +} + +/*! @} */ + +/*! + * @name PMIC Power Related Interfaces + * @{ + */ + +/*! + * @brief Trigger PMIC standby ON/OFF. + * + * @param base PMIC module base address. + * @param enable Trigger on/off PMIC standby. + * - \b true Trigger PMIC standby ON. + * - \b false Trigger PMIC standby OFF. + */ +static inline void PGMC_PPC_TriggerPMICStandbySoftMode(PGMC_PPC_Type *base, bool enable) +{ + if (enable) + { + PGMC_PPC0->PPC_STBY_CM_CTRL |= PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT_MASK; + } + else + { + PGMC_PPC0->PPC_STBY_CM_CTRL |= PGMC_PPC_PPC_STBY_CM_CTRL_STBY_OFF_SOFT_MASK; + } +} + +/*! + * @brief Makes the PMIC module controlled by the target CPU power mode, such as Wait mode. + * + * @param base PMIC module base address. + * @param mode Target CPU power mode. + */ +void PGMC_PPC_ControlByCpuPowerMode(PGMC_PPC_Type *base, pgmc_cpu_mode_t mode); + +/*! + * @brief Makes the PMIC module controlled by the target set points. + * + * This function makes the module controlled by specific set point, It also supports PMIC standby on. + * + * @note When setting more than one set point, use "|" between the map values in @ref _pgmc_setpoint_map. + * + * @param base PMIC module base address. + * @param setPointMap Should be the OR'ed value of @ref _pgmc_setpoint_map. + * @param enableStandby true: PMIC standby on when system enters set point number and system is in standby mode. + * false: PMIC standby on when system enters set point number + */ +void PGMC_PPC_ControlBySetPointMode(PGMC_PPC_Type *base, uint32_t setPointMap, bool enableStandby); + +/*! + * @brief Disables low power mode control. + * + * @param base PMIC module bsase address. + */ +static inline void PGMC_PPC_DisableLowPower(PGMC_PPC_Type *base) +{ + base->PPC_MODE = PGMC_PPC_PPC_MODE_CTRL_MODE(kPGMC_DisableLowPowerControl); +} + +/*! + * @brief Allows user mode access or not for PMIC module. + * + * @note If locked access related settings, the setting via this function is useless. + * + * @param base PMIC module base address. + * @param enable Used to control whether allow user mode access. + * - \b true Allow both privilege and user mode to access CPU mode control registers. + * - \b false Allow only privilege mode to access CPU mode control registers. + */ +static inline void PGMC_PPC_AllowUserModeAccess(PGMC_PPC_Type *base, bool enable) +{ + if (enable) + { + base->PPC_AUTHEN_CTRL |= PGMC_PPC_PPC_AUTHEN_CTRL_USER_MASK; + } + else + { + base->PPC_AUTHEN_CTRL &= ~PGMC_PPC_PPC_AUTHEN_CTRL_USER_MASK; + } +} + +/*! + * @brief Allows non-secure mode access or not for the PMIC module. + * + * @note If locked access related settings, the setting via this function is useless. + * + * @param base PMIC module base address. + * @param enable Used to control whether allow non-secure mode to access CPU mode control registers. + * - \b true Allow both secure and non-secure mode to access CPU mode control registers. + * - \b false Allow only secure mode to access CPU mode control registers. + */ +static inline void PGMC_PPC_AllowNonSecureModeAccess(PGMC_PPC_Type *base, bool enable) +{ + if (enable) + { + base->PPC_AUTHEN_CTRL |= PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE_MASK; + } + else + { + base->PPC_AUTHEN_CTRL &= ~PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE_MASK; + } +} + +/*! + * @brief Locks access related settings, including secure access setting and user access setting, for the PMIC module. + * + * @note This function used to lock access related settings. After locked the related bit field + * can not be written unless POR. + * + * @param base PMIC module base address. + */ +static inline void PGMC_PPC_LockAccessSetting(PGMC_PPC_Type *base) +{ + base->PPC_AUTHEN_CTRL |= PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_SETTING_MASK; +} + +/*! + * @brief Sets the corrsponding domain ID that can access CPU mode control registers for the PMIC module. + * + * @note If the domain ID whitelist is locked, the setting via this function is useless. + * + * @param base PMIC module base address. + * @param domainId Should be the OR'ed value of @ref pgmc_bpc_assign_domain_t. + */ +static inline void PGMC_PPC_SetDomainIdWhiteList(PGMC_PPC_Type *base, uint8_t domainId) +{ + base->PPC_AUTHEN_CTRL = (base->PPC_AUTHEN_CTRL & (~PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST_MASK)) | + PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST(domainId); +} + +/*! + * @brief Locks the value of Domain ID white list for the PMIC module. + * + * @note After locked the domain ID white list can not be written again unless POR. + * + * @param base PMIC module base address. + */ +static inline void PGMC_PPC_LockDomainIDWhiteList(PGMC_PPC_Type *base) +{ + base->PPC_AUTHEN_CTRL |= PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_LIST_MASK; +} + +/*! + * @brief Locks low power configuration fields for the PMIC module. + * + * @note After locked the low power configurations fields can not be updated unless POR. + * + * @param base PMIC module base address. + */ +static inline void PGMC_PPC_LockLowPowerConfigurationFields(PGMC_PPC_Type *base) +{ + base->PPC_AUTHEN_CTRL |= PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_CFG_MASK; +} + +/*! + * @} + */ + +#if defined(__cplusplus) +} +#endif +/*! + * @} + */ +#endif /* _FSL_PGMC_H_ */ diff --git a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_pmu.c b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_pmu.c new file mode 100644 index 0000000000..3cf953f294 --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_pmu.c @@ -0,0 +1,959 @@ +/* + * Copyright 2020-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_pmu.h" +#include "fsl_anatop_ai.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.pmu_1" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define PMU_LDO_LPSR_DIG_TRG_SPX_REG_SETPOINT_COUNTS 4U +#define PMU_LDO_LPSR_DIG_TRG_SPX_VOLTAGE_SETPOINTX_BIT_WIDTH 8UL + +#define PMU_POWER_DETECT_CTRL_REGISTER (ANADIG_PMU->PMU_POWER_DETECT_CTRL) + +#define PMU_BIAS_CTRL_WB_CFG_1P8_WELL_SELECT_MASK (0x1U) + +#define PMU_BIAS_CTRL_WB_CFG_1P8_VOLTAGE_THRESHOLD_MASK (0x2U) +#define PMU_BIAS_CTRL_WB_CFG_1P8_VOLTAGE_THRESHOLD_SHIFT 1U +#define PMU_BIAS_CTRL_WB_CFG_1P8_VOLTAGE_THRESHOLD(x) \ + (((uint32_t)(((uint32_t)(x)) << PMU_BIAS_CTRL_WB_CFG_1P8_VOLTAGE_THRESHOLD_SHIFT)) & \ + PMU_BIAS_CTRL_WB_CFG_1P8_VOLTAGE_THRESHOLD_MASK) + +#define PMU_BIAS_CTRL_WB_CFG_1P8_DRIVE_STRENGTH_MASK (0x1CU) +#define PMU_BIAS_CTRL_WB_CFG_1P8_DRIVE_STRENGTH_SHIFT 2U +#define PMU_BIAS_CTRL_WB_CFG_1P8_DRIVE_STRENGTH(x) \ + (((uint32_t)(((uint32_t)(x)) << PMU_BIAS_CTRL_WB_CFG_1P8_DRIVE_STRENGTH_SHIFT)) & \ + PMU_BIAS_CTRL_WB_CFG_1P8_DRIVE_STRENGTH_MASK) + +#define PMU_BIAS_CTRL_WB_CFG_1P8_OSCILLATOR_FREQ_MASK (0x1E0U) +#define PMU_BIAS_CTRL_WB_CFG_1P8_OSCILLATOR_FREQ_SHIFT 5U +#define PMU_BIAS_CTRL_WB_CFG_1P8_OSCILLATOR_FREQ(x) \ + (((uint32_t)(((uint32_t)(x)) << PMU_BIAS_CTRL_WB_CFG_1P8_OSCILLATOR_FREQ_SHIFT)) & \ + PMU_BIAS_CTRL_WB_CFG_1P8_OSCILLATOR_FREQ_MASK) + +#define PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(member) \ + ((uint32_t)((ANADIG_PMU_BASE) + (uint32_t)offsetof(ANADIG_PMU_Type, member))) + +#define PMU_LDO_ENABLE_SETPOINT_REGISTERS \ + { \ + PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_PLL_ENABLE_SP), \ + PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_ANA_ENABLE_SP), \ + PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_DIG_ENABLE_SP), 0UL \ + } + +#define PMU_LDO_LP_MODE_EN_SETPOINT_REGISTERS \ + { \ + 0UL, PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_ANA_LP_MODE_SP), \ + PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_DIG_LP_MODE_SP), 0UL \ + } + +#define PMU_LDO_TRACKING_EN_SETPOINT_REGISTERS \ + { \ + 0UL, PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_ANA_TRACKING_EN_SP), \ + PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_DIG_TRACKING_EN_SP), 0UL \ + } + +#define PMU_LDO_BYPASS_EN_SETPOINT_REGISTERS \ + { \ + 0UL, PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_ANA_BYPASS_EN_SP), \ + PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_DIG_BYPASS_EN_SP), 0UL \ + } + +#define PMU_LDO_STBY_EN_REGISTERS \ + { \ + PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(PLL_LDO_STBY_EN_SP), \ + PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_ANA_STBY_EN_SP), \ + PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_DIG_STBY_EN_SP), 0UL \ + } + +#define PMU_LPSR_DIG_TRG_REGISTERS \ + { \ + PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_DIG_TRG_SP0), \ + PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_DIG_TRG_SP1), \ + PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_DIG_TRG_SP2), \ + PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_DIG_TRG_SP3) \ + } + +#if (defined(PMU_HAS_FBB) && PMU_HAS_FBB) +#define PMU_BODY_BIAS_ENABLE_REGISTERS \ + { \ + PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(FBB_M7_ENABLE_SP), PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(RBB_SOC_ENABLE_SP), \ + PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(RBB_LPSR_ENABLE_SP) \ + } +#else +#define PMU_BODY_BIAS_ENABLE_REGISTERS \ + { \ + PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(RBB_SOC_ENABLE_SP), PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(RBB_LPSR_ENABLE_SP) \ + } +#endif /* PMU_HAS_FBB */ + +#if (defined(PMU_HAS_FBB) && PMU_HAS_FBB) +#define PMU_BODY_BIAS_STBY_EN_REGISTERS \ + { \ + PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(FBB_M7_STBY_EN_SP), PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(RBB_SOC_STBY_EN_SP), \ + PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(RBB_LPSR_STBY_EN_SP) \ + } +#else +#define PMU_BODY_BIAS_STBY_EN_REGISTERS \ + { \ + PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(RBB_SOC_STBY_EN_SP), PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(RBB_LPSR_STBY_EN_SP) \ + } +#endif /* PMU_HAS_FBB */ + +#if (defined(PMU_HAS_FBB) && PMU_HAS_FBB) +#define PMU_BODY_BIAS_CONFIGURE_REGISTERS \ + { \ + PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(FBB_M7_CONFIGURE), PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(RBB_SOC_CONFIGURE), \ + PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(RBB_LPSR_CONFIGURE) \ + } +#else +#define PMU_BODY_BIAS_CONFIGURE_REGISTERS \ + { \ + PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(RBB_SOC_CONFIGURE), PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(RBB_LPSR_CONFIGURE) \ + } +#endif /* PMU_HAS_FBB */ +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Selects the control mode of the PLL LDO. + * + * param base PMU peripheral base address. + * param mode The control mode of the PLL LDO. Please refer to pmu_control_mode_t. + */ +void PMU_SetPllLdoControlMode(ANADIG_PMU_Type *base, pmu_control_mode_t mode) +{ + if (mode == kPMU_StaticMode) + { + base->PMU_LDO_PLL &= ~ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK; + } + else + { + base->PMU_LDO_PLL |= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK; + } +} + +/*! + * brief Switches the PLL LDO from Static/Software Mode to GPC/Hardware Mode. + * + * param base PMU peripheral base address. + */ +void PMU_SwitchPllLdoToGPCMode(ANADIG_PMU_Type *base) +{ + if ((base->LDO_PLL_ENABLE_SP & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0_MASK) != 0UL) + { + base->PMU_LDO_PLL |= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_MASK; + } + else + { + base->PMU_LDO_PLL &= ~ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_MASK; + } +} + +/*! + * brief Enables PLL LDO via AI interface in Static/Software mode. + * + * param base PMU peripheral base address. + */ +void PMU_StaticEnablePllLdo(ANADIG_PMU_Type *base) +{ + uint32_t temp32; + + temp32 = ANATOP_AI_Read(kAI_Itf_Ldo, kAI_PHY_LDO_CTRL0); + + if (temp32 != + (AI_PHY_LDO_CTRL0_OUTPUT_TRG(0x10) | AI_PHY_LDO_CTRL0_LINREG_EN_MASK | AI_PHY_LDO_CTRL0_LIMIT_EN_MASK)) + { + ANATOP_AI_Write( + kAI_Itf_Ldo, kAI_PHY_LDO_CTRL0, + (AI_PHY_LDO_CTRL0_OUTPUT_TRG(0x10) | AI_PHY_LDO_CTRL0_LINREG_EN_MASK | AI_PHY_LDO_CTRL0_LIMIT_EN_MASK)); + SDK_DelayAtLeastUs(1, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + + /* Enable Voltage Reference for PLLs before those PLLs were enabled. */ + base->PMU_REF_CTRL |= ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER_MASK; + } +} + +/*! + * brief Disables PLL LDO via AI interface in Static/Software mode. + */ +void PMU_StaticDisablePllLdo(void) +{ + ANATOP_AI_Write(kAI_Itf_Ldo, kAI_PHY_LDO_CTRL0, 0UL); +} + +/*! + * brief Selects the control mode of the LPSR ANA LDO. + * + * param base PMU peripheral base address. + * param mode The control mode of the LPSR ANA LDO. Please refer to pmu_control_mode_t. + */ +void PMU_SetLpsrAnaLdoControlMode(ANADIG_LDO_SNVS_Type *base, pmu_control_mode_t mode) +{ + if (mode == kPMU_StaticMode) + { + base->PMU_LDO_LPSR_ANA &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE_MASK; + } + else + { + base->PMU_LDO_LPSR_ANA |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE_MASK; + } +} + +/*! + * brief Sets the Bypass mode of the LPSR ANA LDO. + * + * param base ANADIG_LDO_SNVS peripheral base address. + * param enable Enable/Disable bypass mode. + * - \b true Enable LPSR ANA Bypass mode. + * - \b false Disable LPSR ANA Bypass mode. + */ +void PMU_StaticEnableLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS_Type *base, bool enable) +{ + if (enable == false) + { + /* Enable LPSR ANA LDO and HP mode. */ + base->PMU_LDO_LPSR_ANA &= + ~(ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_MASK | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_MASK); + SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + + /* Clear Bypass. */ + base->PMU_LDO_LPSR_ANA &= ~(ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK); + SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + + /* Disable Tracking mode. */ + base->PMU_LDO_LPSR_ANA &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_MASK; + } + else + { + /* Enable HP mode. */ + base->PMU_LDO_LPSR_ANA &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_MASK; + SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + + /* Enable Tracking mode. */ + base->PMU_LDO_LPSR_ANA |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_MASK; + SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + + /* Enabled Bypass. */ + base->PMU_LDO_LPSR_ANA |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK; + SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + + /* Disable LPSR ANA LDO. */ + base->PMU_LDO_LPSR_ANA |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_MASK; + } +} + +/*! + * brief Fill the LPSR ANA LDO configuration structure with default settings. + * + * The default values are: + * code + * config->mode = kPMU_HighPowerMode; + config->enable2mALoad = true; + config->enable20uALoad = false; + config->enable4mALoad = true; + config->enableStandbyMode = false; + config->driverStrength = kPMU_LpsrAnaLdoDriverStrength0; + config->brownOutDetectorConfig = kPMU_LpsrAnaLdoBrownOutDetectorDisable; + config->chargePumpCurrent = kPMU_LpsrAnaChargePump300nA; + config->outputRange = kPMU_LpsrAnaLdoOutputFrom1P77To1P83; + * endcode + * + * param config Pointer to the structure pmu_static_lpsr_ana_ldo_config_t. Please refer to @ref + * pmu_static_lpsr_ana_ldo_config_t. + */ +void PMU_StaticGetLpsrAnaLdoDefaultConfig(pmu_static_lpsr_ana_ldo_config_t *config) +{ + assert(config != NULL); + + (void)memset(config, 0, sizeof(*config)); + + config->mode = kPMU_HighPowerMode; + config->enable2mALoad = true; + config->enable20uALoad = false; + config->enable4mALoad = true; + config->enableStandbyMode = false; +} + +/*! + * brief Initialize the LPSR ANA LDO in Static/Sofware Mode. + * + * param base ANADIG_LDO_SNVS peripheral base address. + * param config Pointer to the structure pmu_static_lpsr_ana_ldo_config_t. Please refer to @ref + * pmu_static_lpsr_ana_ldo_config_t. + */ +void PMU_StaticLpsrAnaLdoInit(ANADIG_LDO_SNVS_Type *base, const pmu_static_lpsr_ana_ldo_config_t *config) +{ + assert(config != NULL); + + uint32_t regValue = base->PMU_LDO_LPSR_ANA; + + regValue &= + ~(ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_MASK | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN_MASK | + ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN_MASK | + ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN_MASK | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN_MASK); + + if ((config->mode) == kPMU_LowPowerMode) + { + regValue |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_MASK; + } + regValue |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN(config->enable2mALoad); + regValue |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN(config->enable4mALoad); + regValue |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN(config->enable20uALoad); + regValue |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN(config->enableStandbyMode); + + base->PMU_LDO_LPSR_ANA = regValue; + + /* Enable LPSR ANA DIG. */ + base->PMU_LDO_LPSR_ANA &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_MASK; +} + +/*! + * brief Disable the output of LPSR ANA LDO. + * + * param base ANADIG_LDO_SNVS peripheral base address. + */ +void PMU_StaticLpsrAnaLdoDeinit(ANADIG_LDO_SNVS_Type *base) +{ + /* Disable LPSR ANA LDO. */ + base->PMU_LDO_LPSR_ANA |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_MASK; +} + +/*! + * brief Selects the control mode of the LPSR DIG LDO. + * + * param base ANADIG_LDO_SNVS peripheral base address. + * param mode The control mode of the LPSR DIG LDO. Please refer to pmu_control_mode_t. + */ +void PMU_SetLpsrDigLdoControlMode(ANADIG_LDO_SNVS_Type *base, pmu_control_mode_t mode) +{ + if (mode == kPMU_StaticMode) + { + base->PMU_LDO_LPSR_DIG &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE_MASK; + } + else + { + base->PMU_LDO_LPSR_DIG |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE_MASK; + } +} + +/*! + * brief Turn on/off Bypass mode of the LPSR DIG LDO in Static/Software mode. + * + * param base ANADIG_LDO_SNVS peripheral base address. + * param enable + * true - Turn on Bypass mode of the LPSR DIG LDO. + * false - Turn off Bypass mode of the LPSR DIG LDO. + */ +void PMU_StaticEnableLpsrDigLdoBypassMode(ANADIG_LDO_SNVS_Type *base, bool enable) +{ + if (enable) + { + /* tracking */ + base->PMU_LDO_LPSR_DIG |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_MASK; + SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + + /* set BYPASS */ + base->PMU_LDO_LPSR_DIG |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK; + SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + + /* Disable LPSR DIG LDO */ + base->PMU_LDO_LPSR_DIG &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_MASK; + } + else + { + /* Enable LPSR DIG LDO and HP mode */ + base->PMU_LDO_LPSR_DIG |= (ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_MASK); + SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + + /* Clear BYPASS */ + base->PMU_LDO_LPSR_DIG &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK; + SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + + /* Disable tracking */ + base->PMU_LDO_LPSR_DIG &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_MASK; + } +} + +/*! + * @brief Gets the default configuration of LPSR DIG LDO. + * + * @param config Pointer to the structure pmu_static_lpsr_dig_config_t. Please refer to @ref + * pmu_static_lpsr_dig_config_t. + */ +void PMU_StaticGetLpsrDigLdoDefaultConfig(pmu_static_lpsr_dig_config_t *config) +{ + assert(config != NULL); + + (void)memset(config, 0, sizeof(*config)); + + config->voltageStepTime = kPMU_LpsrDigVoltageStepInc50us; + config->targetVoltage = kPMU_LpsrDigTargetStableVoltage1P0V; +} + +/*! + * @brief Initialize the LPSR DIG LDO in static mode. + * + * @param base ANADIG_LDO_SNVS peripheral base address. + * @param config Pointer to the structure pmu_static_lpsr_dig_config_t. Please refer to @ref + * pmu_static_lpsr_dig_config_t. + */ +void PMU_StaticLpsrDigLdoInit(ANADIG_LDO_SNVS_Type *base, const pmu_static_lpsr_dig_config_t *config) +{ + assert(config != NULL); + + uint32_t temp32 = base->PMU_LDO_LPSR_DIG; + + temp32 &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_MASK; + temp32 |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT(config->targetVoltage); + base->PMU_LDO_LPSR_DIG = temp32; + + temp32 = base->PMU_LDO_LPSR_DIG_2; + temp32 &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC_MASK; + temp32 |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC(config->voltageStepTime); + base->PMU_LDO_LPSR_DIG_2 = temp32; + + /* Enable LPSR DIG LDO. */ + base->PMU_LDO_LPSR_DIG |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_MASK; + SDK_DelayAtLeastUs(125U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + PMU_POWER_DETECT_CTRL_REGISTER |= ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0_MASK; +} + +/*! + * @brief Disable the LPSR DIG LDO. + * + * @param base ANADIG_LDO_SNVS peripheral base address. + */ +void PMU_StaticLpsrDigLdoDeinit(ANADIG_LDO_SNVS_Type *base) +{ + PMU_POWER_DETECT_CTRL_REGISTER &= ~ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0_MASK; + base->PMU_LDO_LPSR_DIG &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_MASK; +} + +/*! + * brief Sets the voltage step of LPSR DIG LDO in the certain setpoint during GPC mode. + * + * note The function provides the feature to set the voltage step to the different setpoints. + * + * param setpointMap The map of setpoints should be the OR'ed Value of _pmu_setpoint_map. + * param voltageStep The voltage step to be set. + */ +void PMU_GPCSetLpsrDigLdoTargetVoltage(uint32_t setpointMap, pmu_lpsr_dig_target_output_voltage_t voltageValue) +{ + uint32_t regValue = 0UL; + const uint32_t lpsrDigTrgRegArray[] = PMU_LPSR_DIG_TRG_REGISTERS; + uint8_t regIndex; + uint8_t temp8; + uint32_t i; + + for (regIndex = 0U; regIndex < ARRAY_SIZE(lpsrDigTrgRegArray); regIndex++) + { + temp8 = (((uint8_t)(setpointMap >> (PMU_LDO_LPSR_DIG_TRG_SPX_REG_SETPOINT_COUNTS * regIndex))) & 0xFU); + if (temp8 != 0UL) + { + regValue = (*(volatile uint32_t *)lpsrDigTrgRegArray[regIndex]); + for (i = 0U; i < PMU_LDO_LPSR_DIG_TRG_SPX_REG_SETPOINT_COUNTS; i++) + { + if (((temp8 >> (1U * i)) & 0x1U) != 0U) + { + regValue &= ~(0xFFUL << (PMU_LDO_LPSR_DIG_TRG_SPX_VOLTAGE_SETPOINTX_BIT_WIDTH * i)); + regValue |= (uint32_t)voltageValue << (PMU_LDO_LPSR_DIG_TRG_SPX_VOLTAGE_SETPOINTX_BIT_WIDTH * i); + } + } + (*(volatile uint32_t *)lpsrDigTrgRegArray[regIndex]) = regValue; + } + } +} + +/*! + * brief Gets the default config of the SNVS DIG LDO. + * + * The default values are: + * code + * config->mode = kPMU_LowPowerMode; + * config->chargePumpCurrent = kPMU_SnvsDigChargePump12P5nA; + * config->dischargeResistorValue = kPMU_SnvsDigDischargeResistor15K; + * config->trimValue = 0U; + * config->enablePullDown = true; + * config->enableLdoStable = false; + * endcode + * + * param config Pointer to the structure pmu_snvs_dig_config_t. Please refer to pmu_snvs_dig_config_t. + */ +void PMU_GetSnvsDigLdoDefaultConfig(pmu_snvs_dig_config_t *config) +{ + assert(config != NULL); + + (void)memset(config, 0, sizeof(*config)); + + config->mode = kPMU_LowPowerMode; + config->chargePumpCurrent = kPMU_SnvsDigChargePump12P5nA; + config->dischargeResistorValue = kPMU_SnvsDigDischargeResistor15K; + config->trimValue = 0U; + config->enablePullDown = true; + config->enableLdoStable = false; +} + +/*! + * brief Initialize the SNVS DIG LDO. + * + * param base LDO SNVS DIG peripheral base address. + * param mode Used to control LDO power mode, please refer to pmu_ldo_operate_mode_t. + */ +void PMU_SnvsDigLdoInit(ANADIG_LDO_SNVS_DIG_Type *base, pmu_ldo_operate_mode_t mode) +{ + uint32_t temp32 = base->PMU_LDO_SNVS_DIG; + + temp32 &= ~(ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN_MASK); + + temp32 |= (ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN(mode) | ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN_MASK); + + base->PMU_LDO_SNVS_DIG = temp32; +} + +/*! + * brief Controls the ON/OFF of the selected LDO in the certain setpoints with GPC mode. + * + * param name The name of the selected ldo. Please see the enumeration pmu_ldo_name_t for details. + * param setpointMap The map of setpoints should be the OR'ed Value of @ref _pmu_setpoint_map, 1b'1 + * means enable specific ldo in that setpoint. + * For example, the code PMU_GPCEnableLdo(kPMU_PllLdo, 0x1U) means enable PLL LDO in setpoint 0, disable + * PLL LDO in other setpoint. + */ +void PMU_GPCEnableLdo(pmu_ldo_name_t name, uint32_t setpointMap) +{ + assert(name != kPMU_SnvsDigLdo); + + uint32_t ldoEnableRegArray[] = PMU_LDO_ENABLE_SETPOINT_REGISTERS; + + (*(volatile uint32_t *)ldoEnableRegArray[(uint8_t)name]) = ~setpointMap; +} + +/*! + * brief Sets the operating mode of the selected LDO in the certain setpoints with GPC mode. + * + * param name The name of the selected ldo. Please see the enumeration pmu_ldo_name_t for details. + * param setpointMap The map of setpoints should be the OR'ed Value of _pmu_setpoint_map. + * param mode The operating mode of the selected ldo. Please refer to the enumeration pmu_ldo_operate_mode_t for + * details. + */ +void PMU_GPCSetLdoOperateMode(pmu_ldo_name_t name, uint32_t setpointMap, pmu_ldo_operate_mode_t mode) +{ + assert(name > kPMU_PllLdo); + assert(name < kPMU_SnvsDigLdo); + + uint32_t ldoLpModeRegArray[] = PMU_LDO_LP_MODE_EN_SETPOINT_REGISTERS; + + if (mode == kPMU_LowPowerMode) + { + (*(volatile uint32_t *)ldoLpModeRegArray[(uint8_t)name]) &= ~setpointMap; + } + else + { + (*(volatile uint32_t *)ldoLpModeRegArray[(uint8_t)name]) |= setpointMap; + } +} + +/*! + * brief Controls the ON/OFF of the selected LDOs' Tracking mode in the certain setpoints with GPC mode. + * + * param name The name of the selected ldo. Please see the enumeration pmu_ldo_name_t for details. + * param setpointMap The map of setpoints that the LDO tracking mode will be enabled in those setpoints, this value + * should be the OR'ed Value of @ref _pmu_setpoint_map. + */ +void PMU_GPCEnableLdoTrackingMode(pmu_ldo_name_t name, uint32_t setpointMap) +{ + assert(name > kPMU_PllLdo); + assert(name < kPMU_SnvsDigLdo); + + uint32_t ldoTrackingEnableRegArray[] = PMU_LDO_TRACKING_EN_SETPOINT_REGISTERS; + + (*(volatile uint32_t *)ldoTrackingEnableRegArray[(uint8_t)name]) = setpointMap; +} + +/*! + * brief Controls the ON/OFF of the selected LDOs' Bypass mode in the certain setpoints with GPC mode. + * + * param name The name of the selected ldo. Please see the enumeration pmu_ldo_name_t for details. + * param setpointMap The map of setpoints that the LDO bypass mode will be enabled in those setpoints, this value + * should be the OR'ed Value of @ref _pmu_setpoint_map. + */ +void PMU_GPCEnableLdoBypassMode(pmu_ldo_name_t name, uint32_t setpointMap) +{ + assert(name > kPMU_PllLdo); + assert(name < kPMU_SnvsDigLdo); + + uint32_t ldoBypassEnableRegArray[] = PMU_LDO_BYPASS_EN_SETPOINT_REGISTERS; + + (*(volatile uint32_t *)ldoBypassEnableRegArray[(uint8_t)name]) = setpointMap; +} + +/*! + * brief When STBY assert, enable/disable the selected LDO enter it's Low power mode. + * + * param name The name of the selected ldo. Please see the enumeration pmu_ldo_name_t for details. + * param setpointMap The map of setpoints that the LDO low power mode will be enabled in those setpoints if STBY + * assert, this value should be the OR'ed Value of @ref _pmu_setpoint_map. + */ +void PMU_GPCEnableLdoStandbyMode(pmu_ldo_name_t name, uint32_t setpointMap) +{ + assert(name != kPMU_SnvsDigLdo); + + uint32_t ldoStandbyEnableRegArray[] = PMU_LDO_STBY_EN_REGISTERS; + + (*(volatile uint32_t *)ldoStandbyEnableRegArray[(uint8_t)name]) = setpointMap; +} + +/*! + * brief Selects the control mode of the Bandgap Reference. + * + * param base PMU peripheral base address. + * param mode The control mode of the Bandgap Reference. Please refer to pmu_control_mode_t. + */ +void PMU_SetBandgapControlMode(ANADIG_PMU_Type *base, pmu_control_mode_t mode) +{ + if (mode == kPMU_StaticMode) + { + base->PMU_REF_CTRL &= ~ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_MASK; + } + else + { + base->PMU_REF_CTRL |= ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_MASK; + } +} + +/*! + * brief Switches the Bandgap from Static/Software Mode to GPC/Hardware Mode. + * + * param base PMU peripheral base address. + */ +void PMU_SwitchBandgapToGPCMode(ANADIG_PMU_Type *base) +{ + if ((base->BANDGAP_ENABLE_SP & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0_MASK) == 0UL) + { + base->PMU_REF_CTRL &= ~ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE_MASK; + } + else + { + base->PMU_REF_CTRL |= ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE_MASK; + } +} + +/*! + * brief Disables Bandgap self bias for best noise performance. + * + * This function waits for the bandgap to be stable and disables the bandgap self bias. + * After being powered up, it needs to wait for the bandgap stable to be stable and then disable Bandgap + * Self bias for best noise performance. + */ +void PMU_DisableBandgapSelfBiasAfterPowerUp(void) +{ + uint32_t temp32; + uint32_t regValue; + + /* Wait Bandgap stable. */ + do + { + regValue = ANATOP_AI_Read(kAI_Itf_Bandgap, kAI_BANDGAP_STAT0); + } while ((regValue & AI_BANDGAP_STAT0_REFTOP_VBGUP_MASK) == 0UL); + + /* Disable Bandgap self bias for best noise performance. */ + temp32 = ANATOP_AI_Read(kAI_Itf_Bandgap, kAI_BANDGAP_CTRL0); + temp32 |= AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK; + ANATOP_AI_Write(kAI_Itf_Bandgap, kAI_BANDGAP_CTRL0, temp32); +} + +/*! + * brief Enables Bandgap self bias before power down. + * + * This function will enable Bandgap self bias feature before powering down or there + * will be risk of Bandgap not starting properly. + */ +void PMU_EnableBandgapSelfBiasBeforePowerDown(void) +{ + uint32_t temp32; + + temp32 = ANATOP_AI_Read(kAI_Itf_Bandgap, kAI_BANDGAP_CTRL0); + temp32 &= ~AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK; + ANATOP_AI_Write(kAI_Itf_Bandgap, kAI_BANDGAP_CTRL0, temp32); +} + +/*! + * brief Init Bandgap. + * + * param config. Pointer to the structure pmu_static_bandgap_config_t. Please refer to pmu_static_bandgap_config_t. + */ +void PMU_StaticBandgapInit(const pmu_static_bandgap_config_t *config) +{ + assert(config != NULL); + + uint32_t temp32; + + temp32 = ANATOP_AI_Read(kAI_Itf_Bandgap, kAI_BANDGAP_CTRL0); + temp32 &= ~(AI_BANDGAP_CTRL0_REFTOP_PWD_MASK | AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK | + AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP_MASK | AI_BANDGAP_CTRL0_REFTOP_LOWPOWER_MASK | + AI_BANDGAP_CTRL0_REFTOP_VBGADJ_MASK | AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ_MASK); + temp32 |= ((uint32_t)(config->powerDownOption) & + (AI_BANDGAP_CTRL0_REFTOP_PWD_MASK | AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK | + AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP_MASK)); + temp32 |= AI_BANDGAP_CTRL0_REFTOP_LOWPOWER(config->enableLowPowerMode); + temp32 |= AI_BANDGAP_CTRL0_REFTOP_VBGADJ(config->outputVoltage); + temp32 |= AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ(config->outputCurrent); + + ANATOP_AI_Write(kAI_Itf_Bandgap, kAI_BANDGAP_CTRL0, temp32); +} + +/*! + * brief Configures Well bias, such as power source, clock source and so on. + * + * param base PMU peripheral base address. + * param config Pointer to the pmu_well_bias_config_t structure. + */ +void PMU_WellBiasInit(ANADIG_PMU_Type *base, const pmu_well_bias_config_t *config) +{ + assert(config != NULL); + + uint32_t tmp32; + + tmp32 = base->PMU_BIAS_CTRL; + tmp32 &= ~(ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_MASK | ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_MASK); + tmp32 |= ((uint32_t)config->wellBiasOption.wellBiasData & + (ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_MASK | ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_MASK)); + base->PMU_BIAS_CTRL = tmp32; + + tmp32 = base->PMU_BIAS_CTRL2; + tmp32 &= ~ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_MASK; + tmp32 |= ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8(config->adjustment); + base->PMU_BIAS_CTRL2 = tmp32; +} + +/*! + * brief Enables/disables the selected body bias. + * + * param base PMU peripheral base address. + * param name The name of the body bias to be turned on/off, please refer to pmu_body_bias_name_t. + * param enable Used to turn on/off the specific body bias. + * - \b true Enable the selected body bias. + * - \b false Disable the selected body bias. + */ +void PMU_GetWellBiasDefaultConfig(pmu_well_bias_config_t *config) +{ + assert(config != NULL); + + (void)memset(config, 0, sizeof(*config)); + + config->wellBiasOption.wellBiasData = 0U; + config->adjustment = kPMU_Cref0fFCspl0fFDeltaC0fF; +} + +/*! + * brief Selects the control mode of the Body Bias. + * + * param base PMU peripheral base address. + * param name The name of the body bias. Please refer to pmu_body_bias_name_t. + * param mode The control mode of the Body Bias. Please refer to pmu_control_mode_t. + */ +void PMU_SetBodyBiasControlMode(ANADIG_PMU_Type *base, pmu_body_bias_name_t name, pmu_control_mode_t mode) +{ + uint32_t temp32; + + switch (name) + { +#if (defined(PMU_HAS_FBB) && PMU_HAS_FBB) + case kPMU_FBB_CM7: + { + temp32 = base->PMU_BIAS_CTRL2; + temp32 &= ~ANADIG_PMU_PMU_BIAS_CTRL2_FBB_M7_CONTROL_MODE_MASK; + temp32 |= ANADIG_PMU_PMU_BIAS_CTRL2_FBB_M7_CONTROL_MODE(mode); + base->PMU_BIAS_CTRL2 = temp32; + break; + } +#endif /* PMU_HAS_FBB */ + case kPMU_RBB_SOC: + { + temp32 = base->PMU_BIAS_CTRL2; + temp32 &= ~ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE_MASK; + temp32 |= ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE(mode); + base->PMU_BIAS_CTRL2 = temp32; + break; + } + case kPMU_RBB_LPSR: + { + temp32 = base->PMU_BIAS_CTRL2; + temp32 &= ~ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE_MASK; + temp32 |= ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE(mode); + base->PMU_BIAS_CTRL2 = temp32; + break; + } + default: + /* This branch should never be hit. */ + break; + } +} + +/*! + * brief Enables/disables the selected body bias. + * + * param base PMU peripheral base address. + * param name The name of the body bias to be turned on/off, please refer to pmu_body_bias_name_t. + * param enable Used to turn on/off the specific body bias. + * - \b true Enable the selected body bias. + * - \b false Disable the selected body bias. + */ +void PMU_EnableBodyBias(ANADIG_PMU_Type *base, pmu_body_bias_name_t name, bool enable) +{ + uint32_t tmp32; + + if (enable) + { + switch (name) + { +#if (defined(PMU_HAS_FBB) && PMU_HAS_FBB) + case kPMU_FBB_CM7: + { + tmp32 = base->PMU_BIAS_CTRL; + tmp32 &= ~PMU_BIAS_CTRL_WB_CFG_1P8_WELL_SELECT_MASK; + tmp32 |= PMU_BIAS_CTRL_WB_CFG_1P8_VOLTAGE_THRESHOLD_MASK; + base->PMU_BIAS_CTRL = tmp32; + + tmp32 = base->PMU_BIAS_CTRL2; + tmp32 &= ~(ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK); + tmp32 |= ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8(1U) | ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK; + base->PMU_BIAS_CTRL2 = tmp32; + + while ((base->PMU_BIAS_CTRL2 & ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK) != + ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK) + { + } + break; + } +#endif /* PMU_HAS_FBB */ + case kPMU_RBB_SOC: + { + tmp32 = base->PMU_BIAS_CTRL; + tmp32 &= ~(PMU_BIAS_CTRL_WB_CFG_1P8_WELL_SELECT_MASK | PMU_BIAS_CTRL_WB_CFG_1P8_VOLTAGE_THRESHOLD_MASK); + base->PMU_BIAS_CTRL = tmp32; + + tmp32 = base->PMU_BIAS_CTRL2; + tmp32 &= ~(ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK); + tmp32 |= ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8(2U) | ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK; + base->PMU_BIAS_CTRL2 = tmp32; + while ((base->PMU_BIAS_CTRL2 & ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK) != + ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK) + { + } + break; + } + case kPMU_RBB_LPSR: + { + tmp32 = base->PMU_BIAS_CTRL; + tmp32 &= ~(PMU_BIAS_CTRL_WB_CFG_1P8_WELL_SELECT_MASK | PMU_BIAS_CTRL_WB_CFG_1P8_VOLTAGE_THRESHOLD_MASK); + base->PMU_BIAS_CTRL = tmp32; + + tmp32 = base->PMU_BIAS_CTRL2; + tmp32 &= ~(ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK); + tmp32 |= ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8(4U) | ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK; + base->PMU_BIAS_CTRL2 = tmp32; + while ((base->PMU_BIAS_CTRL2 & ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK) != + ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK) + { + } + break; + } + default: + /* This branch should never be hit. */ + break; + } + } + else + { + base->PMU_BIAS_CTRL2 &= + ~(ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK | ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK); + } +} + +/*! + * brief Controls the ON/OFF of the selected body bias in the certain setpoints with GPC mode. + * + * param name The name of the selected body bias. Please see the enumeration pmu_body_bias_name_t for details. + * param setpointMap The map of setpoints that the specific body bias will be enabled in those setpoints, this value + * should be the OR'ed Value of _pmu_setpoint_map. + */ +void PMU_GPCEnableBodyBias(pmu_body_bias_name_t name, uint32_t setpointMap) +{ + uint32_t bodyBiasEnableRegArray[] = PMU_BODY_BIAS_ENABLE_REGISTERS; + + (*(volatile uint32_t *)bodyBiasEnableRegArray[(uint8_t)name]) = ~setpointMap; +} + +/*! + * brief Controls the ON/OFF of the selected Body Bias' Wbias power switch in certain setpoints with GPC mode. + * + * param name The name of the selected body bias. Please see the enumeration pmu_body_bias_name_t for details. + * param setpointMap The map of setpoints that the specific body bias's wbias power switch will be turn on in those + * setpoints, this value should be the OR'ed Value of _pmu_setpoint_map. + */ +void PMU_GPCEnableBodyBiasStandbyMode(pmu_body_bias_name_t name, uint32_t setpointMap) +{ + uint32_t BBStandbyEnableRegArray[] = PMU_BODY_BIAS_STBY_EN_REGISTERS; + + (*(volatile uint32_t *)BBStandbyEnableRegArray[(uint8_t)name]) = setpointMap; +} + +/*! + * brief Gets the default config of body bias in GPC mode. + * + * param config Pointer to the structure pmu_gpc_body_bias_config_t. + */ +void PMU_GPCGetBodyBiasDefaultConfig(pmu_gpc_body_bias_config_t *config) +{ + assert(config != NULL); + + config->PWELLRegulatorSize = 1U; + config->NWELLRegulatorSize = 1U; + config->oscillatorSize = 7U; + config->regulatorStrength = 5U; +} + +/*! + * brief Sets the config of the selected Body Bias in GPC mode. + * + * param name The name of the selected body bias. Please see the enumeration pmu_body_bias_name_t for details. + * param config Pointer to the structure pmu_gpc_body_bias_config_t. + */ +void PMU_GPCSetBodyBiasConfig(pmu_body_bias_name_t name, const pmu_gpc_body_bias_config_t *config) +{ + assert(config != NULL); + + uint32_t bodyBiasConfigRegArray[] = PMU_BODY_BIAS_CONFIGURE_REGISTERS; + uint32_t temp32; + + temp32 = (*(volatile uint32_t *)bodyBiasConfigRegArray[(uint8_t)name]); + temp32 &= + (ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW_MASK | ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW_MASK | + ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS_MASK | ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH_MASK); + temp32 |= ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW(config->PWELLRegulatorSize) | + ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW(config->NWELLRegulatorSize) | + ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS(config->oscillatorSize) | + ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH(config->regulatorStrength); + (*(volatile uint32_t *)bodyBiasConfigRegArray[(uint8_t)name]) = temp32; +} diff --git a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_pmu.h b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_pmu.h new file mode 100644 index 0000000000..cd22e42d4f --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_pmu.h @@ -0,0 +1,855 @@ +/* + * Copyright 2020-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_PMU_H_ +#define _FSL_PMU_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup pmu + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version + * @{ + */ + +/*! @brief PMU driver version */ +#define FSL_PMU_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0. */ + +/*! + * @} + */ + +#if defined(ANADIG_PMU_PMU_BIAS_CTRL2_FBB_M7_CONTROL_MODE_MASK) +#define PMU_HAS_FBB (1U) +#else +#define PMU_HAS_FBB (0U) +#endif /* ANADIG_PMU_PMU_BIAS_CTRL2_FBB_M7_CONTROL_MODE_MASK */ + +/*! + * @brief System setpoints enumeration. + */ +enum _pmu_setpoint_map +{ + kPMU_SetPoint0 = 1UL << 0UL, /*!< Set point 0. */ + kPMU_SetPoint1 = 1UL << 1UL, /*!< Set point 1. */ + kPMU_SetPoint2 = 1UL << 2UL, /*!< Set point 2. */ + kPMU_SetPoint3 = 1UL << 3UL, /*!< Set point 3. */ + kPMU_SetPoint4 = 1UL << 4UL, /*!< Set point 4. */ + kPMU_SetPoint5 = 1UL << 5UL, /*!< Set point 5. */ + kPMU_SetPoint6 = 1UL << 6UL, /*!< Set point 6. */ + kPMU_SetPoint7 = 1UL << 7UL, /*!< Set point 7. */ + kPMU_SetPoint8 = 1UL << 8UL, /*!< Set point 8. */ + kPMU_SetPoint9 = 1UL << 9UL, /*!< Set point 9. */ + kPMU_SetPoint10 = 1UL << 10UL, /*!< Set point 10. */ + kPMU_SetPoint11 = 1UL << 11UL, /*!< Set point 11. */ + kPMU_SetPoint12 = 1UL << 12UL, /*!< Set point 12. */ + kPMU_SetPoint13 = 1UL << 13UL, /*!< Set point 13. */ + kPMU_SetPoint14 = 1UL << 14UL, /*!< Set point 14. */ + kPMU_SetPoint15 = 1UL << 15UL /*!< Set point 15. */ +}; + +/*! + * @brief The name of LDOs + */ +typedef enum _pmu_ldo_name +{ + kPMU_PllLdo = 0U, /*!< The PLL LDO in SOC domain. */ + kPMU_LpsrAnaLdo = 1U, /*!< The LPSR ANA LDO in LPSR domain. */ + kPMU_LpsrDigLdo = 2U, /*!< The LPSR DIG LDO in LPSR domain. */ + kPMU_SnvsDigLdo = 3U /*!< The SNVS DIG LDO in SNVS domain. */ +} pmu_ldo_name_t; + +/*! + * @brief The name of body bias. + */ +typedef enum _pmu_body_bias_name +{ +#if (defined(PMU_HAS_FBB) && PMU_HAS_FBB) + kPMU_FBB_CM7 = 0x0U, /*!< The FBB implemented in Cortex-M7 Platform. */ + kPMU_RBB_SOC = 0x1U, /*!< The RBB implemented in SOC. */ + kPMU_RBB_LPSR = 0x2U, /*!< The RBB implemented in LPSRMIX. */ +#else + kPMU_RBB_SOC = 0x0U, /*!< The RBB implemented in SOC. */ + kPMU_RBB_LPSR = 0x1U, /*!< The RBB implemented in LPSRMIX. */ +#endif /* PMU_HAS_FBB */ +} pmu_body_bias_name_t; + +/*! + * @brief The control mode of LDOs/Bandgaps/Body Bias. + */ +typedef enum _pmu_control_mode +{ + kPMU_StaticMode = 0U, /*!< Static/Software Control mode. */ + kPMU_GPCMode = 1U, /*!< GPC/Hardware Control mode. */ +} pmu_control_mode_t; + +/*! + * @brief The operation mode for the LDOs. + */ +typedef enum _pmu_ldo_operate_mode +{ + kPMU_LowPowerMode = 0x0U, /*!< LDOs operate in Low power mode. */ + kPMU_HighPowerMode = 0x1U, /*!< LDOs operate in High power mode. */ +} pmu_ldo_operate_mode_t; + +/*! + * @brief The enumeration of LPSR ANA LDO's charge pump current. + */ +typedef enum _pmu_lpsr_ana_ldo_charge_pump_current +{ + kPMU_LpsrAnaChargePump300nA = 0U, /*!< The current of the charge pump is selected as 300nA. */ + kPMU_LpsrAnaChargePump400nA = 1U, /*!< The current of the charge pump is selected as 400nA. */ + kPMU_LpsrAnaChargePump500nA = 2U, /*!< The current of the charge pump is selected as 500nA. */ + kPMU_LpsrAnaChargePump600nA = 3U, /*!< The current of the charge pump is selected as 600nA. */ +} pmu_lpsr_ana_ldo_charge_pump_current_t; + +/*! + * @brief The enumeration of LPSR ANA LDO's output range. + */ +typedef enum _pmu_lpsr_ana_ldo_output_range +{ + kPMU_LpsrAnaLdoOutputFrom1P77To1P83 = 0U, /*!< The output voltage varies from 1.77V to 1.83V. */ + kPMU_LpsrAnaLdoOutputFrom1P72To1P77 = 1U, /*!< The output voltage varies from 1.72V to 1.77V. */ + kPMU_LpsrAnaLdoOutputFrom1P82To1P88 = 2U, /*!< The output voltage varies from 1.82V to 1.88V. */ +} pmu_lpsr_ana_ldo_output_range_t; + +/*! + * @brief The enumeration of voltage step time for LPSR DIG LDO. + */ +typedef enum _pmu_lpsr_dig_voltage_step_time +{ + kPMU_LpsrDigVoltageStepInc15us = 0x0U, /*!< LPSR DIG LDO voltage step time selected as 15us. */ + kPMU_LpsrDigVoltageStepInc25us = 0x1U, /*!< LPSR DIG LDO voltage step time selected as 25us. */ + kPMU_LpsrDigVoltageStepInc50us = 0x2U, /*!< LPSR DIG LDO voltage step time selected as 50us. */ + kPMU_LpsrDigVoltageStepInc100us = 0x3U, /*!< LPSR DIG LDO voltage step time selected as 100us. */ +} pmu_lpsr_dig_voltage_step_time_t; + +/*! + * @brief The target output voltage of LPSR DIG LDO. + */ +typedef enum _pmu_lpsr_dig_target_output_voltage +{ + kPMU_LpsrDigTargetStableVoltage0P631V = 0x0U, /*!< The target voltage selected as 0.631V */ + kPMU_LpsrDigTargetStableVoltage0P65V = 0x1U, /*!< The target voltage selected as 0.65V */ + kPMU_LpsrDigTargetStableVoltage0P67V = 0x2U, /*!< The target voltage selected as 0.67V */ + kPMU_LpsrDigTargetStableVoltage0P689V = 0x3U, /*!< The target voltage selected as 0.689V */ + kPMU_LpsrDigTargetStableVoltage0P709V = 0x4U, /*!< The target voltage selected as 0.709V */ + kPMU_LpsrDigTargetStableVoltage0P728V = 0x5U, /*!< The target voltage selected as 0.728V */ + kPMU_LpsrDigTargetStableVoltage0P748V = 0x6U, /*!< The target voltage selected as 0.748V */ + kPMU_LpsrDigTargetStableVoltage0P767V = 0x7U, /*!< The target voltage selected as 0.767V */ + kPMU_LpsrDigTargetStableVoltage0P786V = 0x8U, /*!< The target voltage selected as 0.786V */ + kPMU_LpsrDigTargetStableVoltage0P806V = 0x9U, /*!< The target voltage selected as 0.806V */ + kPMU_LpsrDigTargetStableVoltage0P825V = 0xAU, /*!< The target voltage selected as 0.825V */ + kPMU_LpsrDigTargetStableVoltage0P845V = 0xBU, /*!< The target voltage selected as 0.845V */ + kPMU_LpsrDigTargetStableVoltage0P864V = 0xCU, /*!< The target voltage selected as 0.864V */ + kPMU_LpsrDigTargetStableVoltage0P883V = 0xDU, /*!< The target voltage selected as 0.883V */ + kPMU_LpsrDigTargetStableVoltage0P903V = 0xEU, /*!< The target voltage selected as 0.903V */ + kPMU_LpsrDigTargetStableVoltage0P922V = 0xFU, /*!< The target voltage selected as 0.922V */ + kPMU_LpsrDigTargetStableVoltage0P942V = 0x10U, /*!< The target voltage selected as 0.942V */ + kPMU_LpsrDigTargetStableVoltage0P961V = 0x11U, /*!< The target voltage selected as 0.961V */ + kPMU_LpsrDigTargetStableVoltage0P981V = 0x12U, /*!< The target voltage selected as 0.981V */ + kPMU_LpsrDigTargetStableVoltage1P0V = 0x13U, /*!< The target voltage selected as 1.0V */ + kPMU_LpsrDigTargetStableVoltage1P019V = 0x14U, /*!< The target voltage selected as 1.019V */ + kPMU_LpsrDigTargetStableVoltage1P039V = 0x15U, /*!< The target voltage selected as 1.039V */ + kPMU_LpsrDigTargetStableVoltage1P058V = 0x16U, /*!< The target voltage selected as 1.058V */ + kPMU_LpsrDigTargetStableVoltage1P078V = 0x17U, /*!< The target voltage selected as 1.078V */ + kPMU_LpsrDigTargetStableVoltage1P097V = 0x18U, /*!< The target voltage selected as 1.097V */ + kPMU_LpsrDigTargetStableVoltage1P117V = 0x19U, /*!< The target voltage selected as 1.117V */ + kPMU_LpsrDigTargetStableVoltage1P136V = 0x1AU, /*!< The target voltage selected as 1.136V */ + kPMU_LpsrDigTargetStableVoltage1P155V = 0x1BU, /*!< The target voltage selected as 1.155V */ + kPMU_LpsrDigTargetStableVoltage1P175V = 0x1CU, /*!< The target voltage selected as 1.175V */ + kPMU_LpsrDigTargetStableVoltage1P194V = 0x1DU, /*!< The target voltage selected as 1.194V */ + kPMU_LpsrDigTargetStableVoltage1P214V = 0x1EU, /*!< The target voltage selected as 1.214V */ + kPMU_LpsrDigTargetStableVoltage1P233V = 0x1FU, /*!< The target voltage selected as 1.233V */ +} pmu_lpsr_dig_target_output_voltage_t; + +/*! + * @brief The enumeration of the SNVS DIG LDO's charge pump current. + */ +typedef enum _pmu_snvs_dig_charge_pump_current +{ + kPMU_SnvsDigChargePump12P5nA = 0U, /*!< The current of SNVS DIG LDO's charge pump is selected as 12.5nA. */ + kPMU_SnvsDigChargePump6P25nA = 1U, /*!< The current of SNVS DIG LDO's charge pump is selected as 6.25nA. */ + kPMU_SnvsDigChargePump18P75nA = 2U, /*!< The current of SNVS DIG LDO's charge pump is selected as 18.75nA. */ +} pmu_snvs_dig_charge_pump_current_t; + +/*! + * @brief The enumeration of the SNVS DIG LDO's discharge resistor. + */ +typedef enum _pmu_snvs_dig_discharge_resistor_value +{ + kPMU_SnvsDigDischargeResistor15K = 0U, /*!< The Discharge Resistor is selected as 15K ohm */ + kPMU_SnvsDigDischargeResistor30K = 1U, /*!< The Discharge Resistor is selected as 30K ohm */ + kPMU_SnvsDigDischargeResistor9K = 2U, /*!< The Discharge Resistor is selected as 9K ohm */ +} pmu_snvs_dig_discharge_resistor_value_t; + +/*! + * @brief The enumeration of bandgap power down option. + */ +enum _pmu_static_bandgap_power_down_option +{ + kPMU_PowerDownBandgapFully = 1U << 0U, /*!< Fully power down the bandgap module. */ + kPMU_PowerDownVoltageReferenceOutputOnly = 1U << 1U, /*!< Power down only the reference output + section of the bandgap */ + kPMU_PowerDownBandgapVBGUPDetector = 1U << 2U, /*!< Power down the VBGUP detector of the bandgap without + affecting any additional functionality. */ +}; + +/*! + * @brief The enumeration of output VBG voltage. + */ +typedef enum _pmu_bandgap_output_VBG_voltage_value +{ + kPMU_BandgapOutputVBGVoltageNominal = 0x0U, /*!< Output nominal voltage. */ + kPMU_BandgapOutputVBGVoltagePlus10mV = 0x1U, /*!< Output VBG voltage Plus 10mV. */ + kPMU_BandgapOutputVBGVoltagePlus20mV = 0x2U, /*!< Output VBG voltage Plus 20mV. */ + kPMU_BandgapOutputVBGVoltagePlus30mV = 0x3U, /*!< Output VBG voltage Plus 30mV. */ + kPMU_BandgapOutputVBGVoltageMinus10mV = 0x4U, /*!< Output VBG voltage Minus 10mV. */ + kPMU_BandgapOutputVBGVoltageMinus20mV = 0x5U, /*!< Output VBG voltage Minus 20mV. */ + kPMU_BandgapOutputVBGVoltageMinus30mV = 0x6U, /*!< Output VBG voltage Minus 30mV. */ + kPMU_BandgapOutputVBGVoltageMinus40mV = 0x7U, /*!< Output VBG voltage Minus 40mV. */ +} pmu_bandgap_output_VBG_voltage_value_t; + +/*! + * @brief The enumeration of output current. + */ +typedef enum _pmu_bandgap_output_current_value +{ + kPMU_OutputCurrent11P5uA = 0x0U, /*!< Output 11.5uA current from the bandgap. */ + kPMU_OutputCurrent11P8uA = 0x1U, /*!< Output 11.8uA current from the bandgap. */ + kPMU_OutputCurrent12P1uA = 0x2U, /*!< Output 12.1uA current from the bandgap. */ + kPMU_OutputCurrent12P4uA = 0x4U, /*!< Output 12.4uA current from the bandgap. */ + kPMU_OutputCurrent12P7uA = 0x5U, /*!< Output 12.7uA current from the bandgap. */ + kPMU_OutputCurrent13P0uA = 0x6U, /*!< Output 13.0uA current from the bandgap. */ + kPMU_OutputCurrent13P3uA = 0x7U, /*!< Output 13.3uA current from the bandgap. */ +} pmu_bandgap_output_current_value_t; + +/*! + * @brief The enumerator of well bias power source. + */ +typedef enum _pmu_well_bias_power_source +{ + kPMU_WellBiasPowerFromLpsrDigLdo = 0U, /*!< LPSR Dig LDO supplies the power stage and NWELL sampler. */ + kPMU_WellBiasPowerFromDCDC, /*!< DCDC supplies the power stage and NWELL sampler. */ +} pmu_well_bias_power_source_t; + +/*! + * @brief The enumerator of bias area size. + */ +typedef enum _pmu_bias_area_size +{ + kPMU_180uA_6mm2At125C = 0U, /*!< Imax = 180uA; Areamax-RVT = 6.00mm2 at 125C */ + kPMU_150uA_5mm2At125C, /*!< Imax = 150uA; Areamax-RVT = 5.00mm2 at 125C */ + kPMU_120uA_4mm2At125C, /*!< Imax = 120uA; Areamax-RVT = 4.00mm2 at 125C */ + kPMU_90uA_3mm2At125C, /*!< Imax = 90uA; Areamax-RVT = 3.00mm2 at 125C */ + kPMU_60uA_2mm2At125C, /*!< Imax = 60uA; Areamax-RVT = 2.00mm2 at 125C */ + kPMU_45uA_1P5mm2At125C, /*!< Imax = 45uA; Areamax-RVT = 1P5mm2 at 125C */ + kPMU_30uA_1mm2At125C, /*!< Imax = 30uA; Areamax-RVT = 1.00mm2 at 125C */ + kPMU_15uA_0P5mm2At125C, /*!< Imax = 15uA; Areamax-RVT = 0.50mm2 at 125C */ +} pmu_bias_area_size_t; + +/*! + * @brief The enumerator of well bias typical frequency. + */ +typedef enum _pmu_well_bias_typical_freq +{ + kPMU_OscFreqDiv128 = 0U, /*!< Typical frequency = osc_freq / 128. */ + kPMU_OscFreqDiv64 = 1U, /*!< Typical frequency = osc_freq / 64. */ + kPMU_OscFreqDiv32 = 2U, /*!< Typical frequency = osc_freq / 32. */ + kPMU_OscFreqDiv16 = 3U, /*!< Typical frequency = osc_freq / 16. */ + kPMU_OscFreqDiv8 = 4U, /*!< Typical frequency = osc_freq / 8. */ + kPMU_OscFreqDiv2 = 6U, /*!< Typical frequency = osc_freq / 2. */ + kPMU_OscFreq = 7U, /*!< Typical frequency = oscillator frequency. */ +} pmu_well_bias_typical_freq_t; + +/*! + * @brief The enumerator of well bias adaptive clock source. + */ +typedef enum _pmu_adaptive_clock_source +{ + kPMU_AdaptiveClkSourceOscClk = 0U, /*!< The adaptive clock source is oscillator clock. */ + kPMU_AdaptiveClkSourceChargePumpClk, /*!< The adaptive clock source is charge pump clock. */ +} pmu_adaptive_clock_source_t; + +/*! + * @brief The enumerator of frequency reduction due to cap increment. + */ +typedef enum _pmu_freq_reduction +{ + kPMU_FreqReductionNone = 0U, /*!< No frequency reduction. */ + kPMU_FreqReduction30PCT, /*!< 30% frequency reduction due to cap increment. */ + kPMU_FreqReduction40PCT, /*!< 40% frequency reduction due to cap increment. */ + kPMU_FreqReduction50PCT, /*!< 50% frequency reduction due to cap increment. */ +} pmu_freq_reduction_t; + +/*! + * @brief The enumerator of well bias 1P8 adjustment. + */ +typedef enum _pmu_well_bias_1P8_adjustment +{ + kPMU_Cref0fFCspl0fFDeltaC0fF = 0U, /*!< Cref = 0fF, Cspl = 0fF, DeltaC = 0fF. */ + kPMU_Cref0fFCspl30fFDeltaCN30fF, /*!< Cref = 0fF, Cspl = 30fF, DeltaC = -30fF. */ + kPMU_Cref0fFCspl43fFDeltaCN43fF, /*!< Cref = 0fF, Cspl = 43fF, DeltaC = -43fF. */ + kPMU_Cref0fFCspl62fFDeltaCN62fF, /*!< Cref = 0fF, Cspl = 62fF, DeltaC = -62fF. */ + kPMU_Cref0fFCspl105fFDeltaCN105fF, /*!< Cref = 0fF, Cspl = 105fF, DeltaC = -105fF. */ + kPMU_Cref30fFCspl0fFDeltaC30fF, /*!< Cref = 30fF, Cspl = 0fF, DeltaC = 30fF. */ + kPMU_Cref30fFCspl43fFDeltaCN12fF, /*!< Cref = 30fF, Cspl = 43fF, DeltaC = -12fF. */ + kPMU_Cref30fFCspl105fFDeltaCN75fF, /*!< Cref = 30fF, Cspl = 105fF, DeltaC = -75fF. */ + kPMU_Cref43fFCspl0fFDeltaC43fF, /*!< Cref = 43fF, Cspl = 0fF, DeltaC = 43fF. */ + kPMU_Cref43fFCspl30fFDeltaC13fF, /*!< Cref = 43fF, Cspl = 30fF, DeltaC = 13fF. */ + kPMU_Cref43fFCspl62fFDeltaCN19fF, /*!< Cref = 43fF, Cspl = 62fF, DeltaC = -19fF. */ + kPMU_Cref62fFCspl0fFDeltaC62fF, /*!< Cref = 62fF, Cspl = 0fF, DeltaC = 62fF. */ + kPMU_Cref62fFCspl43fFDeltaC19fF, /*!< Cref = 62fF, Cspl = 43fF, DeltaC = 19fF. */ + kPMU_Cref105fFCspl0fFDeltaC105fF, /*!< Cref = 105fF, Cspl = 0fF, DeltaC = 105fF. */ + kPMU_Cref105fFCspl30fFDeltaC75fF, /*!< Cref = 105fF, Cspl = 30fF, DeltaC = 75fF. */ +} pmu_well_bias_1P8_adjustment_t; + +/*! + * @brief LPSR ANA LDO config. + */ +typedef struct _pmu_static_lpsr_ana_ldo_config +{ + pmu_ldo_operate_mode_t mode; /*!< The operate mode of LPSR ANA LDO. */ + bool enable2mALoad; /*!< Enable/Disable 2mA load. + - \b true Enables 2mA loading to prevent overshoot; + - \b false Disables 2mA loading.*/ + bool enable4mALoad; /*!< Enable/Disable 4mA load. + - \b true Enables 4mA loading to prevent dramatic voltage drop; + - \b false Disables 4mA load. */ + bool enable20uALoad; /*!< Enable/Disable 20uA load. + - \b true Enables 20uA loading to prevent overshoot; + - \b false Disables 20uA load. */ + bool enableStandbyMode; /*!< Enable/Disable Standby Mode. + - \b true Enables Standby mode, if the STBY assert, the LPSR ANA LDO enter LP mode + - \b false Disables Standby mode. */ +} pmu_static_lpsr_ana_ldo_config_t; + +/*! + * @brief LPSR DIG LDO Config in Static/Software Mode. + */ +typedef struct _pmu_static_lpsr_dig_config +{ + bool enableStableDetect; /*!< Enable/Disable Stable Detect. + - \b true Enables Stable Detect. + - \b false Disables Stable Detect. */ + pmu_lpsr_dig_voltage_step_time_t voltageStepTime; /*!< Step time. */ + pmu_lpsr_dig_target_output_voltage_t targetVoltage; /*!< The target output voltage. */ +} pmu_static_lpsr_dig_config_t; + +/*! + * @brief SNVS DIG LDO config. + */ +typedef struct _pmu_snvs_dig_config +{ + pmu_ldo_operate_mode_t mode; /*!< The operate mode the SNVS DIG LDO. */ + pmu_snvs_dig_charge_pump_current_t chargePumpCurrent; /*!< The current of SNVS DIG LDO's charge pump current. */ + pmu_snvs_dig_discharge_resistor_value_t dischargeResistorValue; /*!< The value of SNVS DIG LDO's + Discharge Resistor. */ + uint8_t trimValue; /*!< The trim value. */ + bool enablePullDown; /*!< Enable/Disable Pull down. + - \b true Enables the feature of using 1M ohm resistor to discharge the LDO output. + - \b false Disables the feature of using 1M ohm resistor to discharge the LDO output. */ + bool enableLdoStable; /*!< Enable/Disable SNVS DIG LDO Stable. */ +} pmu_snvs_dig_config_t; + +/*! + * @brief Bandgap config in static mode. + */ +typedef struct _pmu_static_bandgap_config +{ + uint8_t powerDownOption; /*!< The OR'ed value of @ref _pmu_static_bandgap_power_down_option. Please refer to @ref + _pmu_static_bandgap_power_down_option. */ + bool enableLowPowerMode; /*!< Turn on/off the Low power mode. + - \b true Turns on the low power operation of the bandgap. + - \b false Turns off the low power operation of the bandgap. */ + pmu_bandgap_output_VBG_voltage_value_t outputVoltage; /*!< The output VBG voltage of Bandgap. */ + pmu_bandgap_output_current_value_t outputCurrent; /*!< The output current from the bandgap to + the temperature sensors. */ +} pmu_static_bandgap_config_t; + +/*! + * @brief The union of well bias basic options, such as clock source, power source and so on. + */ +typedef union _pmu_well_bias_option +{ + uint16_t wellBiasData; /*!< well bias configuration data. */ + struct + { + uint16_t enablePWellOnly : 1U; /*!< Turn on both PWELL and NWELL, or only trun on PWELL. + - \b 1b0 PWELL and NEWLL are both turned on. + - \b 1b1 PWELL is turned on only. */ + uint16_t reserved1 : 1U; /*!< Reserved. */ + uint16_t biasAreaSize : 3U; /*!< Select size of bias area, please refer to @ref pmu_bias_area_size_t */ + uint16_t disableAdaptiveFreq : 1U; /*!< Enable/Disable adaptive frequency. + - \b 1b0 Frequency change after each half cycle minimum frequency + determined by typical frequency. + - \b 1b1 Adaptive frequency disabled. Frequency determined by typical + frequency. */ + uint16_t wellBiasFreq : 3U; /*!< Set well bias typical frequency, please refer to @ref + pmu_well_bias_typical_freq_t. */ + uint16_t clkSource : 1U; /*!< Config the adaptive clock source, please @ref pmu_adaptive_clock_source_t. */ + uint16_t freqReduction : 2U; /*!< Config the percent of frequency reduction due to cap increment, + please refer to @ref pmu_freq_reduction_t. */ + uint16_t enablePowerDownOption : 1U; /*!< Enable/Disable pull down option. + - \b false Pull down option is disabled. + - \b true Pull down option is enabled. */ + uint16_t reserved2 : 1U; /*!< Reserved. */ + uint16_t powerSource : 1U; /*!< Set power source, please refer to @ref pmu_well_bias_power_source_t. */ + uint16_t reserved3 : 1U; /*!< Reserved. */ + } wellBiasStruct; +} pmu_well_bias_option_t; + +/*! + * @brief The structure of well bias configuration. + */ +typedef struct _pmu_well_bias_config +{ + pmu_well_bias_option_t wellBiasOption; /*!< Well bias basic function, please + refer to @ref pmu_well_bias_option_t. */ + pmu_well_bias_1P8_adjustment_t adjustment; /*!< Well bias adjustment 1P8, please + refer to @ref pmu_well_bias_1P8_adjustment_t. */ +} pmu_well_bias_config_t; + +/*! + * @brief The stucture of body bias config in GPC mode. + */ +typedef struct _pmu_gpc_body_bias_config +{ + uint8_t PWELLRegulatorSize; /*!< The size of the PWELL Regulator. */ + uint8_t NWELLRegulatorSize; /*!< The size of the NWELL Regulator. */ + uint8_t oscillatorSize; /*!< The size of the oscillator bits. */ + uint8_t regulatorStrength; /*!< The strength of the selected regulator. */ +} pmu_gpc_body_bias_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name LDOs Control APIs + * @{ + */ + +/*! + * @brief Selects the control mode of the PLL LDO. + * + * @param base PMU peripheral base address. + * @param mode The control mode of the PLL LDO. Please refer to @ref pmu_control_mode_t. + */ +void PMU_SetPllLdoControlMode(ANADIG_PMU_Type *base, pmu_control_mode_t mode); + +/*! + * @brief Switches the PLL LDO from Static/Software Mode to GPC/Hardware Mode. + * + * @param base PMU peripheral base address. + */ +void PMU_SwitchPllLdoToGPCMode(ANADIG_PMU_Type *base); + +/*! + * @brief Enables PLL LDO via AI interface in Static/Software mode. + * + * @param base PMU peripheral base address. + */ +void PMU_StaticEnablePllLdo(ANADIG_PMU_Type *base); + +/*! + * @brief Disables PLL LDO via AI interface in Static/Software mode. + */ +void PMU_StaticDisablePllLdo(void); + +/*! + * @brief Selects the control mode of the LPSR ANA LDO. + * + * @param base PMU peripheral base address. + * @param mode The control mode of the LPSR ANA LDO. Please refer to @ref pmu_control_mode_t. + */ +void PMU_SetLpsrAnaLdoControlMode(ANADIG_LDO_SNVS_Type *base, pmu_control_mode_t mode); + +/*! + * @brief Sets the Bypass mode of the LPSR ANA LDO. + * + * @param base ANADIG_LDO_SNVS peripheral base address. + * @param enable Enable/Disable bypass mode. + * - \b true Enable LPSR ANA Bypass mode. + * - \b false Disable LPSR ANA Bypass mode. + */ +void PMU_StaticEnableLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS_Type *base, bool enable); + +/*! + * @brief Checks whether the LPSR ANA LDO is in bypass mode. + * + * @param base ANADIG_LDO_SNVS peripheral base address. + * @return The result used to indicates whether the LPSR ANA LDO is in bypass mode. + * - \b true The LPSR ANA LDO is in bypass mode. + * - \b false The LPSR ANA LDO not in bypass mode. + */ +static inline bool PMU_StaticCheckLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS_Type *base) +{ + return ((ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK) != 0UL); +} + +/*! + * @brief Fill the LPSR ANA LDO configuration structure with default settings. + * + * The default values are: + * @code + * config->mode = kPMU_HighPowerMode; + config->enable2mALoad = true; + config->enable20uALoad = false; + config->enable4mALoad = true; + config->enableStandbyMode = false; + config->driverStrength = kPMU_LpsrAnaLdoDriverStrength0; + config->brownOutDetectorConfig = kPMU_LpsrAnaLdoBrownOutDetectorDisable; + config->chargePumpCurrent = kPMU_LpsrAnaChargePump300nA; + config->outputRange = kPMU_LpsrAnaLdoOutputFrom1P77To1P83; + * @endcode + * + * @param config Pointer to the structure @ref pmu_static_lpsr_ana_ldo_config_t. + */ +void PMU_StaticGetLpsrAnaLdoDefaultConfig(pmu_static_lpsr_ana_ldo_config_t *config); + +/*! + * @brief Initialize the LPSR ANA LDO in Static/Sofware Mode. + * + * @param base ANADIG_LDO_SNVS peripheral base address. + * @param config Pointer to the structure @ref pmu_static_lpsr_ana_ldo_config_t. + */ +void PMU_StaticLpsrAnaLdoInit(ANADIG_LDO_SNVS_Type *base, const pmu_static_lpsr_ana_ldo_config_t *config); + +/*! + * @brief Disable the output of LPSR ANA LDO. + * + * @param base ANADIG_LDO_SNVS peripheral base address. + */ +void PMU_StaticLpsrAnaLdoDeinit(ANADIG_LDO_SNVS_Type *base); + +/*! + * @brief Selects the control mode of the LPSR DIG LDO. + * + * @param base PMU peripheral base address. + * @param mode The control mode of the LPSR DIG LDO. Please refer to @ref pmu_control_mode_t. + */ +void PMU_SetLpsrDigLdoControlMode(ANADIG_LDO_SNVS_Type *base, pmu_control_mode_t mode); + +/*! + * @brief Turn on/off Bypass mode of the LPSR DIG LDO in Static/Software mode. + * + * @param base ANADIG_LDO_SNVS peripheral base address. + * @param enable + * - \b true Turns on Bypass mode of the LPSR DIG LDO. + * - \b false Turns off Bypass mode of the LPSR DIG LDO. + */ +void PMU_StaticEnableLpsrDigLdoBypassMode(ANADIG_LDO_SNVS_Type *base, bool enable); + +/*! + * @brief Checks whether the LPSR DIG LDO is in bypass mode. + * + * @param base PMU peripheral base address. + * @return The result used to indicates whether the LPSR DIG LDO is in bypass mode. + * - \b true The LPSR DIG LDO is in bypass mode. + * - \b false The LPSR DIG LDO not in bypass mode. + */ +static inline bool PMU_StaticCheckLpsrDigLdoBypassMode(ANADIG_LDO_SNVS_Type *base) +{ + return ((ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK) != 0UL); +} + +/*! + * @brief Gets the default configuration of LPSR DIG LDO. + * + * The default values are: + * @code + * config->enableStableDetect = false; + * config->voltageStepTime = kPMU_LpsrDigVoltageStepInc50us; + * config->brownOutConfig = kPMU_LpsrDigBrownOutDisable; + * config->targetVoltage = kPMU_LpsrDigTargetStableVoltage1P0V; + * config->mode = kPMU_HighPowerMode; + * @endcode + * @param config Pointer to the structure @ref pmu_static_lpsr_dig_config_t. + */ +void PMU_StaticGetLpsrDigLdoDefaultConfig(pmu_static_lpsr_dig_config_t *config); + +/*! + * @brief Initialize the LPSR DIG LDO in static mode. + * + * @param base ANADIG_LDO_SNVS peripheral base address. + * @param config Pointer to the structure @ref pmu_static_lpsr_dig_config_t. + */ +void PMU_StaticLpsrDigLdoInit(ANADIG_LDO_SNVS_Type *base, const pmu_static_lpsr_dig_config_t *config); + +/*! + * @brief Disable the LPSR DIG LDO. + * + * @param base ANADIG_LDO_SNVS peripheral base address. + */ +void PMU_StaticLpsrDigLdoDeinit(ANADIG_LDO_SNVS_Type *base); + +/*! + * @brief Sets the voltage step of LPSR DIG LDO in certain setpoint during GPC mode. + * + * @note The function provides the feature to set the voltage step to different setpoints. + * + * @param setpointMap The map of setpoints should be the OR'ed Value of @ref _pmu_setpoint_map. + * @param voltageValue The voltage step to be set. See enumeration @ref pmu_lpsr_dig_target_output_voltage_t. + */ +void PMU_GPCSetLpsrDigLdoTargetVoltage(uint32_t setpointMap, pmu_lpsr_dig_target_output_voltage_t voltageValue); + +/*! + * @brief Gets the default config of the SNVS DIG LDO. + * + * The default values are: + * @code + * config->mode = kPMU_LowPowerMode; + * config->chargePumpCurrent = kPMU_SnvsDigChargePump12P5nA; + * config->dischargeResistorValue = kPMU_SnvsDigDischargeResistor15K; + * config->trimValue = 0U; + * config->enablePullDown = true; + * config->enableLdoStable = false; + * @endcode + * + * @param config Pointer to @ref pmu_snvs_dig_config_t. + */ +void PMU_GetSnvsDigLdoDefaultConfig(pmu_snvs_dig_config_t *config); + +/*! + * @brief Initialize the SNVS DIG LDO. + * + * @param base LDO SNVS DIG peripheral base address. + * @param mode Used to control LDO power mode, please refer to @ref pmu_ldo_operate_mode_t. + */ +void PMU_SnvsDigLdoInit(ANADIG_LDO_SNVS_DIG_Type *base, pmu_ldo_operate_mode_t mode); + +/*! + * @brief Disable SNVS DIG LDO. + */ +static inline void PMU_SnvsDigLdoDeinit(ANADIG_LDO_SNVS_DIG_Type *base) +{ + base->PMU_LDO_SNVS_DIG &= ~ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN_MASK; +} + +/*! + * @brief Controls the ON/OFF of the selected LDO in certain setpoints with GPC mode. + * + * @param name The name of the selected ldo. Please see enumeration @ref pmu_ldo_name_t for details. + * @param setpointMap The map of setpoints should be the OR'ed Value of @ref _pmu_setpoint_map, 1b'1 + * means enable specific ldo in that setpoint. + * For example, the code PMU_GPCEnableLdo(kPMU_PllLdo, 0x1U) means to enable PLL LDO in setpoint 0 and disable + * PLL LDO in other setpoint. + */ +void PMU_GPCEnableLdo(pmu_ldo_name_t name, uint32_t setpointMap); + +/*! + * @brief Sets the operating mode of the selected LDO in certain setpoints with GPC mode. + * + * @param name The name of the selected ldo. Please see enumeration @ref pmu_ldo_name_t for details. + * @param setpointMap The map of setpoints should be the OR'ed Value of @ref _pmu_setpoint_map. + * @param mode The operating mode of the selected ldo. Please refer to enumeration @ref pmu_ldo_operate_mode_t for + * details. + */ +void PMU_GPCSetLdoOperateMode(pmu_ldo_name_t name, uint32_t setpointMap, pmu_ldo_operate_mode_t mode); + +/*! + * @brief Controls the ON/OFF of the selected LDOs' Tracking mode in certain setpoints with GPC mode. + * + * @param name The name of the selected ldo. Please see enumeration @ref pmu_ldo_name_t for details. + * @param setpointMap The map of setpoints that the LDO tracking mode will be enabled in those setpoints, this value + * should be the OR'ed Value of @ref _pmu_setpoint_map. + */ +void PMU_GPCEnableLdoTrackingMode(pmu_ldo_name_t name, uint32_t setpointMap); + +/*! + * @brief Controls the ON/OFF of the selected LDOs' Bypass mode in certain setpoints with GPC mode. + * + * @param name The name of the selected ldo. Please see enumeration @ref pmu_ldo_name_t for details. + * @param setpointMap The map of setpoints that the LDO bypass mode will be enabled in those setpoints, this value + * should be the OR'ed Value of @ref _pmu_setpoint_map. + */ +void PMU_GPCEnableLdoBypassMode(pmu_ldo_name_t name, uint32_t setpointMap); + +/*! + * @brief When STBY assert, enable/disable the selected LDO enter it's Low power mode. + * + * @param name The name of the selected ldo. Please see enumeration @ref pmu_ldo_name_t for details. + * @param setpointMap The map of setpoints that the LDO low power mode will be enabled in those setpoints if STBY + * assert, this value should be the OR'ed Value of @ref _pmu_setpoint_map. + */ +void PMU_GPCEnableLdoStandbyMode(pmu_ldo_name_t name, uint32_t setpointMap); + +/*! + * @} + */ + +/*! + * @name Bandgap Control APIs + * @{ + */ + +/*! + * @brief Selects the control mode of the Bandgap Reference. + * + * @param base PMU peripheral base address. + * @param mode The control mode of the Bandgap Reference. Please refer to @ref pmu_control_mode_t. + */ +void PMU_SetBandgapControlMode(ANADIG_PMU_Type *base, pmu_control_mode_t mode); + +/*! + * @brief Switches the Bandgap from Static/Software Mode to GPC/Hardware Mode. + * + * @param base PMU peripheral base address. + */ +void PMU_SwitchBandgapToGPCMode(ANADIG_PMU_Type *base); + +/*! + * @brief Disables Bandgap self bias for best noise performance. + * + * This function should be invoked after powering up. This function will wait for the bandgap stable and disable the + * bandgap self bias. After powering up, it need to wait for the bandgap to get stable and then disable Bandgap Self + * bias for best noise performance. + */ +void PMU_DisableBandgapSelfBiasAfterPowerUp(void); + +/*! + * @brief Enables Bandgap self bias before power down. + * + * This function will enable Bandgap self bias feature before powering down or there + * will be risk of Bandgap not starting properly. + */ +void PMU_EnableBandgapSelfBiasBeforePowerDown(void); + +/*! + * @brief Initialize Bandgap. + * + * @param config Pointer to the structure @ref pmu_static_bandgap_config_t. + */ +void PMU_StaticBandgapInit(const pmu_static_bandgap_config_t *config); + +/*! + * @brief Controls the ON/OFF of the Bandgap in certain setpoints with GPC mode. + * + * For example, the code PMU_GPCEnableBandgap(PMU, kPMU_SetPoint0 | kPMU_SetPoint1); means enable bandgap in + * setpoint0 and setpoint1 and disable bandgap in other setpoints. + * + * @param base PMU peripheral base address. + * @param setpointMap The map of setpoints that the bandgap will be enabled in those setpoints, this parameter + * should be the OR'ed Value of @ref _pmu_setpoint_map. + */ +static inline void PMU_GPCEnableBandgap(ANADIG_PMU_Type *base, uint32_t setpointMap) +{ + base->BANDGAP_ENABLE_SP = ~setpointMap; +} + +/*! + * @brief Controls the ON/OFF of the Bandgap's Standby mode in certain setpoints with GPC mode. + * + * @param base PMU peripheral base address. + * @param setpointMap The map of setpoints that the bandgap standby mode will be enabled in those setpoints, this value + * should be the OR'ed Value of @ref _pmu_setpoint_map. + */ +static inline void PMU_GPCEnableBandgapStandbyMode(ANADIG_PMU_Type *base, uint32_t setpointMap) +{ + base->BANDGAP_STBY_EN_SP = setpointMap; +} + +/*! + * @} + */ + +/*! + * @name Body Bias Control APIs + * @{ + */ + +/*! + * @brief Configures Well bias, such as power source, clock source and so on. + * + * @param base PMU peripheral base address. + * @param config Pointer to the @ref pmu_well_bias_config_t structure. + */ +void PMU_WellBiasInit(ANADIG_PMU_Type *base, const pmu_well_bias_config_t *config); + +/*! + * @brief Gets the default configuration of well bias. + * + * @param config The pointer to the @ref pmu_well_bias_config_t structure. + */ +void PMU_GetWellBiasDefaultConfig(pmu_well_bias_config_t *config); + +/*! + * @brief Selects the control mode of the Body Bias. + * + * @param base PMU peripheral base address. + * @param name The name of the body bias. Please refer to @ref pmu_body_bias_name_t. + * @param mode The control mode of the Body Bias. Please refer to @ref pmu_control_mode_t. + */ +void PMU_SetBodyBiasControlMode(ANADIG_PMU_Type *base, pmu_body_bias_name_t name, pmu_control_mode_t mode); + +/*! + * @brief Enables/disables the selected body bias. + * + * @param base PMU peripheral base address. + * @param name The name of the body bias to be turned on/off, please refer to @ref pmu_body_bias_name_t. + * @param enable Used to turn on/off the specific body bias. + * - \b true Enable the selected body bias. + * - \b false Disable the selected body bias. + */ +void PMU_EnableBodyBias(ANADIG_PMU_Type *base, pmu_body_bias_name_t name, bool enable); + +/*! + * @brief Controls the ON/OFF of the selected body bias in certain setpoints with GPC mode. + * + * @param name The name of the selected body bias. Please see enumeration @ref pmu_body_bias_name_t for details. + * @param setpointMap The map of setpoints that the specific body bias will be enabled in those setpoints, this value + * should be the OR'ed Value of _pmu_setpoint_map. + */ +void PMU_GPCEnableBodyBias(pmu_body_bias_name_t name, uint32_t setpointMap); + +/*! + * @brief Controls the ON/OFF of the selected Body Bias' Wbias power switch in certain setpoints with GPC mode. + * + * @param name The name of the selected body bias. Please see the enumeration @ref pmu_body_bias_name_t for details. + * @param setpointMap The map of setpoints that the specific body bias's wbias power switch will be turn on in those + * setpoints, this value should be the OR'ed Value of @ref _pmu_setpoint_map. + */ +void PMU_GPCEnableBodyBiasStandbyMode(pmu_body_bias_name_t name, uint32_t setpointMap); + +/*! + * @brief Gets the default config of body bias in GPC mode. + * + * @param config Pointer to structure @ref pmu_gpc_body_bias_config_t. + */ +void PMU_GPCGetBodyBiasDefaultConfig(pmu_gpc_body_bias_config_t *config); + +/*! + * @brief Sets the config of the selected Body Bias in GPC mode. + * + * @param name The name of the selected body bias. Please see enumeration @ref pmu_body_bias_name_t for details. + * @param config Pointer to structure @ref pmu_gpc_body_bias_config_t. + */ +void PMU_GPCSetBodyBiasConfig(pmu_body_bias_name_t name, const pmu_gpc_body_bias_config_t *config); + +/*! + * @} + */ + +#if defined(__cplusplus) +} +#endif +/*! + * @} + */ + +#endif /* _FSL_PMU_H_ */ diff --git a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_romapi.c b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_romapi.c new file mode 100644 index 0000000000..20feafd40f --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_romapi.c @@ -0,0 +1,250 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_romapi.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "driver.romapi" +#endif + +typedef status_t (*clearCacheCommand_t)(uint32_t instance); + +/*! + * @brief Structure of version property. + * + * @ingroup bl_core + */ +typedef union _standard_version +{ + struct + { + uint8_t bugfix; /*!< bugfix version [7:0] */ + uint8_t minor; /*!< minor version [15:8] */ + uint8_t major; /*!< major version [23:16] */ + char name; /*!< name [31:24] */ + }; + uint32_t version; /*!< combined version numbers */ + +#if defined(__cplusplus) + StandardVersion() : version(0) + { + } + StandardVersion(uint32_t version) : version(version) + { + } +#endif +} standard_version_t; + +/*! + * @brief Interface for the ROM FLEXSPI NOR flash driver. + */ +typedef struct +{ + uint32_t version; + status_t (*init)(uint32_t instance, flexspi_nor_config_t *config); + status_t (*page_program)(uint32_t instance, flexspi_nor_config_t *config, uint32_t dst_addr, const uint32_t *src); + status_t (*erase_all)(uint32_t instance, flexspi_nor_config_t *config); + status_t (*erase)(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length); + status_t (*read)(uint32_t instance, flexspi_nor_config_t *config, uint32_t *dst, uint32_t start, uint32_t bytes); + void (*clear_cache)(uint32_t instance); + status_t (*xfer)(uint32_t instance, flexspi_xfer_t *xfer); + status_t (*update_lut)(uint32_t instance, uint32_t seqIndex, const uint32_t *lutBase, uint32_t numberOfSeq); + status_t (*get_config)(uint32_t instance, flexspi_nor_config_t *config, serial_nor_config_option_t *option); + status_t (*erase_sector)(uint32_t instance, flexspi_nor_config_t *config, uint32_t address); + status_t (*erase_block)(uint32_t instance, flexspi_nor_config_t *config, uint32_t address); + const uint32_t reserved0; /*!< Reserved */ + status_t (*wait_busy)(uint32_t instance, flexspi_nor_config_t *config, bool isParallelMode, uint32_t address); + const uint32_t reserved1[2]; /*!< Reserved */ +} flexspi_nor_driver_interface_t; + +/*! + * @brief Root of the bootloader api tree. + * + * An instance of this struct resides in read-only memory in the bootloader. It + * provides a user application access to APIs exported by the bootloader. + * + * @note The order of existing fields must not be changed. + */ +typedef struct +{ + void (*runBootloader)(void *arg); /*!< Function to start the bootloader executing.*/ + standard_version_t version; /*!< Bootloader version number.*/ + const char *copyright; /*!< Copyright string.*/ + const flexspi_nor_driver_interface_t *flexSpiNorDriver; /*!< FlexSPI NOR FLASH Driver API.*/ + const uint32_t reserved[8]; /*!< Reserved */ +} bootloader_api_entry_t; + +/******************************************************************************* + * Variables + ******************************************************************************/ +#if defined(FSL_FEATURE_BOOT_ROM_HAS_ROMAPI) && FSL_FEATURE_BOOT_ROM_HAS_ROMAPI + +#define g_bootloaderTree ((bootloader_api_entry_t *)*(uint32_t *)0x0021001cU) + +/******************************************************************************* + * ROM FLEXSPI NOR driver + ******************************************************************************/ + +#if defined(FSL_ROM_HAS_RUNBOOTLOADER_API) && FSL_ROM_HAS_RUNBOOTLOADER_API +/*! + * @brief Enter Bootloader. + * + * @param arg A pointer to the storage for the bootloader param. + * refer to System Boot Chapter in device reference manual for details. + */ +void ROM_RunBootloader(void *arg) +{ + g_bootloaderTree->runBootloader(arg); +} +#endif /* FSL_ROM_HAS_RUNBOOTLOADER_API */ + +#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_GET_CONFIG) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_GET_CONFIG +/*! @brief Get FLEXSPI NOR Configuration Block based on specified option. */ +status_t ROM_FLEXSPI_NorFlash_GetConfig(uint32_t instance, + flexspi_nor_config_t *config, + serial_nor_config_option_t *option) +{ + return g_bootloaderTree->flexSpiNorDriver->get_config(instance, config, option); +} +#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_GET_CONFIG */ + +/*! + * @brief Initialize Serial NOR devices via FLEXSPI. + * + * @param instance storage the instance of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + */ +status_t ROM_FLEXSPI_NorFlash_Init(uint32_t instance, flexspi_nor_config_t *config) +{ + return g_bootloaderTree->flexSpiNorDriver->init(instance, config); +} + +/*! + * @brief Program data to Serial NOR via FLEXSPI. + * + * @param instance storage the instance of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * @param dst_addr A pointer to the desired flash memory to be programmed. + * @param src A pointer to the source buffer of data that is to be programmed + * into the NOR flash. + */ +status_t ROM_FLEXSPI_NorFlash_ProgramPage(uint32_t instance, + flexspi_nor_config_t *config, + uint32_t dst_addr, + const uint32_t *src) +{ + return g_bootloaderTree->flexSpiNorDriver->page_program(instance, config, dst_addr, src); +} + +#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_READ) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_READ +/*! + * @brief Read data from Serial NOR + * + * @param instance storage the instance of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * @param dst A pointer to the dest buffer of data that is to be read from the NOR flash. + * @param lengthInBytes The length, given in bytes to be read. + */ +status_t ROM_FLEXSPI_NorFlash_Read( + uint32_t instance, flexspi_nor_config_t *config, uint32_t *dst, uint32_t start, uint32_t lengthInBytes) +{ + return g_bootloaderTree->flexSpiNorDriver->read(instance, config, dst, start, lengthInBytes); +} +#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_READ */ + +/*! + * @brief Erase Flash Region specified by address and length. + * + * @param instance storage the index of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired NOR flash memory to be erased. + * @param length The length, given in bytes to be erased. + */ +status_t ROM_FLEXSPI_NorFlash_Erase(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length) +{ + return g_bootloaderTree->flexSpiNorDriver->erase(instance, config, start, length); +} + +#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR +/*! + * @brief Erase one sector specified by address. + * + * @param instance storage the index of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired NOR flash memory to be erased. + */ +status_t ROM_FLEXSPI_NorFlash_EraseSector(uint32_t instance, flexspi_nor_config_t *config, uint32_t start) +{ + return g_bootloaderTree->flexSpiNorDriver->erase_sector(instance, config, start); +} +#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR */ + +#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_BLOCK) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_BLOCK +/*! + * @brief Erase one block specified by address. + * + * @param instance storage the index of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired NOR flash memory to be erased. + */ +status_t ROM_FLEXSPI_NorFlash_EraseBlock(uint32_t instance, flexspi_nor_config_t *config, uint32_t start) +{ + return g_bootloaderTree->flexSpiNorDriver->erase_block(instance, config, start); +} +#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_BLOCK */ + +#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_ALL) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_ALL +/*! @brief Erase all the Serial NOR devices connected on FLEXSPI. */ +status_t ROM_FLEXSPI_NorFlash_EraseAll(uint32_t instance, flexspi_nor_config_t *config) +{ + return g_bootloaderTree->flexSpiNorDriver->erase_all(instance, config); +} +#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_ALL */ + +#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER +/*! @brief FLEXSPI command */ +status_t ROM_FLEXSPI_NorFlash_CommandXfer(uint32_t instance, flexspi_xfer_t *xfer) +{ + return g_bootloaderTree->flexSpiNorDriver->xfer(instance, xfer); +} +#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER */ + +#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT +/*! @brief Configure FLEXSPI Lookup table. */ +status_t ROM_FLEXSPI_NorFlash_UpdateLut(uint32_t instance, + uint32_t seqIndex, + const uint32_t *lutBase, + uint32_t seqNumber) +{ + return g_bootloaderTree->flexSpiNorDriver->update_lut(instance, seqIndex, lutBase, seqNumber); +} +#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT */ + +/*! @brief Software reset for the FLEXSPI logic. */ +void ROM_FLEXSPI_NorFlash_ClearCache(uint32_t instance) +{ + uint32_t clearCacheFunctionAddress = 0x0021a3b7U; + clearCacheCommand_t clearCacheCommand; + MISRA_CAST(clearCacheCommand_t, clearCacheCommand, uint32_t, clearCacheFunctionAddress); + (void)clearCacheCommand(instance); +} + +/*! @brief Wait until device is idle*/ +status_t ROM_FLEXSPI_NorFlash_WaitBusy(uint32_t instance, + flexspi_nor_config_t *config, + bool isParallelMode, + uint32_t address) +{ + return g_bootloaderTree->flexSpiNorDriver->wait_busy(instance, config, isParallelMode, address); +} + +#endif /* FSL_FEATURE_BOOT_ROM_HAS_ROMAPI */ diff --git a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_romapi.h b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_romapi.h new file mode 100644 index 0000000000..271ee9d313 --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_romapi.h @@ -0,0 +1,724 @@ +/* + * Copyright 2017-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_ROMAPI_H_ +#define _FSL_ROMAPI_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup romapi + * @{ + */ + +/*! @brief ROM API version 1.1.1. */ +#define FSL_ROM_ROMAPI_VERSION (MAKE_VERSION(1U, 1U, 1U)) +/*! @brief ROM FLEXSPI NOR driver version 1.7.0. */ +#define FSL_ROM_FLEXSPINOR_DRIVER_VERSION (MAKE_VERSION(1U, 7U, 0U)) + +/*! + * @name Common ROMAPI features info defines + * @{ + */ +/*! @brief ROM has FLEXSPI NOR API. */ +#define FSL_ROM_HAS_FLEXSPINOR_API (1) +/*! @brief ROM has run bootloader API. */ +#define FSL_ROM_HAS_RUNBOOTLOADER_API (1) +/*! @brief ROM has FLEXSPI NOR get config API. */ +#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_GET_CONFIG (1) +/*! @brief ROM has flash init API. */ +#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_FLASH_INIT (1) +/*! @brief ROM has erase API. */ +#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE (1) +/*! @brief ROM has erase sector API. */ +#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR (1) +/*! @brief ROM has erase block API. */ +#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_BLOCK (1) +/*! @brief ROM has erase all API. */ +#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_ALL (1) +/*! @brief ROM has read API. */ +#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_READ (1) +/*! @brief ROM has update lut API. */ +#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT (1) +/*! @brief ROM has FLEXSPI command API. */ +#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER (1) + +/*@}*/ + +#define kROM_StatusGroup_FLEXSPINOR 201U /*!< ROM FLEXSPI NOR status group number.*/ + +#define FSL_ROM_FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ + FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +/*! @brief Generate bit mask */ +#define FSL_ROM_FLEXSPI_BITMASK(bit_offset) (1U << (bit_offset)) + +/*! @brief FLEXSPI memory config block related definitions */ +#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) /*!< ascii "FCFB" Big Endian */ +#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) /*!< V1.4.0 */ + +#define CMD_SDR 0x01U +#define CMD_DDR 0x21U +#define RADDR_SDR 0x02U +#define RADDR_DDR 0x22U +#define CADDR_SDR 0x03U +#define CADDR_DDR 0x23U +#define MODE1_SDR 0x04U +#define MODE1_DDR 0x24U +#define MODE2_SDR 0x05U +#define MODE2_DDR 0x25U +#define MODE4_SDR 0x06U +#define MODE4_DDR 0x26U +#define MODE8_SDR 0x07U +#define MODE8_DDR 0x27U +#define WRITE_SDR 0x08U +#define WRITE_DDR 0x28U +#define READ_SDR 0x09U +#define READ_DDR 0x29U +#define LEARN_SDR 0x0AU +#define LEARN_DDR 0x2AU +#define DATSZ_SDR 0x0BU +#define DATSZ_DDR 0x2BU +#define DUMMY_SDR 0x0CU +#define DUMMY_DDR 0x2CU +#define DUMMY_RWDS_SDR 0x0DU +#define DUMMY_RWDS_DDR 0x2DU +#define JMP_ON_CS 0x1FU +#define STOP 0U + +#define FLEXSPI_1PAD 0U +#define FLEXSPI_2PAD 1U +#define FLEXSPI_4PAD 2U +#define FLEXSPI_8PAD 3U + +/*! + * NOR LUT sequence index used for default LUT assignment. + * + * @note It will take effect if the lut sequences are not customized. + */ +#define NOR_CMD_LUT_SEQ_IDX_READ 0U /*!< READ LUT sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS 1U /*!< Read Status LUT sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ + 2U /*!< Read status DPI/QPI/OPI sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE 3U /*!< Write Enable sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ + 4U /*!< Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5U /*!< Erase Sector sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_READID 7U +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8U /*!< Erase Block sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM 9U /*!< Program sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11U /*!< Chip Erase sequence in lookupTable id stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13U /*!< Read SFDP sequence in lookupTable id stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ + 14U /*!< Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block */ +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ + 15U /*!< Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block */ + +/*! + * @name Configuration Option + * @{ + */ +/*! @brief Serial NOR Configuration Option. */ +typedef struct _serial_nor_config_option +{ + union + { + struct + { + uint32_t max_freq : 4; /*!< Maximum supported Frequency */ + uint32_t misc_mode : 4; /*!< miscellaneous mode */ + uint32_t quad_mode_setting : 4; /*!< Quad mode setting */ + uint32_t cmd_pads : 4; /*!< Command pads */ + uint32_t query_pads : 4; /*!< SFDP read pads */ + uint32_t device_type : 4; /*!< Device type */ + uint32_t option_size : 4; /*!< Option size, in terms of uint32_t, size = (option_size + 1) * 4 */ + uint32_t tag : 4; /*!< Tag, must be 0x0E */ + } B; + uint32_t U; + } option0; + + union + { + struct + { + uint32_t dummy_cycles : 8; /*!< Dummy cycles before read */ + uint32_t status_override : 8; /*!< Override status register value during device mode configuration */ + uint32_t pinmux_group : 4; /*!< The pinmux group selection */ + uint32_t dqs_pinmux_group : 4; /*!< The DQS Pinmux Group Selection */ + uint32_t drive_strength : 4; /*!< The Drive Strength of FlexSPI Pads */ + uint32_t flash_connection : 4; /*!< Flash connection option: 0 - Single Flash connected to port A, 1 - + Parallel mode, 2 - Single Flash connected to Port B */ + } B; + uint32_t U; + } option1; + +} serial_nor_config_option_t; + +/*@}*/ + +/*! + * @name Support for init FLEXSPI NOR configuration + * @{ + */ +/*! @brief Flash Pad Definitions */ +enum +{ + kSerialFlash_1Pad = 1U, /*!< 1-wire communication */ + kSerialFlash_2Pads = 2U, /*!< 2-wire communication */ + kSerialFlash_4Pads = 4U, /*!< 4-wire communication */ + kSerialFlash_8Pads = 8U, /*!< 8-wire communication */ +}; + +/*! @brief FLEXSPI clock configuration type */ +enum +{ + kFLEXSPIClk_SDR, /*!< Clock configure for SDR mode */ + kFLEXSPIClk_DDR, /*!< Clock configure for DDR mode */ +}; + +/*! @brief FLEXSPI Read Sample Clock Source definition */ +enum _flexspi_read_sample_clk +{ + kFLEXSPIReadSampleClk_LoopbackInternally = 0U, /*!< FLEXSPI Read Sample Clock Source from the Internal loopback */ + kFLEXSPIReadSampleClk_LoopbackFromDqsPad = 1U, /*!< FLEXSPI Read Sample Clock Source from the Dqs Pad loopback */ + kFLEXSPIReadSampleClk_LoopbackFromSckPad = 2U, /*!< FLEXSPI Read Sample Clock Source from the Sck Pad loopback */ + kFLEXSPIReadSampleClk_ExternalInputFromDqsPad = 3U, /*!< FLEXSPI Read Sample Clock Source from the External Input + by the Dqs Pad */ +}; + +/*! @brief Flash Type Definition */ +enum +{ + kFLEXSPIDeviceType_SerialNOR = 1U, /*!< Flash device is Serial NOR */ +}; + +/*! @brief Flash Configuration Command Type */ +enum +{ + kDeviceConfigCmdType_Generic, /*!< Generic command, for example: configure dummy cycles, drive strength, etc. */ + kDeviceConfigCmdType_QuadEnable, /*!< Quad Enable command */ + kDeviceConfigCmdType_Spi2Xpi, /*!< Switch from SPI to DPI/QPI/OPI mode */ + kDeviceConfigCmdType_Xpi2Spi, /*!< Switch from DPI/QPI/OPI to SPI mode */ + kDeviceConfigCmdType_Spi2NoCmd, /*!< Switch to 0-4-4/0-8-8 mode */ + kDeviceConfigCmdType_Reset, /*!< Reset device command */ +}; + +/*! @brief Definitions for FLEXSPI Serial Clock Frequency */ +enum _flexspi_serial_clk_freq +{ + kFLEXSPISerialClk_NoChange = 0U, /*!< FlexSPI serial clock no changed */ + kFLEXSPISerialClk_30MHz = 1U, /*!< FlexSPI serial clock 30MHz */ + kFLEXSPISerialClk_50MHz = 2U, /*!< FlexSPI serial clock 50MHz */ + kFLEXSPISerialClk_60MHz = 3U, /*!< FlexSPI serial clock 60MHz */ + kFLEXSPISerialClk_75MHz = 4U, /*!< FlexSPI serial clock 75MHz */ + kFLEXSPISerialClk_80MHz = 5U, /*!< FlexSPI serial clock 80MHz */ + kFLEXSPISerialClk_100MHz = 6U, /*!< FlexSPI serial clock 100MHz */ + kFLEXSPISerialClk_133MHz = 7U, /*!< FlexSPI serial clock 133MHz */ + kFLEXSPISerialClk_166MHz = 8U, /*!< FlexSPI serial clock 166MHz */ +}; + +/*! @brief Misc feature bit definitions */ +enum +{ + kFLEXSPIMiscOffset_DiffClkEnable = 0U, /*!< Bit for Differential clock enable */ + kFLEXSPIMiscOffset_Ck2Enable = 1U, /*!< Bit for CK2 enable */ + kFLEXSPIMiscOffset_ParallelEnable = 2U, /*!< Bit for Parallel mode enable */ + kFLEXSPIMiscOffset_WordAddressableEnable = 3U, /*!< Bit for Word Addressable enable */ + kFLEXSPIMiscOffset_SafeConfigFreqEnable = 4U, /*!< Bit for Safe Configuration Frequency enable */ + kFLEXSPIMiscOffset_PadSettingOverrideEnable = 5U, /*!< Bit for Pad setting override enable */ + kFLEXSPIMiscOffset_DdrModeEnable = 6U, /*!< Bit for DDR clock configuration indication. */ + kFLEXSPIMiscOffset_UseValidTimeForAllFreq = 7U, /*!< Bit for DLLCR settings under all modes */ +}; + +/*@}*/ + +/*! @brief Manufacturer ID */ +enum +{ + kSerialFlash_ISSI_ManufacturerID = 0x9DU, /*!< Manufacturer ID of the ISSI serial flash */ + kSerialFlash_Adesto_ManufacturerID = 0x1F, /*!< Manufacturer ID of the Adesto Technologies serial flash*/ + kSerialFlash_Winbond_ManufacturerID = 0xEFU, /*!< Manufacturer ID of the Winbond serial flash */ + kSerialFlash_Cypress_ManufacturerID = 0x01U, /*!< Manufacturer ID for Cypress */ +}; + +/*! @brief ROM FLEXSPI NOR flash status */ +enum _flexspi_nor_status +{ + kStatus_ROM_FLEXSPI_SequenceExecutionTimeout = + MAKE_STATUS(kStatusGroup_FLEXSPI, 0), /*!< Status for Sequence Execution timeout */ + kStatus_ROM_FLEXSPI_InvalidSequence = MAKE_STATUS(kStatusGroup_FLEXSPI, 1), /*!< Status for Invalid Sequence */ + kStatus_ROM_FLEXSPI_DeviceTimeout = MAKE_STATUS(kStatusGroup_FLEXSPI, 2), /*!< Status for Device timeout */ + kStatus_ROM_FLEXSPINOR_SFDP_NotFound = + MAKE_STATUS(kROM_StatusGroup_FLEXSPINOR, 7), /*!< Status for SFDP read failure */ + kStatus_ROM_FLEXSPINOR_Flash_NotFound = + MAKE_STATUS(kROM_StatusGroup_FLEXSPINOR, 9), /*!< Status for Flash detection failure */ + kStatus_FLEXSPINOR_DTRRead_DummyProbeFailed = + MAKE_STATUS(kROM_StatusGroup_FLEXSPINOR, 10), /*!< Status for DDR Read dummy probe failure */ +}; + +/*! + * @name FLEXSPI NOR Configuration + * @{ + */ + +/*! @brief FLEXSPI LUT Sequence structure */ +typedef struct _flexspi_lut_seq +{ + uint8_t seqNum; /*!< Sequence Number, valid number: 1-16 */ + uint8_t seqId; /*!< Sequence Index, valid number: 0-15 */ + uint16_t reserved; +} flexspi_lut_seq_t; + +/*! @brief FLEXSPI DLL time */ +typedef struct +{ + uint8_t time_100ps; /*!< Data valid time, in terms of 100ps */ + uint8_t delay_cells; /*!< Data valid time, in terms of delay cells */ +} flexspi_dll_time_t; + +/*! @brief FLEXSPI Memory Configuration Block */ +typedef struct _flexspi_mem_config +{ + uint32_t tag; /*!< [0x000-0x003] Tag, fixed value 0x42464346UL */ + uint32_t version; /*!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix */ + uint32_t reserved0; /*!< [0x008-0x00b] Reserved for future use */ + uint8_t readSampleClkSrc; /*!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 */ + uint8_t csHoldTime; /*!< [0x00d-0x00d] Data hold time, default value: 3 */ + uint8_t csSetupTime; /*!< [0x00e-0x00e] Date setup time, default value: 3 */ + uint8_t columnAddressWidth; /*!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For + Serial NAND, need to refer to datasheet */ + uint8_t deviceModeCfgEnable; /*!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable */ + uint8_t deviceModeType; /*!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, + Generic configuration, etc. */ + uint16_t waitTimeCfgCommands; /*!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for + DPI/QPI/OPI switch or reset command */ + flexspi_lut_seq_t deviceModeSeq; /*!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt + sequence number, [31:16] Reserved */ + uint32_t deviceModeArg; /*!< [0x018-0x01b] Argument/Parameter for device configuration */ + uint8_t configCmdEnable; /*!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable */ + uint8_t configModeType[3]; /*!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe */ + flexspi_lut_seq_t + configCmdSeqs[3]; /*!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq */ + uint32_t reserved1; /*!< [0x02c-0x02f] Reserved for future use */ + uint32_t configCmdArgs[3]; /*!< [0x030-0x03b] Arguments/Parameters for device Configuration commands */ + uint32_t reserved2; /*!< [0x03c-0x03f] Reserved for future use */ + uint32_t controllerMiscOption; /*!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more + details */ + uint8_t deviceType; /*!< [0x044-0x044] Device Type: See Flash Type Definition for more details */ + uint8_t sflashPadType; /*!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal */ + uint8_t serialClkFreq; /*!< [0x046-0x046] Serial Flash Frequency, device specific definitions. See System Boot + Chapter for more details */ + uint8_t + lutCustomSeqEnable; /*!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot + be done using 1 LUT sequence, currently, only applicable to HyperFLASH */ + uint32_t reserved3[2]; /*!< [0x048-0x04f] Reserved for future use */ + uint32_t sflashA1Size; /*!< [0x050-0x053] Size of Flash connected to A1 */ + uint32_t sflashA2Size; /*!< [0x054-0x057] Size of Flash connected to A2 */ + uint32_t sflashB1Size; /*!< [0x058-0x05b] Size of Flash connected to B1 */ + uint32_t sflashB2Size; /*!< [0x05c-0x05f] Size of Flash connected to B2 */ + uint32_t csPadSettingOverride; /*!< [0x060-0x063] CS pad setting override value */ + uint32_t sclkPadSettingOverride; /*!< [0x064-0x067] SCK pad setting override value */ + uint32_t dataPadSettingOverride; /*!< [0x068-0x06b] data pad setting override value */ + uint32_t dqsPadSettingOverride; /*!< [0x06c-0x06f] DQS pad setting override value */ + uint32_t timeoutInMs; /*!< [0x070-0x073] Timeout threshold for read status command */ + uint32_t commandInterval; /*!< [0x074-0x077] CS deselect interval between two commands */ + flexspi_dll_time_t dataValidTime[2]; /*!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B */ + uint16_t busyOffset; /*!< [0x07c-0x07d] Busy offset, valid value: 0-31 */ + uint16_t busyBitPolarity; /*!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - + busy flag is 0 when flash device is busy */ + uint32_t lookupTable[64]; /*!< [0x080-0x17f] Lookup table holds Flash command sequences */ + flexspi_lut_seq_t lutCustomSeq[12]; /*!< [0x180-0x1af] Customizable LUT Sequences */ + uint32_t reserved4[4]; /*!< [0x1b0-0x1bf] Reserved for future use */ +} flexspi_mem_config_t; + +/*! @brief Serial NOR configuration block */ +typedef struct _flexspi_nor_config +{ + flexspi_mem_config_t memConfig; /*!< Common memory configuration info via FLEXSPI */ + uint32_t pageSize; /*!< Page size of Serial NOR */ + uint32_t sectorSize; /*!< Sector size of Serial NOR */ + uint8_t ipcmdSerialClkFreq; /*!< Clock frequency for IP command */ + uint8_t isUniformBlockSize; /*!< Sector/Block size is the same */ + uint8_t isDataOrderSwapped; /*!< Data order (D0, D1, D2, D3) is swapped (D1,D0, D3, D2) */ + uint8_t reserved0[1]; /*!< Reserved for future use */ + uint8_t serialNorType; /*!< Serial NOR Flash type: 0/1/2/3 */ + uint8_t needExitNoCmdMode; /*!< Need to exit NoCmd mode before other IP command */ + uint8_t halfClkForNonReadCmd; /*!< Half the Serial Clock for non-read command: true/false */ + uint8_t needRestoreNoCmdMode; /*!< Need to Restore NoCmd mode after IP command execution */ + uint32_t blockSize; /*!< Block size */ + uint32_t reserve2[11]; /*!< Reserved for future use */ +} flexspi_nor_config_t; + +/*@}*/ + +/*! @brief FLEXSPI Operation Context */ +typedef enum _flexspi_operation +{ + kFLEXSPIOperation_Command, /*!< FLEXSPI operation: Only command, both TX and RX buffer are ignored. */ + kFLEXSPIOperation_Config, /*!< FLEXSPI operation: Configure device mode, the TX FIFO size is fixed in LUT. */ + kFLEXSPIOperation_Write, /*!< FLEXSPI operation: Write, only TX buffer is effective */ + kFLEXSPIOperation_Read, /*!< FLEXSPI operation: Read, only Rx Buffer is effective. */ +} flexspi_operation_t; + +#define kFLEXSPIOperation_End kFLEXSPIOperation_Read + +/*! @brief FLEXSPI Transfer Context */ +typedef struct _flexspi_xfer +{ + flexspi_operation_t operation; /*!< FLEXSPI operation */ + uint32_t baseAddress; /*!< FLEXSPI operation base address */ + uint32_t seqId; /*!< Sequence Id */ + uint32_t seqNum; /*!< Sequence Number */ + bool isParallelModeEnable; /*!< Is a parallel transfer */ + uint32_t *txBuffer; /*!< Tx buffer */ + uint32_t txSize; /*!< Tx size in bytes */ + uint32_t *rxBuffer; /*!< Rx buffer */ + uint32_t rxSize; /*!< Rx size in bytes */ +} flexspi_xfer_t; + +/*! @brief convert the type for MISRA */ +#define MISRA_CAST(to_type, to_var, from_type, from_var) \ + do \ + { \ + union \ + { \ + to_type to_var_tmp; \ + from_type from_var_tmp; \ + } type_converter_var = {.from_var_tmp = (from_var)}; \ + (to_var) = type_converter_var.to_var_tmp; \ + } while (false) + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(FSL_FEATURE_BOOT_ROM_HAS_ROMAPI) && FSL_FEATURE_BOOT_ROM_HAS_ROMAPI + +/*! + * @name Enter Bootloader + * @{ + */ + +#if defined(FSL_ROM_HAS_RUNBOOTLOADER_API) && FSL_ROM_HAS_RUNBOOTLOADER_API +/*! + * @brief Enter Bootloader. + * + * @param arg A pointer to the storage for the bootloader param. + * refer to System Boot Chapter in device reference manual for details. + */ +void ROM_RunBootloader(void *arg); +#endif /* FSL_ROM_HAS_RUNBOOTLOADER_API */ + +/*@}*/ + +/*! + * @name GetConfig + * @{ + */ +#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_GET_CONFIG) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_GET_CONFIG +/*! + * @brief Get FLEXSPI NOR Configuration Block based on specified option. + * + * @param instance storage the instance of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * @param option A pointer to the storage Serial NOR Configuration Option Context. + * + * @retval kStatus_Success Api was executed successfully. + * @retval kStatus_InvalidArgument A invalid argument is provided. + * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout + */ +status_t ROM_FLEXSPI_NorFlash_GetConfig(uint32_t instance, + flexspi_nor_config_t *config, + serial_nor_config_option_t *option); +#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_GET_CONFIG */ + +/*! + * @name Initialization + * @{ + */ + +/*! + * @brief Initialize Serial NOR devices via FLEXSPI + * + * This function checks and initializes the FLEXSPI module for the other FLEXSPI APIs. + * + * @param instance storage the instance of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * + * @retval kStatus_Success Api was executed successfully. + * @retval kStatus_InvalidArgument A invalid argument is provided. + * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout + */ +status_t ROM_FLEXSPI_NorFlash_Init(uint32_t instance, flexspi_nor_config_t *config); + +/*@}*/ + +/*! + * @name Programming + * @{ + */ + +/*! + * @brief Program data to Serial NOR via FLEXSPI. + * + * This function programs the NOR flash memory with the dest address for a given + * flash area as determined by the dst address and the length. + * + * @param instance storage the instance of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * @param dst_addr A pointer to the desired flash memory to be programmed. + * @note It is recommended that use page aligned access; + * If the dst_addr is not aligned to page, the driver automatically + * aligns address down with the page address. + * @param src A pointer to the source buffer of data that is to be programmed + * into the NOR flash. + * + * @retval kStatus_Success Api was executed successfully. + * @retval kStatus_InvalidArgument A invalid argument is provided. + * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout + */ +status_t ROM_FLEXSPI_NorFlash_ProgramPage(uint32_t instance, + flexspi_nor_config_t *config, + uint32_t dst_addr, + const uint32_t *src); + +/*@}*/ + +/*! + * @name Reading + * @{ + */ + +#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_READ) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_READ +/*! + * @brief Read data from Serial NOR via FLEXSPI. + * + * This function read the NOR flash memory with the start address for a given + * flash area as determined by the dst address and the length. + * + * @param instance storage the instance of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * @param dst A pointer to the dest buffer of data that is to be read from the NOR flash. + * @note It is recommended that use page aligned access; + * If the dstAddr is not aligned to page, the driver automatically + * aligns address down with the page address. + * @param start The start address of the desired NOR flash memory to be read. + * @param lengthInBytes The length, given in bytes to be read. + * + * @retval kStatus_Success Api was executed successfully. + * @retval kStatus_InvalidArgument A invalid argument is provided. + * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout + */ +status_t ROM_FLEXSPI_NorFlash_Read( + uint32_t instance, flexspi_nor_config_t *config, uint32_t *dst, uint32_t start, uint32_t lengthInBytes); +#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_READ */ + +/*@}*/ + +/*! + * @name Erasing + * @{ + */ + +/*! + * @brief Erase Flash Region specified by address and length + * + * This function erases the appropriate number of flash sectors based on the + * desired start address and length. + * + * @param instance storage the index of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired NOR flash memory to be erased. + * @note It is recommended that use sector-aligned access nor device; + * If dstAddr is not aligned with the sector,the driver automatically + * aligns address down with the sector address. + * @param length The length, given in bytes to be erased. + * @note It is recommended that use sector-aligned access nor device; + * If length is not aligned with the sector,the driver automatically + * aligns up with the sector. + * @retval kStatus_Success Api was executed successfully. + * @retval kStatus_InvalidArgument A invalid argument is provided. + * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout + */ +status_t ROM_FLEXSPI_NorFlash_Erase(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length); + +#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR +/*! + * @brief Erase one sector specified by address + * + * This function erases one of NOR flash sectors based on the desired address. + * + * @param instance storage the index of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired NOR flash memory to be erased. + * @note It is recommended that use sector-aligned access nor device; + * If dstAddr is not aligned with the sector, the driver automatically + * aligns address down with the sector address. + * + * @retval kStatus_Success Api was executed successfully. + * @retval kStatus_InvalidArgument A invalid argument is provided. + * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout + */ +status_t ROM_FLEXSPI_NorFlash_EraseSector(uint32_t instance, flexspi_nor_config_t *config, uint32_t start); +#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR */ + +#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_BLOCK) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_BLOCK +/*! + * @brief Erase one block specified by address + * + * This function erases one block of NOR flash based on the desired address. + * + * @param instance storage the index of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired NOR flash memory to be erased. + * @note It is recommended that use block-aligned access nor device; + * If dstAddr is not aligned with the block, the driver automatically + * aligns address down with the block address. + * + * @retval kStatus_Success Api was executed successfully. + * @retval kStatus_InvalidArgument A invalid argument is provided. + * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout + */ +status_t ROM_FLEXSPI_NorFlash_EraseBlock(uint32_t instance, flexspi_nor_config_t *config, uint32_t start); +#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_BLOCK */ + +#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_ALL) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_ALL +/*! + * @brief Erase all the Serial NOR devices connected on FLEXSPI. + * + * @param instance storage the instance of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * + * @retval kStatus_Success Api was executed successfully. + * @retval kStatus_InvalidArgument A invalid argument is provided. + * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout + */ +status_t ROM_FLEXSPI_NorFlash_EraseAll(uint32_t instance, flexspi_nor_config_t *config); +#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_ALL */ + +/*@}*/ + +/*! + * @name Command + * @{ + */ +#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER +/*! + * @brief FLEXSPI command + * + * This function is used to perform the command write sequence to the NOR device. + * + * @param instance storage the index of FLEXSPI. + * @param xfer A pointer to the storage FLEXSPI Transfer Context. + * + * @retval kStatus_Success Api was executed successfully. + * @retval kStatus_InvalidArgument A invalid argument is provided. + * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + */ +status_t ROM_FLEXSPI_NorFlash_CommandXfer(uint32_t instance, flexspi_xfer_t *xfer); +#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER */ +/*@}*/ + +/*! + * @name UpdateLut + * @{ + */ +#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT +/*! + * @brief Configure FLEXSPI Lookup table + * + * @param instance storage the index of FLEXSPI. + * @param seqIndex storage the sequence Id. + * @param lutBase A pointer to the look-up-table for command sequences. + * @param seqNumber storage sequence number. + * + * @retval kStatus_Success Api was executed successfully. + * @retval kStatus_InvalidArgument A invalid argument is provided. + * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + */ +status_t ROM_FLEXSPI_NorFlash_UpdateLut(uint32_t instance, + uint32_t seqIndex, + const uint32_t *lutBase, + uint32_t seqNumber); +#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT */ + +/*@}*/ + +/*! + * @name Device status + * @{ + */ +/*! + * @brief Wait until device is idle. + * + * @param instance Indicates the index of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state + * @param isParallelMode Indicates whether NOR flash is in parallel mode. + * @param address Indicates the operation(erase/program/read) address for serial NOR flash. + * + * @retval kStatus_Success Api was executed successfully. + * @retval kStatus_InvalidArgument A invalid argument is provided. + * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval kStatus_ROM_FLEXSPI_DeviceTimeout Device timeout. + */ +status_t ROM_FLEXSPI_NorFlash_WaitBusy(uint32_t instance, + flexspi_nor_config_t *config, + bool isParallelMode, + uint32_t address); +/*@}*/ + +/*! + * @name ClearCache + * @{ + */ + +/*! + * @name ClearCache + * @{ + */ + +/*! + * @brief Software reset for the FLEXSPI logic. + * + * This function sets the software reset flags for both AHB and buffer domain and + * resets both AHB buffer and also IP FIFOs. + * + * @param instance storage the index of FLEXSPI. + */ +void ROM_FLEXSPI_NorFlash_ClearCache(uint32_t instance); + +/*@}*/ + +#endif /* FSL_FEATURE_BOOT_ROM_HAS_ROMAPI */ + +#ifdef __cplusplus +} +#endif + +/*! @}*/ + +#endif /* _FSL_ROMAPI_H_ */ diff --git a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_soc_mipi_csi2rx.c b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_soc_mipi_csi2rx.c new file mode 100644 index 0000000000..f945b28e4a --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_soc_mipi_csi2rx.c @@ -0,0 +1,71 @@ +/* + * Copyright 2019-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_soc_mipi_csi2rx.h" +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.soc_mipi_csi2rx" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +void MIPI_CSI2RX_SoftwareReset(MIPI_CSI2RX_Type *base, bool reset) +{ + if (reset) + { + IOMUXC_GPR->GPR59 &= ~IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK; + } + else + { + IOMUXC_GPR->GPR59 |= IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK; + } +} + +void MIPI_CSI2RX_InitInterface(MIPI_CSI2RX_Type *base, uint8_t tHsSettle_EscClk) +{ + /* Pixel link control */ + VIDEO_MUX->PLM_CTRL.RW = 0U; + + IOMUXC_GPR->GPR59 = (IOMUXC_GPR->GPR59 & ~(IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_MASK)) | + IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_MASK | /* Enable RX. */ + IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_MASK | /* Auto power down unused lanes. */ + IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK | IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_MASK | + IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_MASK | /* Enable the DDR clock. */ + IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_MASK | /* Continue clock. */ + IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE(tHsSettle_EscClk - 1UL); /* T(HS-SETTLE) */ + + /* Don't mask any data type */ + VIDEO_MUX->CFG_DT_DISABLE.RW = 0U; + + /* Enable pixel link master. */ + VIDEO_MUX->PLM_CTRL.SET = (VIDEO_MUX_PLM_CTRL_ENABLE_MASK | VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_MASK); + + /* Power up PHY. */ + IOMUXC_GPR->GPR59 &= ~IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_MASK; +} + +void MIPI_CSI2RX_DeinitInterface(MIPI_CSI2RX_Type *base) +{ + IOMUXC_GPR->GPR59 = (IOMUXC_GPR->GPR59 & (~IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_MASK)) | IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_MASK; + + /* Pixel link control */ + VIDEO_MUX->PLM_CTRL.RW = 0U; +} diff --git a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_soc_mipi_csi2rx.h b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_soc_mipi_csi2rx.h new file mode 100644 index 0000000000..d82023802d --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_soc_mipi_csi2rx.h @@ -0,0 +1,66 @@ +/* + * Copyright 2019-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_SOC_MIPI_CSI2RX_H_ +#define _FSL_SOC_MIPI_CSI2RX_H_ + +#include "fsl_common.h" + +/*! @addtogroup soc_mipi_csi2rx */ +/*! @{ */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Driver version. */ +#define FSL_SOC_MIPI_CSI2RX_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @brief Assert or deassert CSI2RX reset in system level. + * + * @param base The CSI2RX peripheral base address. + * @param reset Pass in true to set to reset state, false to release reset. + * @note Don't call this function directly. + */ +void MIPI_CSI2RX_SoftwareReset(MIPI_CSI2RX_Type *base, bool reset); + +/*! + * @brief Initialize the CSI2RX interface. + * + * @param base The CSI2RX peripheral base address. + * @param tHsSettle_EscClk t-HS_SETTLE in esc clock period. + * @note Don't call this function directly. + */ +void MIPI_CSI2RX_InitInterface(MIPI_CSI2RX_Type *base, uint8_t tHsSettle_EscClk); + +/*! + * @brief Deinitialize the CSI2RX interface. + * + * @param base The CSI2RX peripheral base address. + * @note Don't call this function directly. + */ +void MIPI_CSI2RX_DeinitInterface(MIPI_CSI2RX_Type *base); + +/* @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_SOC_MIPI_CSI2RX_H_ */ diff --git a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_soc_src.c b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_soc_src.c new file mode 100644 index 0000000000..36fe004d3d --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_soc_src.c @@ -0,0 +1,183 @@ +/* + * Copyright 2019-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_soc_src.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.soc_src" +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define SRC_GLOBAL_SYSTEM_RESET_BEHAVIOR_MASK (0x3U) +#define SRC_GLOBAL_SYSTEM_RESET_BEHAVIOR_CONFIG(resetSource, resetMode) \ + ((uint32_t)(resetMode) << (uint32_t)(resetSource)) + +#define SRC_SLICE_CTRL_SW_RESET_MASK (0x1U) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Release related core reset operation. + * + * The core reset will be held until boot core to release it. + * + * param base SRC peripheral base address. + * param coreName The name of the reset core to be released. + */ +void SRC_ReleaseCoreReset(SRC_Type *base, src_core_name_t coreName) +{ + uint32_t coreMaskArray[] = {SRC_SCR_BT_RELEASE_M7_MASK, SRC_SCR_BT_RELEASE_M4_MASK}; + uint32_t regValue; + + regValue = base->SCR; + + if ((regValue & coreMaskArray[((uint32_t)coreName) - 1UL]) == 0UL) + { + base->SCR |= coreMaskArray[((uint32_t)coreName) - 1UL]; + } +} + +/*! + * brief Sets the reset mode of global system reset source. + * + * This function sets the selected mode of the input global system reset sources. This function will return as soon as + * the reset if finished. + * + * param base SRC peripheral base address. + * param resetSource The global system reset source. See @ref src_global_system_reset_source_t for more details. + * param resetMode The reset mode of each reset source. See @ref src_global_system_reset_mode_t for more details. + */ +void SRC_SetGlobalSystemResetMode(SRC_Type *base, + src_global_system_reset_source_t resetSource, + src_global_system_reset_mode_t resetMode) +{ + uint32_t regValue; + + regValue = base->SRMR; + regValue &= ~SRC_GLOBAL_SYSTEM_RESET_BEHAVIOR_CONFIG(resetSource, SRC_GLOBAL_SYSTEM_RESET_BEHAVIOR_MASK); + regValue |= SRC_GLOBAL_SYSTEM_RESET_BEHAVIOR_CONFIG(resetSource, resetMode); + + base->SRMR = regValue; +} + +/*! + * brief Asserts software reset for the selected slice. + * + * param base SRC peripheral base address. + * param sliceName The selected reset slice. See @ref src_reset_slice_name_t for more details. + */ +void SRC_AssertSliceSoftwareReset(SRC_Type *base, src_reset_slice_name_t sliceName) +{ + uint32_t regAddress; + uint32_t sliceStatusRegAddress; + + regAddress = SRC_GET_SLICE_REGISTER_ADDRESS(base, sliceName, SRC_SLICE_CONTROL_REGISTER_OFFSET); + sliceStatusRegAddress = SRC_GET_SLICE_REGISTER_ADDRESS(base, sliceName, SRC_SLICE_STATUS_REGISTER_OFFSET); + + *(volatile uint32_t *)regAddress |= SRC_SLICE_CTRL_SW_RESET_MASK; + + while (((*(volatile uint32_t *)sliceStatusRegAddress) & SRC_SLICE_STAT_UNDER_RST_MASK) != 0UL) + { + ; + } +} + +/*! + * brief Locks the value of SETPOINT_MODE and DOMAIN_MODE for the selected reset slice. + * + * param base SRC peripheral base address. + * param sliceName The selected reset slice. See @ref src_reset_slice_name_t for more details. + */ +void SRC_LockSliceMode(SRC_Type *base, src_reset_slice_name_t sliceName) +{ + uint32_t authenticationRegAddress; + + authenticationRegAddress = + SRC_GET_SLICE_REGISTER_ADDRESS(base, sliceName, SRC_SLICE_AUTHENTICATION_REGISTER_OFFSET); + + *(volatile uint32_t *)authenticationRegAddress |= SRC_SLICE_AUTHEN_LOCK_MODE_MASK; +} + +/*! + * brief Sets setpoint configuration for the selected reset slice. + * + * param base SRC peripheral base address. + * param sliceName The selected reset slice. See @ref src_reset_slice_name_t for more details. + * param setPointConfig The logic OR'ed value of @ref _src_setpoint_selection. When the system in the selected setpoint + * slice reset will be assert. + */ +void SRC_SetSliceSetPointConfig(SRC_Type *base, src_reset_slice_name_t sliceName, uint32_t setpointConfig) +{ + uint32_t setpointConfigRegAddress; + + setpointConfigRegAddress = + SRC_GET_SLICE_REGISTER_ADDRESS(base, sliceName, SRC_SLICE_SETPOINT_CONFIG_REGISTER_OFFSET); + + if (setpointConfig != 0UL) + { + *(volatile uint32_t *)setpointConfigRegAddress = setpointConfig; + } +} + +/*! + * brief Sets domain mode configuration for the selected reset slice. + * + * param base SRC peripheral base address. + * param sliceName The selected reset slice. See src_reset_slice_name_t for more details. + * param domainConfig The logic OR'ed value of _src_domain_mode_selection. + */ +void SRC_SetSliceDomainModeConfig(SRC_Type *base, src_reset_slice_name_t sliceName, uint32_t domainConfig) +{ + uint32_t domainConfigRegAddress; + + domainConfigRegAddress = SRC_GET_SLICE_REGISTER_ADDRESS(base, sliceName, SRC_SLICE_DOMAIN_CONFIG_REGISTER_OFFSET); + + if (domainConfig != 0UL) + { + *(volatile uint32_t *)domainConfigRegAddress = domainConfig; + } +} + +/*! + * brief Gets the reset state of the selected slice. + * + * param base SRC peripheral base address. + * param sliceName The selected slice. See @ref src_reset_slice_name_t for more details. + * retval kSRC_SliceResetInProcess The reset is in process. + * retval kSRC_SliceResetFinished The reset is finished. + */ +src_slice_reset_state_t SRC_GetSliceResetState(SRC_Type *base, src_reset_slice_name_t sliceName) +{ + uint32_t statusRegAddress; + src_slice_reset_state_t ret; + + statusRegAddress = SRC_GET_SLICE_REGISTER_ADDRESS(base, sliceName, SRC_SLICE_STATUS_REGISTER_OFFSET); + + if (((*(uint32_t *)statusRegAddress) & SRC_SLICE_STAT_UNDER_RST_MASK) != 0UL) + { + ret = kSRC_SliceResetInProcess; + } + else + { + ret = kSRC_SliceResetFinished; + } + + return ret; +} diff --git a/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_soc_src.h b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_soc_src.h new file mode 100644 index 0000000000..1a8a85c8c4 --- /dev/null +++ b/bsps/arm/imxrt/mcux-sdk/devices/MIMXRT1166/drivers/fsl_soc_src.h @@ -0,0 +1,754 @@ +/* + * Copyright 2019-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_SRC_H_ +#define _FSL_SRC_H_ + +#include "fsl_common.h" + +/*! @addtogroup soc_src */ +/*! @{ */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief SRC driver version 2.1.1. */ +#define FSL_SRC_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) +/*@}*/ + +#define SRC_SLICE_ADDRESS_OFFSET (0x200U) + +#define SRC_SLICE_AUTHENTICATION_REGISTER_OFFSET (0x0U) +#define SRC_SLICE_CONTROL_REGISTER_OFFSET (0x4U) +#define SRC_SLICE_SETPOINT_CONFIG_REGISTER_OFFSET (0x8U) +#define SRC_SLICE_DOMAIN_CONFIG_REGISTER_OFFSET (0x0CU) +#define SRC_SLICE_STATUS_REGISTER_OFFSET (0x10U) + +#define SRC_GET_SLICE_REGISTER_ADDRESS(base, sliceName, registerOffset) \ + (((uint32_t)base) + SRC_SLICE_ADDRESS_OFFSET + ((uint32_t)(sliceName) << 5UL) + (registerOffset)) + +#define SRC_SLICE_STAT_UNDER_RST_MASK (0x1U) +#define SRC_SLICE_STAT_RST_BY_HW_MASK (0x4U) +#define SRC_SLICE_STAT_RST_BY_SW_MASK (0x8U) + +#define SRC_WHITE_LIST_VALUE(coreName) (1UL << (uint32_t)(coreName)) +#define SRC_ASSIGN_LIST_VALUE(coreName) (1UL << (uint32_t)(coreName)) + +#define SRC_SLICE_AUTHEN_DOMAIN_MODE_MASK (0x1U) +#define SRC_SLICE_AUTHEN_SETPOINT_MODE_MASK (0x2U) + +#define SRC_SLICE_AUTHEN_LOCK_MODE_MASK (0x80U) +#define SRC_SLICE_AUTHEN_LOCK_MODE_SHIFT (7U) +#define SRC_SLICE_AUTHEN_LOCK_MODE(x) \ + (((uint32_t)(((uint32_t)(x)) << SRC_SLICE_AUTHEN_LOCK_MODE_SHIFT)) & SRC_SLICE_AUTHEN_LOCK_MODE_MASK) + +#define SRC_SLICE_AUTHEN_ASSIGN_LIST_MASK (0xF00U) +#define SRC_SLICE_AUTHEN_ASSIGN_LIST_SHIFT (8U) +#define SRC_SLICE_AUTHEN_ASSIGN_LIST(x) \ + (((uint32_t)(((uint32_t)(x)) << SRC_SLICE_AUTHEN_ASSIGN_LIST_SHIFT)) & SRC_SLICE_AUTHEN_ASSIGN_LIST_MASK) + +#define SRC_SLICE_AUTHEN_LOCK_ASSIGN_MASK (0x8000U) +#define SRC_SLICE_AUTHEN_LOCK_ASSIGN_SHIFT (15) +#define SRC_SLICE_AUTHEN_LOCK_ASSIGN(x) \ + (((uint32_t)(((uint32_t)(x)) << SRC_SLICE_AUTHEN_LOCK_ASSIGN_SHIFT)) & SRC_SLICE_AUTHEN_LOCK_ASSIGN_MASK) + +#define SRC_SLICE_AUTHEN_WHITE_LIST_MASK (0xF0000U) +#define SRC_SLICE_AUTHEN_WHITE_LIST_SHIFT (16U) +#define SRC_SLICE_AUTHEN_WHITE_LIST(x) \ + (((uint32_t)(((uint32_t)(x)) << SRC_SLICE_AUTHEN_WHITE_LIST_SHIFT)) & SRC_SLICE_AUTHEN_WHITE_LIST_MASK) + +#define SRC_SLICE_AUTHEN_LOCK_LIST_MASK (0x800000U) +#define SRC_SLICE_AUTHEN_LOCK_LIST_SHIFT (23U) +#define SRC_SLICE_AUTHEN_LOCK_LIST(x) \ + (((uint32_t)(((uint32_t)(x)) << SRC_SLICE_AUTHEN_LOCK_LIST_SHIFT)) & SRC_SLICE_AUTHEN_LOCK_LIST_MASK) + +#define SRC_SLICE_AUTHEN_USER_MASK (0x1000000U) +#define SRC_SLICE_AUTHEN_USER_SHIFT (24U) +#define SRC_SLICE_AUTHEN_USER(x) \ + (((uint32_t)(((uint32_t)(x)) << SRC_SLICE_AUTHEN_USER_SHIFT)) & SRC_SLICE_AUTHEN_USER_MASK) + +#define SRC_SLICE_AUTHEN_NONSECURE_MASK (0x2000000U) +#define SRC_SLICE_AUTHEN_NONSECURE_SHIFT (25U) +#define SRC_SLICE_AUTHEN_NONSECURE(x) \ + (((uint32_t)(((uint32_t)(x)) << SRC_SLICE_AUTHEN_NONSECURE_SHIFT)) & SRC_SLICE_AUTHEN_NONSECURE_MASK) + +#define SRC_SLICE_AUTHEN_LOCK_SETTING_MASK (0x80000000U) +#define SRC_SLICE_AUTHEN_LOCK_SETTING_SHIFT (31U) +#define SRC_SLICE_AUTHEN_LOCK_SETTING(x) \ + (((uint32_t)(((uint32_t)(x)) << SRC_SLICE_AUTHEN_LOCK_SETTING_SHIFT)) & SRC_SLICE_AUTHEN_LOCK_SETTING_MASK) + +/*! + * @brief System core. + */ +typedef enum _src_core_name +{ + kSRC_CM7Core = 0x1U, /*!< System Core CM4. */ + kSRC_CM4Core = 0x2U, /*!< System Core CM7. */ +} src_core_name_t; + +/*! + * @brief The enumeration of the boot fuse selection. + */ +typedef enum _src_boot_fuse_selection +{ + kSRC_SerialDownloaderBootFlow = 0U, /*!< The Boot flow jumps directly to the serial downloader. */ + kSRC_NormalBootFlow = 1U /*!< The Boot flow follows the Normal Boot flow. */ +} src_boot_fuse_selection_t; + +/*! + * @brief The enumeration of global system reset sources. + */ +typedef enum _src_global_system_reset_source +{ + kSRC_WdogReset = 0U, /*!< WDOG triggers the global system reset. */ + kSRC_Wdog3Reset = 2U, /*!< WDOG3 triggers the global system reset. */ + kSRC_Wdog4Reset = 4U, /*!< WODG4 triggers the global system reset. */ + kSRC_M4LockUpReset = 6U, /*!< M4 core lockup triggers the global system reset. */ + kSRC_M7LockUpReset = 8U, /*!< M7 core lockup triggers the global system reset. */ + kSRC_M4RequestReset = 10U, /*!< M4 core request triggers the global system reset. */ + kSRC_M7RequestReset = 12U, /*!< M7 core request triggers the global system reset. */ + kSRC_TempsenseReset = 14U, /*!< Tempsense trigggers the global system reset. */ + kSRC_CSUReset = 16U, /*!< CSU triggers the global system reset. */ + kSRC_JageSoftwareReset = 18U, /*!< JATG software triggers the global system reset. */ + kSRC_OverVoltageReset = 20U, /*!< Over voltage triggers the global system reset. */ +} src_global_system_reset_source_t; + +/*! + * @brief The enumeration of reset status flags. + */ +enum _src_global_system_reset_status_flags +{ + kSRC_M7CoreIppResetFlag = 1UL << 0UL, /*!< The M7 Core reset is the result of ipp_reset_b pin. */ + kSRC_M7CoreM7RequestResetFlag = 1UL << 1UL, /*!< The M7 Core reset is the result of M7 core reset request. */ + kSRC_M7CoreM7LockUpResetFlag = 1UL << 2UL, /*!< The M7 Core reset is the result of M7 core lock up. */ + kSRC_M7CoreCSUResetFlag = 1UL << 3UL, /*!< The M7 Core reset is the result of csu_reset_b input. */ + kSRC_M7CoreIppUserResetFlag = 1UL << 4UL, /*!< The M7 Core reset is the result of + ipp_user_reset_b qualified reset. */ + kSRC_M7CoreWdogResetFlag = 1UL << 5UL, /*!< The M7 Core reset is the result of the watchdog time-out event. */ + kSRC_M7CoreJtagResetFlag = 1UL << 6UL, /*!< The M7 Core reset is the result of HIGH-Z reset from JTAG. */ + kSRC_M7CoreJtagSWResetFlag = 1UL << 7UL, /*!< The M7 Core reset is the result of software reset from JTAG. */ + kSRC_M7CoreWdog3ResetFlag = 1UL << 8UL, /*!< The M7 Core reset is the result of watchdog3 time-out event. */ + kSRC_M7CoreWdog4ResetFlag = 1UL << 9UL, /*!< The M7 Core reset is the result of watchdog4 time-out event. */ + kSRC_M7CoreTempsenseResetFlag = 1UL << 10UL, /*!< The M7 Core reset is the result of on-chip temperature sensor. */ + kSRC_M7CoreM4RequestResetFlag = 1UL << 11UL, /*!< The M7 Core reset is the result of M4 CPU reset request. */ + kSRC_M7CoreM4LockUpResetFlag = 1UL << 12UL, /*!< The M7 Core reset is the result of M4 CPU lock up. */ + kSRC_M7CoreOverVoltageResetFlag = 1UL << 13UL, /*!< The M7 Core reset is the result of over voltage. */ + kSRC_M7CoreCdogResetFlag = 1UL << 14UL, /*!< The M7 Core reset is the result of Cdog. */ + + kSRC_M4CoreIppResetFlag = 1UL << 16UL, /*!< The M4 Core reset is the result of ipp_reset_b pin. */ + kSRC_M4CoreM4RequestResetFlag = 1UL << 17UL, /*!< The M4 Core reset is the result of M4 core reset request. */ + kSRC_M4CoreM4LockUpResetFlag = 1UL << 18UL, /*!< The M4 Core reset is the result of M4 core lock up. */ + kSRC_M4CoreCSUResetFlag = 1UL << 19UL, /*!< The M4 Core reset is the result of csu_reset_b input. */ + kSRC_M4CoreIppUserResetFlag = 1UL << 20UL, /*!< The M4 Core reset is the result of + ipp_user_reset_b qualified reset. */ + kSRC_M4CoreWdogResetFlag = 1UL << 21UL, /*!< The M4 Core reset is the result of the watchdog time-out event. */ + kSRC_M4CoreJtagResetFlag = 1UL << 22UL, /*!< The M4 Core reset is the result of HIGH-Z reset from JTAG. */ + kSRC_M4CoreJtagSWResetFlag = 1UL << 23UL, /*!< The M4 Core reset is the result of software reset from JTAG. */ + kSRC_M4CoreWdog3ResetFlag = 1UL << 24UL, /*!< The M4 Core reset is the result of watchdog3 time-out event. */ + kSRC_M4CoreWdog4ResetFlag = 1UL << 25UL, /*!< The M4 Core reset is the result of watchdog4 time-out event. */ + kSRC_M4CoreTempsenseResetFlag = 1UL << 26UL, /*!< The M4 Core reset is the result of on-chip temperature sensor. */ + kSRC_M4CoreM7RequestResetFlag = 1UL << 27UL, /*!< The M4 Core reset is the result of M7 CPU reset request. */ + kSRC_M4CoreM7LockUpResetFlag = 1UL << 28UL, /*!< The M4 Core reset is the result of M7 CPU lock up. */ + kSRC_M4CoreOverVoltageResetFlag = 1UL << 29UL, /*!< The M4 Core reset is the result of over voltage. */ + kSRC_M4CoreCdogResetFlag = 1UL << 30UL, /*!< The M4 Core reset is the result of Cdog. */ +}; + +/*! + * @brief The enumeration of global system reset mode. + */ +typedef enum _src_global_system_reset_mode +{ + kSRC_ResetSystem = 0x0U, /*!< Generate the global system reset. */ + kSRC_DoNotResetSystem = 0x3U, /*!< Do not generate the global system reset. */ +} src_global_system_reset_mode_t; + +/*! + * @brief The enumeration of the slice name. + */ +typedef enum _src_reset_slice_name +{ + kSRC_MegaSlice = 0x0U, /*!< Megamix reset slice. */ + kSRC_DisplaySlice = 0x1U, /*!< Displaymix reset slice. */ + kSRC_WakeUpSlice = 0x2U, /*!< Wakeupmix reset slice. */ + kSRC_LpsrSlice = 0x3U, /*!< Lpsrmix reset slice. */ + kSRC_M4CoreSlice = 0x4U, /*!< M4 core reset slice. */ + kSRC_M7CoreSlice = 0x5U, /*!< M7 core reset slice. */ + kSRC_M4DebugSlice = 0x6U, /*!< M4 debug reset slice. */ + kSRC_M7DebugSlice = 0x7U, /*!< M7 debug reset slice. */ + kSRC_Usbphy1Slice = 0x8U, /*!< USBPHY1 reset slice. */ + kSRC_Usbphy2Slice = 0x9U, /*!< USBPHY2 reset slice. */ +} src_reset_slice_name_t; + +/*! + * @brief The enumeration of the domain mode. + */ +enum _src_domain_mode_selection +{ + kSRC_Cpu0RunModeAssertReset = 1UL << 0UL, /*!< CPU0 in run mode will assert slice reset. */ + kSRC_Cpu0WaitModeAssertReset = 1UL << 1UL, /*!< CPU0 in wait mode will assert reset. */ + kSRC_Cpu0StopModeAssertReset = 1UL << 2UL, /*!< CPU0 in stop mode will assert reset. */ + kSRC_Cpu0SuspendModeAssertReset = 1UL << 3UL, /*!< CPU0 in suspend mode will assert reset. */ + kSRC_Cpu1RunModeAssertReset = 1UL << 4UL, /*!< CPU1 in run mode will assert slice reset. */ + kSRC_Cpu1WaitModeAssertReset = 1UL << 5UL, /*!< CPU1 in wait mode will assert reset. */ + kSRC_Cpu1StopModeAssertReset = 1UL << 6UL, /*!< CPU1 in stop mode will assert reset. */ + kSRC_Cpu1SuspendModeAssertReset = 1UL << 7UL, /*!< CPU1 in suspend mode will assert reset. */ +}; + +/*! + * @brief The enumeration of setpoint. + */ +enum _src_setpoint_selection +{ + kSRC_SetPoint0AssertReset = 1UL << 0UL, /*!< In setpoint0 will assert slice reset. */ + kSRC_SetPoint1AssertReset = 1UL << 1UL, /*!< In setpoint1 will assert slice reset. */ + kSRC_SetPoint2AssertReset = 1UL << 2UL, /*!< In setpoint2 will assert slice reset. */ + kSRC_SetPoint3AssertReset = 1UL << 3UL, /*!< In setpoint3 will assert slice reset. */ + kSRC_SetPoint4AssertReset = 1UL << 4UL, /*!< In setpoint4 will assert slice reset. */ + kSRC_SetPoint5AssertReset = 1UL << 5UL, /*!< In setpoint5 will assert slice reset. */ + kSRC_SetPoint6AssertReset = 1UL << 6UL, /*!< In setpoint6 will assert slice reset. */ + kSRC_SetPoint7AssertReset = 1UL << 7UL, /*!< In setpoint7 will assert slice reset. */ + kSRC_SetPoint8AssertReset = 1UL << 8UL, /*!< In setpoint8 will assert slice reset. */ + kSRC_SetPoint9AssertReset = 1UL << 9UL, /*!< In setpoint9 will assert slice reset. */ + kSRC_SetPoint10AssertReset = 1UL << 10UL, /*!< In setpoint10 will assert slice reset. */ + kSRC_SetPoint11AssertReset = 1UL << 11UL, /*!< In setpoint11 will assert slice reset. */ + kSRC_SetPoint12AssertReset = 1UL << 12UL, /*!< In setpoint12 will assert slice reset. */ + kSRC_SetPoint13AssertReset = 1UL << 13UL, /*!< In setpoint13 will assert slice reset. */ + kSRC_SetPoint14AssertReset = 1UL << 14UL, /*!< In setpoint14 will assert slice reset. */ + kSRC_SetPoint15AssertReset = 1UL << 15UL, /*!< In setpoint15 will assert slice reset. */ +}; + +/*! + * @brief The index of each general purpose register. + */ +typedef enum _src_general_purpose_register_index +{ + kSRC_GeneralPurposeRegister1 = 0U, /*!< The index of General Purpose Register1. */ + kSRC_GeneralPurposeRegister2, /*!< The index of General Purpose Register2. */ + kSRC_GeneralPurposeRegister3, /*!< The index of General Purpose Register3. */ + kSRC_GeneralPurposeRegister4, /*!< The index of General Purpose Register4. */ + kSRC_GeneralPurposeRegister5, /*!< The index of General Purpose Register5. */ + kSRC_GeneralPurposeRegister6, /*!< The index of General Purpose Register6. */ + kSRC_GeneralPurposeRegister7, /*!< The index of General Purpose Register7. */ + kSRC_GeneralPurposeRegister8, /*!< The index of General Purpose Register8. */ + kSRC_GeneralPurposeRegister9, /*!< The index of General Purpose Register9. */ + kSRC_GeneralPurposeRegister10, /*!< The index of General Purpose Register10. */ + kSRC_GeneralPurposeRegister11, /*!< The index of General Purpose Register11. */ + kSRC_GeneralPurposeRegister12, /*!< The index of General Purpose Register12. */ + kSRC_GeneralPurposeRegister13, /*!< The index of General Purpose Register13. */ + kSRC_GeneralPurposeRegister14, /*!< The index of General Purpose Register14. */ + kSRC_GeneralPurposeRegister15, /*!< The index of General Purpose Register15. */ + kSRC_GeneralPurposeRegister16, /*!< The index of General Purpose Register16. */ + kSRC_GeneralPurposeRegister17, /*!< The index of General Purpose Register17. */ + kSRC_GeneralPurposeRegister18, /*!< The index of General Purpose Register18. */ + kSRC_GeneralPurposeRegister19, /*!< The index of General Purpose Register19. */ + kSRC_GeneralPurposeRegister20, /*!< The index of General Purpose Register20. */ +} src_general_purpose_register_index_t; + +/*! + * @brief The structure of setpoint authentication. + */ +typedef struct _src_setpoint_authentication +{ + bool enableSetpointTranferReset; /*!< Control whether reset slice is in setpoint mode. + - \b true Slice hardware reset will be triggered by set point transition. + - \b false Slice hardware reset will not be trigged by set point transition. + */ + uint32_t whiteList; /*!< Select the core to access set point control register. + The logic OR'ed value of @ref src_core_name_t enumeration. */ + bool lockWhiteList; /*!< Control whether lock the value in white list */ + bool lockSetting; /*!< Control whether lock the setpoint access setting. */ + bool allowNonSecureModeAccess; /*!< Allow both secure and non-secure modes to config setpoint. */ + bool allowUserModeAccess; /*!< Allow both privilege and user modes to config setpoint. */ +} src_setpoint_authentication_t; + +/*! + * @brief The stucture of domain mode authentication. + */ +typedef struct _src_domain_mode_authentication +{ + bool enableDomainModeTransferReset; /*!< Control whether reset slice is in domaim mode. + - \b true Slice hardware reset will be triggered by cpu power mode transition. + - \b false Slice hardware reset will not be trigged by cpu power mode + transition. */ + uint32_t assignList; /*!< Select the core that reset of slice would be subject to the selected core status + transition. The logic OR'ed value of @ref src_core_name_t enumeration. */ + bool lockAssignList; /*!< Control whether lock the value in Assign list. */ +} src_domain_mode_authentication_t; + +/*! + * @brief The enumeration of the reset source of each slice. + */ +enum _src_slice_reset_source +{ + kSRC_SoftwareReset = SRC_SLICE_STAT_RST_BY_SW_MASK, /*!< Reset is caused by software setting. */ + kSRC_PowerModeTransferReset = SRC_SLICE_STAT_RST_BY_HW_MASK, /*!< Reset is caused by the power mode transfer. */ +}; + +/*! + * @brief The enumeration of the reset state of each slice. + */ +typedef enum _src_slice_reset_state +{ + kSRC_SliceResetFinished = 0U, /*!< The reset is finished. */ + kSRC_SliceResetInProcess = 1U, /*!< The reset is in process. */ +} src_slice_reset_state_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Core Reset release + * @{ + */ + +/*! + * @brief Releases related core reset operation. + * + * The core reset will be held until the boot core to release it. + * + * @param base SRC peripheral base address. + * @param coreName The name of the reset core to be released. + */ +void SRC_ReleaseCoreReset(SRC_Type *base, src_core_name_t coreName); + +/*! @} */ + +/*! + * @name Latched Boot Arguments Related Interfaces + * @{ + */ + +/*! + * @brief Gets Boot configuration. + * + * @param base SRC peripheral base address. + * @return Boot configuration. Please refer to fusemap. + */ +static inline uint32_t SRC_GetBootConfig(SRC_Type *base) +{ + return base->SBMR1; +} + +/*! + * @brief Gets the latched state of the BOOT_MODE1 and BOOT_MODE0 signals. + * + * @param base SRC peripheral base address. + * @return Boot mode. Please refer to the Boot mode pin setting section of System Boot. + */ +static inline uint8_t SRC_GetBootMode(SRC_Type *base) +{ + return (uint8_t)((base->SBMR2 & SRC_SBMR2_BMOD_MASK) >> SRC_SBMR2_BMOD_SHIFT); +} + +/*! + * @brief Gets the state of the BT_FUSE_SEL fuse. + * + * @param base SRC peripheral base address. + * @return The state of the BT_FUSE_SEL fuse, please refer to fusemap for more information. + */ +static inline src_boot_fuse_selection_t SRC_GetBootFuseSelection(SRC_Type *base) +{ + return (src_boot_fuse_selection_t)(uint32_t)((base->SBMR2 & SRC_SBMR2_BT_FUSE_SEL_MASK) >> + SRC_SBMR2_BT_FUSE_SEL_SHIFT); +} + +/*! + * @brief Gets the state of the SECCONFIG[1] fuse. + * + * @param base SRC peripheral base address. + * @return The state of the SECCONFIG[1] fuse. Please refer to fusemap for more information. + */ +static inline uint8_t SRC_GetSECConfigFuseState(SRC_Type *base) +{ + return (uint8_t)((base->SBMR2 & SRC_SBMR2_SEC_CONFIG_MASK) >> SRC_SBMR2_SEC_CONFIG_SHIFT); +} + +/* ! @} */ + +/*! + * @name Global System Related Interfaces + * @{ + */ + +/*! + * @brief Sets the reset mode of global system reset source. + * + * This function sets the selected mode of the input global system reset sources. + * + * @param base SRC peripheral base address. + * @param resetSource The global system reset source. See @ref src_global_system_reset_source_t for more details. + * @param resetMode The reset mode of each reset source. See @ref src_global_system_reset_mode_t for more details. + */ +void SRC_SetGlobalSystemResetMode(SRC_Type *base, + src_global_system_reset_source_t resetSource, + src_global_system_reset_mode_t resetMode); + +/*! + * @brief Gets global system reset status flags. + * + * @param base SRC peripheral base address. + * @return The status of global system reset status. See @ref _src_global_system_reset_status_flags for more details. + */ +static inline uint32_t SRC_GetResetStatusFlags(SRC_Type *base) +{ + return base->SRSR; +} + +/*! + * @brief Clears the status of global reset. + * + * @param base SRC peripheral base address. + * @param mask The reset status flag to be cleared. See @ref _src_global_system_reset_status_flags for more details. + */ +static inline void SRC_ClearGlobalSystemResetStatus(SRC_Type *base, uint32_t mask) +{ + base->SRSR = mask; +} + +/*! @} */ + +/*! + * @name Slice Software Reset Related Interfaces + * @{ + */ + +/*! + * @brief Asserts software reset for the selected slice. + * + * @note This function will return as soon as the resset is finished. + * + * @param base SRC peripheral base address. + * @param sliceName The slice to be reset. See @ref src_reset_slice_name_t for more details. + */ +void SRC_AssertSliceSoftwareReset(SRC_Type *base, src_reset_slice_name_t sliceName); + +/*! @} */ + +/*! + * @name Slice Low-Power Mode Transition Related Interfaces + * @{ + */ + +/*! + * @brief Allows/disallows user mode access + * + * @param base SRC peripheral base address. + * @param sliceName The slice name to set, please refer to @ref src_reset_slice_name_t for details. + * @param enable Used to control user mode access. + * - \b true Allow user mode access. + * - \b false Disallow user mode access. + */ +static inline void SRC_AllowUserModeAccess(SRC_Type *base, src_reset_slice_name_t sliceName, bool enable) +{ + uint32_t authRegAddr; + + authRegAddr = SRC_GET_SLICE_REGISTER_ADDRESS(base, sliceName, SRC_SLICE_AUTHENTICATION_REGISTER_OFFSET); + + if (enable) + { + *(volatile uint32_t *)authRegAddr |= SRC_SLICE_AUTHEN_USER_MASK; + } + else + { + *(volatile uint32_t *)authRegAddr &= ~SRC_SLICE_AUTHEN_USER_MASK; + } +} + +/*! + * @brief Allows/disallows non secure mode access. + * + * @param base SRC peripheral base address. + * @param sliceName The slice name to set, please refer to @ref src_reset_slice_name_t for details. + * @param enable Used to control non secure mode access. + * - \b true Allow non secure mode access. + * - \b false Disallow non secure mode access. + */ +static inline void SRC_AllowNonSecureModeAccess(SRC_Type *base, src_reset_slice_name_t sliceName, bool enable) +{ + uint32_t authRegAddr; + + authRegAddr = SRC_GET_SLICE_REGISTER_ADDRESS(base, sliceName, SRC_SLICE_AUTHENTICATION_REGISTER_OFFSET); + + if (enable) + { + *(volatile uint32_t *)authRegAddr |= SRC_SLICE_AUTHEN_NONSECURE_MASK; + } + else + { + *(volatile uint32_t *)authRegAddr &= ~SRC_SLICE_AUTHEN_NONSECURE_MASK; + } +} + +/*! + * @brief Locks the setting of user mode access and non secure mode access. + * + * @note Once locked only reset can unlock related settings. + * + * @param base SRC peripheral base address. + * @param sliceName The slice name to set, please refer to @ref src_reset_slice_name_t for details. + */ +static inline void SRC_LockAccessSetting(SRC_Type *base, src_reset_slice_name_t sliceName) +{ + uint32_t authRegAddr; + + authRegAddr = SRC_GET_SLICE_REGISTER_ADDRESS(base, sliceName, SRC_SLICE_AUTHENTICATION_REGISTER_OFFSET); + + *(volatile uint32_t *)authRegAddr |= SRC_SLICE_AUTHEN_LOCK_SETTING_MASK; +} + +/*! + * @brief Sets the domain ID white list for the selected slice. + * + * @param base SRC peripheral base address. + * @param sliceName The slice name to set, please refer to @ref src_reset_slice_name_t for details. + * @param domainId The core to access registers, should be the OR'ed value of @ref src_core_name_t. + */ +static inline void SRC_SetDomainIdWhiteList(SRC_Type *base, src_reset_slice_name_t sliceName, uint8_t domainId) +{ + uint32_t authRegAddr; + + authRegAddr = SRC_GET_SLICE_REGISTER_ADDRESS(base, sliceName, SRC_SLICE_AUTHENTICATION_REGISTER_OFFSET); + + *(volatile uint32_t *)authRegAddr = ((*(volatile uint32_t *)authRegAddr) & (~SRC_SLICE_AUTHEN_WHITE_LIST_MASK)) | + SRC_SLICE_AUTHEN_WHITE_LIST(domainId); +} + +/*! + * @brief Locks the value of white list. + * + * @note Once locked only reset can unlock related settings. + * + * @param base SRC peripheral base address. + * @param sliceName The slice name to set, please refer to @ref src_reset_slice_name_t for details. + */ +static inline void SRC_LockDomainIdWhiteList(SRC_Type *base, src_reset_slice_name_t sliceName) +{ + uint32_t authRegAddr; + + authRegAddr = SRC_GET_SLICE_REGISTER_ADDRESS(base, sliceName, SRC_SLICE_AUTHENTICATION_REGISTER_OFFSET); + + *(volatile uint32_t *)authRegAddr |= SRC_SLICE_AUTHEN_LOCK_LIST_MASK; +} + +/*! + * @brief Sets the value of assign list. + * + * @param base SRC peripheral base address. + * @param sliceName The slice name to set, please refer to @ref src_reset_slice_name_t for details. + * @param assignList Cores that subject to corresponding core status transition, + * should be the OR'ed value of @ref src_core_name_t. + */ +static inline void SRC_SetAssignList(SRC_Type *base, src_reset_slice_name_t sliceName, uint32_t assignList) +{ + uint32_t authRegAddr; + + authRegAddr = SRC_GET_SLICE_REGISTER_ADDRESS(base, sliceName, SRC_SLICE_AUTHENTICATION_REGISTER_OFFSET); + + *(volatile uint32_t *)authRegAddr = ((*(volatile uint32_t *)authRegAddr) & (~SRC_SLICE_AUTHEN_ASSIGN_LIST_MASK)) | + SRC_SLICE_AUTHEN_ASSIGN_LIST(assignList); +} + +/*! + * @brief Locks the value of assign list. + * + * @note Once locked only reset can unlock related settings. + * + * @param base SRC peripheral base address. + * @param sliceName The slice name to set, please refer to @ref src_reset_slice_name_t for details. + */ +static inline void SRC_LockAssignList(SRC_Type *base, src_reset_slice_name_t sliceName) +{ + uint32_t authRegAddr; + + authRegAddr = SRC_GET_SLICE_REGISTER_ADDRESS(base, sliceName, SRC_SLICE_AUTHENTICATION_REGISTER_OFFSET); + + *(volatile uint32_t *)authRegAddr |= SRC_SLICE_AUTHEN_LOCK_ASSIGN_MASK; +} + +/*! + * @brief Enable/disable setpoint transfer reset. + * + * @param base SRC peripheral base address. + * @param sliceName The slice name to set, please refer to @ref src_reset_slice_name_t for details. + * @param enable User to control setpoint transfer reset. + * - \b true Enable setpoint transfer reset. + * - \b false Disable setpoint transfer reset. + */ +static inline void SRC_EnableSetPointTransferReset(SRC_Type *base, src_reset_slice_name_t sliceName, bool enable) +{ + uint32_t authRegAddr; + + authRegAddr = SRC_GET_SLICE_REGISTER_ADDRESS(base, sliceName, SRC_SLICE_AUTHENTICATION_REGISTER_OFFSET); + + if (enable) + { + /* If the setpoint mode transfer reset is enabled, domain mode transfer reset should be disabled. */ + *(volatile uint32_t *)authRegAddr = + ((*(volatile uint32_t *)authRegAddr) & (~SRC_SLICE_AUTHEN_DOMAIN_MODE_MASK)) | + SRC_SLICE_AUTHEN_SETPOINT_MODE_MASK; + } + else + { + *(volatile uint32_t *)authRegAddr &= ~SRC_SLICE_AUTHEN_SETPOINT_MODE_MASK; + } +} + +/*! + * @brief Enable/disable domain mode transfer reset. + * + * @param base SRC peripheral base address. + * @param sliceName The slice name to set, please refer to @ref src_reset_slice_name_t for details. + * @param enable User to control domain mode reset. + * - \b true Enable domain mode reset. + * - \b false Disable domain mode reset. + */ +static inline void SRC_EnableDomainModeTransferReset(SRC_Type *base, src_reset_slice_name_t sliceName, bool enable) +{ + uint32_t authRegAddr; + + authRegAddr = SRC_GET_SLICE_REGISTER_ADDRESS(base, sliceName, SRC_SLICE_AUTHENTICATION_REGISTER_OFFSET); + + if (enable) + { + /* If the domain mode transfer reset is enabled, setpoint mode transfer reset should be disabled. */ + *(volatile uint32_t *)authRegAddr = + ((*(volatile uint32_t *)authRegAddr) & (~SRC_SLICE_AUTHEN_SETPOINT_MODE_MASK)) | + SRC_SLICE_AUTHEN_DOMAIN_MODE_MASK; + } + else + { + *(volatile uint32_t *)authRegAddr &= ~SRC_SLICE_AUTHEN_DOMAIN_MODE_MASK; + } +} + +/*! + * @brief Sets setpoint configuration for the selected reset slice. + * + * @param base SRC peripheral base address. + * @param sliceName The selected reset slice. See @ref src_reset_slice_name_t for more details. + * @param setpointConfig The logic OR'ed value of _src_setpoint_selection enumeration, when the system in the + * selected setpoint slice reset will be asserted. + */ +void SRC_SetSliceSetPointConfig(SRC_Type *base, src_reset_slice_name_t sliceName, uint32_t setpointConfig); + +/*! + * @brief Sets domain mode configuration for the selected reset slice. + * + * @param base SRC peripheral base address. + * @param sliceName The selected reset slice. See @ref src_reset_slice_name_t for more details. + * @param domainConfig The logic OR'ed value of _src_domain_mode_selection enumerations. + */ +void SRC_SetSliceDomainModeConfig(SRC_Type *base, src_reset_slice_name_t sliceName, uint32_t domainConfig); + +/*! + * @brief Locks the value of SETPOINT_MODE and DOMAIN_MODE for the selected reset slice. + * + * @param base SRC peripheral base address. + * @param sliceName The selected reset slice. See @ref src_reset_slice_name_t for more details. + */ +void SRC_LockSliceMode(SRC_Type *base, src_reset_slice_name_t sliceName); + +/*! @} */ + +/*! + * @name Get/Clear Slice Reset Status Flags + * @{ + */ + +/*! + * @brief Gets the reset status flags of the selected slice. + * + * @param base SRC peripheral base address. + * @param sliceName The slice to be reset. See @ref src_reset_slice_name_t for more details. + * @return The reset status flags for the selected slice. Please refer to @ref _src_slice_reset_source for details. + */ +static inline uint32_t SRC_GetSliceResetStatusFlags(SRC_Type *base, src_reset_slice_name_t sliceName) +{ + return (*(volatile uint32_t *)(SRC_GET_SLICE_REGISTER_ADDRESS(base, sliceName, SRC_SLICE_STATUS_REGISTER_OFFSET)) & + (SRC_SLICE_STAT_RST_BY_HW_MASK | SRC_SLICE_STAT_RST_BY_SW_MASK)); +} + +/*! + * @brief Clears the reset status flags of the selected slice. + * + * @param base SRC peripheral base address. + * @param sliceName The selected slice. See @ref src_reset_slice_name_t for more details. + * @param mask The reset status flags to be cleared. Please refer to @ref _src_slice_reset_source for more details. + */ +static inline void SRC_ClearSliceResetStatusFlags(SRC_Type *base, src_reset_slice_name_t sliceName, uint32_t mask) +{ + *(volatile uint32_t *)SRC_GET_SLICE_REGISTER_ADDRESS(base, sliceName, SRC_SLICE_STATUS_REGISTER_OFFSET) = mask; +} + +/* @} */ + +/*! + * @name Get Slice Reset State + * @{ + */ + +/*! + * @brief Gets the reset state of the selected slice. + * + * @param base SRC peripheral base address. + * @param sliceName The selected slice. See @ref src_reset_slice_name_t for more details. + * @retval kSRC_SliceResetInProcess The reset is in process. + * @retval kSRC_SliceResetFinished The reset is finished. + */ +src_slice_reset_state_t SRC_GetSliceResetState(SRC_Type *base, src_reset_slice_name_t sliceName); + +/*! @} */ + +/*! + * @name General Purpose Registers Related Interfaces + * @{ + */ + +/*! + * @brief Sets value to general purpose registers. + * + * @param base SRC peripheral base address. + * @param index The index of GPRx register array. Please refer to @ref src_general_purpose_register_index_t. + * @param value Setting value for GPRx register. + */ +static inline void SRC_SetGeneralPurposeRegister(SRC_Type *base, + src_general_purpose_register_index_t index, + uint32_t value) +{ + base->GPR[index] = value; +} + +/*! + * @brief Gets the value from general purpose registers. + * + * @param base SRC peripheral base address. + * @param index The index of GPRx register array. Please refer to @ref src_general_purpose_register_index_t. + * @return The setting value for GPRx register. + */ +static inline uint32_t SRC_GetGeneralPurposeRegister(SRC_Type *base, src_general_purpose_register_index_t index) +{ + assert((uint8_t)index < (uint8_t)SRC_GPR_COUNT); + + return base->GPR[index]; +} + +/*! @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_SRC_H_ */ |