diff options
Diffstat (limited to 'bsps/arm/imxrt/dts/imxrt1050-evkb.dts')
| -rw-r--r-- | bsps/arm/imxrt/dts/imxrt1050-evkb.dts | 410 |
1 files changed, 410 insertions, 0 deletions
diff --git a/bsps/arm/imxrt/dts/imxrt1050-evkb.dts b/bsps/arm/imxrt/dts/imxrt1050-evkb.dts new file mode 100644 index 0000000000..968ca1dbdc --- /dev/null +++ b/bsps/arm/imxrt/dts/imxrt1050-evkb.dts @@ -0,0 +1,410 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/* + * Copyright (C) 2020 embedded brains GmbH (http://www.embedded-brains.de) + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * FIXME: Compilation should be automated. + * + * Compile this file with the following commands: + * export BSP_DIR="${RTEMS_SRC_DIR}/bsps/arm/imxrt/" + * arm-rtems6-cpp -P -x assembler-with-cpp -I "${BSP_DIR}/include/" -include "${BSP_DIR}/dts/imxrt1050-evkb.dts" /dev/null | \ + * dtc -@ -O dtb -o "${BSP_DIR}/dts/imxrt1050-evkb.dtb" -b 0 -p 1024 + * rtems-bin2c -C -N imxrt_dtb "${BSP_DIR}/dts/imxrt1050-evkb.dtb" "${BSP_DIR}/dts/imxrt1050-evkb.c" + */ + +#include <imxrt/imxrt1050-pinfunc.h> + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + chosen: chosen {}; + + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + }; + + nvic: interrupt-controller@e000e100 { + compatible = "arm,armv7m-nvic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xe000e100 0xc00>; + }; + + systick: timer@e000e010 { + compatible = "arm,armv7m-systick"; + reg = <0xe000e010 0x10>; + status = "disabled"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&nvic>; + ranges; + + aips-bus@40000000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40000000 0x00100000>; + ranges; + + gpio5: gpio@400c0000 { + compatible = "fsl,imxrt-gpio", + "fsl,imx6ul-gpio", "fsl,imx35-gpio"; + reg = <0x400c0000 0x4000>; + interrupts = <88>, <89>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + aips-bus@40100000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40100000 0x00100000>; + ranges; + + gpio4: gpio@401c4000 { + compatible = "fsl,imxrt-gpio", + "fsl,imx6ul-gpio", "fsl,imx35-gpio"; + reg = <0x401c4000 0x4000>; + interrupts = <86>, <87>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@401c0000 { + compatible = "fsl,imxrt-gpio", + "fsl,imx6ul-gpio", "fsl,imx35-gpio"; + reg = <0x401c0000 0x4000>; + interrupts = <84>, <85>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@401bc000 { + compatible = "fsl,imxrt-gpio", + "fsl,imx6ul-gpio", "fsl,imx35-gpio"; + reg = <0x401bc000 0x4000>; + interrupts = <82>, <83>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@401b8000 { + compatible = "fsl,imxrt-gpio", + "fsl,imx6ul-gpio", "fsl,imx35-gpio"; + reg = <0x401b8000 0x4000>; + interrupts = <80>, <81>, <72>, <73>, <74>, + <75>, <76>, <77>, <78>, <79>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + lpuart1: uart@40184000 { + compatible = "nxp,imxrt-lpuart"; + reg = <0x40184000 0x4000>; + interrupts = <20>; + status = "disabled"; + rtems,path = "/dev/ttyS1"; + }; + + lpuart2: uart@40188000 { + compatible = "nxp,imxrt-lpuart"; + reg = <0x40188000 0x4000>; + interrupts = <21>; + status = "disabled"; + rtems,path = "/dev/ttyS2"; + }; + + lpuart3: uart@4018c000 { + compatible = "nxp,imxrt-lpuart"; + reg = <0x4018c000 0x4000>; + interrupts = <22>; + status = "disabled"; + rtems,path = "/dev/ttyS3"; + }; + + lpuart4: uart@40190000 { + compatible = "nxp,imxrt-lpuart"; + reg = <0x40190000 0x4000>; + interrupts = <23>; + status = "disabled"; + rtems,path = "/dev/ttyS4"; + }; + + lpuart5: uart@40194000 { + compatible = "nxp,imxrt-lpuart"; + reg = <0x40194000 0x4000>; + interrupts = <24>; + status = "disabled"; + rtems,path = "/dev/ttyS5"; + }; + + lpuart6: uart@40198000 { + compatible = "nxp,imxrt-lpuart"; + reg = <0x40198000 0x4000>; + interrupts = <25>; + status = "disabled"; + rtems,path = "/dev/ttyS6"; + }; + + lpuart7: uart@4019c000 { + compatible = "nxp,imxrt-lpuart"; + reg = <0x4019c000 0x4000>; + interrupts = <26>; + status = "disabled"; + rtems,path = "/dev/ttyS7"; + }; + + lpuart8: uart@401a0000 { + compatible = "nxp,imxrt-lpuart"; + reg = <0x401a0000 0x4000>; + interrupts = <27>; + status = "disabled"; + rtems,path = "/dev/ttyS8"; + }; + + iomuxc: pinctrl@401f8000 { + compatible = "nxp,imxrt1050-iomuxc"; + reg = <0x401f8000 0x4000>; + }; + }; + + aips-bus@40200000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40200000 0x00100000>; + ranges; + + fec1: ethernet@402d8000 { + compatible = "fsl,imxrt-fec", "fsl,imx6ul-fec"; + reg = <0x402d8000 0x4000>; + interrupt-names = "int0", "pps"; + interrupts = <114>, <115>; + fsl,num-tx-queues = <1>; + fsl,num-rx-queues = <1>; + phy-mode = "rmii"; + status = "disabled"; + }; + }; + + aips-bus@40300000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40300000 0x00100000>; + ranges; + + lpspi1: lpspi@40394000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imxrt-lpspi"; + reg = <0x40394000 0x4000>; + interrupts = <32>; + status = "disabled"; + rtems,path = "/dev/spi1"; + }; + + lpspi2: lpspi@40398000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imxrt-lpspi"; + reg = <0x40398000 0x4000>; + interrupts = <33>; + status = "disabled"; + rtems,path = "/dev/spi2"; + }; + + lpspi3: lpspi@4039c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imxrt-lpspi"; + reg = <0x4039c000 0x4000>; + interrupts = <34>; + status = "disabled"; + rtems,path = "/dev/spi3"; + }; + + lpspi4: lpspi@403a0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imxrt-lpspi"; + reg = <0x403a0000 0x4000>; + interrupts = <35>; + status = "disabled"; + rtems,path = "/dev/spi4"; + }; + + lpi2c1: lpi2c@403f0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imxrt-lpi2c"; + reg = <0x403f0000 0x4000>; + interrupts = <28>; + status = "disabled"; + rtems,path = "/dev/i2c1"; + }; + + lpi2c2: lpi2c@403f4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imxrt-lpi2c"; + reg = <0x403f4000 0x4000>; + interrupts = <29>; + status = "disabled"; + rtems,path = "/dev/i2c2"; + }; + + lpi2c3: lpi2c@403f8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imxrt-lpi2c"; + reg = <0x403f8000 0x4000>; + interrupts = <30>; + status = "disabled"; + rtems,path = "/dev/i2c3"; + }; + + lpi2c4: lpi2c@403fc000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imxrt-lpi2c"; + reg = <0x403fc000 0x4000>; + interrupts = <31>; + status = "disabled"; + rtems,path = "/dev/i2c4"; + }; + }; + }; +}; + +&lpuart1 { + pinctrl-0 = <&pinctrl_lpuart1>; + status = "okay"; +}; + +&chosen { + stdout-path = &lpuart1; +}; + +&lpuart3 { + pinctrl-0 = <&pinctrl_lpuart3>; + status = "okay"; +}; + +&lpspi1 { + pinctrl-0 = <&pinctrl_lpspi1>; + status = "okay"; +}; + +&lpi2c1 { + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; +}; + +&lpi2c1 { + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; +}; + +&fec1 { + pinctrl-0 = <&pinctrl_fec1>; + phy-reset-gpios = <&gpio1 9 1>; + rtems,phy-interrupt-gpios = <&gpio1 10 1>; + status = "okay"; +}; + +&iomuxc { + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + IMXRT_PAD_GPIO_AD_B0_12__LPUART1_TX 0x8 + IMXRT_PAD_GPIO_AD_B0_13__LPUART1_RX 0x13000 + >; + }; + + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + IMXRT_PAD_GPIO_AD_B1_06__LPUART3_TX 0x8 + IMXRT_PAD_GPIO_AD_B1_07__LPUART3_RX 0x13000 + >; + }; + + pinctrl_lpspi1: lpspi1grp { + fsl,pins = < + IMXRT_PAD_GPIO_SD_B0_01__LPSPI1_PCS0 0x8 + IMXRT_PAD_GPIO_SD_B0_02__LPSPI1_SDO 0x8 + IMXRT_PAD_GPIO_SD_B0_03__LPSPI1_SDI 0x1b000 + IMXRT_PAD_GPIO_SD_B0_00__LPSPI1_SCK 0x8 + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + IMXRT_PAD_GPIO_AD_B1_00__LPI2C1_SCL 0x4000f830 + IMXRT_PAD_GPIO_AD_B1_01__LPI2C1_SDA 0x4000f830 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + IMXRT_PAD_GPIO_EMC_41__ENET_enet_mdio 0xb829 + IMXRT_PAD_GPIO_EMC_40__ENET_enet_mdc 0xb0e9 + IMXRT_PAD_GPIO_B1_04__ENET_enet_rx_data0 0xb0e9 + IMXRT_PAD_GPIO_B1_05__ENET_enet_rx_data1 0xb0e9 + IMXRT_PAD_GPIO_B1_06__ENET_enet_rx_en 0xb0e9 + IMXRT_PAD_GPIO_B1_07__ENET_enet_tx_data0 0xb0e9 + IMXRT_PAD_GPIO_B1_08__ENET_enet_tx_data1 0xb0e9 + IMXRT_PAD_GPIO_B1_09__ENET_enet_tx_en 0xb0e9 + IMXRT_PAD_GPIO_B1_10__ENET_enet_ref_clk 0x40000031 + IMXRT_PAD_GPIO_B1_11__ENET_enet_rx_er 0xb0e9 + /* ENET_RST */ + IMXRT_PAD_GPIO_AD_B0_09__GPIO1_gpio_io09 0x810 + /* ENET_INT */ + IMXRT_PAD_GPIO_AD_B0_10__GPIO1_gpio_io10 0xb0a9 + >; + }; +}; |