diff options
24 files changed, 122 insertions, 14 deletions
diff --git a/c/src/exec/score/cpu/h8300/ChangeLog b/c/src/exec/score/cpu/h8300/ChangeLog index 15005bbf75..57e5358c57 100644 --- a/c/src/exec/score/cpu/h8300/ChangeLog +++ b/c/src/exec/score/cpu/h8300/ChangeLog @@ -1,3 +1,9 @@ +2001-01-03 Joel Sherrill <joel@OARcorp.com> + + * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). + * cpu_asm.S: Modify to properly dereference _ISR_Vector_table + now that it is dynamically allocated. + 2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS. diff --git a/c/src/exec/score/cpu/h8300/cpu_asm.S b/c/src/exec/score/cpu/h8300/cpu_asm.S index d9c22f588e..1cef5abf67 100644 --- a/c/src/exec/score/cpu/h8300/cpu_asm.S +++ b/c/src/exec/score/cpu/h8300/cpu_asm.S @@ -128,7 +128,7 @@ nested: /* Vector to ISR */ - mov.l #__ISR_Vector_table,er1 + mov.l @__ISR_Vector_table,er1 mov er0,er2 ; copy vector shll.l er2 shll.l er2 ; vector = vector * 4 (sizeof(int)) diff --git a/c/src/exec/score/cpu/h8300/rtems/score/cpu.h b/c/src/exec/score/cpu/h8300/rtems/score/cpu.h index 8e3f081d30..055a006aed 100644 --- a/c/src/exec/score/cpu/h8300/rtems/score/cpu.h +++ b/c/src/exec/score/cpu/h8300/rtems/score/cpu.h @@ -601,7 +601,15 @@ SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)(); #define CPU_STACK_ALIGNMENT 2 -/* ISR handler macros */ +/* + * ISR handler macros + */ + +/* + * Support routine to initialize the RTEMS vector table after it is allocated. + */ + +#define _CPU_Initialize_vectors() /* COPE With Brain dead version of GCC distributed with Hitachi HIView Tools. Note requires ISR_Level be unsigned16 or assembler croaks. diff --git a/c/src/exec/score/cpu/hppa1.1/ChangeLog b/c/src/exec/score/cpu/hppa1.1/ChangeLog index 2650906187..d746a28b50 100644 --- a/c/src/exec/score/cpu/hppa1.1/ChangeLog +++ b/c/src/exec/score/cpu/hppa1.1/ChangeLog @@ -1,3 +1,9 @@ +2001-01-03 Joel Sherrill <joel@OARcorp.com> + + * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). + * cpu_asm.S: Modify to properly dereference _ISR_Vector_table + now that it is dynamically allocated. + 2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS. diff --git a/c/src/exec/score/cpu/hppa1.1/cpu_asm.S b/c/src/exec/score/cpu/hppa1.1/cpu_asm.S index e6d9fd08d8..1c6874f8a9 100644 --- a/c/src/exec/score/cpu/hppa1.1/cpu_asm.S +++ b/c/src/exec/score/cpu/hppa1.1/cpu_asm.S @@ -311,6 +311,7 @@ stack_done: .import _ISR_Vector_table,data ldil L%_ISR_Vector_table,%r8 ldo R%_ISR_Vector_table(%r8),%r8 + ldw (%r8),%r8 ldwx,s %r9(%r8),%r8 /* diff --git a/c/src/exec/score/cpu/hppa1.1/rtems/score/cpu.h b/c/src/exec/score/cpu/hppa1.1/rtems/score/cpu.h index 037226fa21..469b071532 100644 --- a/c/src/exec/score/cpu/hppa1.1/rtems/score/cpu.h +++ b/c/src/exec/score/cpu/hppa1.1/rtems/score/cpu.h @@ -338,13 +338,21 @@ SCORE_EXTERN void *_CPU_Interrupt_stack_high; * ISR handler macros * * These macros perform the following functions: + * + initialize the RTEMS vector table * + disable all maskable CPU interrupts * + restore previous interrupt level (enable) * + temporarily restore interrupts (flash) * + set a particular level */ +/* + * Support routine to initialize the RTEMS vector table after it is allocated. + */ + +#define _CPU_Initialize_vectors() + /* Disable interrupts; returning previous psw bits in _isr_level */ + #define _CPU_ISR_Disable( _isr_level ) \ do { \ HPPA_ASM_RSM(HPPA_PSW_I, _isr_level); \ @@ -353,7 +361,9 @@ SCORE_EXTERN void *_CPU_Interrupt_stack_high; } while(0) /* Enable interrupts to previous level from _CPU_ISR_Disable - * does not change 'level' */ + * does not change 'level' + */ + #define _CPU_ISR_Enable( _isr_level ) \ { \ register int _ignore; \ diff --git a/c/src/exec/score/cpu/m68k/ChangeLog b/c/src/exec/score/cpu/m68k/ChangeLog index 533d182258..13ec23bbf5 100644 --- a/c/src/exec/score/cpu/m68k/ChangeLog +++ b/c/src/exec/score/cpu/m68k/ChangeLog @@ -1,3 +1,9 @@ +2001-01-03 Joel Sherrill <joel@OARcorp.com> + + * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). + * cpu_asm.S: Modify to properly dereference _ISR_Vector_table + now that it is dynamically allocated. + 2000-12-19 Joel Sherrill <joel@OARcorp.com> * cpu.c: Do not read or write raw interrupt vector table if diff --git a/c/src/exec/score/cpu/m68k/cpu_asm.S b/c/src/exec/score/cpu/m68k/cpu_asm.S index 3d663372a0..5f29d67469 100644 --- a/c/src/exec/score/cpu/m68k/cpu_asm.S +++ b/c/src/exec/score/cpu/m68k/cpu_asm.S @@ -177,10 +177,10 @@ SYM (_ISR_Handler): addql #1,SYM (_ISR_Nest_level) | one nest level deeper #endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */ + movel SYM (_ISR_Vector_table),a0 | a0= base of RTEMS table #if ( M68K_HAS_PREINDEXING == 1 ) - movel @( SYM (_ISR_Vector_table),d0:w:1),a0| fetch the ISR + movel (a0,d0:w:1),a0 | a0 = address of user routine #else - movel # SYM (_ISR_Vector_table),a0 | a0 = base of RTEMS table addal d0,a0 | a0 = address of vector movel (a0),a0 | a0 = address of user routine #endif diff --git a/c/src/exec/score/cpu/m68k/rtems/score/cpu.h b/c/src/exec/score/cpu/m68k/rtems/score/cpu.h index 2353332620..c1d3f6ac58 100644 --- a/c/src/exec/score/cpu/m68k/rtems/score/cpu.h +++ b/c/src/exec/score/cpu/m68k/rtems/score/cpu.h @@ -309,12 +309,15 @@ SCORE_EXTERN _CPU_ISR_handler_entry _CPU_ISR_jump_table[256]; * ISR handler macros * * These macros perform the following functions: + * + initialize the RTEMS vector table * + disable all maskable CPU interrupts * + restore previous interrupt level (enable) * + temporarily restore interrupts (flash) * + set a particular level */ +#define _CPU_Initialize_vectors() + #define _CPU_ISR_Disable( _level ) \ m68k_disable_interrupts( _level ) diff --git a/c/src/exec/score/cpu/sparc/ChangeLog b/c/src/exec/score/cpu/sparc/ChangeLog index 1cc5e1d422..ad958a08a9 100644 --- a/c/src/exec/score/cpu/sparc/ChangeLog +++ b/c/src/exec/score/cpu/sparc/ChangeLog @@ -1,3 +1,9 @@ +2001-01-03 Joel Sherrill <joel@OARcorp.com> + + * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). + * cpu_asm.S: Modify to properly dereference _ISR_Vector_table + now that it is dynamically allocated. + 2000-12-06 Joel Sherrill <joel@OARcorp.com> * cpu.c: Added include of <rtems/rtems/cache.h> to eliminate warning. diff --git a/c/src/exec/score/cpu/sparc/cpu_asm.S b/c/src/exec/score/cpu/sparc/cpu_asm.S index e7c2cf68db..9e186a0bb9 100644 --- a/c/src/exec/score/cpu/sparc/cpu_asm.S +++ b/c/src/exec/score/cpu/sparc/cpu_asm.S @@ -585,7 +585,7 @@ dont_fix_pil2: */ sethi %hi(SYM(_ISR_Vector_table)), %g4 - or %g4, %lo(SYM(_ISR_Vector_table)), %g4 + ld [%g4+%lo(SYM(_ISR_Vector_table))], %g4 and %l3, 0xFF, %g5 ! remove synchronous trap indicator sll %g5, 2, %g5 ! g5 = offset into table ld [%g4 + %g5], %g4 ! g4 = _ISR_Vector_table[ vector ] diff --git a/c/src/exec/score/cpu/sparc/rtems/score/cpu.h b/c/src/exec/score/cpu/sparc/rtems/score/cpu.h index f7fbf121f9..7f6383a0e1 100644 --- a/c/src/exec/score/cpu/sparc/rtems/score/cpu.h +++ b/c/src/exec/score/cpu/sparc/rtems/score/cpu.h @@ -718,7 +718,15 @@ SCORE_EXTERN unsigned8 _CPU_Trap_Table_area[ 8192 ] extern unsigned int sparc_disable_interrupts(); extern void sparc_enable_interrupts(); -/* ISR handler macros */ +/* + * ISR handler macros + */ + +/* + * Support routine to initialize the RTEMS vector table after it is allocated. + */ + +#define _CPU_Initialize_vectors() /* * Disable all interrupts for a critical section. The previous diff --git a/cpukit/score/cpu/h8300/ChangeLog b/cpukit/score/cpu/h8300/ChangeLog index 15005bbf75..57e5358c57 100644 --- a/cpukit/score/cpu/h8300/ChangeLog +++ b/cpukit/score/cpu/h8300/ChangeLog @@ -1,3 +1,9 @@ +2001-01-03 Joel Sherrill <joel@OARcorp.com> + + * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). + * cpu_asm.S: Modify to properly dereference _ISR_Vector_table + now that it is dynamically allocated. + 2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS. diff --git a/cpukit/score/cpu/h8300/cpu_asm.S b/cpukit/score/cpu/h8300/cpu_asm.S index d9c22f588e..1cef5abf67 100644 --- a/cpukit/score/cpu/h8300/cpu_asm.S +++ b/cpukit/score/cpu/h8300/cpu_asm.S @@ -128,7 +128,7 @@ nested: /* Vector to ISR */ - mov.l #__ISR_Vector_table,er1 + mov.l @__ISR_Vector_table,er1 mov er0,er2 ; copy vector shll.l er2 shll.l er2 ; vector = vector * 4 (sizeof(int)) diff --git a/cpukit/score/cpu/h8300/rtems/score/cpu.h b/cpukit/score/cpu/h8300/rtems/score/cpu.h index 8e3f081d30..055a006aed 100644 --- a/cpukit/score/cpu/h8300/rtems/score/cpu.h +++ b/cpukit/score/cpu/h8300/rtems/score/cpu.h @@ -601,7 +601,15 @@ SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)(); #define CPU_STACK_ALIGNMENT 2 -/* ISR handler macros */ +/* + * ISR handler macros + */ + +/* + * Support routine to initialize the RTEMS vector table after it is allocated. + */ + +#define _CPU_Initialize_vectors() /* COPE With Brain dead version of GCC distributed with Hitachi HIView Tools. Note requires ISR_Level be unsigned16 or assembler croaks. diff --git a/cpukit/score/cpu/hppa1.1/ChangeLog b/cpukit/score/cpu/hppa1.1/ChangeLog index 2650906187..d746a28b50 100644 --- a/cpukit/score/cpu/hppa1.1/ChangeLog +++ b/cpukit/score/cpu/hppa1.1/ChangeLog @@ -1,3 +1,9 @@ +2001-01-03 Joel Sherrill <joel@OARcorp.com> + + * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). + * cpu_asm.S: Modify to properly dereference _ISR_Vector_table + now that it is dynamically allocated. + 2000-11-09 Ralf Corsepius <corsepiu@faw.uni-ulm.de> * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS. diff --git a/cpukit/score/cpu/hppa1.1/cpu_asm.S b/cpukit/score/cpu/hppa1.1/cpu_asm.S index e6d9fd08d8..1c6874f8a9 100644 --- a/cpukit/score/cpu/hppa1.1/cpu_asm.S +++ b/cpukit/score/cpu/hppa1.1/cpu_asm.S @@ -311,6 +311,7 @@ stack_done: .import _ISR_Vector_table,data ldil L%_ISR_Vector_table,%r8 ldo R%_ISR_Vector_table(%r8),%r8 + ldw (%r8),%r8 ldwx,s %r9(%r8),%r8 /* diff --git a/cpukit/score/cpu/hppa1.1/rtems/score/cpu.h b/cpukit/score/cpu/hppa1.1/rtems/score/cpu.h index 037226fa21..469b071532 100644 --- a/cpukit/score/cpu/hppa1.1/rtems/score/cpu.h +++ b/cpukit/score/cpu/hppa1.1/rtems/score/cpu.h @@ -338,13 +338,21 @@ SCORE_EXTERN void *_CPU_Interrupt_stack_high; * ISR handler macros * * These macros perform the following functions: + * + initialize the RTEMS vector table * + disable all maskable CPU interrupts * + restore previous interrupt level (enable) * + temporarily restore interrupts (flash) * + set a particular level */ +/* + * Support routine to initialize the RTEMS vector table after it is allocated. + */ + +#define _CPU_Initialize_vectors() + /* Disable interrupts; returning previous psw bits in _isr_level */ + #define _CPU_ISR_Disable( _isr_level ) \ do { \ HPPA_ASM_RSM(HPPA_PSW_I, _isr_level); \ @@ -353,7 +361,9 @@ SCORE_EXTERN void *_CPU_Interrupt_stack_high; } while(0) /* Enable interrupts to previous level from _CPU_ISR_Disable - * does not change 'level' */ + * does not change 'level' + */ + #define _CPU_ISR_Enable( _isr_level ) \ { \ register int _ignore; \ diff --git a/cpukit/score/cpu/m68k/ChangeLog b/cpukit/score/cpu/m68k/ChangeLog index 533d182258..13ec23bbf5 100644 --- a/cpukit/score/cpu/m68k/ChangeLog +++ b/cpukit/score/cpu/m68k/ChangeLog @@ -1,3 +1,9 @@ +2001-01-03 Joel Sherrill <joel@OARcorp.com> + + * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). + * cpu_asm.S: Modify to properly dereference _ISR_Vector_table + now that it is dynamically allocated. + 2000-12-19 Joel Sherrill <joel@OARcorp.com> * cpu.c: Do not read or write raw interrupt vector table if diff --git a/cpukit/score/cpu/m68k/cpu_asm.S b/cpukit/score/cpu/m68k/cpu_asm.S index 3d663372a0..5f29d67469 100644 --- a/cpukit/score/cpu/m68k/cpu_asm.S +++ b/cpukit/score/cpu/m68k/cpu_asm.S @@ -177,10 +177,10 @@ SYM (_ISR_Handler): addql #1,SYM (_ISR_Nest_level) | one nest level deeper #endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */ + movel SYM (_ISR_Vector_table),a0 | a0= base of RTEMS table #if ( M68K_HAS_PREINDEXING == 1 ) - movel @( SYM (_ISR_Vector_table),d0:w:1),a0| fetch the ISR + movel (a0,d0:w:1),a0 | a0 = address of user routine #else - movel # SYM (_ISR_Vector_table),a0 | a0 = base of RTEMS table addal d0,a0 | a0 = address of vector movel (a0),a0 | a0 = address of user routine #endif diff --git a/cpukit/score/cpu/m68k/rtems/score/cpu.h b/cpukit/score/cpu/m68k/rtems/score/cpu.h index 2353332620..c1d3f6ac58 100644 --- a/cpukit/score/cpu/m68k/rtems/score/cpu.h +++ b/cpukit/score/cpu/m68k/rtems/score/cpu.h @@ -309,12 +309,15 @@ SCORE_EXTERN _CPU_ISR_handler_entry _CPU_ISR_jump_table[256]; * ISR handler macros * * These macros perform the following functions: + * + initialize the RTEMS vector table * + disable all maskable CPU interrupts * + restore previous interrupt level (enable) * + temporarily restore interrupts (flash) * + set a particular level */ +#define _CPU_Initialize_vectors() + #define _CPU_ISR_Disable( _level ) \ m68k_disable_interrupts( _level ) diff --git a/cpukit/score/cpu/sparc/ChangeLog b/cpukit/score/cpu/sparc/ChangeLog index 1cc5e1d422..ad958a08a9 100644 --- a/cpukit/score/cpu/sparc/ChangeLog +++ b/cpukit/score/cpu/sparc/ChangeLog @@ -1,3 +1,9 @@ +2001-01-03 Joel Sherrill <joel@OARcorp.com> + + * rtems/score/cpu.h: Added _CPU_Initialize_vectors(). + * cpu_asm.S: Modify to properly dereference _ISR_Vector_table + now that it is dynamically allocated. + 2000-12-06 Joel Sherrill <joel@OARcorp.com> * cpu.c: Added include of <rtems/rtems/cache.h> to eliminate warning. diff --git a/cpukit/score/cpu/sparc/cpu_asm.S b/cpukit/score/cpu/sparc/cpu_asm.S index e7c2cf68db..9e186a0bb9 100644 --- a/cpukit/score/cpu/sparc/cpu_asm.S +++ b/cpukit/score/cpu/sparc/cpu_asm.S @@ -585,7 +585,7 @@ dont_fix_pil2: */ sethi %hi(SYM(_ISR_Vector_table)), %g4 - or %g4, %lo(SYM(_ISR_Vector_table)), %g4 + ld [%g4+%lo(SYM(_ISR_Vector_table))], %g4 and %l3, 0xFF, %g5 ! remove synchronous trap indicator sll %g5, 2, %g5 ! g5 = offset into table ld [%g4 + %g5], %g4 ! g4 = _ISR_Vector_table[ vector ] diff --git a/cpukit/score/cpu/sparc/rtems/score/cpu.h b/cpukit/score/cpu/sparc/rtems/score/cpu.h index f7fbf121f9..7f6383a0e1 100644 --- a/cpukit/score/cpu/sparc/rtems/score/cpu.h +++ b/cpukit/score/cpu/sparc/rtems/score/cpu.h @@ -718,7 +718,15 @@ SCORE_EXTERN unsigned8 _CPU_Trap_Table_area[ 8192 ] extern unsigned int sparc_disable_interrupts(); extern void sparc_enable_interrupts(); -/* ISR handler macros */ +/* + * ISR handler macros + */ + +/* + * Support routine to initialize the RTEMS vector table after it is allocated. + */ + +#define _CPU_Initialize_vectors() /* * Disable all interrupts for a critical section. The previous |