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-rw-r--r--c/src/lib/libbsp/sparc/erc32/ChangeLog5
-rw-r--r--c/src/lib/libbsp/sparc/erc32/include/bsp.h62
-rw-r--r--c/src/lib/libbsp/sparc/erc32/include/tm27.h80
-rw-r--r--c/src/lib/libbsp/sparc/leon/ChangeLog5
-rw-r--r--c/src/lib/libbsp/sparc/leon/include/bsp.h61
-rw-r--r--c/src/lib/libbsp/sparc/leon/include/tm27.h79
6 files changed, 169 insertions, 123 deletions
diff --git a/c/src/lib/libbsp/sparc/erc32/ChangeLog b/c/src/lib/libbsp/sparc/erc32/ChangeLog
index 053e96db93..033216b733 100644
--- a/c/src/lib/libbsp/sparc/erc32/ChangeLog
+++ b/c/src/lib/libbsp/sparc/erc32/ChangeLog
@@ -1,3 +1,8 @@
+2004-04-22 Ralf Corsepius <ralf_corsepius@rtems.org>
+
+ * include/bsp.h: Split out tmtest27 support.
+ * include/tm27.h: New.
+
2004-04-21 Ralf Corsepius <ralf_corsepius@rtems.org>
PR 613/bsps
diff --git a/c/src/lib/libbsp/sparc/erc32/include/bsp.h b/c/src/lib/libbsp/sparc/erc32/include/bsp.h
index c85e4d68e6..81bb4b779d 100644
--- a/c/src/lib/libbsp/sparc/erc32/include/bsp.h
+++ b/c/src/lib/libbsp/sparc/erc32/include/bsp.h
@@ -54,68 +54,6 @@ extern int rtems_erc32_sonic_driver_attach (struct rtems_bsdnet_ifconfig *config
#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_erc32_sonic_driver_attach
/*
- * Define the interrupt mechanism for Time Test 27
- *
- * NOTE: Since the interrupt code for the SPARC supports both synchronous
- * and asynchronous trap handlers, support for testing with both
- * is included.
- */
-
-#define ERC32_BSP_USE_SYNCHRONOUS_TRAP 0
-
-/*
- * The synchronous trap is an arbitrarily chosen software trap.
- */
-
-#if (ERC32_BSP_USE_SYNCHRONOUS_TRAP == 1)
-
-#define TEST_VECTOR SPARC_SYNCHRONOUS_TRAP( 0x90 )
-
-#define MUST_WAIT_FOR_INTERRUPT 1
-
-#define Install_tm27_vector( handler ) \
- set_vector( (handler), TEST_VECTOR, 1 );
-
-#define Cause_tm27_intr() \
- asm volatile( "ta 0x10; nop " );
-
-#define Clear_tm27_intr()
-
-#define Lower_tm27_intr()
-
-/*
- * The asynchronous trap is an arbitrarily chosen ERC32 interrupt source.
- */
-
-#else /* use a regular asynchronous trap */
-
-#define TEST_INTERRUPT_SOURCE ERC32_INTERRUPT_EXTERNAL_1
-#define TEST_INTERRUPT_SOURCE2 (ERC32_INTERRUPT_EXTERNAL_1+1)
-#define TEST_VECTOR ERC32_TRAP_TYPE( TEST_INTERRUPT_SOURCE )
-#define TEST_VECTOR2 ERC32_TRAP_TYPE( TEST_INTERRUPT_SOURCE2 )
-
-#define MUST_WAIT_FOR_INTERRUPT 1
-
-#define Install_tm27_vector( handler ) \
- set_vector( (handler), TEST_VECTOR, 1 ); \
- set_vector( (handler), TEST_VECTOR2, 1 );
-
-#define Cause_tm27_intr() \
- do { \
- ERC32_Force_interrupt( TEST_INTERRUPT_SOURCE+(Interrupt_nest>>1) ); \
- nop(); \
- nop(); \
- nop(); \
- } while (0)
-
-#define Clear_tm27_intr() \
- ERC32_Clear_interrupt( TEST_INTERRUPT_SOURCE )
-
-#define Lower_tm27_intr()
-
-#endif
-
-/*
* Simple spin delay in microsecond units for device drivers.
* This is very dependent on the clock speed of the target.
*/
diff --git a/c/src/lib/libbsp/sparc/erc32/include/tm27.h b/c/src/lib/libbsp/sparc/erc32/include/tm27.h
new file mode 100644
index 0000000000..872077c3cd
--- /dev/null
+++ b/c/src/lib/libbsp/sparc/erc32/include/tm27.h
@@ -0,0 +1,80 @@
+/*
+ * tm27.h
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ *
+ * $Id$
+ */
+
+#ifndef _TMTEST27
+#error "This is an RTEMS internal file you must not include directly."
+#endif
+
+#ifndef __tm27_h
+#define __tm27_h
+
+/*
+ * Define the interrupt mechanism for Time Test 27
+ *
+ * NOTE: Since the interrupt code for the SPARC supports both synchronous
+ * and asynchronous trap handlers, support for testing with both
+ * is included.
+ */
+
+#define ERC32_BSP_USE_SYNCHRONOUS_TRAP 0
+
+/*
+ * The synchronous trap is an arbitrarily chosen software trap.
+ */
+
+#if (ERC32_BSP_USE_SYNCHRONOUS_TRAP == 1)
+
+#define TEST_VECTOR SPARC_SYNCHRONOUS_TRAP( 0x90 )
+
+#define MUST_WAIT_FOR_INTERRUPT 1
+
+#define Install_tm27_vector( handler ) \
+ set_vector( (handler), TEST_VECTOR, 1 );
+
+#define Cause_tm27_intr() \
+ asm volatile( "ta 0x10; nop " );
+
+#define Clear_tm27_intr()
+
+#define Lower_tm27_intr()
+
+/*
+ * The asynchronous trap is an arbitrarily chosen ERC32 interrupt source.
+ */
+
+#else /* use a regular asynchronous trap */
+
+#define TEST_INTERRUPT_SOURCE ERC32_INTERRUPT_EXTERNAL_1
+#define TEST_INTERRUPT_SOURCE2 (ERC32_INTERRUPT_EXTERNAL_1+1)
+#define TEST_VECTOR ERC32_TRAP_TYPE( TEST_INTERRUPT_SOURCE )
+#define TEST_VECTOR2 ERC32_TRAP_TYPE( TEST_INTERRUPT_SOURCE2 )
+
+#define MUST_WAIT_FOR_INTERRUPT 1
+
+#define Install_tm27_vector( handler ) \
+ set_vector( (handler), TEST_VECTOR, 1 ); \
+ set_vector( (handler), TEST_VECTOR2, 1 );
+
+#define Cause_tm27_intr() \
+ do { \
+ ERC32_Force_interrupt( TEST_INTERRUPT_SOURCE+(Interrupt_nest>>1) ); \
+ nop(); \
+ nop(); \
+ nop(); \
+ } while (0)
+
+#define Clear_tm27_intr() \
+ ERC32_Clear_interrupt( TEST_INTERRUPT_SOURCE )
+
+#define Lower_tm27_intr()
+
+#endif
+
+#endif
diff --git a/c/src/lib/libbsp/sparc/leon/ChangeLog b/c/src/lib/libbsp/sparc/leon/ChangeLog
index 35aca21ca4..32c8dad4e4 100644
--- a/c/src/lib/libbsp/sparc/leon/ChangeLog
+++ b/c/src/lib/libbsp/sparc/leon/ChangeLog
@@ -1,3 +1,8 @@
+2004-04-22 Ralf Corsepius <ralf_corsepius@rtems.org>
+
+ * include/bsp.h: Split out tmtest27 support.
+ * include/tm27.h: New.
+
2004-04-21 Ralf Corsepius <ralf_corsepius@rtems.org>
PR 613/bsps
diff --git a/c/src/lib/libbsp/sparc/leon/include/bsp.h b/c/src/lib/libbsp/sparc/leon/include/bsp.h
index 602693bad9..ee63921dea 100644
--- a/c/src/lib/libbsp/sparc/leon/include/bsp.h
+++ b/c/src/lib/libbsp/sparc/leon/include/bsp.h
@@ -54,67 +54,6 @@ extern int rtems_leon_open_eth_driver_attach (struct rtems_bsdnet_ifconfig *conf
#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_leon_open_eth_driver_attach
/*
- * Define the interrupt mechanism for Time Test 27
- *
- * NOTE: Since the interrupt code for the SPARC supports both synchronous
- * and asynchronous trap handlers, support for testing with both
- * is included.
- */
-
-#define SIS_USE_SYNCHRONOUS_TRAP 0
-
-/*
- * The synchronous trap is an arbitrarily chosen software trap.
- */
-
-#if (SIS_USE_SYNCHRONOUS_TRAP == 1)
-
-#define TEST_VECTOR SPARC_SYNCHRONOUS_TRAP( 0x90 )
-
-#define MUST_WAIT_FOR_INTERRUPT 1
-
-#define Install_tm27_vector( handler ) \
- set_vector( (handler), TEST_VECTOR, 1 );
-
-#define Cause_tm27_intr() \
- asm volatile( "ta 0x10; nop " );
-
-#define Clear_tm27_intr()
-
-#define Lower_tm27_intr()
-
-/*
- * The asynchronous trap is an arbitrarily chosen ERC32 interrupt source.
- */
-
-#else /* use a regular asynchronous trap */
-
-#define TEST_INTERRUPT_SOURCE LEON_INTERRUPT_EXTERNAL_1
-#define TEST_VECTOR LEON_TRAP_TYPE( TEST_INTERRUPT_SOURCE )
-#define TEST_INTERRUPT_SOURCE2 LEON_INTERRUPT_EXTERNAL_1+1
-#define TEST_VECTOR2 LEON_TRAP_TYPE( TEST_INTERRUPT_SOURCE2 )
-#define MUST_WAIT_FOR_INTERRUPT 1
-
-#define Install_tm27_vector( handler ) \
- set_vector( (handler), TEST_VECTOR, 1 ); \
- set_vector( (handler), TEST_VECTOR2, 1 );
-
-#define Cause_tm27_intr() \
- do { \
- LEON_Force_interrupt( TEST_INTERRUPT_SOURCE+(Interrupt_nest>>1)); \
- nop(); \
- nop(); \
- nop(); \
- } while (0)
-
-#define Clear_tm27_intr() \
- LEON_Clear_interrupt( TEST_INTERRUPT_SOURCE )
-
-#define Lower_tm27_intr()
-
-#endif
-
-/*
* Simple spin delay in microsecond units for device drivers.
* This is very dependent on the clock speed of the target.
*/
diff --git a/c/src/lib/libbsp/sparc/leon/include/tm27.h b/c/src/lib/libbsp/sparc/leon/include/tm27.h
new file mode 100644
index 0000000000..c493ef67be
--- /dev/null
+++ b/c/src/lib/libbsp/sparc/leon/include/tm27.h
@@ -0,0 +1,79 @@
+/*
+ * tm27.h
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ *
+ * $Id$
+ */
+
+#ifndef _TMTEST27
+#error "This is an RTEMS internal file you must not include directly."
+#endif
+
+#ifndef __tm27_h
+#define __tm27_h
+
+/*
+ * Define the interrupt mechanism for Time Test 27
+ *
+ * NOTE: Since the interrupt code for the SPARC supports both synchronous
+ * and asynchronous trap handlers, support for testing with both
+ * is included.
+ */
+
+#define SIS_USE_SYNCHRONOUS_TRAP 0
+
+/*
+ * The synchronous trap is an arbitrarily chosen software trap.
+ */
+
+#if (SIS_USE_SYNCHRONOUS_TRAP == 1)
+
+#define TEST_VECTOR SPARC_SYNCHRONOUS_TRAP( 0x90 )
+
+#define MUST_WAIT_FOR_INTERRUPT 1
+
+#define Install_tm27_vector( handler ) \
+ set_vector( (handler), TEST_VECTOR, 1 );
+
+#define Cause_tm27_intr() \
+ asm volatile( "ta 0x10; nop " );
+
+#define Clear_tm27_intr()
+
+#define Lower_tm27_intr()
+
+/*
+ * The asynchronous trap is an arbitrarily chosen ERC32 interrupt source.
+ */
+
+#else /* use a regular asynchronous trap */
+
+#define TEST_INTERRUPT_SOURCE LEON_INTERRUPT_EXTERNAL_1
+#define TEST_VECTOR LEON_TRAP_TYPE( TEST_INTERRUPT_SOURCE )
+#define TEST_INTERRUPT_SOURCE2 LEON_INTERRUPT_EXTERNAL_1+1
+#define TEST_VECTOR2 LEON_TRAP_TYPE( TEST_INTERRUPT_SOURCE2 )
+#define MUST_WAIT_FOR_INTERRUPT 1
+
+#define Install_tm27_vector( handler ) \
+ set_vector( (handler), TEST_VECTOR, 1 ); \
+ set_vector( (handler), TEST_VECTOR2, 1 );
+
+#define Cause_tm27_intr() \
+ do { \
+ LEON_Force_interrupt( TEST_INTERRUPT_SOURCE+(Interrupt_nest>>1)); \
+ nop(); \
+ nop(); \
+ nop(); \
+ } while (0)
+
+#define Clear_tm27_intr() \
+ LEON_Clear_interrupt( TEST_INTERRUPT_SOURCE )
+
+#define Lower_tm27_intr()
+
+#endif
+
+#endif
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