diff options
Diffstat (limited to '')
53 files changed, 3294 insertions, 1679 deletions
diff --git a/bsps/include/bsp/fatal.h b/bsps/include/bsp/fatal.h index f9b9e39193..a11235d00f 100644 --- a/bsps/include/bsp/fatal.h +++ b/bsps/include/bsp/fatal.h @@ -174,6 +174,9 @@ typedef enum { IMXRT_FATAL_LPI2C_HW_INIT_FAILED, IMXRT_FATAL_LPI2C_REGISTER_FAILED, IMXRT_FATAL_LPI2C_UNSUPPORTED_HARDWARE, + + /* MicroBlaze fatal codes */ + MICROBLAZE_FATAL_CLOCK_IRQ_INSTALL = BSP_FATAL_CODE_BLOCK(16), } bsp_fatal_code; RTEMS_NO_RETURN static inline void diff --git a/c/src/lib/libbsp/microblaze/shared/include/linker-symbols.h b/bsps/microblaze/include/bsp/linker-symbols.h index 60a5057486..da162060b5 100644 --- a/c/src/lib/libbsp/microblaze/shared/include/linker-symbols.h +++ b/bsps/microblaze/include/bsp/linker-symbols.h @@ -1,5 +1,7 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /* - * Copyright (C) 2015 Hesham Almatary + * Copyright (C) 2015 Hesham Almatary * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -7,8 +9,8 @@ * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE diff --git a/bsps/microblaze/include/common/xil_types.h b/bsps/microblaze/include/common/xil_types.h new file mode 100644 index 0000000000..929e83f8f0 --- /dev/null +++ b/bsps/microblaze/include/common/xil_types.h @@ -0,0 +1,197 @@ +/****************************************************************************** +* Copyright (c) 2010 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xil_types.h +* +* @addtogroup common_types Basic Data types for Xilinx® Software IP +* +* The xil_types.h file contains basic types for Xilinx software IP. These data types +* are applicable for all processors supported by Xilinx. +* @{ +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 1.00a hbm 07/14/09 First release +* 3.03a sdm 05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros +* 5.00 pkp 05/29/14 Made changes for 64 bit architecture +* srt 07/14/14 Use standard definitions from stdint.h and stddef.h +* Define LONG and ULONG datatypes and mask values +* 7.00 mus 01/07/19 Add cpp extern macro +* 7.1 aru 08/19/19 Shift the value in UPPER_32_BITS only if it +* is 64-bit processor +* </pre> +* +******************************************************************************/ + +#ifndef XIL_TYPES_H /* prevent circular inclusions */ +#define XIL_TYPES_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +#include <stdint.h> +#include <stddef.h> + +/************************** Constant Definitions *****************************/ + +#ifndef TRUE +# define TRUE 1U +#endif + +#ifndef FALSE +# define FALSE 0U +#endif + +#ifndef NULL +#define NULL 0U +#endif + +#define XIL_COMPONENT_IS_READY 0x11111111U /**< In device drivers, This macro will be + assigend to "IsReady" member of driver + instance to indicate that driver + instance is initialized and ready to use. */ +#define XIL_COMPONENT_IS_STARTED 0x22222222U /**< In device drivers, This macro will be assigend to + "IsStarted" member of driver instance + to indicate that driver instance is + started and it can be enabled. */ + +/* @name New types + * New simple types. + * @{ + */ +#ifndef __KERNEL__ +#ifndef XBASIC_TYPES_H +/* + * guarded against xbasic_types.h. + */ +typedef uint8_t u8; +typedef uint16_t u16; +typedef uint32_t u32; +/** @}*/ +#define __XUINT64__ +typedef struct +{ + u32 Upper; + u32 Lower; +} Xuint64; + + +/*****************************************************************************/ +/** +* @brief Return the most significant half of the 64 bit data type. +* +* @param x is the 64 bit word. +* +* @return The upper 32 bits of the 64 bit word. +* +******************************************************************************/ +#define XUINT64_MSW(x) ((x).Upper) + +/*****************************************************************************/ +/** +* @brief Return the least significant half of the 64 bit data type. +* +* @param x is the 64 bit word. +* +* @return The lower 32 bits of the 64 bit word. +* +******************************************************************************/ +#define XUINT64_LSW(x) ((x).Lower) + +#endif /* XBASIC_TYPES_H */ + +/* + * xbasic_types.h does not typedef s* or u64 + */ +/** @{ */ +typedef char char8; +typedef int8_t s8; +typedef int16_t s16; +typedef int32_t s32; +typedef int64_t s64; +typedef uint64_t u64; +typedef int sint32; + +typedef intptr_t INTPTR; +typedef uintptr_t UINTPTR; +typedef ptrdiff_t PTRDIFF; +/** @}*/ +#if !defined(LONG) || !defined(ULONG) +typedef long LONG; +typedef unsigned long ULONG; +#endif + +#define ULONG64_HI_MASK 0xFFFFFFFF00000000U +#define ULONG64_LO_MASK ~ULONG64_HI_MASK + +#else +#include <linux/types.h> +#endif + +/** @{ */ +/** + * This data type defines an interrupt handler for a device. + * The argument points to the instance of the component + */ +typedef void (*XInterruptHandler) (void *InstancePtr); + +/** + * This data type defines an exception handler for a processor. + * The argument points to the instance of the component + */ +typedef void (*XExceptionHandler) (void *InstancePtr); + +/** + * @brief Returns 32-63 bits of a number. + * @param n : Number being accessed. + * @return Bits 32-63 of number. + * + * @note A basic shift-right of a 64- or 32-bit quantity. + * Use this to suppress the "right shift count >= width of type" + * warning when that quantity is 32-bits. + */ +#if defined (__aarch64__) || defined (__arch64__) +#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16)) +#else +#define UPPER_32_BITS(n) 0U +#endif +/** + * @brief Returns 0-31 bits of a number + * @param n : Number being accessed. + * @return Bits 0-31 of number + */ +#define LOWER_32_BITS(n) ((u32)(n)) + + + + +/************************** Constant Definitions *****************************/ + +#ifndef TRUE +#define TRUE 1U +#endif + +#ifndef FALSE +#define FALSE 0U +#endif + +#ifndef NULL +#define NULL 0U +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** +* @} End of "addtogroup common_types". +*/
\ No newline at end of file diff --git a/bsps/microblaze/include/dev/serial/uartlite.h b/bsps/microblaze/include/dev/serial/uartlite.h new file mode 100644 index 0000000000..6e288d4dc7 --- /dev/null +++ b/bsps/microblaze/include/dev/serial/uartlite.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief MicroBlaze AXI UART Lite terminal definitions + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_MICROBLAZE_SHARED_UARTLITE_H +#define LIBBSP_MICROBLAZE_SHARED_UARTLITE_H + +#include <rtems/termiostypes.h> + +#include <dev/serial/uartlite_l.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +typedef struct { + rtems_termios_device_context base; + uintptr_t address; + uint32_t initial_baud; +#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS + bool transmitting; +#endif +} uart_lite_context; + +extern const rtems_termios_device_handler microblaze_uart_fns; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_MICROBLAZE_SHARED_UARTLITE_H */ diff --git a/bsps/microblaze/include/dev/serial/uartlite_l.h b/bsps/microblaze/include/dev/serial/uartlite_l.h new file mode 100644 index 0000000000..8c0598e191 --- /dev/null +++ b/bsps/microblaze/include/dev/serial/uartlite_l.h @@ -0,0 +1,323 @@ +/****************************************************************************** +* Copyright (C) 2002 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/****************************************************************************/ +/** +* +* @file xuartlite_l.h +* @addtogroup uartlite_v3_5 +* @{ +* +* This header file contains identifiers and low-level driver functions (or +* macros) that can be used to access the device. High-level driver functions +* are defined in xuartlite.h. +* +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ------------------------------------------------------- +* 1.00b rpm 04/25/02 First release +* 1.00b rpm 07/07/03 Removed references to XUartLite_GetControlReg macro +* since the control register is write-only +* 1.12a mta 03/21/07 Updated to new coding style +* 1.13a sv 01/21/08 Updated driver to support access through DCR bus +* 2.00a ktn 10/20/09 Updated to use HAL Processor APIs. The macros have been +* renamed to remove _m from the name. +* 3.2 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425. +* Changed the prototypes of XUartLite_SendByte, +* XUartLite_RecvByte APIs. +* </pre> +* +*****************************************************************************/ + +#ifndef XUARTLITE_L_H /* prevent circular inclusions */ +#define XUARTLITE_L_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +#ifndef __rtems__ +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" +#else +#include <common/xil_types.h> +static inline u32 Xil_In32(UINTPTR Addr) +{ + return *(volatile u32 *) Addr; +} +static inline void Xil_Out32(UINTPTR Addr, u32 Value) +{ + volatile u32 *LocalAddr = (volatile u32 *)Addr; + *LocalAddr = Value; +} +#endif /* __rtems__ */ + +/* + * XPAR_XUARTLITE_USE_DCR_BRIDGE has to be set to 1 if the UartLite device is + * accessed through a DCR bus connected to a bridge. + */ +#define XPAR_XUARTLITE_USE_DCR_BRIDGE 0 + +#if (XPAR_XUARTLITE_USE_DCR_BRIDGE != 0) +#include "xio_dcr.h" +#endif + + +/************************** Constant Definitions ****************************/ + +/* UART Lite register offsets */ + +#if (XPAR_XUARTLITE_USE_DCR_BRIDGE != 0) +#define XUL_RX_FIFO_OFFSET 0 /* receive FIFO, read only */ +#define XUL_TX_FIFO_OFFSET 1 /* transmit FIFO, write only */ +#define XUL_STATUS_REG_OFFSET 2 /* status register, read only */ +#define XUL_CONTROL_REG_OFFSET 3 /* control reg, write only */ + +#else + +#define XUL_RX_FIFO_OFFSET 0 /* receive FIFO, read only */ +#define XUL_TX_FIFO_OFFSET 4 /* transmit FIFO, write only */ +#define XUL_STATUS_REG_OFFSET 8 /* status register, read only */ +#define XUL_CONTROL_REG_OFFSET 12 /* control reg, write only */ + +#endif + +/* Control Register bit positions */ + +#define XUL_CR_ENABLE_INTR 0x10 /* enable interrupt */ +#define XUL_CR_FIFO_RX_RESET 0x02 /* reset receive FIFO */ +#define XUL_CR_FIFO_TX_RESET 0x01 /* reset transmit FIFO */ + +/* Status Register bit positions */ + +#define XUL_SR_PARITY_ERROR 0x80 +#define XUL_SR_FRAMING_ERROR 0x40 +#define XUL_SR_OVERRUN_ERROR 0x20 +#define XUL_SR_INTR_ENABLED 0x10 /* interrupt enabled */ +#define XUL_SR_TX_FIFO_FULL 0x08 /* transmit FIFO full */ +#define XUL_SR_TX_FIFO_EMPTY 0x04 /* transmit FIFO empty */ +#define XUL_SR_RX_FIFO_FULL 0x02 /* receive FIFO full */ +#define XUL_SR_RX_FIFO_VALID_DATA 0x01 /* data in receive FIFO */ + +/* The following constant specifies the size of the Transmit/Receive FIFOs. + * The FIFO size is fixed to 16 in the Uartlite IP and the size is not + * configurable. This constant is not used in the driver. + */ +#define XUL_FIFO_SIZE 16 + +/* Stop bits are fixed at 1. Baud, parity, and data bits are fixed on a + * per instance basis + */ +#define XUL_STOP_BITS 1 + +/* Parity definitions + */ +#define XUL_PARITY_NONE 0 +#define XUL_PARITY_ODD 1 +#define XUL_PARITY_EVEN 2 + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/* + * Define the appropriate I/O access method to memory mapped I/O or DCR. + */ +#if (XPAR_XUARTLITE_USE_DCR_BRIDGE != 0) + +#define XUartLite_In32 XIo_DcrIn +#define XUartLite_Out32 XIo_DcrOut + +#else + +#define XUartLite_In32 Xil_In32 +#define XUartLite_Out32 Xil_Out32 + +#endif + + +/****************************************************************************/ +/** +* +* Write a value to a UartLite register. A 32 bit write is performed. +* +* @param BaseAddress is the base address of the UartLite device. +* @param RegOffset is the register offset from the base to write to. +* @param Data is the data written to the register. +* +* @return None. +* +* @note C-style signature: +* void XUartLite_WriteReg(u32 BaseAddress, u32 RegOffset, +* u32 Data) +* +****************************************************************************/ +#define XUartLite_WriteReg(BaseAddress, RegOffset, Data) \ + XUartLite_Out32((BaseAddress) + (RegOffset), (u32)(Data)) + +/****************************************************************************/ +/** +* +* Read a value from a UartLite register. A 32 bit read is performed. +* +* @param BaseAddress is the base address of the UartLite device. +* @param RegOffset is the register offset from the base to read from. +* +* @return Data read from the register. +* +* @note C-style signature: +* u32 XUartLite_ReadReg(u32 BaseAddress, u32 RegOffset) +* +****************************************************************************/ +#define XUartLite_ReadReg(BaseAddress, RegOffset) \ + XUartLite_In32((BaseAddress) + (RegOffset)) + + +/****************************************************************************/ +/** +* +* Set the contents of the control register. Use the XUL_CR_* constants defined +* above to create the bit-mask to be written to the register. +* +* @param BaseAddress is the base address of the device +* @param Mask is the 32-bit value to write to the control register +* +* @return None. +* +* @note C-style Signature: +* void XUartLite_SetControlReg(u32 BaseAddress, u32 Mask); +* +*****************************************************************************/ +#define XUartLite_SetControlReg(BaseAddress, Mask) \ + XUartLite_WriteReg((BaseAddress), XUL_CONTROL_REG_OFFSET, (Mask)) + + +/****************************************************************************/ +/** +* +* Get the contents of the status register. Use the XUL_SR_* constants defined +* above to interpret the bit-mask returned. +* +* @param BaseAddress is the base address of the device +* +* @return A 32-bit value representing the contents of the status register. +* +* @note C-style Signature: +* u32 XUartLite_GetStatusReg(u32 BaseAddress); +* +*****************************************************************************/ +#define XUartLite_GetStatusReg(BaseAddress) \ + XUartLite_ReadReg((BaseAddress), XUL_STATUS_REG_OFFSET) + + +/****************************************************************************/ +/** +* +* Check to see if the receiver has data. +* +* @param BaseAddress is the base address of the device +* +* @return TRUE if the receiver is empty, FALSE if there is data present. +* +* @note C-style Signature: +* int XUartLite_IsReceiveEmpty(u32 BaseAddress); +* +*****************************************************************************/ +#define XUartLite_IsReceiveEmpty(BaseAddress) \ + ((XUartLite_GetStatusReg((BaseAddress)) & XUL_SR_RX_FIFO_VALID_DATA) != \ + XUL_SR_RX_FIFO_VALID_DATA) + + +/****************************************************************************/ +/** +* +* Check to see if the transmitter is full. +* +* @param BaseAddress is the base address of the device +* +* @return TRUE if the transmitter is full, FALSE otherwise. +* +* @note C-style Signature: +* int XUartLite_IsTransmitFull(u32 BaseAddress); +* +*****************************************************************************/ +#define XUartLite_IsTransmitFull(BaseAddress) \ + ((XUartLite_GetStatusReg((BaseAddress)) & XUL_SR_TX_FIFO_FULL) == \ + XUL_SR_TX_FIFO_FULL) + + +/****************************************************************************/ +/** +* +* Check to see if the interrupt is enabled. +* +* @param BaseAddress is the base address of the device +* +* @return TRUE if the interrupt is enabled, FALSE otherwise. +* +* @note C-style Signature: +* int XUartLite_IsIntrEnabled(u32 BaseAddress); +* +*****************************************************************************/ +#define XUartLite_IsIntrEnabled(BaseAddress) \ + ((XUartLite_GetStatusReg((BaseAddress)) & XUL_SR_INTR_ENABLED) == \ + XUL_SR_INTR_ENABLED) + + +/****************************************************************************/ +/** +* +* Enable the device interrupt. We cannot read the control register, so we +* just write the enable interrupt bit and clear all others. Since the only +* other ones are the FIFO reset bits, this works without side effects. +* +* @param BaseAddress is the base address of the device +* +* @return None. +* +* @note C-style Signature: +* void XUartLite_EnableIntr(u32 BaseAddress); +* +*****************************************************************************/ +#define XUartLite_EnableIntr(BaseAddress) \ + XUartLite_SetControlReg((BaseAddress), XUL_CR_ENABLE_INTR) + + +/****************************************************************************/ +/** +* +* Disable the device interrupt. We cannot read the control register, so we +* just clear all bits. Since the only other ones are the FIFO reset bits, +* this works without side effects. +* +* @param BaseAddress is the base address of the device +* +* @return None. +* +* @note C-style Signature: +* void XUartLite_DisableIntr(u32 BaseAddress); +* +*****************************************************************************/ +#define XUartLite_DisableIntr(BaseAddress) \ + XUartLite_SetControlReg((BaseAddress), 0) + +/************************** Function Prototypes *****************************/ + +void XUartLite_SendByte(UINTPTR BaseAddress, u8 Data); +u8 XUartLite_RecvByte(UINTPTR BaseAddress); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ + + +/** @} */ diff --git a/bsps/microblaze/microblaze_fpga/clock/clock.c b/bsps/microblaze/microblaze_fpga/clock/clock.c new file mode 100644 index 0000000000..957d0fdadb --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/clock/clock.c @@ -0,0 +1,145 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief MicroBlaze AXI Timer clock support + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <bsp/fatal.h> +#include <bsp/timer.h> + +#include <rtems.h> +#include <rtems/irq-extension.h> +#include <rtems/timecounter.h> + +static rtems_timecounter_simple mblaze_tc; + +static uint32_t microblaze_tc_get( rtems_timecounter_simple *tc ) +{ + volatile Microblaze_Timer *timer = _Microblaze_Timer; + return timer->tcr0; +} + +static bool microblaze_tc_is_pending( rtems_timecounter_simple *tc ) +{ + volatile Microblaze_Timer *timer = _Microblaze_Timer; + return ( timer->tcsr0 & MICROBLAZE_TIMER_TCSR0_T0INT ) != 0; +} + +static uint32_t microblaze_tc_get_timecount( struct timecounter *tc ) +{ + return rtems_timecounter_simple_downcounter_get( + tc, + microblaze_tc_get, + microblaze_tc_is_pending + ); +} + +static void microblaze_clock_initialize( void ) +{ + volatile Microblaze_Timer *timer = _Microblaze_Timer; + /* Set load register to 0 */ + timer->tlr0 = 0; + /* Reset the timer and interrupt */ + timer->tcsr0 = MICROBLAZE_TIMER_TCSR0_T0INT | MICROBLAZE_TIMER_TCSR0_LOAD0; + /* Release the reset */ + timer->tcsr0 = 0; + /* + * Enable interrupt, auto reload mode, external interrupt signal, + * and down counter + */ + timer->tcsr0 = MICROBLAZE_TIMER_TCSR0_ARHT0 | MICROBLAZE_TIMER_TCSR0_ENIT0 | + MICROBLAZE_TIMER_TCSR0_GENT0 | MICROBLAZE_TIMER_TCSR0_UDT0; + + uint64_t us_per_tick = rtems_configuration_get_microseconds_per_tick(); + uint32_t counter_frequency_in_hz = BSP_MICROBLAZE_FPGA_TIMER_FREQUENCY; + uint32_t counter_ticks_per_clock_tick = + ( counter_frequency_in_hz * us_per_tick ) / 1000000; + + /* Set a reset value for the timer counter */ + timer->tlr0 = counter_ticks_per_clock_tick; + uint32_t control_status_reg = timer->tcsr0; + /* Load the reset value into the counter register */ + timer->tcsr0 = MICROBLAZE_TIMER_TCSR0_LOAD0; + /* Enable the timer */ + timer->tcsr0 = control_status_reg | MICROBLAZE_TIMER_TCSR0_ENT0; + + rtems_timecounter_simple_install( + &mblaze_tc, + counter_frequency_in_hz, + counter_ticks_per_clock_tick, + microblaze_tc_get_timecount + ); +} + +static void microblaze_clock_at_tick( rtems_timecounter_simple *tc ) +{ + volatile Microblaze_Timer *timer = _Microblaze_Timer; + if ( ( timer->tcsr0 & MICROBLAZE_TIMER_TCSR0_T0INT ) == 0 ) { + return; + } + /* Clear the interrupt */ + timer->tcsr0 |= MICROBLAZE_TIMER_TCSR0_T0INT; +} + +static void microblaze_tc_tick( void ) +{ + rtems_timecounter_simple_downcounter_tick( + &mblaze_tc, + microblaze_tc_get, + microblaze_clock_at_tick + ); +} + +static void microblaze_clock_handler_install( rtems_interrupt_handler isr ) +{ + rtems_status_code sc = RTEMS_SUCCESSFUL; + + sc = rtems_interrupt_handler_install( + 0, + "Clock", + RTEMS_INTERRUPT_UNIQUE, + isr, + NULL + ); + + if ( sc != RTEMS_SUCCESSFUL ) { + bsp_fatal( MICROBLAZE_FATAL_CLOCK_IRQ_INSTALL ); + } +} + +#define Clock_driver_support_initialize_hardware() microblaze_clock_initialize() +#define Clock_driver_support_install_isr( isr ) \ + microblaze_clock_handler_install( isr ) +#define Clock_driver_timecounter_tick() microblaze_tc_tick() + +/* Include shared source clock driver code */ +#include "../../shared/dev/clock/clockimpl.h" diff --git a/bsps/microblaze/microblaze_fpga/console/console-io.c b/bsps/microblaze/microblaze_fpga/console/console-io.c new file mode 100644 index 0000000000..cb2e367035 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/console/console-io.c @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief MicroBlaze console configuration + */ + +/* + * Copyright (C) 2015 Hesham Almatary + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <bsp/console-termios.h> +#include <dev/serial/uartlite.h> + +#include <bspopts.h> + +uart_lite_context microblaze_qemu_uart_context = { + .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "UARTLITE" ), + .address = BSP_MICROBLAZE_FPGA_UART_BASE, + .initial_baud = 115200 +}; + +const console_device console_device_table[] = { + { + .device_file = "/dev/ttyS0", + .probe = console_device_probe_default, + .handler = µblaze_uart_fns, + .context = µblaze_qemu_uart_context.base + } +}; + +const size_t console_device_count = RTEMS_ARRAY_SIZE( console_device_table ); diff --git a/c/src/lib/libbsp/microblaze/microblaze_fpga/console/console-io.c b/bsps/microblaze/microblaze_fpga/console/debug-io.c index 47592967ac..e88f5468a7 100644 --- a/c/src/lib/libbsp/microblaze/microblaze_fpga/console/console-io.c +++ b/bsps/microblaze/microblaze_fpga/console/debug-io.c @@ -1,13 +1,16 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** * @file * - * @ingroup microblaze_uart + * @ingroup RTEMSBSPsMicroblaze * - * @brief Console Configuration. + * @brief MicroBlaze debug IO support */ /* - * Copyright (C) 2015 Hesham Almatary + * Copyright (C) 2015 Hesham Almatary + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -15,8 +18,8 @@ * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE @@ -31,44 +34,33 @@ * POSSIBILITY OF SUCH DAMAGE. */ +#include <dev/serial/uartlite_l.h> #include <rtems/bspIo.h> -#include <libchip/serial.h> - #include <bspopts.h> -#include <bsp/uart.h> -console_tbl Console_Configuration_Ports [] = { - { - .sDeviceName = "/dev/ttyS0", - .deviceType = SERIAL_CUSTOM, - .pDeviceFns = µblaze_uart_fns, - .deviceProbe = NULL, - .pDeviceFlow = NULL, - .ulCtrlPort1 = UART_BASEADDRESS, - .ulCtrlPort2 = 0, - .ulClock = 9600, - .ulIntVector = 0 - } -}; +static void output_char( char c ) +{ + if ( c == '\n' ) { + XUartLite_SendByte( BSP_MICROBLAZE_FPGA_UART_BASE, '\r' ); + } + XUartLite_SendByte( BSP_MICROBLAZE_FPGA_UART_BASE, c ); +} -#define PORT_COUNT \ - (sizeof(Console_Configuration_Ports) \ - / sizeof(Console_Configuration_Ports [0])) +static int xUartLite_RecvByte( int minor ) +{ + if ( XUartLite_IsReceiveEmpty( BSP_MICROBLAZE_FPGA_UART_BASE ) ) { + return -1; + } -unsigned long Console_Configuration_Count = PORT_COUNT; + return XUartLite_ReadReg( BSP_MICROBLAZE_FPGA_UART_BASE, XUL_RX_FIFO_OFFSET ); +} -static void output_char(char c) +static int get_char( void ) { - const console_fns *con = - Console_Configuration_Ports [Console_Port_Minor].pDeviceFns; - - if (c == '\n') { - con->deviceWritePolled((int) Console_Port_Minor, '\r'); - } - con->deviceWritePolled((int) Console_Port_Minor, c); + return xUartLite_RecvByte( 0 ); } BSP_output_char_function_type BSP_output_char = output_char; -BSP_polling_getchar_function_type BSP_poll_char = NULL; +BSP_polling_getchar_function_type BSP_poll_char = get_char; diff --git a/c/src/lib/libbsp/microblaze/microblaze_fpga/include/bsp.h b/bsps/microblaze/microblaze_fpga/include/bsp.h index cb72835571..e83e632553 100644 --- a/c/src/lib/libbsp/microblaze/microblaze_fpga/include/bsp.h +++ b/bsps/microblaze/microblaze_fpga/include/bsp.h @@ -1,5 +1,16 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief Core BSP definitions + */ + /* - * Copyright (C) 2015 Hesham Almatary + * Copyright (C) 2015 Hesham Almatary + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -7,8 +18,8 @@ * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE @@ -23,26 +34,20 @@ * POSSIBILITY OF SUCH DAMAGE. */ -#ifndef _BSP_H -#define _BSP_H +#ifndef LIBBSP_MICROBLAZE_FPGA_BSP_H +#define LIBBSP_MICROBLAZE_FPGA_BSP_H #ifdef __cplusplus extern "C" { #endif #include <bspopts.h> +#include <bsp/default-initial-extension.h> #include <rtems.h> -#include <rtems/iosupp.h> -#include <rtems/console.h> -#include <rtems/clockdrv.h> - -/* support for simulated clock tick */ -Thread clock_driver_sim_idle_body(uintptr_t); -#define BSP_IDLE_TASK_BODY clock_driver_sim_idle_body #ifdef __cplusplus } #endif -#endif +#endif /* LIBBSP_MICROBLAZE_FPGA_BSP_H */ diff --git a/bsps/microblaze/microblaze_fpga/include/bsp/intc.h b/bsps/microblaze/microblaze_fpga/include/bsp/intc.h new file mode 100644 index 0000000000..df4554386d --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/include/bsp/intc.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief MicroBlaze AXI Interrupt Controller definitions + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_MICROBLAZE_FPGA_INTC_H +#define LIBBSP_MICROBLAZE_FPGA_INTC_H + +#include <bspopts.h> + +#include <bsp/utility.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +typedef struct { + /* Interrupt Status Register */ + uint32_t isr; + uint32_t ipr; + /* Interrupt Enable Register */ + uint32_t ier; + /* Interrupt Acknowledge Register */ + uint32_t iar; + uint32_t sie; + uint32_t cie; + uint32_t ivr; +#define MICROBLAZE_INTC_MER_HIE BSP_BIT32(1) +#define MICROBLAZE_INTC_MER_ME BSP_BIT32(0) + /* Master Enable Register */ + uint32_t mer; + /* Interrupt Mode Register, this is present only for Fast Interrupt */ + uint32_t imr; + /* Interrupt Level Register */ + uint32_t ilr; +} Microblaze_INTC; + +#define _Microblaze_INTC ((volatile Microblaze_INTC *) BSP_MICROBLAZE_FPGA_INTC_BASE) + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_MICROBLAZE_FPGA_INTC_H */ diff --git a/bsps/microblaze/microblaze_fpga/include/bsp/irq.h b/bsps/microblaze/microblaze_fpga/include/bsp/irq.h new file mode 100644 index 0000000000..0a7c211fb0 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/include/bsp/irq.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief BSP IRQ definitions + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_MICROBLAZE_FPGA_IRQ_H +#define LIBBSP_MICROBLAZE_FPGA_IRQ_H + +#ifndef ASM + +#include <rtems.h> +#include <rtems/irq.h> +#include <rtems/irq-extension.h> + +#endif /* ASM */ + +#define BSP_INTERRUPT_VECTOR_COUNT 32 + +#endif /* LIBBSP_MICROBLAZE_FPGA_IRQ_H */ diff --git a/bsps/microblaze/microblaze_fpga/include/bsp/timer.h b/bsps/microblaze/microblaze_fpga/include/bsp/timer.h new file mode 100644 index 0000000000..562fdd79b0 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/include/bsp/timer.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief MicroBlaze AXI Timer definitions + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef LIBBSP_MICROBLAZE_FPGA_TIMER_H +#define LIBBSP_MICROBLAZE_FPGA_TIMER_H + +#include <bspopts.h> + +#include <bsp/utility.h> + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +typedef struct { +#define MICROBLAZE_TIMER_TCSR0_T0INT BSP_BIT32(8) +#define MICROBLAZE_TIMER_TCSR0_ENT0 BSP_BIT32(7) +#define MICROBLAZE_TIMER_TCSR0_ENIT0 BSP_BIT32(6) +#define MICROBLAZE_TIMER_TCSR0_LOAD0 BSP_BIT32(5) +#define MICROBLAZE_TIMER_TCSR0_ARHT0 BSP_BIT32(4) +#define MICROBLAZE_TIMER_TCSR0_GENT0 BSP_BIT32(2) +#define MICROBLAZE_TIMER_TCSR0_UDT0 BSP_BIT32(1) + /* Control/Status register */ + uint32_t tcsr0; + /* Load register */ + uint32_t tlr0; + /* Timer counter register */ + uint32_t tcr0; +} Microblaze_Timer; + +#define _Microblaze_Timer ((volatile Microblaze_Timer *) BSP_MICROBLAZE_FPGA_TIMER_BASE) + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* LIBBSP_MICROBLAZE_FPGA_TIMER_H */ diff --git a/c/src/lib/libbsp/microblaze/microblaze_fpga/include/tm27.h b/bsps/microblaze/microblaze_fpga/include/tm27.h index 393990157f..f2e384b534 100644 --- a/c/src/lib/libbsp/microblaze/microblaze_fpga/include/tm27.h +++ b/bsps/microblaze/microblaze_fpga/include/tm27.h @@ -1,6 +1,15 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief BSP tm27 header + */ + /* - * COPYRIGHT (c) 1989-2011. - * On-Line Applications Research Corporation (OAR). + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -8,8 +17,8 @@ * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE @@ -32,17 +41,18 @@ #define __tm27_h /* - * Define the interrupt mechanism for Time Test 27 + * Time Test 27 cannot be implemented reliably because the AXI interrupt + * controller is not guaranteed to support software interrupts. */ #define MUST_WAIT_FOR_INTERRUPT 0 #define Install_tm27_vector( handler ) /* set_vector( (handler), 6, 1 ) */ -#define Cause_tm27_intr() /* XXX */ +#define Cause_tm27_intr() /* empty */ -#define Clear_tm27_intr() /* XXX */ +#define Clear_tm27_intr() /* empty */ #define Lower_tm27_intr() /* empty */ -#endif +#endif /* __tm27_h */ diff --git a/bsps/microblaze/microblaze_fpga/irq/irq.c b/bsps/microblaze/microblaze_fpga/irq/irq.c new file mode 100644 index 0000000000..67ddf02079 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/irq/irq.c @@ -0,0 +1,168 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief MicroBlaze interrupt support + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <bsp/intc.h> +#include <bsp/irq-generic.h> + +#include <rtems/score/cpu.h> + +static void ack_interrupt( uint8_t source ) +{ + volatile Microblaze_INTC *intc = _Microblaze_INTC; + intc->iar = 0x1 << source; +} + +rtems_status_code bsp_interrupt_get_attributes( + rtems_vector_number vector, + rtems_interrupt_attributes *attributes +) +{ + attributes->is_maskable = true; + attributes->maybe_enable = true; + attributes->maybe_disable = true; + attributes->can_clear = true; + attributes->cleared_by_acknowledge = true; + + return RTEMS_SUCCESSFUL; +} + +rtems_status_code bsp_interrupt_is_pending( + rtems_vector_number vector, + bool *pending +) +{ + bsp_interrupt_assert( bsp_interrupt_is_valid_vector( vector ) ); + bsp_interrupt_assert( pending != NULL ); + *pending = false; + return RTEMS_UNSATISFIED; +} + +rtems_status_code bsp_interrupt_raise( rtems_vector_number vector ) +{ + bsp_interrupt_assert( bsp_interrupt_is_valid_vector( vector ) ); + return RTEMS_UNSATISFIED; +} + +rtems_status_code bsp_interrupt_clear( rtems_vector_number vector ) +{ + bsp_interrupt_assert( bsp_interrupt_is_valid_vector( vector ) ); + + volatile Microblaze_INTC *intc = _Microblaze_INTC; + intc->iar = 0x1 << vector; + + return RTEMS_SUCCESSFUL; +} + +rtems_status_code bsp_interrupt_vector_is_enabled( + rtems_vector_number vector, + bool *enabled +) +{ + bsp_interrupt_assert( bsp_interrupt_is_valid_vector( vector ) ); + bsp_interrupt_assert( enabled != NULL ); + + volatile Microblaze_INTC *intc = _Microblaze_INTC; + uint32_t mask = 1 << vector; + + *enabled = (intc->ier & mask) != 0; + return RTEMS_SUCCESSFUL; +} + +rtems_status_code bsp_interrupt_vector_enable( rtems_vector_number vector ) +{ + bsp_interrupt_assert( bsp_interrupt_is_valid_vector( vector ) ); + + volatile Microblaze_INTC *intc = _Microblaze_INTC; + uint32_t mask = 1 << vector; + + intc->ier |= mask; + + return RTEMS_SUCCESSFUL; +} + +rtems_status_code bsp_interrupt_vector_disable( rtems_vector_number vector ) +{ + bsp_interrupt_assert( bsp_interrupt_is_valid_vector( vector ) ); + + volatile Microblaze_INTC *intc = _Microblaze_INTC; + uint32_t mask = 1 << vector; + + intc->ier &= ~mask; + + return RTEMS_SUCCESSFUL; +} + +void bsp_interrupt_facility_initialize( void ) +{ + volatile Microblaze_INTC *intc = _Microblaze_INTC; + /* + * Enable HW interrupts on the interrupt controller. This happens before + * interrupts are enabled on the processor. + */ + intc->mer = MICROBLAZE_INTC_MER_ME | MICROBLAZE_INTC_MER_HIE; +} + +void bsp_interrupt_dispatch( uint32_t source ) +{ + volatile Microblaze_INTC *intc = _Microblaze_INTC; + uint32_t vector_number = 0; + + if ( source == 0xFF ) { + /* Read interrupt controller to get the source */ + vector_number = intc->isr; + + /* Handle and the first interrupt that is set */ + uint8_t interrupt_status = 0; + for ( int i = 0; i < 32; i++ ) { + interrupt_status = vector_number >> i & 0x1; + if ( interrupt_status != 0 ) { + /* save current ILR */ + uint32_t interrupt_levels = intc->ilr; + /* set ILR to block out every interrupt less than or equal to priority of i */ + intc->ilr = 0xFFFFFFFF >> (32 - i); + bsp_interrupt_handler_dispatch( i ); + ack_interrupt( i ); + /* restore ILR */ + intc->ilr = interrupt_levels; + break; + } + } + } else { + vector_number = source; + + /* Fast interrupt mode. Handle interrupt. Ack happens automatically */ + bsp_interrupt_handler_dispatch( vector_number ); + } +} diff --git a/c/src/lib/libbsp/microblaze/microblaze_fpga/startup/_exception_handler.S b/bsps/microblaze/microblaze_fpga/start/_exception_handler.S index dd9fee22f6..1d96b694a7 100644 --- a/c/src/lib/libbsp/microblaze/microblaze_fpga/startup/_exception_handler.S +++ b/bsps/microblaze/microblaze_fpga/start/_exception_handler.S @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + /* Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved. Redistribution and use in source and binary forms, with or without @@ -34,5 +36,17 @@ .align 2 _exception_handler: +#ifndef __rtems__ rtsd r17, 0 nop +#else /* __rtems__ */ + /* Subtract stack frame */ + addik r1, r1, -52 + + swi r5, r1, 8 + + addi r5, r0, 0xFFFF + + braid _ISR_Handler + nop +#endif /* __rtems__ */ diff --git a/c/src/lib/libbsp/microblaze/gdbmbsim/startup/_hw_exception_handler.S b/bsps/microblaze/microblaze_fpga/start/_hw_exception_handler.S index 7b54d37dda..30436a43e9 100644 --- a/c/src/lib/libbsp/microblaze/gdbmbsim/startup/_hw_exception_handler.S +++ b/bsps/microblaze/microblaze_fpga/start/_hw_exception_handler.S @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + /* Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved. Redistribution and use in source and binary forms, with or without @@ -34,5 +36,17 @@ .align 2 _hw_exception_handler: - rted r17, 0 +#ifndef __rtems__ + rtsd r17, 0 + nop +#else /* __rtems__ */ + /* Subtract stack frame */ + addik r1, r1, -52 + + swi r5, r1, 8 + + addi r5, r0, 0xFFFF + + braid _ISR_Handler nop +#endif /* __rtems__ */ diff --git a/c/src/lib/libbsp/microblaze/microblaze_fpga/startup/_interrupt_handler.S b/bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S index 50326c1a93..b817503922 100644 --- a/c/src/lib/libbsp/microblaze/microblaze_fpga/startup/_interrupt_handler.S +++ b/bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + /* Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved. Redistribution and use in source and binary forms, with or without @@ -34,5 +36,18 @@ .align 2 _interrupt_handler: +#ifndef __rtems__ rtid r14, 0 nop +#else /* __rtems__ */ + /* Subtract stack frame */ + addik r1, r1, -52 + + swi r5, r1, 8 + + /* Indicate unknown interrupt source */ + addi r5, r0, 0xFF + + braid _ISR_Handler + nop +#endif /* __rtems__ */ diff --git a/bsps/microblaze/microblaze_fpga/start/bspreset.c b/bsps/microblaze/microblaze_fpga/start/bspreset.c new file mode 100644 index 0000000000..6a7455f522 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/start/bspreset.c @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief BSP Reset + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <rtems.h> +#include <bsp/bootcard.h> + +void bsp_reset( void ) +{ + __asm__ volatile ( + "brai 0xFFFFFFFFFFFFFFFF" + ); +} diff --git a/bsps/microblaze/microblaze_fpga/start/bspstart.c b/bsps/microblaze/microblaze_fpga/start/bspstart.c new file mode 100644 index 0000000000..0caf385b46 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/start/bspstart.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief BSP Startup + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <bsp.h> +#include <bsp/bootcard.h> +#include <bsp/irq-generic.h> + +void bsp_start( void ) +{ + bsp_interrupt_initialize(); +} diff --git a/bsps/microblaze/microblaze_fpga/start/crtinit.S b/bsps/microblaze/microblaze_fpga/start/crtinit.S new file mode 100644 index 0000000000..a9779404b2 --- /dev/null +++ b/bsps/microblaze/microblaze_fpga/start/crtinit.S @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + +/* Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are + met: + + 1. Redistributions source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + 3. Neither the name of Xilinx nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS + IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + .globl _crtinit + .align 2 + .ent _crtinit + .type _crtinit, @function +_crtinit: + addi r1, r1, -20 /* Save Link register */ + swi r15, r1, 0 + +#ifndef __rtems__ + addi r6, r0, __sbss_start /* clear SBSS */ + addi r7, r0, __sbss_end + rsub r18, r6, r7 + blei r18, .Lendsbss + +.Lloopsbss: + swi r0, r6, 0 + addi r6, r6, 4 + rsub r18, r6, r7 + bgti r18, .Lloopsbss +.Lendsbss: +#endif /* __rtems__ */ + +#ifndef __rtems__ + addi r6, r0, __bss_start /* clear BSS */ + addi r7, r0, __bss_end +#else + addi r6, r0, bsp_section_bss_begin + addi r7, r0, bsp_section_bss_end +#endif /* __rtems__ */ + rsub r18, r6, r7 + blei r18, .Lendbss +.Lloopbss: + swi r0, r6, 0 + addi r6, r6, 4 + rsub r18, r6, r7 + bgti r18, .Lloopbss +.Lendbss: + +#ifndef __rtems__ + brlid r15, _program_init /* Initialize the program */ + nop + + brlid r15, __init /* Invoke language initialization functions */ + nop +#endif /* __rtems__ */ + + addi r6, r0, 0 /* Initialize argc = 1 and argv = NULL and envp = NULL */ + addi r7, r0, 0 +#ifndef __rtems__ + brlid r15, main /* Execute the program */ +#else + brlid r15, boot_card +#endif /* __rtems__ */ + addi r5, r0, 0 + + addik r19, r3, 0 /* Save return value */ + +#ifndef __rtems__ + brlid r15, __fini /* Invoke language cleanup functions */ + nop + + brlid r15, _program_clean /* Cleanup the program */ + nop +#endif /* __rtems__ */ + + lw r15, r1, r0 /* Return back to CRT */ + + addik r3, r19, 0 /* Restore return value */ + rtsd r15, 8 + addi r1, r1, 20 + .end _crtinit diff --git a/bsps/microblaze/shared/cache/cache.c b/bsps/microblaze/shared/cache/cache.c new file mode 100644 index 0000000000..472f3c04f4 --- /dev/null +++ b/bsps/microblaze/shared/cache/cache.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief MicroBlaze cache support + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include "../../../bsps/shared/cache/cacheimpl.h" diff --git a/bsps/microblaze/shared/dev/serial/uartlite.c b/bsps/microblaze/shared/dev/serial/uartlite.c new file mode 100644 index 0000000000..7387e22635 --- /dev/null +++ b/bsps/microblaze/shared/dev/serial/uartlite.c @@ -0,0 +1,145 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSBSPsMicroblaze + * + * @brief MicroBlaze AXI UART Lite support + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <bsp/irq.h> +#include <dev/serial/uartlite.h> + +#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS +static void microblaze_uart_interrupt( void *arg ) +{ + rtems_termios_tty *tty = arg; + uart_lite_context *ctx = rtems_termios_get_device_context( tty ); + + while ( !XUartLite_IsReceiveEmpty( ctx->address ) ) { + char c = (char) XUartLite_ReadReg( ctx->address, XUL_RX_FIFO_OFFSET ); + rtems_termios_enqueue_raw_characters( tty, &c, 1 ); + } + + while ( ctx->transmitting && !XUartLite_IsTransmitEmpty( ctx ) ) { + rtems_termios_dequeue_characters( tty, 1 ); + } +} +#endif + +static bool uart_first_open( + struct rtems_termios_tty *tty, + rtems_termios_device_context *base, + struct termios *term, + rtems_libio_open_close_args_t *args +) +{ + uart_lite_context *ctx = (uart_lite_context *) base; +#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS + rtems_status_code sc; +#endif + + rtems_termios_set_initial_baud( tty, ctx->initial_baud ); + +#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS + XUartLite_EnableIntr( ctx->address ); + sc = rtems_interrupt_handler_install( + 1, + "UART", + RTEMS_INTERRUPT_SHARED, + microblaze_uart_interrupt, + tty + ); + if ( sc != RTEMS_SUCCESSFUL ) { + return false; + } +#endif + + return true; +} + +static void uart_last_close( + rtems_termios_tty *tty, + rtems_termios_device_context *base, + rtems_libio_open_close_args_t *args +) +{ +#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS + rtems_interrupt_handler_remove( 1, microblaze_uart_interrupt, tty ); +#endif +} + +#ifndef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS +static int uart_read_polled( rtems_termios_device_context *base ) +{ + uart_lite_context *ctx = (uart_lite_context *) base; + + if ( XUartLite_IsReceiveEmpty( ctx->address ) ) { + return -1; + } + + return XUartLite_ReadReg( ctx->address, XUL_RX_FIFO_OFFSET ); +} +#endif + +static void uart_write( + rtems_termios_device_context *base, + const char *s, + size_t n +) +{ + uart_lite_context *ctx = (uart_lite_context *) base; + +#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS + if ( n > 0 ) { + ctx->transmitting = true; + XUartLite_SendByte( ctx->address, s[0] ); + } else { + ctx->transmitting = false; + } +#else + size_t i = 0; + + for ( i = 0; i < n; ++i ) { + XUartLite_SendByte( ctx->address, s[i] ); + } +#endif +} + +const rtems_termios_device_handler microblaze_uart_fns = { + .first_open = uart_first_open, + .last_close = uart_last_close, + .write = uart_write, +#ifdef BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS + .mode = TERMIOS_IRQ_DRIVEN +#else + .poll_read = uart_read_polled, + .mode = TERMIOS_POLLED +#endif +}; diff --git a/bsps/microblaze/shared/dev/serial/uartlite_l.c b/bsps/microblaze/shared/dev/serial/uartlite_l.c new file mode 100644 index 0000000000..5acbd6c505 --- /dev/null +++ b/bsps/microblaze/shared/dev/serial/uartlite_l.c @@ -0,0 +1,99 @@ +/****************************************************************************** +* Copyright (C) 2002 - 2020 Xilinx, Inc. All rights reserved. +* SPDX-License-Identifier: MIT +******************************************************************************/ + +/****************************************************************************/ +/** +* +* @file xuartlite_l.c +* @addtogroup uartlite_v3_5 +* @{ +* +* This file contains low-level driver functions that can be used to access the +* device. The user should refer to the hardware device specification for more +* details of the device operation. + +* <pre> +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------- +* 1.00b rpm 04/25/02 First release +* 1.12a rpm 07/16/07 Fixed arg type for RecvByte +* 2.00a ktn 10/20/09 The macros have been renamed to remove _m from the name. +* 3.2 sk 11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425. +* Changed the prototypes of XUartLite_SendByte, +* XUartLite_RecvByte APIs. +* </pre> +* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#ifndef __rtems__ +#include "xuartlite_l.h" +#else +#include <dev/serial/uartlite_l.h> +#endif /* __rtems__ */ + +/************************** Constant Definitions *****************************/ + + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + + +/************************** Variable Prototypes ******************************/ + + +/****************************************************************************/ +/** +* +* This functions sends a single byte using the UART. It is blocking in that it +* waits for the transmitter to become non-full before it writes the byte to +* the transmit register. +* +* @param BaseAddress is the base address of the device +* @param Data is the byte of data to send +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XUartLite_SendByte(UINTPTR BaseAddress, u8 Data) +{ + while (XUartLite_IsTransmitFull(BaseAddress)); + + XUartLite_WriteReg(BaseAddress, XUL_TX_FIFO_OFFSET, Data); +} + + +/****************************************************************************/ +/** +* +* This functions receives a single byte using the UART. It is blocking in that +* it waits for the receiver to become non-empty before it reads from the +* receive register. +* +* @param BaseAddress is the base address of the device +* +* @return The byte of data received. +* +* @note None. +* +******************************************************************************/ +u8 XUartLite_RecvByte(UINTPTR BaseAddress) +{ + while (XUartLite_IsReceiveEmpty(BaseAddress)); + + return (u8)XUartLite_ReadReg(BaseAddress, XUL_RX_FIFO_OFFSET); +} + +/** @} */
\ No newline at end of file diff --git a/c/src/lib/libbsp/microblaze/microblaze_fpga/start/start.S b/bsps/microblaze/shared/start/start.S index bb3dc3dd65..97250f9316 100644 --- a/c/src/lib/libbsp/microblaze/microblaze_fpga/start/start.S +++ b/bsps/microblaze/shared/start/start.S @@ -1,3 +1,5 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ + /* Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved. Redistribution and use in source and binary forms, with or without @@ -34,76 +36,79 @@ Address Vector type Label ------- ----------- ------ - # 0x00 # (-- IMM --) - # 0x04 # Reset _start1 + # 0x00 # (-- IMM --) + # 0x04 # Reset _start1 - # 0x08 # (-- IMM --) - # 0x0c # Software Exception _exception_handler + # 0x08 # (-- IMM --) + # 0x0c # Software Exception _exception_handler - # 0x10 # (-- IMM --) - # 0x14 # Hardware Interrupt _interrupt_handler + # 0x10 # (-- IMM --) + # 0x14 # Hardware Interrupt _interrupt_handler - # 0x18 # (-- IMM --) - # 0x1C # Breakpoint Exception (-- Don't Care --) + # 0x18 # (-- IMM --) + # 0x1C # Breakpoint Exception (-- Don't Care --) - # 0x20 # (-- IMM --) - # 0x24 # Hardware Exception _hw_exception_handler + # 0x20 # (-- IMM --) + # 0x24 # Hardware Exception _hw_exception_handler */ .globl _start - .section .vectors.reset, "ax" + .section .vectors.reset, "ax" .align 2 - .ent _start - .type _start, @function + .ent _start + .type _start, @function _start: - brai _start1 - .end _start + brai _start1 + .end _start - .section .vectors.sw_exception, "ax" - .align 2 + .section .vectors.sw_exception, "ax" + .align 2 _vector_sw_exception: - brai _exception_handler + brai _exception_handler - .section .vectors.interrupt, "ax" - .align 2 + .section .vectors.interrupt, "ax" + .align 2 _vector_interrupt: - brai _interrupt_handler + brai _interrupt_handler - .section .vectors.hw_exception, "ax" - .align 2 + .section .vectors.hw_exception, "ax" + .align 2 _vector_hw_exception: - brai _hw_exception_handler + brai _hw_exception_handler - .section .text - .globl _start1 - .align 2 - .ent _start1 - .type _start1, @function + .section .text + .globl _start1 + .align 2 + .ent _start1 + .type _start1, @function _start1: - //la r13, r0, _SDA_BASE_ /* Set the Small Data Anchors and the stack pointer */ - //la r2, r0, _SDA2_BASE_ - la r1, r0, bsp_section_stack_begin-16 /* 16 bytes (4 words are needed by crtinit for args and link reg */ + //la r13, r0, _SDA_BASE_ /* Set the Small Data Anchors and the stack pointer */ + //la r2, r0, _SDA2_BASE_ + la r1, r0, _ISR_Stack_area_end-16 /* 16 bytes (4 words are needed by crtinit for args and link reg */ - brlid r15, _crtinit /* Initialize BSS and run program */ + brlid r15, _crtinit /* Initialize BSS and run program */ nop - brlid r15, exit /* Call exit with the return value of main */ - addik r5, r3, 0 - - /* Control does not reach here */ - .end _start1 +#ifndef __rtems__ + brlid r15, exit /* Call exit with the return value of main */ + addik r5, r3, 0 +#endif /* __rtems__ */ + /* Control does not reach here */ + .end _start1 +#ifndef __rtems__ /* - _exit - Our simple _exit + _exit + Our simple _exit */ - .globl _exit - .align 2 - .ent _exit - .type _exit, @function + .globl _exit + .align 2 + .ent _exit + .type _exit, @function _exit: - bri 0 + bri 0 .end _exit +#endif /* __rtems__ */ diff --git a/c/src/lib/libbsp/microblaze/microblaze_fpga/startup/sim-crtinit.S b/c/src/lib/libbsp/microblaze/microblaze_fpga/startup/sim-crtinit.S deleted file mode 100644 index 0cefb63116..0000000000 --- a/c/src/lib/libbsp/microblaze/microblaze_fpga/startup/sim-crtinit.S +++ /dev/null @@ -1,85 +0,0 @@ -## Copyright (c) 2015, Hesham Almatary -## Copyright (c) 2001, 2009 Xilinx, Inc. All rights reserved. -## -## Redistribution and use in source and binary forms, with or without -## modification, are permitted provided that the following conditions are -## met: -## -## 1. Redistributions source code must retain the above copyright notice, -## this list of conditions and the following disclaimer. -## -## 2. Redistributions in binary form must reproduce the above copyright -## notice, this list of conditions and the following disclaimer in the -## documentation and/or other materials provided with the distribution. -## -## 3. Neither the name of Xilinx nor the names of its contributors may be -## used to endorse or promote products derived from this software without -## specific prior written permission. -## -## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS -## IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED -## TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -## PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -## HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -## SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED -## TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -## PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -## LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -## NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -## SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# -# sim-crtinit.s -# -# Default second stage of C run-time initialization that does not peform -# BSS initialization to zero. Typical use is on a simulator. -# - - .globl _crtinit - .align 2 - .ent _crtinit - -_crtinit: - addi r1, r1, -20 /* Save Link register */ - swi r15, r1, 0 - -#ifndef __rtems__ - brlid r15, _program_init /* Initialize the program */ - nop - - brlid r15, __init /* Invoke language initialization functions */ - nop -#endif - - - /* Init .bss */ - addi r6, r0, bsp_section_bss_begin - addi r7, r0, bsp_section_bss_end - -_clear_bss_loop: - swi r0, r6, 0 - - addi r6, r6, 4 - cmpu r8, r6, r7 - bgti r8, _clear_bss_loop - - addi r6, r0, 0 /* Initialize argc = 1 and argv = NULL and envp = NULL */ - addi r7, r0, 0 - brlid r15, boot_card /* Execute the program */ - addi r5, r0, 0 - - addik r19, r3, 0 /* Save return value */ - -#ifndef __rtems__ - brlid r15, __fini /* Invoke language cleanup functions */ - nop - - brlid r15, _program_clean /* Cleanup the program */ - nop -#endif - - lw r15, r1, r0 /* Return back to CRT */ - addik r3, r19, 0 /* Restore return value */ - rtsd r15, 8 - addi r1, r1, 20 - .end _crtinit diff --git a/cpukit/score/cpu/microblaze/__tls_get_addr.c b/cpukit/score/cpu/microblaze/__tls_get_addr.c new file mode 100644 index 0000000000..e779a63488 --- /dev/null +++ b/cpukit/score/cpu/microblaze/__tls_get_addr.c @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSScoreCPUMicroBlaze + * + * @brief MicroBlaze thread-local storage implementation + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifdef HAVE_CONFIG_H +#include "config.h" +#endif + +#include <rtems/score/threadimpl.h> +#include <rtems/score/tls.h> + +#include <assert.h> + +void *__tls_get_addr( const TLS_Index *ti ); + +void *__tls_get_addr( const TLS_Index *ti ) +{ + const Thread_Control *executing = _Thread_Get_executing(); + void *tls_block = (char *) executing->Start.tls_area + + _TLS_Get_thread_control_block_area_size( (uintptr_t) _TLS_Alignment ); + + return (char *) tls_block + ti->offset; +} diff --git a/cpukit/score/cpu/microblaze/cpu.c b/cpukit/score/cpu/microblaze/cpu.c index ca4a3ec2f6..de8fbfbba1 100644 --- a/cpukit/score/cpu/microblaze/cpu.c +++ b/cpukit/score/cpu/microblaze/cpu.c @@ -1,7 +1,16 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSScoreCPUMicroBlaze + * + * @brief MicroBlaze architecture support implementation + */ + /* - * Copyright (c) 2015, Hesham Almatary - * COPYRIGHT (c) 1989-2011. - * On-Line Applications Research Corporation (OAR). + * Copyright (c) 2015, Hesham Almatary + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -9,8 +18,8 @@ * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE @@ -29,31 +38,12 @@ #include "config.h" #endif -#include <rtems/system.h> #include <rtems/score/isr.h> +#include <rtems/score/tls.h> #include <rtems/score/wkspace.h> -/* _CPU_Initialize - * - * This routine performs processor dependent initialization. - * - * INPUT PARAMETERS: NONE - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Initialize(void) +void _CPU_Initialize( void ) { - /* - * If there is not an easy way to initialize the FP context - * during Context_Initialize, then it is usually easier to - * save an "uninitialized" FP context here and copy it to - * the task's during Context_Initialize. - */ - - /* FP context initialization support goes here */ } void _CPU_Context_Initialize( @@ -66,136 +56,66 @@ void _CPU_Context_Initialize( void *tls_area ) { - uint32_t stack = ((uint32_t) stack_area_begin); + uint32_t stack = (uint32_t) stack_area_begin; uint32_t stack_high = stack + stack_area_size; - memset(context, 0, sizeof(*context)); + memset( context, 0, sizeof(*context) ) ; - context->r[0] = stack_high; - context->r[3] = (uint32_t) entry_point; -} - -/*PAGE - * - * _CPU_ISR_Get_level - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ + context->r1 = stack_high - 64; + context->r15 = (uint32_t) entry_point; -uint32_t _CPU_ISR_Get_level( void ) -{ - /* - * This routine returns the current interrupt level. - */ + uint32_t msr; + _CPU_MSR_GET( msr ); + context->rmsr = msr; - return 0; + if ( tls_area != NULL ) { + _TLS_TCB_at_area_begin_initialize( tls_area ); + } } -/*PAGE - * - * _CPU_ISR_install_raw_handler - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -) +void _CPU_Exception_frame_print( const CPU_Exception_frame *ctx ) { - /* - * This is where we install the interrupt handler into the "raw" interrupt - * table used by the CPU to dispatch interrupt handlers. - */ } -/*PAGE - * - * _CPU_ISR_install_vector - * - * This kernel routine installs the RTEMS handler for the - * specified vector. - * - * Input parameters: - * vector - interrupt vector number - * old_handler - former ISR for this vector number - * new_handler - replacement ISR for this vector number - * - * Output parameters: NONE - * - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -) +void _CPU_ISR_Set_level( uint32_t level ) { - *old_handler = _ISR_Vector_table[ vector ]; + uint32_t microblaze_switch_reg; - /* - * If the interrupt vector table is a table of pointer to isr entry - * points, then we need to install the appropriate RTEMS interrupt - * handler for this vector number. - */ + _CPU_MSR_GET( microblaze_switch_reg ); - _CPU_ISR_install_raw_handler( vector, new_handler, old_handler ); + if ( level == 0 ) { + microblaze_switch_reg |= (MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE); + } else { + microblaze_switch_reg &= ~(MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE); + } - /* - * We put the actual user ISR address in '_ISR_vector_table'. This will - * be used by the _ISR_Handler so the user gets control. - */ - - _ISR_Vector_table[ vector ] = new_handler; + _CPU_MSR_SET( microblaze_switch_reg ); } -/*PAGE - * - * _CPU_Install_interrupt_stack - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ - -void _CPU_Install_interrupt_stack( void ) +uint32_t _CPU_ISR_Get_level( void ) { + uint32_t level; + + _CPU_MSR_GET( level ); + + /* This is unique. The MSR register contains an interrupt enable flag where + * most other architectures have an interrupt disable flag. */ + return ( level & (MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE) ) == 0; } -/*PAGE - * - * _CPU_Thread_Idle_body - * - * NOTES: - * - * 1. This is the same as the regular CPU independent algorithm. - * - * 2. If you implement this using a "halt", "idle", or "shutdown" - * instruction, then don't forget to put it in an infinite loop. - * - * 3. Be warned. Some processors with onboard DMA have been known - * to stop the DMA if the CPU were put in IDLE mode. This might - * also be a problem with other on-chip peripherals. So use this - * hook with caution. - * - * NO_CPU Specific Information: - * - * XXX document implementation including references if appropriate - */ +void _CPU_ISR_install_vector( + uint32_t vector, + CPU_ISR_handler new_handler, + CPU_ISR_handler *old_handler +) +{ + *old_handler = _ISR_Vector_table[ vector ]; + _ISR_Vector_table[ vector ] = new_handler; +} void *_CPU_Thread_Idle_body( uintptr_t ignored ) { - - for( ; ; ) - /* insert your "halt" instruction here */ ; - return NULL; + while ( true ) { + __asm__ volatile ( "sleep" ); + } } diff --git a/cpukit/score/cpu/microblaze/cpu_asm.S b/cpukit/score/cpu/microblaze/cpu_asm.S new file mode 100644 index 0000000000..d095e62f69 --- /dev/null +++ b/cpukit/score/cpu/microblaze/cpu_asm.S @@ -0,0 +1,194 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSScoreCPUMicroBlaze + * + * @brief MicroBlaze interrupt handler implementation + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include <rtems/asm.h> +#include <rtems/score/percpu.h> + + .text + .globl _ISR_Handler + .align 2 + +_ISR_Handler: + /* Save stack frame */ + swi r3, r1, MICROBLAZE_INTERRUPT_FRAME_R3 + swi r4, r1, MICROBLAZE_INTERRUPT_FRAME_R4 + swi r6, r1, MICROBLAZE_INTERRUPT_FRAME_R6 + swi r7, r1, MICROBLAZE_INTERRUPT_FRAME_R7 + swi r8, r1, MICROBLAZE_INTERRUPT_FRAME_R8 + swi r9, r1, MICROBLAZE_INTERRUPT_FRAME_R9 + swi r10, r1, MICROBLAZE_INTERRUPT_FRAME_R10 + swi r11, r1, MICROBLAZE_INTERRUPT_FRAME_R11 + swi r12, r1, MICROBLAZE_INTERRUPT_FRAME_R12 + swi r15, r1, MICROBLAZE_INTERRUPT_FRAME_R15 + swi r18, r1, MICROBLAZE_INTERRUPT_FRAME_R18 + + xori r3, r5, 0xFFFF + beqi r3, do_exception + + /* Disable dispatching */ + lwi r3, r0, _Per_CPU_Information + 16 + addik r3, r3, 1 + swi r3, r0, _Per_CPU_Information + 16 + + swi r14, r1, MICROBLAZE_INTERRUPT_FRAME_R14 + + /* Is SP < INTERRUPT_STACK_LOW? */ + lwi r4, r0, _Per_CPU_Information + rsubk r3, r4, r1 + blei r3, switch_to_interrupt_stack + + /* Is SP > INTERRUPT_STACK_HIGH? */ + lwi r4, r0, _Per_CPU_Information + 4 + rsubk r3, r4, r1 + bgei r3, switch_to_interrupt_stack + + bri on_interrupt_stack + +switch_to_interrupt_stack: + add r4, r0, r1 + lwi r1, r0, _Per_CPU_Information + 4 + addik r1, r1, -52 + swi r4, r1, 0 + +on_interrupt_stack: + /* Add 1 to ISR_NEST_LEVEL */ + lwi r3, r0, _Per_CPU_Information + 8 + addik r3, r3, 1 + swi r3, r0, _Per_CPU_Information + 8 + + bralid r15, bsp_interrupt_dispatch + nop + + /* Subtract 1 from ISR_NEST_LEVEL */ + lwi r3, r0, _Per_CPU_Information + 8 + addik r3, r3, -1 + swi r3, r0, _Per_CPU_Information + 8 + + /* Is ISR_NEST_LEVEL > 0? */ + bgti r3, after_stack_switch + + /* Switch back to interrupted thread stack */ + lwi r1, r1, 0 + +after_stack_switch: + /* Subtract 1 from THREAD_DISPATCH_DISABLE_LEVEL */ + lwi r3, r0, _Per_CPU_Information + 16 + addik r3, r3, -1 + swi r3, r0, _Per_CPU_Information + 16 + + /* Is THREAD_DISPATCH_DISABLE_LEVEL != 0? */ + bnei r3, quick_exit + + /* Is DISPATCH_NEEDED == 0? */ + lwi r3, r0, _Per_CPU_Information + 20 + beqi r3, quick_exit + + /* Return to interrupted thread and make it do a dispatch */ + addik r14, r0, thread_dispatch + rtid r14, 0 + nop + +quick_exit: + /* Simple return from nested interrupt */ + /* Restore registers */ + lwi r3, r1, MICROBLAZE_INTERRUPT_FRAME_R3 + lwi r4, r1, MICROBLAZE_INTERRUPT_FRAME_R4 + lwi r5, r1, MICROBLAZE_INTERRUPT_FRAME_R5 + lwi r6, r1, MICROBLAZE_INTERRUPT_FRAME_R6 + lwi r7, r1, MICROBLAZE_INTERRUPT_FRAME_R7 + lwi r8, r1, MICROBLAZE_INTERRUPT_FRAME_R8 + lwi r9, r1, MICROBLAZE_INTERRUPT_FRAME_R9 + lwi r10, r1, MICROBLAZE_INTERRUPT_FRAME_R10 + lwi r11, r1, MICROBLAZE_INTERRUPT_FRAME_R11 + lwi r12, r1, MICROBLAZE_INTERRUPT_FRAME_R12 + lwi r14, r1, MICROBLAZE_INTERRUPT_FRAME_R14 + lwi r15, r1, MICROBLAZE_INTERRUPT_FRAME_R15 + lwi r18, r1, MICROBLAZE_INTERRUPT_FRAME_R18 + + /* Remove stack frame */ + addik r1, r1, 52 + + rtid r14, 0 + nop + +thread_dispatch: + /* Reserve stack */ + addik r1, r1, -52 + /* Save scratch registers */ + swi r3, r1, MICROBLAZE_INTERRUPT_FRAME_R3 + swi r4, r1, MICROBLAZE_INTERRUPT_FRAME_R4 + swi r5, r1, MICROBLAZE_INTERRUPT_FRAME_R5 + swi r6, r1, MICROBLAZE_INTERRUPT_FRAME_R6 + swi r7, r1, MICROBLAZE_INTERRUPT_FRAME_R7 + swi r8, r1, MICROBLAZE_INTERRUPT_FRAME_R8 + swi r9, r1, MICROBLAZE_INTERRUPT_FRAME_R9 + swi r10, r1, MICROBLAZE_INTERRUPT_FRAME_R10 + swi r11, r1, MICROBLAZE_INTERRUPT_FRAME_R11 + swi r12, r1, MICROBLAZE_INTERRUPT_FRAME_R12 + swi r14, r1, MICROBLAZE_INTERRUPT_FRAME_R14 + swi r15, r1, MICROBLAZE_INTERRUPT_FRAME_R15 + swi r18, r1, MICROBLAZE_INTERRUPT_FRAME_R18 + + bralid r15, _Thread_Dispatch + nop + + /* Restore scratch registers */ + lwi r3, r1, MICROBLAZE_INTERRUPT_FRAME_R3 + lwi r4, r1, MICROBLAZE_INTERRUPT_FRAME_R4 + lwi r5, r1, MICROBLAZE_INTERRUPT_FRAME_R5 + lwi r6, r1, MICROBLAZE_INTERRUPT_FRAME_R6 + lwi r7, r1, MICROBLAZE_INTERRUPT_FRAME_R7 + lwi r8, r1, MICROBLAZE_INTERRUPT_FRAME_R8 + lwi r9, r1, MICROBLAZE_INTERRUPT_FRAME_R9 + lwi r10, r1, MICROBLAZE_INTERRUPT_FRAME_R10 + lwi r11, r1, MICROBLAZE_INTERRUPT_FRAME_R11 + lwi r12, r1, MICROBLAZE_INTERRUPT_FRAME_R12 + lwi r14, r1, MICROBLAZE_INTERRUPT_FRAME_R14 + lwi r15, r1, MICROBLAZE_INTERRUPT_FRAME_R15 + lwi r18, r1, MICROBLAZE_INTERRUPT_FRAME_R18 + /* Free stack space */ + addik r1, r1, 52 + + bri quick_exit + +do_exception: + /* exception no longer in progress */ + mfs r3, rmsr + andni r3, r3, 0x200 + mts rmsr, r3 + addi r5, r0, 9 + add r6, r0, r1 + + brai _Terminate diff --git a/cpukit/score/cpu/microblaze/rtems/asm.h b/cpukit/score/cpu/microblaze/include/rtems/asm.h index b5a8702f02..2e35a66294 100644 --- a/cpukit/score/cpu/microblaze/rtems/asm.h +++ b/cpukit/score/cpu/microblaze/include/rtems/asm.h @@ -1,29 +1,41 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + /** - * @file rtems/asm.h + * @file + * + * @brief MicroBlaze assembler support * - * This include file attempts to address the problems - * caused by incompatible flavors of assemblers and - * toolsets. It primarily addresses variations in the - * use of leading underscores on symbols and the requirement - * that register names be preceded by a %. + * This include file attempts to address the problems + * caused by incompatible flavors of assemblers and + * toolsets. It primarily addresses variations in the + * use of leading underscores on symbols and the requirement + * that register names be preceded by a %. */ /* - * NOTE: The spacing in the use of these macros - * is critical to them working as advertised. - * - * COPYRIGHT: + * Copyright (c) 2015, Hesham Almatary + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) * - * This file is based on similar code found in newlib available - * from ftp.cygnus.com. The file which was used had no copyright - * notice. This file is freely distributable as long as the source - * of the file is noted. This file is: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * Copyright (c) 2015, Hesham Almatary - * COPYRIGHT (c) 1994-2006. - * On-Line Applications Research Corporation (OAR). - * - * $Id: asm.h,v 1.16 2006/01/16 15:12:12 joel Exp $ + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. */ #ifndef _RTEMS_ASM_H @@ -36,6 +48,7 @@ #ifndef ASM #define ASM #endif + #include <rtems/score/cpuopts.h> #ifndef __USER_LABEL_PREFIX__ diff --git a/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h b/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h new file mode 100644 index 0000000000..4b11625463 --- /dev/null +++ b/cpukit/score/cpu/microblaze/include/rtems/score/cpu.h @@ -0,0 +1,305 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSScoreCPU + * + * @brief MicroBlaze architecture support + */ + +/* + * Copyright (c) 2015, Hesham Almatary + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _RTEMS_SCORE_CPU_H +#define _RTEMS_SCORE_CPU_H + +#include <rtems/score/basedefs.h> +#include <rtems/score/microblaze.h> + +#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE + +#define CPU_ISR_PASSES_FRAME_POINTER FALSE + +#define CPU_HARDWARE_FP FALSE + +#define CPU_SOFTWARE_FP FALSE + +#define CPU_ALL_TASKS_ARE_FP FALSE + +#define CPU_IDLE_TASK_IS_FP FALSE + +#define CPU_USE_DEFERRED_FP_SWITCH FALSE + +#define CPU_STACK_GROWS_UP FALSE + +/** + * The maximum cache-line size is 16 words. + */ +#define CPU_CACHE_LINE_BYTES 64 + +#define CPU_STRUCTURE_ALIGNMENT + +#define CPU_MODES_INTERRUPT_MASK 0x00000001 + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @ingroup CPUContext Management + * This defines the minimal set of integer and processor state registers + * that must be saved during a voluntary context switch from one thread + * to another. + */ +typedef struct { + uint32_t r1; + uint32_t r13; + uint32_t r14; + uint32_t r15; + uint32_t r16; + uint32_t r17; + uint32_t r18; + uint32_t r19; + uint32_t r20; + uint32_t r21; + uint32_t r22; + uint32_t r23; + uint32_t r24; + uint32_t r25; + uint32_t r26; + uint32_t r27; + uint32_t r28; + uint32_t r29; + uint32_t r30; + uint32_t r31; + uint32_t rmsr; +} Context_Control; + +/** + * @ingroup CPUContext Management + * + * This macro returns the stack pointer associated with @a _context. + * + * @param[in] _context is the thread context area to access + * + * @return This method returns the stack pointer. + */ +#define _CPU_Context_Get_SP( _context ) \ + (_context)->r1 + +#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 + +#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32 + +#define CPU_USE_LIBC_INIT_FINI_ARRAY TRUE + +#define CPU_MAXIMUM_PROCESSORS 32 + +/** + * @ingroup CPUInterrupt + * This defines the highest interrupt vector number for this port. + */ +#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) + +#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE + +#define CPU_STACK_MINIMUM_SIZE (1024*4) + +#define CPU_ALIGNMENT 4 + +#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT + +#define CPU_STACK_ALIGNMENT CPU_ALIGNMENT + +#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES + +#define MICROBLAZE_MSR_IE (1 << 1) +#define MICROBLAZE_MSR_EE (1 << 8) + +#define _CPU_MSR_GET( _msr_value ) \ + do { \ + (_msr_value) = 0; \ + __asm__ volatile ("mfs %0, rmsr" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \ + } while (0) + +#define _CPU_MSR_SET( _msr_value ) \ +{ __asm__ volatile ("mts rmsr, %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); } + +#define _CPU_ISR_Disable( _isr_cookie ) \ + { \ + unsigned int _new_msr; \ + _CPU_MSR_GET(_isr_cookie); \ + _new_msr = (_isr_cookie) & ~(MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE); \ + _CPU_MSR_SET(_new_msr); \ + } + +#define _CPU_ISR_Enable( _isr_cookie ) \ + { \ + uint32_t _microblaze_interrupt_enable; \ + uint32_t _microblaze_switch_reg; \ + \ + _microblaze_interrupt_enable = (_isr_cookie) & (MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE); \ + _CPU_MSR_GET(_microblaze_switch_reg); \ + _microblaze_switch_reg &= ~(MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE); \ + _microblaze_switch_reg |= _microblaze_interrupt_enable; \ + _CPU_MSR_SET(_microblaze_switch_reg); \ + } + +#define _CPU_ISR_Flash( _isr_cookie ) \ + { \ + unsigned int _new_msr; \ + _CPU_MSR_SET(_isr_cookie); \ + _new_msr = (_isr_cookie) & ~(MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE); \ + _CPU_MSR_SET(_new_msr); \ + } + +void _CPU_ISR_Set_level( uint32_t level ); + +uint32_t _CPU_ISR_Get_level( void ); + +RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) +{ + return ( level & (MICROBLAZE_MSR_IE | MICROBLAZE_MSR_EE) ) != 0; +} + +void _CPU_Context_Initialize( + Context_Control *context, + void *stack_area_begin, + size_t stack_area_size, + uint32_t new_level, + void (*entry_point)( void ), + bool is_fp, + void *tls_area +); + +#define _CPU_Context_Restart_self( _the_context ) \ + _CPU_Context_restore( (_the_context) ); + +#define _CPU_Context_Initialize_fp( _destination ) \ + { \ + *(*(_destination)) = _CPU_Null_fp_context; \ + } + +/* end of Context handler macros */ + +/* Fatal Error manager macros */ + +/* TODO */ +#define _CPU_Fatal_halt(_source, _error ) \ + do { \ + __asm__ volatile ( "sleep" ); \ + for(;;) {} \ + } while (0) + +/* end of Fatal Error manager macros */ + +/* Bitfield handler macros */ + +#define CPU_USE_GENERIC_BITFIELD_CODE TRUE + +#define CPU_SIZEOF_POINTER 4 + +#define CPU_PER_CPU_CONTROL_SIZE 0 + +typedef struct { + /* TODO: enumerate registers */ + uint32_t r[32]; +} CPU_Exception_frame; + +/* end of Priority handler macros */ + +/* functions */ + +void _CPU_Initialize( void ); + +typedef void ( *CPU_ISR_handler )( uint32_t ); + +void _CPU_ISR_install_vector( + uint32_t vector, + CPU_ISR_handler new_handler, + CPU_ISR_handler *old_handler +); + +void _CPU_Context_switch( + Context_Control *run, + Context_Control *heir +); + +RTEMS_NO_RETURN void _CPU_Context_restore( + Context_Control *new_context +); + +static inline uint32_t CPU_swap_u32( + uint32_t value +) +{ + uint32_t byte1, byte2, byte3, byte4, swapped; + + byte4 = (value >> 24) & 0xff; + byte3 = (value >> 16) & 0xff; + byte2 = (value >> 8) & 0xff; + byte1 = value & 0xff; + + swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; + return swapped; +} + +#define CPU_swap_u16( value ) \ + (((value&0xff) << 8) | ((value >> 8)&0xff)) + +void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); + +typedef uint32_t CPU_Counter_ticks; + +uint32_t _CPU_Counter_frequency( void ); + +CPU_Counter_ticks _CPU_Counter_read( void ); + +static inline CPU_Counter_ticks _CPU_Counter_difference( + CPU_Counter_ticks second, + CPU_Counter_ticks first +) +{ + return second - first; +} + +void *_CPU_Thread_Idle_body( uintptr_t ignored ); + +void bsp_interrupt_dispatch( uint32_t source ); + +/** Type that can store a 32-bit integer or a pointer. */ +typedef uintptr_t CPU_Uint32ptr; + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +#endif /* _RTEMS_SCORE_CPU_H */ diff --git a/cpukit/score/cpu/microblaze/include/rtems/score/cpuatomic.h b/cpukit/score/cpu/microblaze/include/rtems/score/cpuatomic.h new file mode 100644 index 0000000000..6dc769b95a --- /dev/null +++ b/cpukit/score/cpu/microblaze/include/rtems/score/cpuatomic.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSScoreCPU + * + * @brief MicroBlaze atomic support + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _RTEMS_SCORE_ATOMIC_CPU_H +#define _RTEMS_SCORE_ATOMIC_CPU_H + +#include <rtems/score/cpustdatomic.h> + +#endif /* _RTEMS_SCORE_ATOMIC_CPU_H */ diff --git a/cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h new file mode 100644 index 0000000000..3d0167dd40 --- /dev/null +++ b/cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSScoreCPU + * + * @brief CPU Port Implementation API + */ + +/* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _RTEMS_SCORE_CPUIMPL_H +#define _RTEMS_SCORE_CPUIMPL_H + +#include <rtems/score/cpu.h> + +/** + * @defgroup RTEMSScoreCPUMicroBlaze MicroBlaze + * + * @ingroup RTEMSScoreCPU + * + * @brief MicroBlaze Architecture Support + * + * @{ + */ + +#define CPU_PER_CPU_CONTROL_SIZE 0 +#define CPU_INTERRUPT_FRAME_SIZE 52 + +#define MICROBLAZE_INTERRUPT_FRAME_R3 0 +#define MICROBLAZE_INTERRUPT_FRAME_R4 4 +#define MICROBLAZE_INTERRUPT_FRAME_R5 8 +#define MICROBLAZE_INTERRUPT_FRAME_R6 12 +#define MICROBLAZE_INTERRUPT_FRAME_R7 16 +#define MICROBLAZE_INTERRUPT_FRAME_R8 20 +#define MICROBLAZE_INTERRUPT_FRAME_R9 24 +#define MICROBLAZE_INTERRUPT_FRAME_R10 28 +#define MICROBLAZE_INTERRUPT_FRAME_R11 32 +#define MICROBLAZE_INTERRUPT_FRAME_R12 36 +#define MICROBLAZE_INTERRUPT_FRAME_R14 40 +#define MICROBLAZE_INTERRUPT_FRAME_R15 44 +#define MICROBLAZE_INTERRUPT_FRAME_R18 48 + +#ifndef ASM + +#ifdef __cplusplus +extern "C" { +#endif + +void _CPU_Context_volatile_clobber( uintptr_t pattern ); + +void _CPU_Context_validate( uintptr_t pattern ); + +RTEMS_INLINE_ROUTINE void _CPU_Instruction_illegal( void ) +{ + __asm__ volatile ( ".word 0x0" ); +} + +RTEMS_INLINE_ROUTINE void _CPU_Instruction_no_operation( void ) +{ + __asm__ volatile ( "nop" ); +} + +#ifdef __cplusplus +} +#endif + +#endif /* ASM */ + +/** @} */ + +#endif /* _RTEMS_SCORE_CPUIMPL_H */ diff --git a/cpukit/score/cpu/microblaze/rtems/score/microblaze.h b/cpukit/score/cpu/microblaze/include/rtems/score/microblaze.h index 19e26314e8..6310b4b17d 100644 --- a/cpukit/score/cpu/microblaze/rtems/score/microblaze.h +++ b/cpukit/score/cpu/microblaze/include/rtems/score/microblaze.h @@ -1,7 +1,16 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSScoreCPU + * + * @brief MicroBlaze architecture support + */ + /* - * Copyright (c) 2015, Hesham Almatary - * COPYRIGHT (c) 1989-2008. - * On-Line Applications Research Corporation (OAR). + * Copyright (c) 2015, Hesham Almatary + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -9,8 +18,8 @@ * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE @@ -25,58 +34,15 @@ * POSSIBILITY OF SUCH DAMAGE. */ -/* - * This file sets up basic CPU dependency settings based on - * compiler settings. For example, it can determine if - * floating point is available. This particular implementation - * is specified to the NO CPU port. - * - * $Id: no_cpu.h,v 1.9 2009/12/02 09:48:25 ralf Exp $ - * - */ - - -#ifndef _RTEMS_SCORE_NO_CPU_H -#define _RTEMS_SCORE_NO_CPU_H +#ifndef _RTEMS_SCORE_MICROBLAZE_H +#define _RTEMS_SCORE_MICROBLAZE_H #ifdef __cplusplus extern "C" { #endif -/* - * This file contains the information required to build - * RTEMS for a particular member of the NO CPU family. - * It does this by setting variables to indicate which - * implementation dependent features are present in a particular - * member of the family. - * - * This is a good place to list all the known CPU models - * that this port supports and which RTEMS CPU model they correspond - * to. - */ - -#if defined(rtems_multilib) -/* - * Figure out all CPU Model Feature Flags based upon compiler - * predefines. - */ - -#define CPU_MODEL_NAME "rtems_multilib" -#define NOCPU_HAS_FPU 1 - -#else -/* if defined(__MICROBLAZE__) */ - #define CPU_MODEL_NAME "MicroBlaze" -#define NOCPU_HAS_FPU 1 - -/* -#else - -#error "Unsupported CPU Model" -*/ - -#endif +#define NOCPU_HAS_FPU 1 /* * Define the name of the CPU family. @@ -88,4 +54,4 @@ extern "C" { } #endif -#endif /* _RTEMS_SCORE_NO_CPU_H */ +#endif /* _RTEMS_SCORE_MICROBLAZE_H */ diff --git a/cpukit/score/cpu/microblaze/microblaze-context-switch.S b/cpukit/score/cpu/microblaze/microblaze-context-switch.S index e2ec760080..523e836398 100644 --- a/cpukit/score/cpu/microblaze/microblaze-context-switch.S +++ b/cpukit/score/cpu/microblaze/microblaze-context-switch.S @@ -1,5 +1,16 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ + +/** + * @file + * + * @ingroup RTEMSScoreCPUMicroBlaze + * + * @brief MicroBlaze context switch implementation + */ + /* - * Copyright (c) 2015, Hesham Almatary + * Copyright (c) 2015, Hesham Almatary + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -7,8 +18,8 @@ * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE @@ -59,6 +70,10 @@ SYM(_CPU_Context_switch): swi r30, r5, 72 swi r31, r5, 76 + mfs r21, rmsr + swi r21, r5, 80 + + SYM(restore): lwi r1, r6, 0 lwi r13, r6, 4 @@ -79,6 +94,10 @@ SYM(restore): lwi r28, r6, 64 lwi r29, r6, 68 lwi r30, r6, 72 + + lwi r31, r6, 80 + mts rmsr, r31 + lwi r31, r6, 76 rtsd r15, 8 diff --git a/cpukit/score/cpu/microblaze/microblaze-context-validate.S b/cpukit/score/cpu/microblaze/microblaze-context-validate.S new file mode 100644 index 0000000000..b12d5930f6 --- /dev/null +++ b/cpukit/score/cpu/microblaze/microblaze-context-validate.S @@ -0,0 +1,117 @@ +#ifdef HAVE_CONFIG_H + #include "config.h" +#endif + +#include <rtems/asm.h> + +#define FRAME_OFFSET_R19 0 +#define FRAME_OFFSET_R20 4 +#define FRAME_OFFSET_R21 8 +#define FRAME_OFFSET_R22 12 +#define FRAME_OFFSET_R23 16 +#define FRAME_OFFSET_R24 20 +#define FRAME_OFFSET_R25 24 +#define FRAME_OFFSET_R26 28 +#define FRAME_OFFSET_R27 32 +#define FRAME_OFFSET_R28 36 +#define FRAME_OFFSET_R29 40 +#define FRAME_OFFSET_R30 44 +#define FRAME_OFFSET_R31 48 + +#define FRAME_SIZE (FRAME_OFFSET_R31 + 4) + +.text +.align 4 + +PUBLIC(_CPU_Context_validate) + +SYM(_CPU_Context_validate): + + /* Save */ + addik r1, r1, -FRAME_SIZE + swi r19, r1, FRAME_OFFSET_R19 + swi r20, r1, FRAME_OFFSET_R20 + swi r21, r1, FRAME_OFFSET_R21 + swi r22, r1, FRAME_OFFSET_R22 + swi r23, r1, FRAME_OFFSET_R23 + swi r24, r1, FRAME_OFFSET_R24 + swi r25, r1, FRAME_OFFSET_R25 + swi r26, r1, FRAME_OFFSET_R26 + swi r27, r1, FRAME_OFFSET_R27 + swi r28, r1, FRAME_OFFSET_R28 + swi r29, r1, FRAME_OFFSET_R29 + swi r30, r1, FRAME_OFFSET_R30 + swi r31, r1, FRAME_OFFSET_R31 + + /* Fill */ + + add r4, r0, r3 + + /* r7 contains the stack pointer */ + add r7, r0, r1 + +.macro fill_register reg + addi r4, r4, 1 + add \reg, r0, r4 +.endm + + fill_register r21 + fill_register r22 + fill_register r23 + fill_register r24 + fill_register r25 + fill_register r26 + fill_register r27 + fill_register r28 + fill_register r29 + fill_register r30 + fill_register r31 + + /* Check */ +check: + +.macro check_register reg + addi r4, r4, 1 + cmp r6, \reg, r4 + bnei r6, restore +.endm + + cmp r6, r7, r1 + bnei r6, restore + + add r4, r0, r3 + + check_register r21 + check_register r22 + check_register r23 + check_register r24 + check_register r25 + check_register r26 + check_register r27 + check_register r28 + check_register r29 + check_register r30 + check_register r31 + + brai check + + /* Restore */ +restore: + + lwi r19, r1, FRAME_OFFSET_R19 + lwi r20, r1, FRAME_OFFSET_R20 + lwi r21, r1, FRAME_OFFSET_R21 + lwi r22, r1, FRAME_OFFSET_R22 + lwi r23, r1, FRAME_OFFSET_R23 + lwi r24, r1, FRAME_OFFSET_R24 + lwi r25, r1, FRAME_OFFSET_R25 + lwi r26, r1, FRAME_OFFSET_R26 + lwi r27, r1, FRAME_OFFSET_R27 + lwi r28, r1, FRAME_OFFSET_R28 + lwi r29, r1, FRAME_OFFSET_R29 + lwi r30, r1, FRAME_OFFSET_R30 + lwi r31, r1, FRAME_OFFSET_R31 + + addik r1, r1, FRAME_SIZE + + bra r15 diff --git a/cpukit/score/cpu/microblaze/microblaze-context-volatile-clobber.S b/cpukit/score/cpu/microblaze/microblaze-context-volatile-clobber.S new file mode 100644 index 0000000000..fb49dc5e40 --- /dev/null +++ b/cpukit/score/cpu/microblaze/microblaze-context-volatile-clobber.S @@ -0,0 +1,28 @@ +#ifdef HAVE_CONFIG_H + #include "config.h" +#endif + +#include <rtems/asm.h> + +.text +.align 4 + +PUBLIC(_CPU_Context_volatile_clobber) + +SYM(_CPU_Context_volatile_clobber): + +.macro clobber_register reg + addi r5, r5, -1 + add \reg, r0, r5 +.endm + + clobber_register r3 + clobber_register r4 + clobber_register r6 + clobber_register r7 + clobber_register r8 + clobber_register r9 + clobber_register r10 + + rtsd r15, 8 + nop diff --git a/cpukit/score/cpu/microblaze/rtems/score/cpu.h b/cpukit/score/cpu/microblaze/rtems/score/cpu.h deleted file mode 100644 index d9f9e8add5..0000000000 --- a/cpukit/score/cpu/microblaze/rtems/score/cpu.h +++ /dev/null @@ -1,1280 +0,0 @@ -/* - * Copyright (c) 2015, Hesham Almatary - * COPYRIGHT (c) 1989-2008. - * On-Line Applications Research Corporation (OAR). - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -/** - * @file rtems/score/cpu.h - */ - -/* - * This include file contains information pertaining to the XXX - * processor. - * - * @note This file is part of a porting template that is intended - * to be used as the starting point when porting RTEMS to a new - * CPU family. The following needs to be done when using this as - * the starting point for a new port: - * - * + Anywhere there is an XXX, it should be replaced - * with information about the CPU family being ported to. - * - * + At the end of each comment section, there is a heading which - * says "Port Specific Information:". When porting to RTEMS, - * add CPU family specific information in this section - */ - -#ifndef _RTEMS_SCORE_CPU_H -#define _RTEMS_SCORE_CPU_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/score/types.h> -#include <rtems/score/microblaze.h> - -/* conditional compilation parameters */ - -/** - * Should the calls to @ref _Thread_Enable_dispatch be inlined? - * - * If TRUE, then they are inlined. - * If FALSE, then a subroutine call is made. - * - * This conditional is an example of the classic trade-off of size - * versus speed. Inlining the call (TRUE) typically increases the - * size of RTEMS while speeding up the enabling of dispatching. - * - * @note In general, the @ref _Thread_Dispatch_disable_level will - * only be 0 or 1 unless you are in an interrupt handler and that - * interrupt handler invokes the executive.] When not inlined - * something calls @ref _Thread_Enable_dispatch which in turns calls - * @ref _Thread_Dispatch. If the enable dispatch is inlined, then - * one subroutine call is avoided entirely. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_INLINE_ENABLE_DISPATCH FALSE - -/** - * Should the body of the search loops in _Thread_queue_Enqueue_priority - * be unrolled one time? In unrolled each iteration of the loop examines - * two "nodes" on the chain being searched. Otherwise, only one node - * is examined per iteration. - * - * If TRUE, then the loops are unrolled. - * If FALSE, then the loops are not unrolled. - * - * The primary factor in making this decision is the cost of disabling - * and enabling interrupts (_ISR_Flash) versus the cost of rest of the - * body of the loop. On some CPUs, the flash is more expensive than - * one iteration of the loop body. In this case, it might be desirable - * to unroll the loop. It is important to note that on some CPUs, this - * code is the longest interrupt disable period in RTEMS. So it is - * necessary to strike a balance when setting this parameter. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE - -/** - * Does RTEMS manage a dedicated interrupt stack in software? - * - * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization. - * If FALSE, nothing is done. - * - * If the CPU supports a dedicated interrupt stack in hardware, - * then it is generally the responsibility of the BSP to allocate it - * and set it up. - * - * If the CPU does not support a dedicated interrupt stack, then - * the porter has two options: (1) execute interrupts on the - * stack of the interrupted task, and (2) have RTEMS manage a dedicated - * interrupt stack. - * - * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE - -/** - * Does the CPU follow the simple vectored interrupt model? - * - * If TRUE, then RTEMS allocates the vector table it internally manages. - * If FALSE, then the BSP is assumed to allocate and manage the vector - * table - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE - -/** - * Does this CPU have hardware support for a dedicated interrupt stack? - * - * If TRUE, then it must be installed during initialization. - * If FALSE, then no installation is performed. - * - * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. - * - * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and - * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is - * possible that both are FALSE for a particular CPU. Although it - * is unclear what that would imply about the interrupt processing - * procedure on that CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE - -/** - * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? - * - * If TRUE, then the memory is allocated during initialization. - * If FALSE, then the memory is allocated during initialization. - * - * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALLOCATE_INTERRUPT_STACK TRUE - -/** - * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector - * number (0)? - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ISR_PASSES_FRAME_POINTER 0 - -/** - * @def CPU_HARDWARE_FP - * - * Does the CPU have hardware floating point? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. - * - * If there is a FP coprocessor such as the i387 or mc68881, then - * the answer is TRUE. - * - * The macro name "NO_CPU_HAS_FPU" should be made CPU specific. - * It indicates whether or not this CPU model has FP support. For - * example, it would be possible to have an i386_nofp CPU model - * which set this to false to indicate that you have an i386 without - * an i387 and wish to leave floating point support out of RTEMS. - */ - -/** - * @def CPU_SOFTWARE_FP - * - * Does the CPU have no hardware floating point and GCC provides a - * software floating point implementation which must be context - * switched? - * - * This feature conditional is used to indicate whether or not there - * is software implemented floating point that must be context - * switched. The determination of whether or not this applies - * is very tool specific and the state saved/restored is also - * compiler specific. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#if ( NO_CPU_HAS_FPU == 1 ) -#define CPU_HARDWARE_FP TRUE -#else -#define CPU_HARDWARE_FP FALSE -#endif -#define CPU_SOFTWARE_FP FALSE - -/** - * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? - * - * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. - * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. - * - * So far, the only CPUs in which this option has been used are the - * HP PA-RISC and PowerPC. On the PA-RISC, The HP C compiler and - * gcc both implicitly used the floating point registers to perform - * integer multiplies. Similarly, the PowerPC port of gcc has been - * seen to allocate floating point local variables and touch the FPU - * even when the flow through a subroutine (like vfprintf()) might - * not use floating point formats. - * - * If a function which you would not think utilize the FP unit DOES, - * then one can not easily predict which tasks will use the FP hardware. - * In this case, this option should be TRUE. - * - * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALL_TASKS_ARE_FP TRUE - -/** - * Should the IDLE task have a floating point context? - * - * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task - * and it has a floating point context which is switched in and out. - * If FALSE, then the IDLE task does not have a floating point context. - * - * Setting this to TRUE negatively impacts the time required to preempt - * the IDLE task from an interrupt because the floating point context - * must be saved as part of the preemption. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_IDLE_TASK_IS_FP FALSE - -/** - * Should the saving of the floating point registers be deferred - * until a context switch is made to another different floating point - * task? - * - * If TRUE, then the floating point context will not be stored until - * necessary. It will remain in the floating point registers and not - * disturned until another floating point task is switched to. - * - * If FALSE, then the floating point context is saved when a floating - * point task is switched out and restored when the next floating point - * task is restored. The state of the floating point registers between - * those two operations is not specified. - * - * If the floating point context does NOT have to be saved as part of - * interrupt dispatching, then it should be safe to set this to TRUE. - * - * Setting this flag to TRUE results in using a different algorithm - * for deciding when to save and restore the floating point context. - * The deferred FP switch algorithm minimizes the number of times - * the FP context is saved and restored. The FP context is not saved - * until a context switch is made to another, different FP task. - * Thus in a system with only one FP task, the FP context will never - * be saved or restored. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_USE_DEFERRED_FP_SWITCH TRUE - -/** - * Does this port provide a CPU dependent IDLE task implementation? - * - * If TRUE, then the routine @ref _CPU_Thread_Idle_body - * must be provided and is the default IDLE thread body instead of - * @ref _CPU_Thread_Idle_body. - * - * If FALSE, then use the generic IDLE thread body if the BSP does - * not provide one. - * - * This is intended to allow for supporting processors which have - * a low power or idle mode. When the IDLE thread is executed, then - * the CPU can be powered down. - * - * The order of precedence for selecting the IDLE thread body is: - * - * -# BSP provided - * -# CPU dependent (if provided) - * -# generic (if no BSP and no CPU dependent) - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE - -/** - * Does the stack grow up (toward higher addresses) or down - * (toward lower addresses)? - * - * If TRUE, then the grows upward. - * If FALSE, then the grows toward smaller addresses. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_GROWS_UP TRUE - -/** - * The following is the variable attribute used to force alignment - * of critical RTEMS structures. On some processors it may make - * sense to have these aligned on tighter boundaries than - * the minimum requirements of the compiler in order to have as - * much of the critical data area as possible in a cache line. - * - * The placement of this macro in the declaration of the variables - * is based on the syntactically requirements of the GNU C - * "__attribute__" extension. For example with GNU C, use - * the following to force a structures to a 32 byte boundary. - * - * __attribute__ ((aligned (32))) - * - * @note Currently only the Priority Bit Map table uses this feature. - * To benefit from using this, the data must be heavily - * used so it will stay in the cache and used frequently enough - * in the executive to justify turning this on. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STRUCTURE_ALIGNMENT - -/** - * @defgroup CPUEndian Processor Dependent Endianness Support - * - * This group assists in issues related to processor endianness. - */ - -/** - * @ingroup CPUEndian - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the - * same values. - * - * @see CPU_LITTLE_ENDIAN - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_BIG_ENDIAN TRUE - -/** - * @ingroup CPUEndian - * Define what is required to specify how the network to host conversion - * routines are handled. - * - * @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the - * same values. - * - * @see CPU_BIG_ENDIAN - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_LITTLE_ENDIAN FALSE - -/** - * @ingroup CPUInterrupt - * The following defines the number of bits actually used in the - * interrupt field of the task mode. How those bits map to the - * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_MODES_INTERRUPT_MASK 0x00000001 - -/* - * Processor defined structures required for cpukit/score. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* may need to put some structures here. */ - -/** - * @defgroup CPUContext Processor Dependent Context Management - * - * From the highest level viewpoint, there are 2 types of context to save. - * - * -# Interrupt registers to save - * -# Task level registers to save - * - * Since RTEMS handles integer and floating point contexts separately, this - * means we have the following 3 context items: - * - * -# task level context stuff:: Context_Control - * -# floating point task stuff:: Context_Control_fp - * -# special interrupt level context :: CPU_Interrupt_frame - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/** - * @ingroup CPUContext Management - * This defines the minimal set of integer and processor state registers - * that must be saved during a voluntary context switch from one thread - * to another. - */ -typedef struct { - uint32_t r[32]; -} Context_Control; - -/** - * @ingroup CPUContext Management - * - * This macro returns the stack pointer associated with @a _context. - * - * @param[in] _context is the thread context area to access - * - * @return This method returns the stack pointer. - */ -#define _CPU_Context_Get_SP( _context ) \ - (_context)->r[0] - -/** - * @ingroup CPUContext Management - * This defines the complete set of floating point registers that must - * be saved during any context switch from one thread to another. - */ -typedef struct { - /** FPU registers are listed here */ - double some_float_register; -} Context_Control_fp; - -/** - * @ingroup CPUContext Management - * This defines the set of integer and processor state registers that must - * be saved during an interrupt. This set does not include any which are - * in @ref Context_Control. - */ -typedef struct { - /** This field is a hint that a port will have a number of integer - * registers that need to be saved when an interrupt occurs or - * when a context switch occurs at the end of an ISR. - */ - uint32_t special_interrupt_register; -} CPU_Interrupt_frame; - -/** - * This variable is optional. It is used on CPUs on which it is difficult - * to generate an "uninitialized" FP context. It is filled in by - * @ref _CPU_Initialize and copied into the task's FP context area during - * @ref _CPU_Context_Initialize. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; - -/** - * @defgroup CPUInterrupt Processor Dependent Interrupt Management - * - * On some CPUs, RTEMS supports a software managed interrupt stack. - * This stack is allocated by the Interrupt Manager and the switch - * is performed in @ref _ISR_Handler. These variables contain pointers - * to the lowest and highest addresses in the chunk of memory allocated - * for the interrupt stack. Since it is unknown whether the stack - * grows up or down (in general), this give the CPU dependent - * code the option of picking the version it wants to use. - * - * @note These two variables are required if the macro - * @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* - * Nothing prevents the porter from declaring more CPU specific variables. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -/* XXX: if needed, put more variables here */ - -/** - * @ingroup CPUContext - * The size of the floating point context area. On some CPUs this - * will not be a "sizeof" because the format of the floating point - * area is not defined -- only the size is. This is usually on - * CPUs with a "floating point save context" instruction. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) - -/** - * Amount of extra stack (above minimum stack size) required by - * MPCI receive server thread. Remember that in a multiprocessor - * system this thread must exist and be able to process all directives. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 - -/** - * @ingroup CPUInterrupt - * This defines the number of entries in the @ref _ISR_Vector_table managed - * by RTEMS. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32 - -/** - * @ingroup CPUInterrupt - * This defines the highest interrupt vector number for this port. - */ -#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) - -/** - * @ingroup CPUInterrupt - * This is defined if the port has a special way to report the ISR nesting - * level. Most ports maintain the variable @a _ISR_Nest_level. - */ -#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE - -/** - * @ingroup CPUContext - * Should be large enough to run all RTEMS tests. This ensures - * that a "reasonable" small application should not have any problems. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_MINIMUM_SIZE (1024*4) - -/** - * CPU's worst alignment requirement for data types on a byte boundary. This - * alignment does not take into account the requirements for the stack. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_ALIGNMENT 8 - -/** - * This number corresponds to the byte alignment requirement for the - * heap handler. This alignment requirement may be stricter than that - * for the data types alignment specified by @ref CPU_ALIGNMENT. It is - * common for the heap to follow the same alignment requirement as - * @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is strict enough for - * the heap, then this should be set to @ref CPU_ALIGNMENT. - * - * @note This does not have to be a power of 2 although it should be - * a multiple of 2 greater than or equal to 2. The requirement - * to be a multiple of 2 is because the heap uses the least - * significant field of the front and back flags to indicate - * that a block is in use or free. So you do not want any odd - * length blocks really putting length data in that bit. - * - * On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will - * have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that - * elements allocated from the heap meet all restrictions. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT - -/** - * This number corresponds to the byte alignment requirement for memory - * buffers allocated by the partition manager. This alignment requirement - * may be stricter than that for the data types alignment specified by - * @ref CPU_ALIGNMENT. It is common for the partition to follow the same - * alignment requirement as @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is - * strict enough for the partition, then this should be set to - * @ref CPU_ALIGNMENT. - * - * @note This does not have to be a power of 2. It does have to - * be greater or equal to than @ref CPU_ALIGNMENT. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT - -/** - * This number corresponds to the byte alignment requirement for the - * stack. This alignment requirement may be stricter than that for the - * data types alignment specified by @ref CPU_ALIGNMENT. If the - * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be - * set to 0. - * - * @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define CPU_STACK_ALIGNMENT 0 - -/* - * ISR handler macros - */ - -/** - * @ingroup CPUInterrupt - * Support routine to initialize the RTEMS vector table after it is allocated. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Initialize_vectors() - -/** - * @ingroup CPUInterrupt - * Disable all interrupts for an RTEMS critical section. The previous - * level is returned in @a _isr_cookie. - * - * @param[out] _isr_cookie will contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_MSR_GET( _msr_value ) \ - do { \ - _msr_value = 0; \ - __asm__ volatile ("mfs %0, rmsr" : "=&r" ((_msr_value)) : "0" ((_msr_value))); \ - } while (0) - -#define _CPU_MSR_SET( _msr_value ) \ -{ __asm__ volatile ("mts rmsr, %0" : "=&r" ((_msr_value)) : "0" ((_msr_value))); } - -#define _CPU_ISR_Disable( _isr_cookie ) \ - { \ - unsigned int _new_msr; \ - _CPU_MSR_GET(_isr_cookie); \ - _new_msr = _isr_cookie & ~0x02; \ - _CPU_MSR_SET(_new_msr); \ - } - -/** - * @ingroup CPUInterrupt - * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). - * This indicates the end of an RTEMS critical section. The parameter - * @a _isr_cookie is not modified. - * - * @param[in] _isr_cookie contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Enable( _isr_cookie ) \ - { \ - _CPU_MSR_SET(_isr_cookie); \ - } - -/** - * @ingroup CPUInterrupt - * This temporarily restores the interrupt to @a _isr_cookie before immediately - * disabling them again. This is used to divide long RTEMS critical - * sections into two or more parts. The parameter @a _isr_cookie is not - * modified. - * - * @param[in] _isr_cookie contain the previous level cookie - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Flash( _isr_cookie ) \ - { \ - unsigned int _new_msr; \ - _CPU_MSR_SET(_isr_cookie); \ - _new_msr = _isr_cookie & ~0x02; \ - _CPU_MSR_SET(_new_msr); \ - } - -/** - * @ingroup CPUInterrupt - * - * This routine and @ref _CPU_ISR_Get_level - * Map the interrupt level in task mode onto the hardware that the CPU - * actually provides. Currently, interrupt levels which do not - * map onto the CPU in a generic fashion are undefined. Someday, - * it would be nice if these were "mapped" by the application - * via a callout. For example, m68k has 8 levels 0 - 7, levels - * 8 - 255 would be available for bsp/application specific meaning. - * This could be used to manage a programmable interrupt controller - * via the rtems_task_mode directive. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_ISR_Set_level( new_level ) \ - { \ - } - -/** - * @ingroup CPUInterrupt - * Return the current interrupt disable level for this task in - * the format used by the interrupt level portion of the task mode. - * - * @note This routine usually must be implemented as a subroutine. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -uint32_t _CPU_ISR_Get_level( void ); - -/* end of ISR handler macros */ - -/** - * @brief Initializes the CPU context. - * - * The following steps are performed: - * - setting a starting address - * - preparing the stack - * - preparing the stack and frame pointers - * - setting the proper interrupt level in the context - * - * @param[in] context points to the context area - * @param[in] stack_area_begin is the low address of the allocated stack area - * @param[in] stack_area_size is the size of the stack area in bytes - * @param[in] new_level is the interrupt level for the task - * @param[in] entry_point is the task's entry point - * @param[in] is_fp is set to @c true if the task is a floating point task - * @param[in] tls_area is the thread-local storage (TLS) area - */ -void _CPU_Context_Initialize( - Context_Control *context, - void *stack_area_begin, - size_t stack_area_size, - uint32_t new_level, - void (*entry_point)( void ), - bool is_fp, - void *tls_area -); - -/** - * This routine is responsible for somehow restarting the currently - * executing task. If you are lucky, then all that is necessary - * is restoring the context. Otherwise, there will need to be - * a special assembly routine which does something special in this - * case. For many ports, simply adding a label to the restore path - * of @ref _CPU_Context_switch will work. On other ports, it may be - * possibly to load a few arguments and jump to the restore path. It will - * not work if restarting self conflicts with the stack frame - * assumptions of restoring a context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Restart_self( _the_context ) \ - _CPU_Context_restore( (_the_context) ); - -/** - * @ingroup CPUContext - * The purpose of this macro is to allow the initial pointer into - * a floating point context area (used to save the floating point - * context) to be at an arbitrary place in the floating point - * context area. - * - * This is necessary because some FP units are designed to have - * their context saved as a stack which grows into lower addresses. - * Other FP units can be saved by simply moving registers into offsets - * from the base of the context area. Finally some FP units provide - * a "dump context" instruction which could fill in from high to low - * or low to high based on the whim of the CPU designers. - * - * @param[in] _base is the lowest physical address of the floating point - * context area - * @param[in] _offset is the offset into the floating point area - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Fp_start( _base, _offset ) \ - ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) - -/** - * This routine initializes the FP context area passed to it to. - * There are a few standard ways in which to initialize the - * floating point context. The code included for this macro assumes - * that this is a CPU in which a "initial" FP context was saved into - * @a _CPU_Null_fp_context and it simply copies it to the destination - * context passed to it. - * - * Other floating point context save/restore models include: - * -# not doing anything, and - * -# putting a "null FP status word" in the correct place in the FP context. - * - * @param[in] _destination is the floating point context area - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Context_Initialize_fp( _destination ) \ - { \ - *(*(_destination)) = _CPU_Null_fp_context; \ - } - -/* end of Context handler macros */ - -/* Fatal Error manager macros */ - -/** - * This routine copies _error into a known place -- typically a stack - * location or a register, optionally disables interrupts, and - * halts/stops the CPU. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#define _CPU_Fatal_halt(_source, _error ) \ - printk("Fatal Error %d.%d Halted\n",_source, _error); \ - for(;;) - -/* end of Fatal Error manager macros */ - -/* Bitfield handler macros */ - -/** - * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation - * - * This set of routines are used to implement fast searches for - * the most important ready task. - */ - -/** - * @ingroup CPUBitfield - * This definition is set to TRUE if the port uses the generic bitfield - * manipulation implementation. - */ -#define CPU_USE_GENERIC_BITFIELD_CODE TRUE - -/** - * @ingroup CPUBitfield - * This definition is set to TRUE if the port uses the data tables provided - * by the generic bitfield manipulation implementation. - * This can occur when actually using the generic bitfield manipulation - * implementation or when implementing the same algorithm in assembly - * language for improved performance. It is unlikely that a port will use - * the data if it has a bitfield scan instruction. - */ -#define CPU_USE_GENERIC_BITFIELD_DATA TRUE - -/** - * @ingroup CPUBitfield - * This routine sets @a _output to the bit number of the first bit - * set in @a _value. @a _value is of CPU dependent type - * @a Priority_bit_map_Control. This type may be either 16 or 32 bits - * wide although only the 16 least significant bits will be used. - * - * There are a number of variables in using a "find first bit" type - * instruction. - * - * -# What happens when run on a value of zero? - * -# Bits may be numbered from MSB to LSB or vice-versa. - * -# The numbering may be zero or one based. - * -# The "find first bit" instruction may search from MSB or LSB. - * - * RTEMS guarantees that (1) will never happen so it is not a concern. - * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and - * @ref _CPU_Priority_bits_index. These three form a set of routines - * which must logically operate together. Bits in the _value are - * set and cleared based on masks built by @ref _CPU_Priority_Mask. - * The basic major and minor values calculated by @ref _Priority_Major - * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index - * to properly range between the values returned by the "find first bit" - * instruction. This makes it possible for @ref _Priority_Get_highest to - * calculate the major and directly index into the minor table. - * This mapping is necessary to ensure that 0 (a high priority major/minor) - * is the first bit found. - * - * This entire "find first bit" and mapping process depends heavily - * on the manner in which a priority is broken into a major and minor - * components with the major being the 4 MSB of a priority and minor - * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest - * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next - * to the lowest priority. - * - * If your CPU does not have a "find first bit" instruction, then - * there are ways to make do without it. Here are a handful of ways - * to implement this in software: - * -@verbatim - - a series of 16 bit test instructions - - a "binary search using if's" - - _number = 0 - if _value > 0x00ff - _value >>=8 - _number = 8; - - if _value > 0x0000f - _value >=8 - _number += 4 - - _number += bit_set_table[ _value ] -@endverbatim - - * where bit_set_table[ 16 ] has values which indicate the first - * bit set - * - * @param[in] _value is the value to be scanned - * @param[in] _output is the first bit set - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ - -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) -#define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - { \ - (_output) = 0; /* do something to prevent warnings */ \ - } -#endif - -/* end of Bitfield handler macros */ - -/** - * This routine builds the mask which corresponds to the bit fields - * as searched by @ref _CPU_Bitfield_Find_first_bit. See the discussion - * for that routine. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_Mask( _bit_number ) \ - ( 1 << (_bit_number) ) - -#endif - -/** - * @ingroup CPUBitfield - * This routine translates the bit numbers returned by - * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as - * a major or minor component of a priority. See the discussion - * for that routine. - * - * @param[in] _priority is the major or minor number to translate - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) - -#define _CPU_Priority_bits_index( _priority ) \ - (_priority) - -#endif - -#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC FALSE -#define CPU_TIMESTAMP_USE_INT64 TRUE -#define CPU_TIMESTAMP_USE_INT64_INLINE FALSE - -typedef struct { -/* There is no CPU specific per-CPU state */ -} CPU_Per_CPU_control; - -#define CPU_SIZEOF_POINTER 4 -#define CPU_PER_CPU_CONTROL_SIZE 0 - -typedef struct { - uint32_t r[32]; -} CPU_Exception_frame; - -/* end of Priority handler macros */ - -/* functions */ - -/** - * This routine performs CPU dependent initialization. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Initialize(void); - -/** - * @ingroup CPUInterrupt - * This routine installs a "raw" interrupt handler directly into the - * processor's vector table. - * - * @param[in] vector is the vector number - * @param[in] new_handler is the raw ISR handler to install - * @param[in] old_handler is the previously installed ISR Handler - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_ISR_install_raw_handler( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * @ingroup CPUInterrupt - * This routine installs an interrupt vector. - * - * @param[in] vector is the vector number - * @param[in] new_handler is the RTEMS ISR handler to install - * @param[in] old_handler is the previously installed ISR Handler - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_ISR_install_vector( - uint32_t vector, - proc_ptr new_handler, - proc_ptr *old_handler -); - -/** - * @ingroup CPUInterrupt - * This routine installs the hardware interrupt stack pointer. - * - * @note It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK - * is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Install_interrupt_stack( void ); - -/** - * This routine is the CPU dependent IDLE thread body. - * - * @note It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY - * is TRUE. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void *_CPU_Thread_Idle_body( uintptr_t ignored ); - -/** - * @ingroup CPUContext - * This routine switches from the run context to the heir context. - * - * @param[in] run points to the context of the currently executing task - * @param[in] heir points to the context of the heir task - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_switch( - Context_Control *run, - Context_Control *heir -); - -/** - * @ingroup CPUContext - * This routine is generally used only to restart self in an - * efficient manner. It may simply be a label in @ref _CPU_Context_switch. - * - * @param[in] new_context points to the context to be restored. - * - * @note May be unnecessary to reload some registers. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_restore( - Context_Control *new_context -) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE; - -/** - * @ingroup CPUContext - * This routine saves the floating point context passed to it. - * - * @param[in] fp_context_ptr is a pointer to a pointer to a floating - * point context area - * - * @return on output @a *fp_context_ptr will contain the address that - * should be used with @ref _CPU_Context_restore_fp to restore this context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_save_fp( - Context_Control_fp **fp_context_ptr -); - -/** - * @ingroup CPUContext - * This routine restores the floating point context passed to it. - * - * @param[in] fp_context_ptr is a pointer to a pointer to a floating - * point context area to restore - * - * @return on output @a *fp_context_ptr will contain the address that - * should be used with @ref _CPU_Context_save_fp to save this context. - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -void _CPU_Context_restore_fp( - Context_Control_fp **fp_context_ptr -); - -/** - * @ingroup CPUEndian - * The following routine swaps the endian format of an unsigned int. - * It must be static because it is referenced indirectly. - * - * This version will work on any processor, but if there is a better - * way for your CPU PLEASE use it. The most common way to do this is to: - * - * swap least significant two bytes with 16-bit rotate - * swap upper and lower 16-bits - * swap most significant two bytes with 16-bit rotate - * - * Some CPUs have special instructions which swap a 32-bit quantity in - * a single instruction (e.g. i486). It is probably best to avoid - * an "endian swapping control bit" in the CPU. One good reason is - * that interrupts would probably have to be disabled to ensure that - * an interrupt does not try to access the same "chunk" with the wrong - * endian. Another good reason is that on some CPUs, the endian bit - * endianness for ALL fetches -- both code and data -- so the code - * will be fetched incorrectly. - * - * @param[in] value is the value to be swapped - * @return the value after being endian swapped - * - * Port Specific Information: - * - * XXX document implementation including references if appropriate - */ -static inline uint32_t CPU_swap_u32( - uint32_t value -) -{ - uint32_t byte1, byte2, byte3, byte4, swapped; - - byte4 = (value >> 24) & 0xff; - byte3 = (value >> 16) & 0xff; - byte2 = (value >> 8) & 0xff; - byte1 = value & 0xff; - - swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; - return swapped; -} - -/** - * @ingroup CPUEndian - * This routine swaps a 16 bir quantity. - * - * @param[in] value is the value to be swapped - * @return the value after being endian swapped - */ -#define CPU_swap_u16( value ) \ - (((value&0xff) << 8) | ((value >> 8)&0xff)) - -typedef uint32_t CPU_Counter_ticks; - -CPU_Counter_ticks _CPU_Counter_read( void ); - -CPU_Counter_ticks _CPU_Counter_difference( - CPU_Counter_ticks second, - CPU_Counter_ticks first -); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/spec/build/bsps/microblaze/grp.yml b/spec/build/bsps/microblaze/grp.yml new file mode 100644 index 0000000000..3a238f5d6e --- /dev/null +++ b/spec/build/bsps/microblaze/grp.yml @@ -0,0 +1,15 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +build-type: group +copyrights: +- Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +enabled-by: true +includes: [] +install: +- destination: ${BSP_INCLUDEDIR}/bsp + source: + - bsps/microblaze/include/bsp/linker-symbols.h +ldflags: [] +links: [] +type: build +use-after: [] +use-before: [] diff --git a/spec/build/bsps/microblaze/microblaze_fpga/abi.yml b/spec/build/bsps/microblaze/microblaze_fpga/abi.yml new file mode 100644 index 0000000000..4665f5d42e --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/abi.yml @@ -0,0 +1,20 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-string: null +- split: null +- env-append: null +build-type: option +copyrights: +- Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +default: +- -mlittle-endian +- -mno-xl-soft-div +- -mno-xl-soft-mul +- -Wl,-EL +default-by-variant: [] +description: | + ABI flags +enabled-by: true +links: [] +name: ABI_FLAGS +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/bspkcu105.yml b/spec/build/bsps/microblaze/microblaze_fpga/bspkcu105.yml new file mode 100644 index 0000000000..0a29e9c200 --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/bspkcu105.yml @@ -0,0 +1,24 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +arch: microblaze +bsp: kcu105 +build-type: bsp +cflags: [] +copyrights: +- Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +cppflags: [] +enabled-by: true +family: microblaze_fpga +includes: [] +install: [] +links: +- role: build-dependency + uid: grp +- role: build-dependency + uid: linkcmds +- role: build-dependency + uid: tstkcu105_qemu +- role: build-dependency + uid: ../../opto0 +source: +- bsps/shared/start/bspreset-loop.c +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/bspkcu105_qemu.yml b/spec/build/bsps/microblaze/microblaze_fpga/bspkcu105_qemu.yml new file mode 100644 index 0000000000..9f5d742885 --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/bspkcu105_qemu.yml @@ -0,0 +1,24 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +arch: microblaze +bsp: kcu105_qemu +build-type: bsp +cflags: [] +copyrights: +- Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +cppflags: [] +enabled-by: true +family: microblaze_fpga +includes: [] +install: [] +links: +- role: build-dependency + uid: grp +- role: build-dependency + uid: linkcmds +- role: build-dependency + uid: tstkcu105_qemu +- role: build-dependency + uid: ../../opto0 +source: +- bsps/microblaze/microblaze_fpga/start/bspreset.c +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/grp.yml b/spec/build/bsps/microblaze/microblaze_fpga/grp.yml new file mode 100644 index 0000000000..38cd3e1a83 --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/grp.yml @@ -0,0 +1,36 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +build-type: group +copyrights: +- Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +enabled-by: true +includes: [] +install: [] +ldflags: [] +links: +- role: build-dependency + uid: ../grp +- role: build-dependency + uid: abi +- role: build-dependency + uid: obj +- role: build-dependency + uid: start +- role: build-dependency + uid: optconsoleinterrupts +- role: build-dependency + uid: optintcbaseaddress +- role: build-dependency + uid: opttimerbaseaddress +- role: build-dependency + uid: opttimerfrequency +- role: build-dependency + uid: optuartlitebaseaddress +- role: build-dependency + uid: ../../obj +- role: build-dependency + uid: ../../objirq +- role: build-dependency + uid: ../../bspopts +type: build +use-after: [] +use-before: [] diff --git a/spec/build/bsps/microblaze/microblaze_fpga/linkcmds.yml b/spec/build/bsps/microblaze/microblaze_fpga/linkcmds.yml new file mode 100644 index 0000000000..d478e86fb6 --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/linkcmds.yml @@ -0,0 +1,242 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +build-type: config-file +content: | + /* SPDX-License-Identifier: BSD-2-Clause */ + + /* + * Copyright (C) 2021 On-Line Applications Research Corporation (OAR) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + ENTRY (_start) + STARTUP (start.o) + _TEXT_START_ADDR = DEFINED(_TEXT_START_ADDR) ? _TEXT_START_ADDR : 0x80000000; + + MEMORY + { + BRAM (AIW) : ORIGIN = 0x00000000, LENGTH = 0x10000 + RAM : ORIGIN = _TEXT_START_ADDR, LENGTH = 0x1000000 + } + + REGION_ALIAS ("REGION_START", BRAM); + REGION_ALIAS ("REGION_VECTOR", BRAM); + REGION_ALIAS ("REGION_TEXT", RAM); + REGION_ALIAS ("REGION_TEXT_LOAD", RAM); + REGION_ALIAS ("REGION_RODATA", RAM); + REGION_ALIAS ("REGION_RODATA_LOAD", RAM); + REGION_ALIAS ("REGION_DATA", RAM); + REGION_ALIAS ("REGION_DATA_LOAD", RAM); + REGION_ALIAS ("REGION_FAST_DATA", RAM); + REGION_ALIAS ("REGION_FAST_DATA_LOAD", RAM); + REGION_ALIAS ("REGION_BSS", RAM); + REGION_ALIAS ("REGION_WORK", RAM); + REGION_ALIAS ("REGION_STACK", RAM); + + SECTIONS + { + .vectors.reset 0x0 : { KEEP (*(.vectors.reset)) } = 0 + .vectors.sw_exception 0x8 : { KEEP (*(.vectors.sw_exception)) } = 0 + .vectors.interrupt 0x10 : { KEEP (*(.vectors.interrupt)) } = 0 + .vectors.debug_sw_break 0x18 : { KEEP (*(.vectors.debug_sw_break)) } = 0 + .vectors.hw_exception 0x20 : { KEEP (*(.vectors.hw_exception)) } = 0 + . = _TEXT_START_ADDR; + .text : ALIGN_WITH_INPUT { + bsp_section_text_begin = .; + *(.text.unlikely .text.*_unlikely) + *(.text .stub .text.* .gnu.linkonce.t.*) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx) + } > REGION_TEXT AT > REGION_TEXT_LOAD + .init : ALIGN_WITH_INPUT { + KEEP (*(.init)) + } > REGION_TEXT AT > REGION_TEXT_LOAD + .fini : ALIGN_WITH_INPUT { + KEEP (*(.fini)) + + /* + * If requested, align the size of the combined start and text + * section to the next power of two to meet MPU region + * alignment requirements. + */ + . = DEFINED (bsp_align_text_and_rodata_end_to_power_of_2) ? + bsp_section_start_begin + + ALIGN (. - bsp_section_start_begin, + 1 << LOG2CEIL (. - bsp_section_start_begin)) : .; + + bsp_section_text_end = .; + } > REGION_TEXT AT > REGION_TEXT_LOAD + bsp_section_text_size = bsp_section_text_end - bsp_section_text_begin; + bsp_section_text_load_begin = LOADADDR (.text); + bsp_section_text_load_end = bsp_section_text_load_begin + bsp_section_text_size; + + . = ALIGN(4); + + /* Added to handle pic code */ + .got : { + *(.got) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .got1 : { + *(.got1) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .got2 : { + *(.got2) + } > REGION_RODATA AT > REGION_RODATA_LOAD + + _frodata = . ; + .rodata : { + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + CONSTRUCTORS; /* Is this needed? */ + } > REGION_RODATA AT > REGION_RODATA_LOAD + _erodata = .; + .eh_frame : { + *(.eh_frame) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .jcr : { + *(.jcr) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .gcc_except_table : { + *(.gcc_except_table) + } > REGION_RODATA AT > REGION_RODATA_LOAD + .tdata : ALIGN_WITH_INPUT { + _TLS_Data_begin = .; + *(.tdata .tdata.* .gnu.linkonce.td.*) + _TLS_Data_end = .; + } > REGION_RODATA AT > REGION_RODATA_LOAD + .tbss : ALIGN_WITH_INPUT { + _TLS_BSS_begin = .; + *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) + _TLS_BSS_end = .; + } > REGION_RODATA AT > REGION_RODATA_LOAD + _TLS_Data_size = _TLS_Data_end - _TLS_Data_begin; + _TLS_Data_begin = _TLS_Data_size != 0 ? _TLS_Data_begin : _TLS_BSS_begin; + _TLS_Data_end = _TLS_Data_size != 0 ? _TLS_Data_end : _TLS_BSS_begin; + _TLS_BSS_size = _TLS_BSS_end - _TLS_BSS_begin; + _TLS_Size = _TLS_BSS_end - _TLS_Data_begin; + _TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss)); + + .ctors : { + _dummy_symbol__ = .; + __CTOR_LIST__ = .; + ___CTORS_LIST___ = .; + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors*)) + __CTOR_END__ = .; + ___CTORS_END___ = .; + } > REGION_RODATA AT > REGION_RODATA_LOAD + .dtors : { + __DTOR_LIST__ = .; + ___DTORS_LIST___ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + PROVIDE(__DTOR_END__ = .); + PROVIDE(___DTORS_END___ = .); + } > REGION_RODATA AT > REGION_RODATA_LOAD + .rtemsroset : { + /* Special FreeBSD linker set sections */ + __start_set_sysctl_set = .; + *(set_sysctl_*); + __stop_set_sysctl_set = .; + *(set_domain_*); + *(set_pseudo_*); + + KEEP (*(SORT(.rtemsroset.*))) + bsp_section_rodata_end = .; + } > REGION_RODATA AT > REGION_RODATA_LOAD + + .data : ALIGN_WITH_INPUT { + bsp_section_data_begin = .; + *(.data .data.* .gnu.linkonce.d.*) + SORT(CONSTRUCTORS) + } > REGION_DATA AT > REGION_DATA_LOAD + .data1 : ALIGN_WITH_INPUT { + *(.data1) + } > REGION_DATA AT > REGION_DATA_LOAD + .rtemsrwset : ALIGN_WITH_INPUT { + KEEP (*(SORT(.rtemsrwset.*))) + bsp_section_data_end = .; + } > REGION_DATA AT > REGION_DATA_LOAD + bsp_section_data_size = bsp_section_data_end - bsp_section_data_begin; + bsp_section_data_load_begin = LOADADDR (.data); + bsp_section_data_load_end = bsp_section_data_load_begin + bsp_section_data_size; + + .bss : ALIGN_WITH_INPUT { + bsp_section_bss_begin = .; + *(.dynbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + bsp_section_bss_end = .; + } > REGION_BSS AT > REGION_BSS + bsp_section_bss_size = bsp_section_bss_end - bsp_section_bss_begin; + + . = ALIGN(8); + + .rtemsstack (NOLOAD) : ALIGN_WITH_INPUT { + bsp_section_rtemsstack_begin = .; + *(SORT_BY_ALIGNMENT (SORT_BY_NAME (.rtemsstack*))) + bsp_section_rtemsstack_end = .; + } > REGION_WORK AT > REGION_WORK + bsp_section_rtemsstack_size = bsp_section_rtemsstack_end - bsp_section_rtemsstack_begin; + + .work : ALIGN_WITH_INPUT { + /* + * The work section will occupy the remaining REGION_WORK region and + * contains the RTEMS work space and heap. + */ + bsp_section_work_begin = .; + . += ORIGIN (REGION_WORK) + LENGTH (REGION_WORK) - ABSOLUTE (.); + bsp_section_work_end = .; + } > REGION_WORK AT > REGION_WORK + bsp_section_work_size = bsp_section_work_end - bsp_section_work_begin; + + .stack : ALIGN_WITH_INPUT { + /* + * The stack section will occupy the remaining REGION_STACK region and may + * contain the task stacks. Depending on the region distribution this + * section may be of zero size. + */ + bsp_section_stack_begin = .; + . += ORIGIN (REGION_STACK) + LENGTH (REGION_STACK) - ABSOLUTE (.); + bsp_section_stack_end = .; + } > REGION_STACK AT > REGION_STACK + bsp_section_stack_size = bsp_section_stack_end - bsp_section_stack_begin; + + RamBase = ORIGIN (REGION_WORK); + RamSize = LENGTH (REGION_WORK); + RamEnd = RamBase + RamSize; + WorkAreaBase = bsp_section_work_begin; + HeapSize = 0; + } +copyrights: +- Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +enabled-by: true +install-path: ${BSP_LIBDIR} +links: [] +target: linkcmds +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/obj.yml b/spec/build/bsps/microblaze/microblaze_fpga/obj.yml new file mode 100644 index 0000000000..beebbf9d20 --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/obj.yml @@ -0,0 +1,47 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +build-type: objects +cflags: [] +copyrights: +- Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +cppflags: [] +cxxflags: [] +enabled-by: true +includes: [] +install: +- destination: ${BSP_INCLUDEDIR} + source: + - bsps/microblaze/microblaze_fpga/include/bsp.h + - bsps/microblaze/microblaze_fpga/include/tm27.h +- destination: ${BSP_INCLUDEDIR}/bsp + source: + - bsps/microblaze/microblaze_fpga/include/bsp/irq.h + - bsps/microblaze/include/common/xil_types.h + - bsps/microblaze/include/dev/serial/uartlite.h + - bsps/microblaze/include/dev/serial/uartlite_l.h +links: [] +source: +- bsps/microblaze/microblaze_fpga/clock/clock.c +- bsps/microblaze/microblaze_fpga/console/console-io.c +- bsps/microblaze/microblaze_fpga/console/debug-io.c +- bsps/microblaze/microblaze_fpga/irq/irq.c +- bsps/microblaze/microblaze_fpga/start/_exception_handler.S +- bsps/microblaze/microblaze_fpga/start/_hw_exception_handler.S +- bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S +- bsps/microblaze/microblaze_fpga/start/bspreset.c +- bsps/microblaze/microblaze_fpga/start/bspstart.c +- bsps/microblaze/microblaze_fpga/start/crtinit.S +- bsps/microblaze/shared/dev/serial/uartlite.c +- bsps/microblaze/shared/dev/serial/uartlite_l.c +- bsps/shared/cache/nocache.c +- bsps/shared/dev/btimer/btimer-cpucounter.c +- bsps/shared/dev/cpucounter/cpucounterfrequency.c +- bsps/shared/dev/cpucounter/cpucounterread.c +- bsps/shared/dev/getentropy/getentropy-cpucounter.c +- bsps/shared/dev/serial/console-termios-init.c +- bsps/shared/dev/serial/console-termios.c +- bsps/shared/irq/irq-default-handler.c +- bsps/shared/start/bspfatal-default.c +- bsps/shared/start/bspgetworkarea-default.c +- bsps/shared/start/gettargethash-default.c +- bsps/shared/start/sbrk.c +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optconsoleinterrupts.yml b/spec/build/bsps/microblaze/microblaze_fpga/optconsoleinterrupts.yml new file mode 100644 index 0000000000..c75a4450e1 --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/optconsoleinterrupts.yml @@ -0,0 +1,15 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-boolean: null +- define-condition: null +build-type: option +copyrights: +- Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +default: true +default-by-variant: [] +description: | + use interrupt driven mode for console +enabled-by: true +links: [] +name: BSP_MICROBLAZE_FPGA_CONSOLE_INTERRUPTS +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optintcbaseaddress.yml b/spec/build/bsps/microblaze/microblaze_fpga/optintcbaseaddress.yml new file mode 100644 index 0000000000..5ed9294ff6 --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/optintcbaseaddress.yml @@ -0,0 +1,18 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +default: 0x41200000 +default-by-variant: [] +description: | + base address of the AXI Interrupt Controller +enabled-by: true +format: '{:#010x}' +links: [] +name: BSP_MICROBLAZE_FPGA_INTC_BASE +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/opttimerbaseaddress.yml b/spec/build/bsps/microblaze/microblaze_fpga/opttimerbaseaddress.yml new file mode 100644 index 0000000000..93bea74ea3 --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/opttimerbaseaddress.yml @@ -0,0 +1,18 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +default: 0x41C00000 +default-by-variant: [] +description: | + base address of the AXI Timer +enabled-by: true +format: '{:#010x}' +links: [] +name: BSP_MICROBLAZE_FPGA_TIMER_BASE +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/opttimerfrequency.yml b/spec/build/bsps/microblaze/microblaze_fpga/opttimerfrequency.yml new file mode 100644 index 0000000000..4734f81bc1 --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/opttimerfrequency.yml @@ -0,0 +1,17 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- define: null +build-type: option +copyrights: +- Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +default: 100000000 +default-by-variant: [] +description: | + frequency of the AXI Timer +enabled-by: true +format: '{}' +links: [] +name: BSP_MICROBLAZE_FPGA_TIMER_FREQUENCY +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/optuartlitebaseaddress.yml b/spec/build/bsps/microblaze/microblaze_fpga/optuartlitebaseaddress.yml new file mode 100644 index 0000000000..7dd3123b64 --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/optuartlitebaseaddress.yml @@ -0,0 +1,18 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- get-integer: null +- assert-uint32: null +- env-assign: null +- format-and-define: null +build-type: option +copyrights: +- Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +default: 0x40600000 +default-by-variant: [] +description: | + base address of the AXI UART Lite +enabled-by: true +format: '{:#010x}' +links: [] +name: BSP_MICROBLAZE_FPGA_UART_BASE +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/start.yml b/spec/build/bsps/microblaze/microblaze_fpga/start.yml new file mode 100644 index 0000000000..38de263733 --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/start.yml @@ -0,0 +1,14 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +asflags: [] +build-type: start-file +copyrights: +- Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +cppflags: [] +enabled-by: true +includes: [] +install-path: ${BSP_LIBDIR} +links: [] +source: +- bsps/microblaze/shared/start/start.S +target: start.o +type: build diff --git a/spec/build/bsps/microblaze/microblaze_fpga/tstkcu105_qemu.yml b/spec/build/bsps/microblaze/microblaze_fpga/tstkcu105_qemu.yml new file mode 100644 index 0000000000..fb9f2bdb00 --- /dev/null +++ b/spec/build/bsps/microblaze/microblaze_fpga/tstkcu105_qemu.yml @@ -0,0 +1,14 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +actions: +- set-test-state: + # expected to fail, don't compile these + minimum: exclude +build-type: option +copyrights: +- Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +default: null +default-by-variant: [] +description: '' +enabled-by: true +links: [] +type: build diff --git a/spec/build/cpukit/cpumicroblaze.yml b/spec/build/cpukit/cpumicroblaze.yml new file mode 100644 index 0000000000..36c328216d --- /dev/null +++ b/spec/build/cpukit/cpumicroblaze.yml @@ -0,0 +1,29 @@ +SPDX-License-Identifier: CC-BY-SA-4.0 OR BSD-2-Clause +build-type: objects +cflags: [] +copyrights: +- Copyright (C) 2021 On-Line Applications Research Corporation (OAR) +cppflags: [] +cxxflags: [] +enabled-by: +- microblaze +includes: [] +install: +- destination: ${BSP_INCLUDEDIR}/rtems + source: + - cpukit/score/cpu/microblaze/include/rtems/asm.h +- destination: ${BSP_INCLUDEDIR}/rtems/score + source: + - cpukit/score/cpu/microblaze/include/rtems/score/cpu.h + - cpukit/score/cpu/microblaze/include/rtems/score/cpuatomic.h + - cpukit/score/cpu/microblaze/include/rtems/score/cpuimpl.h + - cpukit/score/cpu/microblaze/include/rtems/score/microblaze.h +links: [] +source: +- cpukit/score/cpu/microblaze/__tls_get_addr.c +- cpukit/score/cpu/microblaze/microblaze-context-switch.S +- cpukit/score/cpu/microblaze/microblaze-context-validate.S +- cpukit/score/cpu/microblaze/microblaze-context-volatile-clobber.S +- cpukit/score/cpu/microblaze/cpu.c +- cpukit/score/cpu/microblaze/cpu_asm.S +type: build diff --git a/spec/build/cpukit/librtemscpu.yml b/spec/build/cpukit/librtemscpu.yml index 68f3d448cc..070bff0d57 100644 --- a/spec/build/cpukit/librtemscpu.yml +++ b/spec/build/cpukit/librtemscpu.yml @@ -472,6 +472,8 @@ links: - role: build-dependency uid: cpumips - role: build-dependency + uid: cpumicroblaze +- role: build-dependency uid: cpumoxie - role: build-dependency uid: cpunios2 |