diff options
Diffstat (limited to '')
| -rw-r--r-- | cpukit/score/cpu/powerpc/ChangeLog | 6 | ||||
| -rw-r--r-- | cpukit/score/cpu/powerpc/rtems/powerpc/registers.h | 16 |
2 files changed, 14 insertions, 8 deletions
diff --git a/cpukit/score/cpu/powerpc/ChangeLog b/cpukit/score/cpu/powerpc/ChangeLog index c8f7fe9c6e..9d1a241b2a 100644 --- a/cpukit/score/cpu/powerpc/ChangeLog +++ b/cpukit/score/cpu/powerpc/ChangeLog @@ -1,3 +1,9 @@ +2011-08-24 Sebastian Huber <sebastian.huber@embedded-brains.de> + + * rtems/powerpc/registers.h: Renamed defines XER in PPC_XER, LR in + PPC_LR, CTR in PPC_CTR, PVR in PPC_PVR, RPA in PPC_RPA, DAR in + PPC_DAR, DEC in PPC_DEC, and EAR in PPC_EAR. + 2011-07-21 Sebastian Huber <sebastian.huber@embedded-brains.de> * rtems/score/cpu.h: Added SPE support to CPU context. diff --git a/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h b/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h index dc97b10e93..7dc3d20c91 100644 --- a/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h +++ b/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h @@ -122,14 +122,14 @@ n: #define TBRL 268 #define TBWU 285 /* Time base Upper/Lower (Writing) */ #define TBWL 284 -#define XER 1 -#define LR 8 -#define CTR 9 +#define PPC_XER 1 +#define PPC_LR 8 +#define PPC_CTR 9 #define HID0 1008 /* Hardware Implementation 0 */ #define HID1 1009 /* Hardware Implementation 1 */ #define HID2 1011 /* Hardware Implementation 2 */ #define DABR 1013 /* Data Access Breakpoint */ -#define PVR 287 /* Processor Version */ +#define PPC_PVR 287 /* Processor Version */ #define IBAT0U 528 /* Instruction BAT #0 Upper/Lower */ #define IBAT0L 529 #define IBAT1U 530 /* Instruction BAT #1 Upper/Lower */ @@ -174,9 +174,9 @@ n: #define HASH2 979 #define IMISS 980 #define ICMP 981 -#define RPA 982 +#define PPC_RPA 982 #define SDR1 25 /* MMU hash base register */ -#define DAR 19 /* Data Address Register */ +#define PPC_DAR 19 /* Data Address Register */ #define DEAR_BOOKE 61 #define DEAR_405 981 #define SPR0 272 /* Supervisor Private Registers */ @@ -196,8 +196,8 @@ n: #define SRR0 26 /* Saved Registers (exception) */ #define SRR1 27 #define IABR 1010 /* Instruction Address Breakpoint */ -#define DEC 22 /* Decrementer */ -#define EAR 282 /* External Address Register */ +#define PPC_DEC 22 /* Decrementer */ +#define PPC_EAR 282 /* External Address Register */ #define MSSCR0 1014 /* Memory Subsystem Control Register */ |