diff options
21 files changed, 3532 insertions, 14 deletions
diff --git a/c/src/exec/score/cpu/m68k/cpu.c b/c/src/exec/score/cpu/m68k/cpu.c index 45484da1f4..662a0440f4 100644 --- a/c/src/exec/score/cpu/m68k/cpu.c +++ b/c/src/exec/score/cpu/m68k/cpu.c @@ -95,3 +95,26 @@ void _CPU_Install_interrupt_stack( void ) #endif } +#if ( M68K_HAS_BFFFO != 1 ) +/* + * Returns log2(x) 0<x<256 + */ +const unsigned char __log2table[256] = { + 0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, + 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, + 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, + 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, + 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, + 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, + 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, + 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, + 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, + 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, + 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, + 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, + 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, + 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, + 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, + 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, +}; +#endif diff --git a/c/src/exec/score/cpu/m68k/cpu.h b/c/src/exec/score/cpu/m68k/cpu.h index 38bd16e0c3..0b36533562 100644 --- a/c/src/exec/score/cpu/m68k/cpu.h +++ b/c/src/exec/score/cpu/m68k/cpu.h @@ -43,11 +43,20 @@ extern "C" { /* * Use the m68k's hardware interrupt stack support and have the * interrupt manager allocate the memory for it. + * + * NOTE: The definitions when M68K_HAS_SEPARATE_STACKS is 0 should + * change when the software interrupt stack support is implemented. */ +#if ( M68K_HAS_SEPARATE_STACKS == 1) #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE #define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE #define CPU_ALLOCATE_INTERRUPT_STACK TRUE +#else +#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE +#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE +#define CPU_ALLOCATE_INTERRUPT_STACK FALSE +#endif /* * Some family members have no FP, some have an FPU such as the @@ -316,10 +325,24 @@ EXTERN void *_CPU_Interrupt_stack_high; #else #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ - (_output) = 0 /* avoids warnings */ - -#warning "FIX ME... NEEDS A SOFTWARE BFFFO IMPLEMENTATION" -#warning "SEE no_cpu/cpu.h FOR POSSIBLE ALGORITHMS" + { \ + extern const unsigned char __log2table[256]; \ + \ + (_output) = 0; /* avoids warnings */ \ + asm ( "move.w %1,%0\n"\ + "\tandi.w #0xff00,%0\n"\ + "\tjbne 0f\n"\ + "\tmoveq.l #0,%0\n"\ + "\tmove.b (%2,%1.w),%0\n"\ + "\tjbra 1f\n"\ + "0:\tmoveq.l #8,%0\n"\ + "\tlsr.w #8,%1\n"\ + "\tadd.b (%2,%1.w),%0\n"\ + "1:"\ + : "=&d" ((_output)) \ + : "d" ((_value)), "ao" (__log2table) \ + : "cc" ) ; \ + } #endif @@ -338,8 +361,13 @@ EXTERN void *_CPU_Interrupt_stack_high; #define _CPU_Priority_Mask( _bit_number ) \ ( 0x8000 >> (_bit_number) ) +#if ( M68K_HAS_BFFFO == 1 ) #define _CPU_Priority_Bits_index( _priority ) \ (_priority) +#else +#define _CPU_Priority_Bits_index( _priority ) \ + (15 - (_priority)) +#endif /* end of Priority handler macros */ diff --git a/c/src/exec/score/cpu/m68k/cpu_asm.s b/c/src/exec/score/cpu/m68k/cpu_asm.s index d8615627a0..968a0d4f9a 100644 --- a/c/src/exec/score/cpu/m68k/cpu_asm.s +++ b/c/src/exec/score/cpu/m68k/cpu_asm.s @@ -132,15 +132,25 @@ SYM (_ISR_Handler): jbsr a0@ | invoke the user ISR addql #4,a7 | remove vector number +/* + * The following entry should be unnecessary once the support is + * in place to know what vector we got on a 68000 core. + */ + + .global SYM (_ISR_Exit) +SYM (_ISR_Exit): + subql #1,SYM (_ISR_Nest_level) | one less nest level subql #1,SYM (_Thread_Dispatch_disable_level) | unnest multitasking bne exit | If dispatch disabled, exit +#if ( M68K_HAS_SEPARATE_STACKS == 1 ) movew #0xf000,d0 | isolate format nibble andw a7@(SAVED+FVO_OFFSET),d0 | get F/VO cmpiw #0x1000,d0 | is it a throwaway isf? bne exit | NOT outer level, so branch +#endif tstl SYM (_Context_Switch_necessary) | Is thread switch necessary? @@ -155,17 +165,19 @@ SYM (_ISR_Handler): bframe: clrl SYM (_ISR_Signals_to_thread_executing) | If sent, will be processed #if ( M68K_HAS_SEPARATE_STACKS == 1 ) - movec msp,a0 | a0 = master stack pointer - movew #0,a0@- | push format word + movec msp,a0 | a0 = master stack pointer + movew #0,a0@- | push format word movel # SYM (_ISR_Dispatch),a0@- | push return addr - movew a0@(6+SR_OFFSET),a0@- | push thread sr - movec a0,msp | set master stack pointer + movew a0@(6+SR_OFFSET),a0@- | push thread sr + movec a0,msp | set master stack pointer #else -#warning "FIX ME ... HOW DO I DISPATCH FROM AN INTERRUPT?" -/* probably will simply need to push the _ISR_Dispatch frame */ + + movew a7@(16+SR_OFFSET),sr + jsr SYM (_Thread_Dispatch) + #endif -exit: moveml a7@+,d0-d1/a0-a1 | restore d0-d1,a0-a1 +exit: moveml a7@+,d0-d1/a0-a1 | restore d0-d1,a0-a1 rte | return to thread | OR _Isr_dispatch diff --git a/c/src/exec/score/cpu/m68k/m68302.h b/c/src/exec/score/cpu/m68k/m68302.h new file mode 100644 index 0000000000..da96478cf3 --- /dev/null +++ b/c/src/exec/score/cpu/m68k/m68302.h @@ -0,0 +1,608 @@ +/* + *------------------------------------------------------------------ + * + * m68302.h - Definitions for Motorola MC68302 processor. + * + * Section references in this file refer to revision 2 of Motorola's + * "MC68302 Integrated Multiprotocol Processor User's Manual". + * (Motorola document MC68302UM/AD REV 2.) + * + * Based on Don Meyer's cpu68302.h that was posted in comp.sys.m68k + * on 17 February, 1993. + * + * Copyright 1995 David W. Glessner. + * + * Redistribution and use in source and binary forms are permitted + * provided that the following conditions are met: + * 1. Redistribution of source code and documentation must retain + * the above copyright notice, this list of conditions and the + * following disclaimer. + * 2. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * This software is provided "AS IS" without warranty of any kind, + * either expressed or implied, including, but not limited to, the + * implied warranties of merchantability, title and fitness for a + * particular purpose. + * + * + * $Id$ + * + *------------------------------------------------------------------ + */ + +#ifndef __MOTOROLA_MC68302_DEFINITIONS_h +#define __MOTOROLA_MC68302_DEFINITIONS_h + +/* + * BAR - Base Address Register + * Section 2.7 + */ +#define M302_BAR (*((volatile rtems_unsigned16 *) 0xf2)) + +/* + * SCR - System Control Register + * Section 3.8.1 + */ +#define M302_SCR (*((volatile rtems_unsigned32 *) 0xf4)) +/* + * SCR bits + */ +#define RBIT_SCR_IPA 0x08000000 +#define RBIT_SCR_HWT 0x04000000 +#define RBIT_SCR_WPV 0x02000000 +#define RBIT_SCR_ADC 0x01000000 + +#define RBIT_SCR_ERRE 0x00400000 +#define RBIT_SCR_VGE 0x00200000 +#define RBIT_SCR_WPVE 0x00100000 +#define RBIT_SCR_RMCST 0x00080000 +#define RBIT_SCR_EMWS 0x00040000 +#define RBIT_SCR_ADCE 0x00020000 +#define RBIT_SCR_BCLM 0x00010000 + +#define RBIT_SCR_FRZW 0x00008000 +#define RBIT_SCR_FRZ2 0x00004000 +#define RBIT_SCR_FRZ1 0x00002000 +#define RBIT_SCR_SAM 0x00001000 +#define RBIT_SCR_HWDEN 0x00000800 +#define RBIT_SCR_HWDCN2 0x00000400 +#define RBIT_SCR_HWDCN1 0x00000200 +#define RBIT_SCR_HWDCN0 0x00000100 + +#define RBIT_SCR_LPREC 0x00000080 +#define RBIT_SCR_LPP16 0x00000040 +#define RBIT_SCR_LPEN 0x00000020 +#define RBIT_SCR_LPCLKDIV 0x0000001f + + +/* + * 68000 interrupt and trap vector numbers + */ +#define M68K_IVEC_BUS_ERROR 2 +#define M68K_IVEC_ADDRESS_ERROR 3 +#define M68K_IVEC_ILLEGAL_OPCODE 4 +#define M68K_IVEC_ZERO_DIVIDE 5 +#define M68K_IVEC_CHK 6 +#define M68K_IVEC_TRAPV 7 +#define M68K_IVEC_PRIVILEGE 8 +#define M68K_IVEC_TRACE 9 +#define M68K_IVEC_LINE_A 10 +#define M68K_IVEC_LINE_F 11 +/* Unassigned, Reserved 12-14 */ +#define M68K_IVEC_UNINITIALIZED_INT 15 +/* Unassigned, Reserved 16-23 */ +#define M68K_IVEC_SPURIOUS_INT 24 + +#define M68K_IVEC_LEVEL1_AUTOVECTOR 25 +#define M68K_IVEC_LEVEL2_AUTOVECTOR 26 +#define M68K_IVEC_LEVEL3_AUTOVECTOR 27 +#define M68K_IVEC_LEVEL4_AUTOVECTOR 28 +#define M68K_IVEC_LEVEL5_AUTOVECTOR 29 +#define M68K_IVEC_LEVEL6_AUTOVECTOR 30 +#define M68K_IVEC_LEVEL7_AUTOVECTOR 31 + +#define M68K_IVEC_TRAP0 32 +#define M68K_IVEC_TRAP1 33 +#define M68K_IVEC_TRAP2 34 +#define M68K_IVEC_TRAP3 35 +#define M68K_IVEC_TRAP4 36 +#define M68K_IVEC_TRAP5 37 +#define M68K_IVEC_TRAP6 38 +#define M68K_IVEC_TRAP7 39 +#define M68K_IVEC_TRAP8 40 +#define M68K_IVEC_TRAP9 41 +#define M68K_IVEC_TRAP10 42 +#define M68K_IVEC_TRAP11 43 +#define M68K_IVEC_TRAP12 44 +#define M68K_IVEC_TRAP13 45 +#define M68K_IVEC_TRAP14 46 +#define M68K_IVEC_TRAP15 47 +/* + * Unassigned, Reserved 48-59 + * + * Note: Vectors 60-63 are used by the MC68302 (e.g. BAR, SCR). + */ + +/* + * MC68302 Interrupt Vectors + * Section 3.2 + */ +enum m68302_ivec_e { + M302_IVEC_ERR =0, + M302_IVEC_PB8 =1, /* General-Purpose Interrupt 0 */ + M302_IVEC_SMC2 =2, + M302_IVEC_SMC1 =3, + M302_IVEC_TIMER3 =4, + M302_IVEC_SCP =5, + M302_IVEC_TIMER2 =6, + M302_IVEC_PB9 =7, /* General-Purpose Interrupt 1 */ + M302_IVEC_SCC3 =8, + M302_IVEC_TIMER1 =9, + M302_IVEC_SCC2 =10, + M302_IVEC_IDMA =11, + M302_IVEC_SDMA =12, /* SDMA Channels Bus Error */ + M302_IVEC_SCC1 =13, + M302_IVEC_PB10 =14, /* General-Purpose Interrupt 2 */ + M302_IVEC_PB11 =15, /* General-Purpose Interrupt 3 */ + M302_IVEC_IRQ1 =17, /* External Device */ + M302_IVEC_IRQ6 =22, /* External Device */ + M302_IVEC_IRQ7 =23 /* External Device */ +}; + + +/* + * GIMR - Global Interrupt Mode Register + * Section 3.2.5.1 + */ +#define RBIT_GIMR_MOD (1<<15) +#define RBIT_GIMR_IV7 (1<<14) +#define RBIT_GIMR_IV6 (1<<13) +#define RBIT_GIMR_IV1 (1<<12) +#define RBIT_GIMR_ET7 (1<<10) +#define RBIT_GIMR_ET6 (1<<9) +#define RBIT_GIMR_ET1 (1<<8) +#define RBIT_GIMR_VECTOR (7<<5) + +/* + * IPR - Interrupt Pending Register (Section 3.2.5.2) + * IMR - Interrupt Mask Register (Section 3.2.5.3) + * ISR - Interrupt In-Service Register (Section 3.2.5.4) + */ +#define RBIT_IPR_PB11 (1<<15) +#define RBIT_IPR_PB10 (1<<14) +#define RBIT_IPR_SCC1 (1<<13) +#define RBIT_IPR_SDMA (1<<12) +#define RBIT_IPR_IDMA (1<<11) +#define RBIT_IPR_SCC2 (1<<10) +#define RBIT_IPR_TIMER1 (1<<9) +#define RBIT_IPR_SCC3 (1<<8) +#define RBIT_IPR_PB9 (1<<7) +#define RBIT_IPR_TIMER2 (1<<6) +#define RBIT_IPR_SCP (1<<5) +#define RBIT_IPR_TIMER3 (1<<4) +#define RBIT_IPR_SMC1 (1<<3) +#define RBIT_IPR_SMC2 (1<<2) +#define RBIT_IPR_PB8 (1<<1) +#define RBIT_IPR_ERR (1<<0) + +#define RBIT_ISR_PB11 (1<<15) +#define RBIT_ISR_PB10 (1<<14) +#define RBIT_ISR_SCC1 (1<<13) +#define RBIT_ISR_SDMA (1<<12) +#define RBIT_ISR_IDMA (1<<11) +#define RBIT_ISR_SCC2 (1<<10) +#define RBIT_ISR_TIMER1 (1<<9) +#define RBIT_ISR_SCC3 (1<<8) +#define RBIT_ISR_PB9 (1<<7) +#define RBIT_ISR_TIMER2 (1<<6) +#define RBIT_ISR_SCP (1<<5) +#define RBIT_ISR_TIMER3 (1<<4) +#define RBIT_ISR_SMC1 (1<<3) +#define RBIT_ISR_SMC2 (1<<2) +#define RBIT_ISR_PB8 (1<<1) + +#define RBIT_IMR_PB11 (1<<15) /* PB11 Interrupt Mask */ +#define RBIT_IMR_PB10 (1<<14) /* PB10 Interrupt Mask */ +#define RBIT_IMR_SCC1 (1<<13) /* SCC1 Interrupt Mask */ +#define RBIT_IMR_SDMA (1<<12) /* SDMA Interrupt Mask */ +#define RBIT_IMR_IDMA (1<<11) /* IDMA Interrupt Mask */ +#define RBIT_IMR_SCC2 (1<<10) /* SCC2 Interrupt Mask */ +#define RBIT_IMR_TIMER1 (1<<9) /* TIMER1 Interrupt Mask */ +#define RBIT_IMR_SCC3 (1<<8) /* SCC3 Interrupt Mask */ +#define RBIT_IMR_PB9 (1<<7) /* PB9 Interrupt Mask */ +#define RBIT_IMR_TIMER2 (1<<6) /* TIMER2 Interrupt Mask */ +#define RBIT_IMR_SCP (1<<5) /* SCP Interrupt Mask */ +#define RBIT_IMR_TIMER3 (1<<4) /* TIMER3 Interrupt Mask */ +#define RBIT_IMR_SMC1 (1<<3) /* SMC1 Interrupt Mask */ +#define RBIT_IMR_SMC2 (1<<2) /* SMC2 Interrupt Mask */ +#define RBIT_IMR_PB8 (1<<1) /* PB8 Interrupt Mask */ + + +/* + * DRAM Refresh + * Section 3.9 + * + * The DRAM refresh memory map replaces the SCC2 Tx BD 6 and Tx BD 7 + * structures in the parameter RAM. + * + * Access to the DRAM registers can be accomplished by + * the following approach: + * + * volatile m302_DRAM_refresh_t *dram; + * dram = (volatile m302_DRAM_refresh_t *) &m302.scc2.bd.tx[6]; + * + * Then simply use pointer references (e.g. dram->count = 3). + */ +typedef struct { + rtems_unsigned16 dram_high; /* DRAM high address and FC */ + rtems_unsigned16 dram_low; /* DRAM low address */ + rtems_unsigned16 increment; /* increment step (bytes/row) */ + rtems_unsigned16 count; /* RAM refresh cycle count (#rows) */ + rtems_unsigned16 t_ptr_h; /* temporary refresh high addr & FC */ + rtems_unsigned16 t_ptr_l; /* temporary refresh low address */ + rtems_unsigned16 t_count; /* temporary refresh cycles count */ + rtems_unsigned16 res; /* reserved */ +} m302_DRAM_refresh_t; + + +/* + * TMR - Timer Mode Register (for timers 1 and 2) + * Section 3.5.2.1 + */ +#define RBIT_TMR_ICLK_STOP (0<<1) +#define RBIT_TMR_ICLK_MASTER (1<<1) +#define RBIT_TMR_ICLK_MASTER16 (2<<1) +#define RBIT_TMR_ICLK_TIN (3<<1) + +#define RBIT_TMR_OM (1<<5) +#define RBIT_TMR_ORI (1<<4) +#define RBIT_TMR_FRR (1<<3) +#define RBIT_TMR_RST (1<<0) + + +/* + * TER - Timer Event Register (for timers 1 and 2) + * Section 3.5.2.5 + */ +#define RBIT_TER_REF (1<<1) /* Output Reference Event */ +#define RBIT_TER_CAP (1<<0) /* Capture Event */ + + +/* + * SCC Buffer Descriptors and Buffer Descriptors Table + * Section 4.5.5 + */ +typedef struct m302_SCC_bd { + rtems_unsigned16 status; /* status and control */ + rtems_unsigned16 length; /* data length */ + rtems_unsigned8 *buffer; /* data buffer pointer */ +} m302_SCC_bd_t; + +typedef struct { + m302_SCC_bd_t rx[8]; /* receive buffer descriptors */ + m302_SCC_bd_t tx[8]; /* transmit buffer descriptors */ +} m302_SCC_bd_table_t; + + +/* + * SCC Parameter RAM (offset 0x080 from an SCC Base) + * Section 4.5.6 + * + * Each SCC parameter RAM area begins at offset 0x80 from each SCC base + * area (0x400, 0x500, or 0x600 from the dual-port RAM base). + * + * Offsets 0x9c-0xbf from each SCC base area compose the protocol-specific + * portion of the SCC parameter RAM. + */ +typedef struct { + rtems_unsigned8 rfcr; /* Rx Function Code */ + rtems_unsigned8 tfcr; /* Tx Function Code */ + rtems_unsigned16 mrblr; /* Maximum Rx Buffer Length */ + rtems_unsigned16 _rstate; /* Rx Internal State */ + rtems_unsigned8 res2; + rtems_unsigned8 rbd; /* Rx Internal Buffer Number */ + rtems_unsigned32 _rdptr; /* Rx Internal Data Pointer */ + rtems_unsigned16 _rcount; /* Rx Internal Byte Count */ + rtems_unsigned16 _rtmp; /* Rx Temp */ + rtems_unsigned16 _tstate; /* Tx Internal State */ + rtems_unsigned8 res7; + rtems_unsigned8 tbd; /* Tx Internal Buffer Number */ + rtems_unsigned32 _tdptr; /* Tx Internal Data Pointer */ + rtems_unsigned16 _tcount; /* Tx Internal Byte Count */ + rtems_unsigned16 _ttmp; /* Tx Temp */ +} m302_SCC_parameters_t; + +/* + * UART-Specific SCC Parameter RAM + * Section 4.5.11.3 + */ +typedef struct { + rtems_unsigned16 max_idl; /* Maximum IDLE Characters (rx) */ + rtems_unsigned16 idlc; /* Temporary rx IDLE counter */ + rtems_unsigned16 brkcr; /* Break Count Register (tx) */ + rtems_unsigned16 parec; /* Receive Parity Error Counter */ + rtems_unsigned16 frmec; /* Receive Framing Error Counter */ + rtems_unsigned16 nosec; /* Receive Noise Counter */ + rtems_unsigned16 brkec; /* Receive Break Condition Counter */ + rtems_unsigned16 uaddr1; /* UART ADDRESS Character 1 */ + rtems_unsigned16 uaddr2; /* UART ADDRESS Character 2 */ + rtems_unsigned16 rccr; /* Receive Control Character Register */ + rtems_unsigned16 character[8]; /* Control Characters 1 through 8*/ +} m302_SCC_UartSpecific_t; +/* + * This definition allows for the checking of receive buffers + * for errors. + */ + +#define RCV_ERR 0x003F + +/* + * UART receive buffer descriptor bit definitions. + * Section 4.5.11.14 + */ +#define RBIT_UART_CTRL (1<<11) /* buffer contains a control char */ +#define RBIT_UART_ADDR (1<<10) /* first byte contains an address */ +#define RBIT_UART_MATCH (1<<9) /* indicates which addr char matched */ +#define RBIT_UART_IDLE (1<<8) /* buffer closed due to IDLE sequence */ +#define RBIT_UART_BR (1<<5) /* break sequence was received */ +#define RBIT_UART_FR (1<<4) /* framing error was received */ +#define RBIT_UART_PR (1<<3) /* parity error was received */ +#define RBIT_UART_OV (1<<1) /* receiver overrun occurred */ +#define RBIT_UART_CD (1<<0) /* carrier detect lost */ +#define RBIT_UART_STATUS 0x003B /* all status bits */ + +/* + * UART transmit buffer descriptor bit definitions. + * Section 4.5.11.15 + */ +#define RBIT_UART_CR (1<<11) /* clear-to-send report + * this results in two idle bits + * between back-to-back frames + */ +#define RBIT_UART_A (1<<10) /* buffer contains address characters + * only valid in multidrop mode (UM0=1) + */ +#define RBIT_UART_PREAMBLE (1<<9) /* send preamble before data */ +#define RBIT_UART_CTS_LOST (1<<0) /* CTS lost */ + +/* + * UART event register + * Section 4.5.11.16 + */ +#define M302_UART_EV_CTS (1<<7) /* CTS status changed */ +#define M302_UART_EV_CD (1<<6) /* carrier detect status changed */ +#define M302_UART_EV_IDL (1<<5) /* IDLE sequence status changed */ +#define M302_UART_EV_BRK (1<<4) /* break character was received */ +#define M302_UART_EV_CCR (1<<3) /* control character received */ +#define M302_UART_EV_TX (1<<1) /* buffer has been transmitted */ +#define M302_UART_EV_RX (1<<0) /* buffer has been received */ + + +/* + * HDLC-Specific SCC Parameter RAM + * Section 4.5.12.3 + * + * c_mask_l should be 0xF0B8 for 16-bit CRC, 0xdebb for 32-bit CRC + * c_mask_h is a don't care for 16-bit CRC, 0x20E2 for 32-bit CRC + */ +typedef struct { + rtems_unsigned16 rcrc_l; /* Temp Receive CRC Low */ + rtems_unsigned16 rcrc_h; /* Temp Receive CRC High */ + rtems_unsigned16 c_mask_l; /* CRC Mask Low */ + rtems_unsigned16 c_mask_h; /* CRC Mask High */ + rtems_unsigned16 tcrc_l; /* Temp Transmit CRC Low */ + rtems_unsigned16 tcrc_h; /* Temp Transmit CRC High */ + + rtems_unsigned16 disfc; /* Discard Frame Counter */ + rtems_unsigned16 crcec; /* CRC Error Counter */ + rtems_unsigned16 abtsc; /* Abort Sequence Counter */ + rtems_unsigned16 nmarc; /* Nonmatching Address Received Cntr */ + rtems_unsigned16 retrc; /* Frame Retransmission Counter */ + + rtems_unsigned16 mflr; /* Maximum Frame Length Register */ + rtems_unsigned16 max_cnt; /* Maximum_Length Counter */ + + rtems_unsigned16 hmask; /* User Defined Frame Address Mask */ + rtems_unsigned16 haddr1; /* User Defined Frame Address */ + rtems_unsigned16 haddr2; /* " */ + rtems_unsigned16 haddr3; /* " */ + rtems_unsigned16 haddr4; /* " */ +} m302_SCC_HdlcSpecific_t; +/* + * HDLC receiver buffer descriptor bit definitions + * Section 4.5.12.10 + */ +#define RBIT_HDLC_EMPTY_BIT 0x8000 /* buffer associated with BD is empty */ +#define RBIT_HDLC_LAST_BIT 0x0800 /* buffer is last in a frame */ +#define RBIT_HDLC_FIRST_BIT 0x0400 /* buffer is first in a frame */ +#define RBIT_HDLC_FRAME_LEN 0x0020 /* receiver frame length violation */ +#define RBIT_HDLC_NONOCT_Rx 0x0010 /* received non-octet aligned frame */ +#define RBIT_HDLC_ABORT_SEQ 0x0008 /* received abort sequence */ +#define RBIT_HDLC_CRC_ERROR 0x0004 /* frame contains a CRC error */ +#define RBIT_HDLC_OVERRUN 0x0002 /* receiver overrun occurred */ +#define RBIT_HDLC_CD_LOST 0x0001 /* carrier detect lost */ + +/* + * HDLC transmit buffer descriptor bit definitions + * Section 4.5.12.11 + */ +#define RBIT_HDLC_READY_BIT 0x8000 /* buffer is ready to transmit */ +#define RBIT_HDLC_EXT_BUFFER 0x4000 /* buffer is in external memory */ +#define RBIT_HDLC_WRAP_BIT 0x2000 /* last buffer in bd table, so wrap */ +#define RBIT_HDLC_WAKE_UP 0x1000 /* interrupt when buffer serviced */ +#define RBIT_HDLC_LAST_BIT 0x0800 /* buffer is last in the frame */ +#define RBIT_HDLC_TxCRC_BIT 0x0400 /* transmit a CRC sequence */ +#define RBIT_HDLC_UNDERRUN 0x0002 /* transmitter underrun */ +#define RBIT_HDLC_CTS_LOST 0x0001 /* CTS lost */ + +/* + * HDLC event register bit definitions + * Section 4.5.12.12 + */ +#define RBIT_HDLC_CTS 0x80 /* CTS status changed */ +#define RBIT_HDLC_CD 0x40 /* carrier detect status changed */ +#define RBIT_HDLC_IDL 0x20 /* IDLE sequence status changed */ +#define RBIT_HDLC_TXE 0x10 /* transmit error */ +#define RBIT_HDLC_RXF 0x08 /* received frame */ +#define RBIT_HDLC_BSY 0x04 /* frame rcvd and discarded due to + * lack of buffers + */ +#define RBIT_HDLC_TXB 0x02 /* buffer has been transmitted */ +#define RBIT_HDLC_RXB 0x01 /* received buffer */ + + + +typedef struct { + m302_SCC_bd_table_t bd; /* +000 Buffer Descriptor Table */ + m302_SCC_parameters_t parm; /* +080 Common Parameter RAM */ + union { /* +09C Protocol-Specific Parm RAM */ + m302_SCC_UartSpecific_t uart; + m302_SCC_HdlcSpecific_t hdlc; + } prot; + rtems_unsigned8 res[0x040]; /* +0C0 reserved, (not implemented) */ +} m302_SCC_t; + + +/* + * Common SCC Registers + */ +typedef struct { + rtems_unsigned16 res1; + rtems_unsigned16 scon; /* SCC Configuration Register 4.5.2 */ + rtems_unsigned16 scm; /* SCC Mode Register 4.5.3 */ + rtems_unsigned16 dsr; /* SCC Data Synchronization Register 4.5.4 */ + rtems_unsigned8 scce; /* SCC Event Register 4.5.8.1 */ + rtems_unsigned8 res2; + rtems_unsigned8 sccm; /* SCC Mask Register 4.5.8.2 */ + rtems_unsigned8 res3; + rtems_unsigned8 sccs; /* SCC Status Register 4.5.8.3 */ + rtems_unsigned8 res4; + rtems_unsigned16 res5; +} m302_SCC_Registers_t; + +/* + * SCON - SCC Configuration Register + * Section 4.5.2 + */ +#define RBIT_SCON_WOMS (1<<15) /* Wired-OR Mode Select (NMSI mode only) + * When set, the TXD driver is an + * open-drain output */ +#define RBIT_SCON_EXTC (1<<14) /* External Clock Source */ +#define RBIT_SCON_TCS (1<<13) /* Transmit Clock Source */ +#define RBIT_SCON_RCS (1<<12) /* Receive Clock Source */ + +/* + * SCM - SCC Mode Register bit definitions + * Section 4.5.3 + * The parameter-specific mode bits occupy bits 15 through 6. + */ +#define RBIT_SCM_ENR (1<<3) /* Enable receiver */ +#define RBIT_SCM_ENT (1<<2) /* Enable transmitter */ + + +/* + * Internal MC68302 Registers + * starts at offset 0x800 from dual-port RAM base + * Section 2.8 + */ +typedef struct { + /* offset +800 */ + rtems_unsigned16 res0; + rtems_unsigned16 cmr; /* IDMA Channel Mode Register */ + rtems_unsigned32 sapr; /* IDMA Source Address Pointer */ + rtems_unsigned32 dapr; /* IDMA Destination Address Pointer */ + rtems_unsigned16 bcr; /* IDMA Byte Count Register */ + rtems_unsigned8 csr; /* IDMA Channel Status Register */ + rtems_unsigned8 res1; + rtems_unsigned8 fcr; /* IDMA Function Code Register */ + rtems_unsigned8 res2; + + /* offset +812 */ + rtems_unsigned16 gimr; /* Global Interrupt Mode Register */ + rtems_unsigned16 ipr; /* Interrupt Pending Register */ + rtems_unsigned16 imr; /* Interrupt Mask Register */ + rtems_unsigned16 isr; /* Interrupt In-Service Register */ + rtems_unsigned16 res3; + rtems_unsigned16 res4; + + /* offset +81e */ + rtems_unsigned16 pacnt; /* Port A Control Register */ + rtems_unsigned16 paddr; /* Port A Data Direction Register */ + rtems_unsigned16 padat; /* Port A Data Register */ + rtems_unsigned16 pbcnt; /* Port B Control Register */ + rtems_unsigned16 pbddr; /* Port B Data Direction Register */ + rtems_unsigned16 pbdat; /* Port B Data Register */ + rtems_unsigned16 res5; + + /* offset +82c */ + rtems_unsigned16 res6; + rtems_unsigned16 res7; + rtems_unsigned16 br0; /* Base Register (CS0) */ + rtems_unsigned16 or0; /* Option Register (CS0) */ + rtems_unsigned16 br1; /* Base Register (CS1) */ + rtems_unsigned16 or1; /* Option Register (CS1) */ + rtems_unsigned16 br2; /* Base Register (CS2) */ + rtems_unsigned16 or2; /* Option Register (CS2) */ + rtems_unsigned16 br3; /* Base Register (CS3) */ + rtems_unsigned16 or3; /* Option Register (CS3) */ + + /* offset +840 */ + rtems_unsigned16 tmr1; /* Timer Unit 1 Mode Register */ + rtems_unsigned16 trr1; /* Timer Unit 1 Reference Register */ + rtems_unsigned16 tcr1; /* Timer Unit 1 Capture Register */ + rtems_unsigned16 tcn1; /* Timer Unit 1 Counter */ + rtems_unsigned8 res8; + rtems_unsigned8 ter1; /* Timer Unit 1 Event Register */ + rtems_unsigned16 wrr; /* Watchdog Reference Register */ + rtems_unsigned16 wcn; /* Watchdog Counter */ + rtems_unsigned16 res9; + rtems_unsigned16 tmr2; /* Timer Unit 2 Mode Register */ + rtems_unsigned16 trr2; /* Timer Unit 2 Reference Register */ + rtems_unsigned16 tcr2; /* Timer Unit 2 Capture Register */ + rtems_unsigned16 tcn2; /* Timer Unit 2 Counter */ + rtems_unsigned8 resa; + rtems_unsigned8 ter2; /* Timer Unit 2 Event Register */ + rtems_unsigned16 resb; + rtems_unsigned16 resc; + rtems_unsigned16 resd; + + /* offset +860 */ + rtems_unsigned8 cr; /* Command Register */ + rtems_unsigned8 rese[0x1f]; + + /* offset +880, +890, +8a0 */ + m302_SCC_Registers_t scc[3]; /* SCC1, SCC2, SCC3 Registers */ + + /* offset +8b0 */ + rtems_unsigned16 spmode; /* SCP,SMC Mode and Clock Cntrl Reg */ + rtems_unsigned16 simask; /* Serial Interface Mask Register */ + rtems_unsigned16 simode; /* Serial Interface Mode Register */ +} m302_internalReg_t ; + + +/* + * MC68302 dual-port RAM structure. + * (Includes System RAM, Parameter RAM, and Internal Registers). + * Section 2.8 + */ +typedef struct { + rtems_unsigned8 mem[0x240]; /* +000 User Data Memory */ + rtems_unsigned8 res1[0x1c0]; /* +240 reserved, (not implemented) */ + m302_SCC_t scc1; /* +400 SCC1 */ + m302_SCC_t scc2; /* +500 SCC2 */ + m302_SCC_t scc3; /* +600 SCC3 */ + rtems_unsigned8 res2[0x100]; /* +700 reserved, (not implemented) */ + m302_internalReg_t reg; /* +800 68302 Internal Registers */ +} m302_dualPortRAM_t; + + +/* + * Declare the variable that's used to reference the variables in + * the dual-port RAM. + */ +extern volatile m302_dualPortRAM_t m302; + +#endif +/* end of include file */ diff --git a/c/src/lib/libbsp/m68k/gen68302/README b/c/src/lib/libbsp/m68k/gen68302/README new file mode 100644 index 0000000000..0261083479 --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68302/README @@ -0,0 +1,154 @@ +# +# $Id$ +# + +BSP NAME: gen68302 +BOARD: proprietary (see below for relevant information) +BUS: none +CPU FAMILY: MC68000 +COPROCESSORS: 68302 communications co-processor +MODE: not applicable + +DEBUG MONITOR: none + +PERIPHERALS +=========== +TIMERS: two 68302 timers, one 68302 watchdog timer + RESOLUTION: ? +SERIAL PORTS: three 68302 SCCs +REAL-TIME CLOCK: +DMA: built-in 68302, not used +VIDEO: none +SCSI: none +NETWORKING: none + +DRIVER INFORMATION +================== +CLOCK DRIVER: 68302 (TIMER1) +IOSUPP DRIVER: 68302 SCC2 +SHMSUPP: none +TIMER DRIVER: 68302 TIMER2 + +STDIO +===== +PORT: ? +ELECTRICAL: EIA-232 +BAUD: 9600 +BITS PER CHARACTER: 8 +PARITY: None +STOP BITS: 1 + +NOTES +===== + +Board description +----------------- +clock rate: 16 MHz +bus width: 16 bits +ROM: 128 kbyte (flash, 0 wait states, chip select 0) +RAM: 256 kbyte (static, 0 wait states, chip select 1) + +The 68302's built-in DRAM refresh controller circuitry is neither used +nor configured at startup. + +Host System +----------- +HP 9000/715, HP-UX 9.05 +gcc-2.6.3 +binutils-2.5.2 + + +Verification +------------ +The 1-ms clock ISR rate was verified with an in-circuit emulator. + +Single processor tests: +Multi-processort tests: not applicable +Timing tests: see results in c/src/tests/tmtests/times + +Note: The board has 256 kbyte RAM, so the timing tests would not run +with the standard executive RAM size configuration of 256 K. +Modifying the conftbl.h files to specify 160 kbyte for workspace +seemed to work. + +* Porting + +** Mod c/src/tests/tmtests/*/conftbl.h + +Modified to use 160 kbyte for executive RAM size. + +** Add c/make/custom/gen68302.cfg + +Based on m68k_no_bsp.cfg. Turned off multiprocessor support. Had to +use a BSP-specific compiler configuration file in order to link the +proper startup file. + +** Mod c/make/compilers/gcc-m68000.cfg + +Added "-m68000" to the AS macro so that non-68000 instructions are +neither generated nor allowed (remember that the GNU assembler +supports pseudo-assembler instructions (e.g. jbsr) that will be +"intelligently" assembled.) Added "m68000/" before libgcc.a so that +non-68000 instructions aren't included. + +** Add c/make/compilers/gcc-gen68302.cfg + +Based on modified gcc-m68000.cfg. + +Changed make-exe define to produce IEEE-695 output files for loading +into the emulator. + +The board has no debug monitor, so I had to create a 68302-specific +startup file (c/src/lib/libbsp/m68k/gen68302/start302/start302.s) to +override the c/src/lib/start/m68k/start.s. START_FILE entry was +modified to causes start302.s to be linked first (in lieu of start.s). + +** Mod c/src/exec/cpu/m68k/cpu.h + +Turned off software and hardware interrupt stack support. Added +support in _CPU_Bitfield_Find_first_bit() and +_CPU_Priority_Bits_index() to replace the bfffo instruction. + +TODO: add software-maintained interrupt stack. + +TODO: optimize things so that subtracting _priority from 15 isn't +required in _CPU_Priority_Bits_index(). + +** Mod c/src/exec/cpu/m68k/cpu.c + +Added the log base 2 table (__log2table) that's required by the BFFFO +replacement in cpu.h. + +** Mod c/src/exec/cpu/m68k/cpu_asm.s + +Added _ISR_Exit that's currently used in TBD.... Added ifdef wrapper +around ISR exit code that accessed the format nibble. Added some code +to restore the status register and call _Thread_Dispatch. + +TODO: add software-maintained interrupt stack. + +** Mod c/src/exec/cpu/m68k/m68k.h + +Changed "typedef char signed8" to "typedef signed char signed8". + +** Add c/src/lib/libbsp/m68k/gen68302/... +*** clock/ + +TODO: Add set_vector support. Figure out what to do with Clock_exit(). +TODO: Pre-compute (BSP_Configuration.microseconds_per_tick/1000) so that +it doesn't have to be re-computed on each Clock_isr(). + +*** console/ + +These files assume SCC2, but it shouldn't be too difficult to re-write +these to use any of the other SCCs. + +*** include/ +*** start302/ + +This contains the start302.s file that does some fairly tricky memory +re-mapping so that RAM ends up at 0 and ROM ends up at 0xc00000. + +*** startup/ +*** timer/ +*** wrapup/ diff --git a/c/src/lib/libbsp/m68k/gen68302/clock/ckinit.c b/c/src/lib/libbsp/m68k/gen68302/clock/ckinit.c new file mode 100644 index 0000000000..be3cf6ab21 --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68302/clock/ckinit.c @@ -0,0 +1,94 @@ +/* Clock_init() + * + * This routine initializes Timer 1 for an MC68302. + * The tick frequency is 1 millisecond. + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $Id$ + */ + +#include <stdlib.h> /* for atexit() */ + +#include <rtems.h> +#include <bsp.h> +#include <clockdrv.h> +#include "m68302.h" + + +#define TMR1_VAL ( RBIT_TMR_RST /* software reset the timer */\ + | RBIT_TMR_ICLK_MASTER16 /* master clock divided by 16 */\ + | RBIT_TMR_FRR /* restart timer after ref reached */\ + | RBIT_TMR_ORI) /* enable interrupt when ref reached */ +#define TRR1_VAL 1000 /* 1000 ticks @ 16MHz/16 + * = 1 millisecond tick. + */ + +/* + * Clock_driver_ticks is a monotonically increasing counter of the + * number of clock ticks since the driver was initialized. + */ +volatile rtems_unsigned32 Clock_driver_ticks; + +/* + * Clock_isrs is the number of clock ISRs until the next invocation of + * the RTEMS clock tick routine. The clock tick device driver + * gets an interrupt once a millisecond and counts down until the + * length of time between the user configured microseconds per tick + * has passed. + */ +rtems_unsigned32 Clock_isrs; + + +rtems_device_driver Clock_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *pargp, + rtems_id tid, + rtems_unsigned32 *rval +) +{ + Install_clock( Clock_isr ); +} + + +void Install_clock( + rtems_isr_entry clock_isr +) +{ + + Clock_driver_ticks = 0; + Clock_isrs = BSP_Configuration.microseconds_per_tick / 1000; + + if ( BSP_Configuration.ticks_per_timeslice ) { +/* set_vector( clock_isr, 137, 1 );*/ + + m302.reg.trr1 = TRR1_VAL; /* set timer reference register */ + m302.reg.tmr1 = TMR1_VAL; /* set timer mode register & enable */ + /* + * Enable TIMER1 interrupts only. + */ + m302.reg.imr = RBIT_IMR_TIMER1; /* set 68302 int-mask to allow ints */ + + atexit( Clock_exit ); + } +} + + +void Clock_exit( void ) +{ + if ( BSP_Configuration.ticks_per_timeslice ) { + /* TODO: figure out what to do here */ + /* do not restore old vector */ + } +} diff --git a/c/src/lib/libbsp/m68k/gen68302/console/console.c b/c/src/lib/libbsp/m68k/gen68302/console/console.c new file mode 100644 index 0000000000..7f488c5cfd --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68302/console/console.c @@ -0,0 +1,241 @@ +/* + * Initialize the MC68302 SCC2 for console IO board support package. + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $Id$ + */ + +#define GEN68302_INIT + +#include <rtems.h> +#include "console.h" +#include <bsp.h> + +#include "m68302.h" + +/* console_initialize + * + * This routine initializes the console IO driver. + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * Return values: + */ + +rtems_device_driver console_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg, + rtems_id self, + rtems_unsigned32 *status +) +{ + volatile m302_dualPortRAM_t *p = &m302; + + p->reg.pacnt |= 0x0003; /* enable RXD2 and TXD2 signals */ + /* + * TODO: Check assembly code. I think gcc's volatile semantics force + * this to not use a CLR. + */ + p->reg.simode = 0; /* NMSI mode */ + + p->reg.scc[1].scon = 0x00d8; /* 9600 baud */ + p->reg.scc[1].scm = 0x01b1; + + p->scc2.parm.rfcr = 0x50; /* Rx buffers in supervisor data */ + p->scc2.parm.tfcr = 0x50; /* Tx buffers in supervisor data */ + p->scc2.parm.mrblr = 0x0001; /* Max Rx buffer length is 1 byte */ + + p->scc2.prot.uart.max_idl = 0x0000; /* 0 = maximum timeout value */ + p->scc2.prot.uart.brkcr = 0x0001; /* send 1 break char on STOP TX cmd */ + p->scc2.prot.uart.parec = 0x0000; /* reset parity error counter */ + p->scc2.prot.uart.frmec = 0x0000; /* reset framing error counter */ + p->scc2.prot.uart.nosec = 0x0000; /* reset noise error counter */ + p->scc2.prot.uart.brkec = 0x0000; /* reset break condition counter */ + + p->scc2.prot.uart.character[0] = 0x0003; /* use <ctrl>c as control char */ + p->scc2.prot.uart.character[1] = 0x8000; /* set end of cntrl char table */ + + p->scc2.bd.rx[0].status = 0xA000; /* RxBD0 empty, wrap, no intr */ + p->scc2.bd.rx[0].length = 0x0000; + p->scc2.bd.rx[0].buffer = + (rtems_unsigned8 *) &m302.scc2.bd.rx[1]; /* RxBD1 is Rx buffer */ + + p->reg.scc[1].dsr = 0x7000; /* set full-length last stop bit */ + + p->scc2.bd.tx[0].status = 0x3000; /* TxBD0 not ready, wrap, intr */ + p->scc2.bd.tx[0].length = 0x0001; + p->scc2.bd.tx[0].buffer = + (rtems_unsigned8 *) &m302.scc2.bd.tx[1]; /* TxBD1 is Tx buffer */ + + p->reg.scc[1].scce = 0xFF; /* clear all SCC event flags */ + p->reg.scc[1].sccm = 0x03; /* enable only Tx & Rx interrupts */ + p->reg.scc[1].scm = 0x01BD; + + *status = RTEMS_SUCCESSFUL; +} + + +/* is_character_ready + * + * Check to see if a character is available on the MC68302's SCC2. If so, + * then return a TRUE (along with the character). Otherwise return FALSE. + * + * Input parameters: pointer to location in which to return character + * + * Output parameters: character (if available) + * + * Return values: TRUE - character available + * FALSE - no character available + */ + +rtems_boolean is_character_ready( + char *ch /* -> character */ +) +{ +#define RXS (m302.scc2.bd.rx[0].status) +#define RXD (* ((volatile char *) m302.scc2.bd.rx[0].buffer)) + + for (;;) { + if (RXS & RBIT_HDLC_EMPTY_BIT) + return FALSE; + + *ch = RXD; + RXS = RBIT_HDLC_EMPTY_BIT | RBIT_HDLC_WRAP_BIT; + if ( *ch >= ' ' && *ch <= '~' ) + return TRUE; + } +} + + +/* inbyte + * + * Receive a character from the MC68302's SCC2. + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * Return values: character read + */ + +char inbyte( void ) +{ + char ch; + +#define RXS (m302.scc2.bd.rx[0].status) +#define RXD (* ((volatile char *) m302.scc2.bd.rx[0].buffer)) + + do { + while (RXS & RBIT_HDLC_EMPTY_BIT) + /* Wait until character received */ ; + + ch = RXD; + RXS = RBIT_HDLC_EMPTY_BIT | RBIT_HDLC_WRAP_BIT; + + if (ch == '\r' || ch == '\n') + break; + } while (ch < ' ' || ch > '~'); + + return ch; +} + + +/* outbyte + * + * Transmit a character out on the MC68302's SCC2. + * It may support XON/XOFF flow control. + * + * Input parameters: + * ch - character to be transmitted + * + * Output parameters: NONE + */ + +void outbyte( + char ch +) +{ +#define TXS (m302.scc2.bd.tx[0].status) +#define TXD (* ((volatile char *) m302.scc2.bd.tx[0].buffer)) + +#define RXS (m302.scc2.bd.rx[0].status) +#define RXD (* ((volatile char *) m302.scc2.bd.rx[0].buffer)) + + while (TXS & RBIT_HDLC_READY_BIT) + /* Wait until okay to transmit */ ; + + /* + * Check for flow control requests and process. + */ + while ( ! (RXS & RBIT_HDLC_EMPTY_BIT)) { + if (RXD == XOFF) + do { + RXS = RBIT_HDLC_EMPTY_BIT | RBIT_HDLC_WRAP_BIT; + while (RXS & RBIT_HDLC_EMPTY_BIT) + /* Wait until character received */ ; + } while (RXD != XON); + RXS = RBIT_HDLC_EMPTY_BIT | RBIT_HDLC_WRAP_BIT; + } + + TXD = ch; + TXS = RBIT_HDLC_READY_BIT | RBIT_HDLC_WRAP_BIT; + if (ch == '\n') + outbyte('\r'); +} + +/* + * __read -- read bytes from the serial port. Ignore fd, since + * we only have stdin. + */ + +int __read( + int fd, + char *buf, + int nbytes +) +{ + int i = 0; + + for (i = 0; i < nbytes; i++) { + *(buf + i) = inbyte(); + if ((*(buf + i) == '\n') || (*(buf + i) == '\r')) { + (*(buf + i++)) = '\n'; + (*(buf + i)) = 0; + break; + } + } + return (i); +} + +/* + * __write -- write bytes to the serial port. Ignore fd, since + * stdout and stderr are the same. Since we have no filesystem, + * open will only return an error. + */ + +int __write( + int fd, + char *buf, + int nbytes +) +{ + int i; + + for (i = 0; i < nbytes; i++) { + if (*(buf + i) == '\n') { + outbyte ('\r'); + } + outbyte (*(buf + i)); + } + return (nbytes); +} diff --git a/c/src/lib/libbsp/m68k/gen68302/include/bsp.h b/c/src/lib/libbsp/m68k/gen68302/include/bsp.h new file mode 100644 index 0000000000..04745e01d6 --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68302/include/bsp.h @@ -0,0 +1,105 @@ +/* bsp.h + * + * This include file contains all board IO definitions. + * + * XXX : put yours in here + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $Id$ + */ + +#ifndef __GEN68302_BSP_h +#define __GEN68302_BSP_h + +#ifdef __cplusplus +extern "C" { +#endif + +#include <rtems.h> +#include <iosupp.h> + +/* + * Define the time limits for RTEMS Test Suite test durations. + * Long test and short test duration limits are provided. These + * values are in seconds and need to be converted to ticks for the + * application. + * + */ + +#define MAX_LONG_TEST_DURATION 300 /* 5 minutes = 300 seconds */ +#define MAX_SHORT_TEST_DURATION 3 /* 3 seconds */ + +/* + * Stuff for Time Test 27 + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) set_vector( (handler), 0, 1 ) + +#define Cause_tm27_intr() + +#define Clear_tm27_intr() + +#define Lower_tm27_intr() + +/* + * Simple spin delay in microsecond units for device drivers. + * This is very dependent on the clock speed of the target. + */ + +#define delay( microseconds ) \ + { register rtems_unsigned32 _delay=(microseconds); \ + register rtems_unsigned32 _tmp=123; \ + asm volatile( "0: \ + nbcd %0 ; \ + nbcd %0 ; \ + dbf %1,0b" \ + : "=d" (_tmp), "=d" (_delay) \ + : "0" (_tmp), "1" (_delay) ); \ + } + +/* Constants */ + +#define RAM_START 0 +#define RAM_END 0x040000 + +/* Structures */ + +#ifdef GEN68302_INIT +#undef EXTERN +#define EXTERN +#else +#undef EXTERN +#define EXTERN extern +#endif + +/* miscellaneous stuff assumed to exist */ + +extern rtems_configuration_table BSP_Configuration; + +extern m68k_isr_entry M68Kvec[]; /* vector table address */ + +/* functions */ + +void bsp_cleanup( void ); + +m68k_isr_entry set_vector( + rtems_isr_entry handler, + rtems_vector_number vector, + int type +); + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ diff --git a/c/src/lib/libbsp/m68k/gen68302/include/coverhd.h b/c/src/lib/libbsp/m68k/gen68302/include/coverhd.h new file mode 100644 index 0000000000..e41c72bf33 --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68302/include/coverhd.h @@ -0,0 +1,115 @@ +/* coverhd.h + * + * This include file has defines to represent the overhead associated + * with calling a particular directive from C. These are used in the + * Timing Test Suite to ignore the overhead required to pass arguments + * to directives. On some CPUs and/or target boards, this overhead + * is significant and makes it difficult to distinguish internal + * RTEMS execution time from that used to call the directive. + * This file should be updated after running the C overhead timing + * test. Once this update has been performed, the RTEMS Time Test + * Suite should be rebuilt to account for these overhead times in the + * timing results. + * + * NOTE: If these are all zero, then the times reported include all + * all calling overhead including passing of arguments. + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $Id$ + */ + +#ifndef __COVERHD_h +#define __COVERHD_h + +#ifdef __cplusplus +extern "C" { +#endif + +#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 14 +#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 11 +#define CALLING_OVERHEAD_TASK_CREATE 22 +#define CALLING_OVERHEAD_TASK_IDENT 17 +#define CALLING_OVERHEAD_TASK_START 18 +#define CALLING_OVERHEAD_TASK_RESTART 15 +#define CALLING_OVERHEAD_TASK_DELETE 12 +#define CALLING_OVERHEAD_TASK_SUSPEND 12 +#define CALLING_OVERHEAD_TASK_RESUME 12 +#define CALLING_OVERHEAD_TASK_SET_PRIORITY 16 +#define CALLING_OVERHEAD_TASK_MODE 15 +#define CALLING_OVERHEAD_TASK_GET_NOTE 16 +#define CALLING_OVERHEAD_TASK_SET_NOTE 16 +#define CALLING_OVERHEAD_TASK_WAKE_WHEN 31 +#define CALLING_OVERHEAD_TASK_WAKE_AFTER 11 +#define CALLING_OVERHEAD_INTERRUPT_CATCH 17 +#define CALLING_OVERHEAD_CLOCK_GET 32 +#define CALLING_OVERHEAD_CLOCK_SET 31 +#define CALLING_OVERHEAD_CLOCK_TICK 8 + +#define CALLING_OVERHEAD_TIMER_CREATE 13 +#define CALLING_OVERHEAD_TIMER_IDENT 12 +#define CALLING_OVERHEAD_TIMER_DELETE 14 +#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 19 +#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 39 +#define CALLING_OVERHEAD_TIMER_RESET 12 +#define CALLING_OVERHEAD_TIMER_CANCEL 12 +#define CALLING_OVERHEAD_SEMAPHORE_CREATE 18 +#define CALLING_OVERHEAD_SEMAPHORE_IDENT 12 +#define CALLING_OVERHEAD_SEMAPHORE_DELETE 17 +#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 17 +#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 12 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 18 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 17 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 12 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 14 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 14 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 17 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 19 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 14 + +#define CALLING_OVERHEAD_EVENT_SEND 15 +#define CALLING_OVERHEAD_EVENT_RECEIVE 18 +#define CALLING_OVERHEAD_SIGNAL_CATCH 14 +#define CALLING_OVERHEAD_SIGNAL_SEND 14 +#define CALLING_OVERHEAD_PARTITION_CREATE 23 +#define CALLING_OVERHEAD_PARTITION_IDENT 17 +#define CALLING_OVERHEAD_PARTITION_DELETE 12 +#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 15 +#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 15 +#define CALLING_OVERHEAD_REGION_CREATE 23 +#define CALLING_OVERHEAD_REGION_IDENT 14 +#define CALLING_OVERHEAD_REGION_DELETE 12 +#define CALLING_OVERHEAD_REGION_GET_SEGMENT 21 +#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 15 +#define CALLING_OVERHEAD_PORT_CREATE 20 +#define CALLING_OVERHEAD_PORT_IDENT 14 +#define CALLING_OVERHEAD_PORT_DELETE 12 +#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 18 +#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 18 + +#define CALLING_OVERHEAD_IO_INITIALIZE 18 +#define CALLING_OVERHEAD_IO_OPEN 18 +#define CALLING_OVERHEAD_IO_CLOSE 18 +#define CALLING_OVERHEAD_IO_READ 18 +#define CALLING_OVERHEAD_IO_WRITE 18 +#define CALLING_OVERHEAD_IO_CONTROL 18 +#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 11 +#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 13 +#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 14 +#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 12 +#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 12 +#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 14 +#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 8 + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ diff --git a/c/src/lib/libbsp/m68k/gen68302/start/start302.s b/c/src/lib/libbsp/m68k/gen68302/start/start302.s new file mode 100644 index 0000000000..2682066e84 --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68302/start/start302.s @@ -0,0 +1,273 @@ +/* entry.s + * + * This file contains the entry point for the application. + * The name of this entry point is compiler dependent. + * It jumps to the BSP which is responsible for performing + * all initialization. + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $Id$ + */ + +#include "asm.h" + + .set BAR, 0xF2 | Base Address Register location + .set SCR, 0xF4 | System Control Register location + .set BAR_VAL, 0x0f7f | BAR value + .set SCR_VAL, 0x00080f00 | SCR value + .set GIMR_VAL, 0x8780 |Global Interrupt Mode Register. (MUST BE WRITTEN). + .set BaseAddr,(BAR_VAL&0x0fff)<<12 | MC68302 internal base address + + .set oSYSRAM, 0x000 | 576 bytes of internal system RAM + + .set oGIMR, 0x812 + + .set oCS0_Base, 0x830 | 16 bits, Chip Sel 0 Base Reg + .set oCS0_Option, 0x832 | 16 bits, Chip Sel 0 Option Reg + .set oCS1_Base, 0x834 | 16 bits, Chip Sel 1 Base Reg + .set oCS1_Option, 0x836 | 16 bits, Chip Sel 1 Option Reg + .set oCS2_Base, 0x838 | 16 bits, Chip Sel 2 Base Reg + .set oCS2_Option, 0x83a | 16 bits, Chip Sel 2 Option Reg + .set oCS3_Base, 0x83c | 16 bits, Chip Sel 3 Base Reg + .set oCS3_Option, 0x83e | 16 bits, Chip Sel 3 Option Reg + + .set tmpSRAM_BASE, 0x400000 | start of temporary SRAM + .set FLASH_BASE, 0xc00000 | start of FLASH''s normal location + + +BEGIN_CODE + PUBLIC (M68Kvec) | Vector Table +SYM (M68Kvec): | standard location for vectors +V___ISSP: .long 0x00001000 |00 0 Reset: Initial SSP +V____IPC: .long SYM(start)-V___ISSP |04 1 Reset: Initial PC +V_BUSERR: .long Bad-V___ISSP |08 2 Bus Error +V_ADRERR: .long Bad-V___ISSP |0c 3 Address Error + .space 240 | reserve space for reset of vectors + +#if ( M68K_HAS_SEPARATE_STACKS == 1 ) +SYM (lowintstack): + .space 4092 | reserve for interrupt stack +SYM (hiintstack): + .space 4 | end of interrupt stack +#endif + + PUBLIC (start) | Default entry point for GNU +SYM (start): + move.w #0x2700,sr | Disable all interrupts + move.w #BAR_VAL,BAR | Set Base Address Register + move.l #SCR_VAL,SCR | Set System Control Register + lea BaseAddr,a5 + move.w #GIMR_VAL,a5@(oGIMR) | Set Global Interrupt Mode Register + +| +| Set up chip select registers for the remapping process. +| + +| +| 0 X x x x x +| 0 000 0 0-- - --- ---- ---- ---- +| x xxx x xxx x xx +| + move.w #0xc001,a5@(oCS0_Base) | Expand CS0 to full size (FLASH) + move.w #0x1f82,a5@(oCS0_Option) | 000000-03ffff, R, 0 WS + +| +| X x x x x x +| 0 100 0 0-- - --- ---- ---- ---- +| x xxx x xxx x xx +| + move.w #0xa801,a5@(oCS1_Base) | Set up and enable CS1 (SRAM) + move.w #0x1f80,a5@(oCS1_Option) | 400000-43ffff, RW, 0 WS + +| +| Copy the initial boot FLASH area to the temporary SRAM location. +| + moveq #0,d0 + movea.l d0,a0 | a0 -> start of FLASH + lea tmpSRAM_BASE,a1 | a1 -> start of tmp SRAM +| moveq #(endPreBoot-V___ISSP)/4,d0 | # longs to copy + moveq #127,d0 +cpy_flash: move.l (a0)+,(a1)+ | copy + subq.l #1,d0 + bne cpy_flash + +| +| Copy remap code to 68302''s internal system RAM. +| + movea.w #begRemap-V___ISSP,a0 | a0 -> remap code + lea a5@(oSYSRAM),a1 | a1 -> internal system RAM +| moveq #(endRemap-begRemap)/2-1,d0 | d0 = # words to copy + moveq #11,d0 +cpy_remap: move.w (a0)+,(a1)+ | copy + dbra d0,cpy_remap + +| +| Jump to the remap code in the 68302''s internal system RAM. +| + jmp a5@(oSYSRAM) | (effectively a jmp begRemap) + +| +| This remap code, when executed from the 68302''s internal system RAM +| will 1) remap CS1 so that SRAM is at 0 +| 2) remap CS0 so that FLASH is at FLASH_BASE +| and 3) jump to executable code in the remapped FLASH. +| +begRemap: move.w #0xa001,a5@(oCS1_Base) | Move CS1 (SRAM) + move.w #0xd801,a5@(oCS0_Base) | Move CS0 (FLASH) + lea FLASH_BASE,a0 + jmp a0@(endRemap-V___ISSP.w) | Jump back to FLASH +endRemap: +| +| Now set up the remaining chip select registers. +| + +| +| 4 0 x x x x +| 1 000 1 111 0 000 0--- ---- ---- +| x xxx x xxx x xx +| + move.w #0xb1e1,a5@(oCS2_Base) | Set up and enable CS2 (dpRAM) + move.w #0x1ff0,a5@(oCS2_Option) | 8f0000-8f07ff, RW, 0 WS + +| +| 8 X x x x x +| 1 000 0 0-- - --- ---- ---- ---- +| x xxx x xxx x xx +| + move.w #0xd001,a5@(oCS3_Base) | Set up and enable CS3 (IO) + move.w #0x1f80,a5@(oCS3_Option) | 800000-83ffff, RW, 0 WS + +endPreBoot: + + move.b #0x30,0x800001 | set status LED amber + + .set oPIOB_Ctrl, 0x824 + .set oPIOB_DDR, 0x826 + .set oPIOB_Data, 0x828 + + .set oPIOA_Ctrl, 0x81e + .set oPIOA_DDR, 0x820 + .set oPIOA_Data, 0x822 + + move.w #0x0ff8,a5@(oPIOB_Data) | Make output follow resistors. + move.w #0x00ff,a5@(oPIOB_DDR) | Set up PB7-PB0 for output. + move.w #0x0080,a5@(oPIOB_Ctrl) | Set up WDOG* as dedicated + | peripheral pins. + + move.w #0x1fff,a5@(oPIOA_Data) | Make output follow resistors. + move.w #0xea2a,a5@(oPIOA_DDR) | Set up PA15-PA0 for in/output. + move.w #0x0003,a5@(oPIOA_Ctrl) | Set up TXD2/RXD2 as dedicated + | peripheral pins. + +| +| Place "Bad" in all vectors from 010 thru 0ec. Vectors 0f0 and 0f4 +| are not set because they are the 68302''s BAR and SCR. +| + movea.w #0x010,a0 + moveq #(0x0f0-0x010)/4-1,d0 + move.l #Bad,d1 +cpy_Bad: move.l d1,(a0)+ + dbra d0,cpy_Bad + + .set vbase, 0x0200 + + lea vbase,a0 + moveq #31,d0 +cpy_Bad1: move.l d1,(a0)+ + dbra d0,cpy_Bad1 + +| +| Fill in special locations to configure OS +| + move.l #Bad,0x008 | Bus Error + move.l #Bad,0x00c | Address Error + move.l #Bad,0x024 | Trace +| move.l #KE_IRET,$0b4 | pSOS+ RET_I Call + +| move.l #_cnsl_isr,vbase+0x028 | SCC2 + move.l #timerisr,vbase+0x018 | Timer ISR + move.l #RTC_ISR,vbase+0x024 | Real Time Clock ISR + + | + | zero out uninitialized data area + | +zerobss: + moveal # SYM (end),a0 | find end of .bss + moveal # SYM (bss_start),a1 | find beginning of .bss + moveq #0,d0 + +loop: movel d0,a1@+ | to zero out uninitialized + cmpal a0,a1 + jlt loop | loop until _end reached + + movel # SYM (end),d0 | d0 = end of bss/start of heap + addl # SYM (heap_size),d0 | d0 = end of heap + movel d0, SYM (stack_start) | Save for brk() routine + addl # SYM (stack_size),d0 | make room for stack + andl #0xffffffc0,d0 | align it on 16 byte boundary + movw #0x3700,sr | SUPV MODE,INTERRUPTS OFF!!! + movel d0,a7 | set master stack pointer + movel d0,a6 | set base pointer + + /* + * RTEMS should maintiain a separate interrupt stack on CPUs + * without one in hardware. This is currently not supported + * on versions of the m68k without a HW intr stack. + */ + +#if ( M68K_HAS_SEPARATE_STACKS == 1 ) + lea SYM (hiintstack),a0 | a0 = high end of intr stack + movec a0,isp | set interrupt stack +#endif + + jsr SYM (bsp_start) + + nop +Bad: bra Bad + + nop +RTC_ISR: + movem.l d0-d1/a0-a1,a7@- | save d0-d1,a0-a1 + addql #1,_ISR_Nest_level | one nest level deeper + addql #1,_Thread_Dispatch_disable_level + | disable multitasking + + jbsr Clock_isr | invoke the user ISR + jmp _ISR_Exit +END_CODE + + +BEGIN_DATA + + PUBLIC (start_frame) +SYM (start_frame): + .space 4,0 + + PUBLIC (stack_start) +SYM (stack_start): + .space 4,0 +END_DATA + +BEGIN_BSS + + PUBLIC (environ) + .align 2 +SYM (environ): + .long 0 + + PUBLIC (heap_size) + .set SYM (heap_size),0x2000 + + PUBLIC (stack_size) + .set SYM (stack_size),0x1000 + + +END_DATA +END diff --git a/c/src/lib/libbsp/m68k/gen68302/start302/start302.s b/c/src/lib/libbsp/m68k/gen68302/start302/start302.s new file mode 100644 index 0000000000..2682066e84 --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68302/start302/start302.s @@ -0,0 +1,273 @@ +/* entry.s + * + * This file contains the entry point for the application. + * The name of this entry point is compiler dependent. + * It jumps to the BSP which is responsible for performing + * all initialization. + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $Id$ + */ + +#include "asm.h" + + .set BAR, 0xF2 | Base Address Register location + .set SCR, 0xF4 | System Control Register location + .set BAR_VAL, 0x0f7f | BAR value + .set SCR_VAL, 0x00080f00 | SCR value + .set GIMR_VAL, 0x8780 |Global Interrupt Mode Register. (MUST BE WRITTEN). + .set BaseAddr,(BAR_VAL&0x0fff)<<12 | MC68302 internal base address + + .set oSYSRAM, 0x000 | 576 bytes of internal system RAM + + .set oGIMR, 0x812 + + .set oCS0_Base, 0x830 | 16 bits, Chip Sel 0 Base Reg + .set oCS0_Option, 0x832 | 16 bits, Chip Sel 0 Option Reg + .set oCS1_Base, 0x834 | 16 bits, Chip Sel 1 Base Reg + .set oCS1_Option, 0x836 | 16 bits, Chip Sel 1 Option Reg + .set oCS2_Base, 0x838 | 16 bits, Chip Sel 2 Base Reg + .set oCS2_Option, 0x83a | 16 bits, Chip Sel 2 Option Reg + .set oCS3_Base, 0x83c | 16 bits, Chip Sel 3 Base Reg + .set oCS3_Option, 0x83e | 16 bits, Chip Sel 3 Option Reg + + .set tmpSRAM_BASE, 0x400000 | start of temporary SRAM + .set FLASH_BASE, 0xc00000 | start of FLASH''s normal location + + +BEGIN_CODE + PUBLIC (M68Kvec) | Vector Table +SYM (M68Kvec): | standard location for vectors +V___ISSP: .long 0x00001000 |00 0 Reset: Initial SSP +V____IPC: .long SYM(start)-V___ISSP |04 1 Reset: Initial PC +V_BUSERR: .long Bad-V___ISSP |08 2 Bus Error +V_ADRERR: .long Bad-V___ISSP |0c 3 Address Error + .space 240 | reserve space for reset of vectors + +#if ( M68K_HAS_SEPARATE_STACKS == 1 ) +SYM (lowintstack): + .space 4092 | reserve for interrupt stack +SYM (hiintstack): + .space 4 | end of interrupt stack +#endif + + PUBLIC (start) | Default entry point for GNU +SYM (start): + move.w #0x2700,sr | Disable all interrupts + move.w #BAR_VAL,BAR | Set Base Address Register + move.l #SCR_VAL,SCR | Set System Control Register + lea BaseAddr,a5 + move.w #GIMR_VAL,a5@(oGIMR) | Set Global Interrupt Mode Register + +| +| Set up chip select registers for the remapping process. +| + +| +| 0 X x x x x +| 0 000 0 0-- - --- ---- ---- ---- +| x xxx x xxx x xx +| + move.w #0xc001,a5@(oCS0_Base) | Expand CS0 to full size (FLASH) + move.w #0x1f82,a5@(oCS0_Option) | 000000-03ffff, R, 0 WS + +| +| X x x x x x +| 0 100 0 0-- - --- ---- ---- ---- +| x xxx x xxx x xx +| + move.w #0xa801,a5@(oCS1_Base) | Set up and enable CS1 (SRAM) + move.w #0x1f80,a5@(oCS1_Option) | 400000-43ffff, RW, 0 WS + +| +| Copy the initial boot FLASH area to the temporary SRAM location. +| + moveq #0,d0 + movea.l d0,a0 | a0 -> start of FLASH + lea tmpSRAM_BASE,a1 | a1 -> start of tmp SRAM +| moveq #(endPreBoot-V___ISSP)/4,d0 | # longs to copy + moveq #127,d0 +cpy_flash: move.l (a0)+,(a1)+ | copy + subq.l #1,d0 + bne cpy_flash + +| +| Copy remap code to 68302''s internal system RAM. +| + movea.w #begRemap-V___ISSP,a0 | a0 -> remap code + lea a5@(oSYSRAM),a1 | a1 -> internal system RAM +| moveq #(endRemap-begRemap)/2-1,d0 | d0 = # words to copy + moveq #11,d0 +cpy_remap: move.w (a0)+,(a1)+ | copy + dbra d0,cpy_remap + +| +| Jump to the remap code in the 68302''s internal system RAM. +| + jmp a5@(oSYSRAM) | (effectively a jmp begRemap) + +| +| This remap code, when executed from the 68302''s internal system RAM +| will 1) remap CS1 so that SRAM is at 0 +| 2) remap CS0 so that FLASH is at FLASH_BASE +| and 3) jump to executable code in the remapped FLASH. +| +begRemap: move.w #0xa001,a5@(oCS1_Base) | Move CS1 (SRAM) + move.w #0xd801,a5@(oCS0_Base) | Move CS0 (FLASH) + lea FLASH_BASE,a0 + jmp a0@(endRemap-V___ISSP.w) | Jump back to FLASH +endRemap: +| +| Now set up the remaining chip select registers. +| + +| +| 4 0 x x x x +| 1 000 1 111 0 000 0--- ---- ---- +| x xxx x xxx x xx +| + move.w #0xb1e1,a5@(oCS2_Base) | Set up and enable CS2 (dpRAM) + move.w #0x1ff0,a5@(oCS2_Option) | 8f0000-8f07ff, RW, 0 WS + +| +| 8 X x x x x +| 1 000 0 0-- - --- ---- ---- ---- +| x xxx x xxx x xx +| + move.w #0xd001,a5@(oCS3_Base) | Set up and enable CS3 (IO) + move.w #0x1f80,a5@(oCS3_Option) | 800000-83ffff, RW, 0 WS + +endPreBoot: + + move.b #0x30,0x800001 | set status LED amber + + .set oPIOB_Ctrl, 0x824 + .set oPIOB_DDR, 0x826 + .set oPIOB_Data, 0x828 + + .set oPIOA_Ctrl, 0x81e + .set oPIOA_DDR, 0x820 + .set oPIOA_Data, 0x822 + + move.w #0x0ff8,a5@(oPIOB_Data) | Make output follow resistors. + move.w #0x00ff,a5@(oPIOB_DDR) | Set up PB7-PB0 for output. + move.w #0x0080,a5@(oPIOB_Ctrl) | Set up WDOG* as dedicated + | peripheral pins. + + move.w #0x1fff,a5@(oPIOA_Data) | Make output follow resistors. + move.w #0xea2a,a5@(oPIOA_DDR) | Set up PA15-PA0 for in/output. + move.w #0x0003,a5@(oPIOA_Ctrl) | Set up TXD2/RXD2 as dedicated + | peripheral pins. + +| +| Place "Bad" in all vectors from 010 thru 0ec. Vectors 0f0 and 0f4 +| are not set because they are the 68302''s BAR and SCR. +| + movea.w #0x010,a0 + moveq #(0x0f0-0x010)/4-1,d0 + move.l #Bad,d1 +cpy_Bad: move.l d1,(a0)+ + dbra d0,cpy_Bad + + .set vbase, 0x0200 + + lea vbase,a0 + moveq #31,d0 +cpy_Bad1: move.l d1,(a0)+ + dbra d0,cpy_Bad1 + +| +| Fill in special locations to configure OS +| + move.l #Bad,0x008 | Bus Error + move.l #Bad,0x00c | Address Error + move.l #Bad,0x024 | Trace +| move.l #KE_IRET,$0b4 | pSOS+ RET_I Call + +| move.l #_cnsl_isr,vbase+0x028 | SCC2 + move.l #timerisr,vbase+0x018 | Timer ISR + move.l #RTC_ISR,vbase+0x024 | Real Time Clock ISR + + | + | zero out uninitialized data area + | +zerobss: + moveal # SYM (end),a0 | find end of .bss + moveal # SYM (bss_start),a1 | find beginning of .bss + moveq #0,d0 + +loop: movel d0,a1@+ | to zero out uninitialized + cmpal a0,a1 + jlt loop | loop until _end reached + + movel # SYM (end),d0 | d0 = end of bss/start of heap + addl # SYM (heap_size),d0 | d0 = end of heap + movel d0, SYM (stack_start) | Save for brk() routine + addl # SYM (stack_size),d0 | make room for stack + andl #0xffffffc0,d0 | align it on 16 byte boundary + movw #0x3700,sr | SUPV MODE,INTERRUPTS OFF!!! + movel d0,a7 | set master stack pointer + movel d0,a6 | set base pointer + + /* + * RTEMS should maintiain a separate interrupt stack on CPUs + * without one in hardware. This is currently not supported + * on versions of the m68k without a HW intr stack. + */ + +#if ( M68K_HAS_SEPARATE_STACKS == 1 ) + lea SYM (hiintstack),a0 | a0 = high end of intr stack + movec a0,isp | set interrupt stack +#endif + + jsr SYM (bsp_start) + + nop +Bad: bra Bad + + nop +RTC_ISR: + movem.l d0-d1/a0-a1,a7@- | save d0-d1,a0-a1 + addql #1,_ISR_Nest_level | one nest level deeper + addql #1,_Thread_Dispatch_disable_level + | disable multitasking + + jbsr Clock_isr | invoke the user ISR + jmp _ISR_Exit +END_CODE + + +BEGIN_DATA + + PUBLIC (start_frame) +SYM (start_frame): + .space 4,0 + + PUBLIC (stack_start) +SYM (stack_start): + .space 4,0 +END_DATA + +BEGIN_BSS + + PUBLIC (environ) + .align 2 +SYM (environ): + .long 0 + + PUBLIC (heap_size) + .set SYM (heap_size),0x2000 + + PUBLIC (stack_size) + .set SYM (stack_size),0x1000 + + +END_DATA +END diff --git a/c/src/lib/libbsp/m68k/gen68302/startup/bspclean.c b/c/src/lib/libbsp/m68k/gen68302/startup/bspclean.c new file mode 100644 index 0000000000..ca498e7806 --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68302/startup/bspclean.c @@ -0,0 +1,26 @@ +/* bsp_cleanup() + * + * This routine normally is part of start.s and usually returns + * control to a monitor. + * + * INPUT: NONE + * + * OUTPUT: NONE + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $Id$ + */ + +#include <rtems.h> +#include <bsp.h> + +void bsp_cleanup( void ) +{ +} diff --git a/c/src/lib/libbsp/m68k/gen68302/startup/bspstart.c b/c/src/lib/libbsp/m68k/gen68302/startup/bspstart.c new file mode 100644 index 0000000000..976046cf9f --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68302/startup/bspstart.c @@ -0,0 +1,169 @@ +/* bsp_start() + * + * This routine starts the application. It includes application, + * board, and monitor specific initialization and configuration. + * The generic CPU dependent initialization has been performed + * before this routine is invoked. + * + * INPUT: NONE + * + * OUTPUT: NONE + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $Id$ + */ + +#include <rtems.h> +#include <bsp.h> +#include <libcsupport.h> + + +/* + * The original table from the application and our copy of it with + * some changes. + */ + +extern rtems_configuration_table Configuration; +rtems_configuration_table BSP_Configuration; + +rtems_cpu_table Cpu_table; + +/* Initialize whatever libc we are using + * called from postdriver hook + */ + +void bsp_libc_init() +{ + extern int end; + rtems_unsigned32 heap_start; + + heap_start = (rtems_unsigned32) &end; + if (heap_start & (CPU_ALIGNMENT-1)) + heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1); + + /* + * The last parameter to RTEMS_Malloc_Initialize is the "chunk" + * size which a multiple of will be requested on each sbrk() + * call by malloc(). A value of 0 indicates that sbrk() should + * not be called to extend the heap. + */ + + RTEMS_Malloc_Initialize((void *) heap_start, 64 * 1024, 0); + + /* + * Set up for the libc handling. + */ + + if (BSP_Configuration.ticks_per_timeslice > 0) + libc_init(1); /* reentrant if possible */ + else + libc_init(0); /* non-reentrant */ + + /* + * Initialize the stack bounds checker + */ + +#ifdef STACK_CHECKER_ON + Stack_check_Initialize(); +#endif +} + + +int bsp_start( + int argc, + char **argv, + char **environp +) +{ + /* + * Allocate the memory for the RTEMS Work Space. This can come from + * a variety of places: hard coded address, malloc'ed from outside + * RTEMS world (e.g. simulator or primitive memory manager), or (as + * typically done by stock BSPs) by subtracting the required amount + * of work space from the last physical address on the CPU board. + */ +#if 0 +a Cpu_table.interrupt_vector_table = (mc68000_isr *) 0/*&M68Kvec*/; +#endif + + + /* + * Copy the Configuration Table .. so we can change it + */ + + BSP_Configuration = Configuration; + + /* + * Add 1 region for the RTEMS Malloc + */ + + BSP_Configuration.maximum_regions++; + + /* + * Add 1 extension for newlib libc + */ + +#ifdef RTEMS_NEWLIB + BSP_Configuration.maximum_extensions++; +#endif + + /* + * Add another extension if using the stack checker + */ + +#ifdef STACK_CHECKER_ON + BSP_Configuration.maximum_extensions++; +#endif + + /* + * Need to "allocate" the memory for the RTEMS Workspace and + * tell the RTEMS configuration where it is. This memory is + * not malloc'ed. It is just "pulled from the air". + */ + + BSP_Configuration.work_space_start = (void *) + (RAM_END - BSP_Configuration.work_space_size); + + /* + * initialize the CPU table for this BSP + */ + + /* + * we do not use the pretasking_hook + */ + + Cpu_table.pretasking_hook = NULL; + + Cpu_table.predriver_hook = bsp_libc_init; /* RTEMS resources available */ + + Cpu_table.postdriver_hook = NULL; + + Cpu_table.idle_task = NULL; /* do not override system IDLE task */ + + Cpu_table.do_zero_of_workspace = TRUE; + + Cpu_table.interrupt_stack_size = 4096; + + Cpu_table.extra_system_initialization_stack = 0; + + /* + * Don't forget the other CPU Table entries. + */ + + /* + * Start RTEMS + */ + + rtems_initialize_executive( &BSP_Configuration, &Cpu_table ); + + bsp_cleanup(); + + return 0; +} diff --git a/c/src/lib/libbsp/m68k/gen68302/timer/timer.c b/c/src/lib/libbsp/m68k/gen68302/timer/timer.c new file mode 100644 index 0000000000..4d60b6a82b --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68302/timer/timer.c @@ -0,0 +1,130 @@ +/* Timer_init() + * + * This routine initializes TIMER 2 for an MC68302. + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * NOTE: It is important that the timer start/stop overhead be + * determined when porting or modifying this code. + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * $Id$ + */ + + +#include <rtems.h> +#include <bsp.h> +#include "m68302.h" + + +#define TMR2_VAL 0x071b /* Timer mode register + * (section 3.5.2.1 in 68302 manual) + * 15-8: "7" prescaler divide by 8 (x+1) + * 7-6: 00 dis. intr. on capture event + * 5: 0 active-low pulse + * 4: 1 intr. on reaching reference + * 3: 1 restart counter on reference + * 2-1: 01 master clock input source + * 0: 1 enable timer + */ +#define TRR2_VAL 2000 /* Timer reference register + * (section 3.5.2.2 in 68302 manual) + * 2000 ticks @ (16MHz/1)/8 = 1-ms count + */ + +rtems_unsigned32 Timer_interrupts; + +rtems_boolean Timer_driver_Find_average_overhead; + +rtems_isr timerisr(); + +void Timer_initialize( void ) +{ + m302.reg.tmr2 = 0; /* disable timer */ + + Timer_interrupts = 0; /* clear timer ISR count */ + + m302.reg.trr2 = TRR2_VAL; /* set timer reference register */ + m302.reg.tmr2 = TMR2_VAL; /* set timer mode register */ + m302.reg.imr |= RBIT_IMR_TIMER2; /* set 68302 int-mask to allow ints */ +} + +/* + * The following controls the behavior of Read_timer(). + * + * FIND_AVG_OVERHEAD * instructs the routine to return the "raw" count. + * + * AVG_OVEREHAD is the overhead for starting and stopping the timer. It + * is usually deducted from the number returned. + * + * LEAST_VALID is the lowest number this routine should trust. Numbers + * below this are "noise" and zero is returned. + */ + +#define AVG_OVERHEAD 0 /* It typically takes X.X microseconds */ + /* (Y countdowns) to start/stop the timer. */ + /* This value is in microseconds. */ +#define LEAST_VALID 1 /* Don't trust a clicks value lower than this */ + +/* + * Return timer value in 1/2-microsecond units + */ +int Read_timer( void ) +{ + rtems_unsigned16 clicks; + rtems_unsigned32 total; + + /* + * Read the timer and see how many clicks it has been since counter + * rolled over. + */ + + clicks = m302.reg.tcn2; + + /* + * Total is calculated by taking into account the number of timer overflow + * interrupts since the timer was initialized and clicks since the last + * interrupts. + */ + + total = (Timer_interrupts * TRR2_VAL) + clicks; + + if ( Timer_driver_Find_average_overhead == 1 ) + return total; /* in XXX microsecond units */ + + if ( total < LEAST_VALID ) + return 0; /* below timer resolution */ + + /* + * Convert 1/2-microsecond count into microseconds + */ + + return (total - AVG_OVERHEAD) >> 1; +} + + +/* + * Empty function call used in loops to measure basic cost of looping + * in Timing Test Suite. + */ + +rtems_status_code Empty_function(void) +{ + return RTEMS_SUCCESSFUL; +} + +void Set_find_average_overhead( + rtems_boolean find_flag +) +{ + Timer_driver_Find_average_overhead = find_flag; +} diff --git a/c/src/lib/libbsp/m68k/gen68302/timer/timerisr.s b/c/src/lib/libbsp/m68k/gen68302/timer/timerisr.s new file mode 100644 index 0000000000..c804b9dfa6 --- /dev/null +++ b/c/src/lib/libbsp/m68k/gen68302/timer/timerisr.s @@ -0,0 +1,28 @@ +/* + * Handle 68302 TIMER2 interrupts. + * + * All code in this routine is pure overhead which can perturb the + * accuracy of RTEMS' timing test suite. + * + * See also: Read_timer() + * + * To reduce overhead this is best to be the "rawest" hardware interupt + * handler you can write. This should be the only interrupt which can + * occur during the measured time period. + * + * An external counter, Timer_interrupts, is incremented. + * + * $Id$ + */ + +#include "asm.h" + +BEGIN_CODE + PUBLIC(timerisr) +SYM(timerisr): + move.w #0x0040,SYM(m302)+2072 | clear interrupt in-service bit + move.b #3,SYM(m302)+2137 | clear timer interrupt event register + addq.l #1,SYM(Timer_interrupts) | increment timer value + rte +END_CODE +END diff --git a/c/src/lib/libmisc/stackchk/check.c b/c/src/lib/libmisc/stackchk/check.c index 2d25f51f3e..ac15973815 100644 --- a/c/src/lib/libmisc/stackchk/check.c +++ b/c/src/lib/libmisc/stackchk/check.c @@ -329,7 +329,7 @@ void *Stack_check_find_high_water_mark( * match pattern */ - base += 4; + base += PATTERN_SIZE_WORDS; for (ebase = base + length; base < ebase; base++) if (*base != U32_PATTERN) return (void *) base; diff --git a/c/src/libmisc/stackchk/check.c b/c/src/libmisc/stackchk/check.c index 2d25f51f3e..ac15973815 100644 --- a/c/src/libmisc/stackchk/check.c +++ b/c/src/libmisc/stackchk/check.c @@ -329,7 +329,7 @@ void *Stack_check_find_high_water_mark( * match pattern */ - base += 4; + base += PATTERN_SIZE_WORDS; for (ebase = base + length; base < ebase; base++) if (*base != U32_PATTERN) return (void *) base; diff --git a/cpukit/libmisc/stackchk/check.c b/cpukit/libmisc/stackchk/check.c index 2d25f51f3e..ac15973815 100644 --- a/cpukit/libmisc/stackchk/check.c +++ b/cpukit/libmisc/stackchk/check.c @@ -329,7 +329,7 @@ void *Stack_check_find_high_water_mark( * match pattern */ - base += 4; + base += PATTERN_SIZE_WORDS; for (ebase = base + length; base < ebase; base++) if (*base != U32_PATTERN) return (void *) base; diff --git a/cpukit/score/cpu/m68k/cpu.c b/cpukit/score/cpu/m68k/cpu.c index 45484da1f4..662a0440f4 100644 --- a/cpukit/score/cpu/m68k/cpu.c +++ b/cpukit/score/cpu/m68k/cpu.c @@ -95,3 +95,26 @@ void _CPU_Install_interrupt_stack( void ) #endif } +#if ( M68K_HAS_BFFFO != 1 ) +/* + * Returns log2(x) 0<x<256 + */ +const unsigned char __log2table[256] = { + 0, 0, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, + 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, + 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, + 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, + 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, + 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, + 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, + 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, + 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, + 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, + 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, + 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, + 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, + 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, + 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, + 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, +}; +#endif diff --git a/cpukit/score/cpu/m68k/m68302.h b/cpukit/score/cpu/m68k/m68302.h new file mode 100644 index 0000000000..da96478cf3 --- /dev/null +++ b/cpukit/score/cpu/m68k/m68302.h @@ -0,0 +1,608 @@ +/* + *------------------------------------------------------------------ + * + * m68302.h - Definitions for Motorola MC68302 processor. + * + * Section references in this file refer to revision 2 of Motorola's + * "MC68302 Integrated Multiprotocol Processor User's Manual". + * (Motorola document MC68302UM/AD REV 2.) + * + * Based on Don Meyer's cpu68302.h that was posted in comp.sys.m68k + * on 17 February, 1993. + * + * Copyright 1995 David W. Glessner. + * + * Redistribution and use in source and binary forms are permitted + * provided that the following conditions are met: + * 1. Redistribution of source code and documentation must retain + * the above copyright notice, this list of conditions and the + * following disclaimer. + * 2. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * This software is provided "AS IS" without warranty of any kind, + * either expressed or implied, including, but not limited to, the + * implied warranties of merchantability, title and fitness for a + * particular purpose. + * + * + * $Id$ + * + *------------------------------------------------------------------ + */ + +#ifndef __MOTOROLA_MC68302_DEFINITIONS_h +#define __MOTOROLA_MC68302_DEFINITIONS_h + +/* + * BAR - Base Address Register + * Section 2.7 + */ +#define M302_BAR (*((volatile rtems_unsigned16 *) 0xf2)) + +/* + * SCR - System Control Register + * Section 3.8.1 + */ +#define M302_SCR (*((volatile rtems_unsigned32 *) 0xf4)) +/* + * SCR bits + */ +#define RBIT_SCR_IPA 0x08000000 +#define RBIT_SCR_HWT 0x04000000 +#define RBIT_SCR_WPV 0x02000000 +#define RBIT_SCR_ADC 0x01000000 + +#define RBIT_SCR_ERRE 0x00400000 +#define RBIT_SCR_VGE 0x00200000 +#define RBIT_SCR_WPVE 0x00100000 +#define RBIT_SCR_RMCST 0x00080000 +#define RBIT_SCR_EMWS 0x00040000 +#define RBIT_SCR_ADCE 0x00020000 +#define RBIT_SCR_BCLM 0x00010000 + +#define RBIT_SCR_FRZW 0x00008000 +#define RBIT_SCR_FRZ2 0x00004000 +#define RBIT_SCR_FRZ1 0x00002000 +#define RBIT_SCR_SAM 0x00001000 +#define RBIT_SCR_HWDEN 0x00000800 +#define RBIT_SCR_HWDCN2 0x00000400 +#define RBIT_SCR_HWDCN1 0x00000200 +#define RBIT_SCR_HWDCN0 0x00000100 + +#define RBIT_SCR_LPREC 0x00000080 +#define RBIT_SCR_LPP16 0x00000040 +#define RBIT_SCR_LPEN 0x00000020 +#define RBIT_SCR_LPCLKDIV 0x0000001f + + +/* + * 68000 interrupt and trap vector numbers + */ +#define M68K_IVEC_BUS_ERROR 2 +#define M68K_IVEC_ADDRESS_ERROR 3 +#define M68K_IVEC_ILLEGAL_OPCODE 4 +#define M68K_IVEC_ZERO_DIVIDE 5 +#define M68K_IVEC_CHK 6 +#define M68K_IVEC_TRAPV 7 +#define M68K_IVEC_PRIVILEGE 8 +#define M68K_IVEC_TRACE 9 +#define M68K_IVEC_LINE_A 10 +#define M68K_IVEC_LINE_F 11 +/* Unassigned, Reserved 12-14 */ +#define M68K_IVEC_UNINITIALIZED_INT 15 +/* Unassigned, Reserved 16-23 */ +#define M68K_IVEC_SPURIOUS_INT 24 + +#define M68K_IVEC_LEVEL1_AUTOVECTOR 25 +#define M68K_IVEC_LEVEL2_AUTOVECTOR 26 +#define M68K_IVEC_LEVEL3_AUTOVECTOR 27 +#define M68K_IVEC_LEVEL4_AUTOVECTOR 28 +#define M68K_IVEC_LEVEL5_AUTOVECTOR 29 +#define M68K_IVEC_LEVEL6_AUTOVECTOR 30 +#define M68K_IVEC_LEVEL7_AUTOVECTOR 31 + +#define M68K_IVEC_TRAP0 32 +#define M68K_IVEC_TRAP1 33 +#define M68K_IVEC_TRAP2 34 +#define M68K_IVEC_TRAP3 35 +#define M68K_IVEC_TRAP4 36 +#define M68K_IVEC_TRAP5 37 +#define M68K_IVEC_TRAP6 38 +#define M68K_IVEC_TRAP7 39 +#define M68K_IVEC_TRAP8 40 +#define M68K_IVEC_TRAP9 41 +#define M68K_IVEC_TRAP10 42 +#define M68K_IVEC_TRAP11 43 +#define M68K_IVEC_TRAP12 44 +#define M68K_IVEC_TRAP13 45 +#define M68K_IVEC_TRAP14 46 +#define M68K_IVEC_TRAP15 47 +/* + * Unassigned, Reserved 48-59 + * + * Note: Vectors 60-63 are used by the MC68302 (e.g. BAR, SCR). + */ + +/* + * MC68302 Interrupt Vectors + * Section 3.2 + */ +enum m68302_ivec_e { + M302_IVEC_ERR =0, + M302_IVEC_PB8 =1, /* General-Purpose Interrupt 0 */ + M302_IVEC_SMC2 =2, + M302_IVEC_SMC1 =3, + M302_IVEC_TIMER3 =4, + M302_IVEC_SCP =5, + M302_IVEC_TIMER2 =6, + M302_IVEC_PB9 =7, /* General-Purpose Interrupt 1 */ + M302_IVEC_SCC3 =8, + M302_IVEC_TIMER1 =9, + M302_IVEC_SCC2 =10, + M302_IVEC_IDMA =11, + M302_IVEC_SDMA =12, /* SDMA Channels Bus Error */ + M302_IVEC_SCC1 =13, + M302_IVEC_PB10 =14, /* General-Purpose Interrupt 2 */ + M302_IVEC_PB11 =15, /* General-Purpose Interrupt 3 */ + M302_IVEC_IRQ1 =17, /* External Device */ + M302_IVEC_IRQ6 =22, /* External Device */ + M302_IVEC_IRQ7 =23 /* External Device */ +}; + + +/* + * GIMR - Global Interrupt Mode Register + * Section 3.2.5.1 + */ +#define RBIT_GIMR_MOD (1<<15) +#define RBIT_GIMR_IV7 (1<<14) +#define RBIT_GIMR_IV6 (1<<13) +#define RBIT_GIMR_IV1 (1<<12) +#define RBIT_GIMR_ET7 (1<<10) +#define RBIT_GIMR_ET6 (1<<9) +#define RBIT_GIMR_ET1 (1<<8) +#define RBIT_GIMR_VECTOR (7<<5) + +/* + * IPR - Interrupt Pending Register (Section 3.2.5.2) + * IMR - Interrupt Mask Register (Section 3.2.5.3) + * ISR - Interrupt In-Service Register (Section 3.2.5.4) + */ +#define RBIT_IPR_PB11 (1<<15) +#define RBIT_IPR_PB10 (1<<14) +#define RBIT_IPR_SCC1 (1<<13) +#define RBIT_IPR_SDMA (1<<12) +#define RBIT_IPR_IDMA (1<<11) +#define RBIT_IPR_SCC2 (1<<10) +#define RBIT_IPR_TIMER1 (1<<9) +#define RBIT_IPR_SCC3 (1<<8) +#define RBIT_IPR_PB9 (1<<7) +#define RBIT_IPR_TIMER2 (1<<6) +#define RBIT_IPR_SCP (1<<5) +#define RBIT_IPR_TIMER3 (1<<4) +#define RBIT_IPR_SMC1 (1<<3) +#define RBIT_IPR_SMC2 (1<<2) +#define RBIT_IPR_PB8 (1<<1) +#define RBIT_IPR_ERR (1<<0) + +#define RBIT_ISR_PB11 (1<<15) +#define RBIT_ISR_PB10 (1<<14) +#define RBIT_ISR_SCC1 (1<<13) +#define RBIT_ISR_SDMA (1<<12) +#define RBIT_ISR_IDMA (1<<11) +#define RBIT_ISR_SCC2 (1<<10) +#define RBIT_ISR_TIMER1 (1<<9) +#define RBIT_ISR_SCC3 (1<<8) +#define RBIT_ISR_PB9 (1<<7) +#define RBIT_ISR_TIMER2 (1<<6) +#define RBIT_ISR_SCP (1<<5) +#define RBIT_ISR_TIMER3 (1<<4) +#define RBIT_ISR_SMC1 (1<<3) +#define RBIT_ISR_SMC2 (1<<2) +#define RBIT_ISR_PB8 (1<<1) + +#define RBIT_IMR_PB11 (1<<15) /* PB11 Interrupt Mask */ +#define RBIT_IMR_PB10 (1<<14) /* PB10 Interrupt Mask */ +#define RBIT_IMR_SCC1 (1<<13) /* SCC1 Interrupt Mask */ +#define RBIT_IMR_SDMA (1<<12) /* SDMA Interrupt Mask */ +#define RBIT_IMR_IDMA (1<<11) /* IDMA Interrupt Mask */ +#define RBIT_IMR_SCC2 (1<<10) /* SCC2 Interrupt Mask */ +#define RBIT_IMR_TIMER1 (1<<9) /* TIMER1 Interrupt Mask */ +#define RBIT_IMR_SCC3 (1<<8) /* SCC3 Interrupt Mask */ +#define RBIT_IMR_PB9 (1<<7) /* PB9 Interrupt Mask */ +#define RBIT_IMR_TIMER2 (1<<6) /* TIMER2 Interrupt Mask */ +#define RBIT_IMR_SCP (1<<5) /* SCP Interrupt Mask */ +#define RBIT_IMR_TIMER3 (1<<4) /* TIMER3 Interrupt Mask */ +#define RBIT_IMR_SMC1 (1<<3) /* SMC1 Interrupt Mask */ +#define RBIT_IMR_SMC2 (1<<2) /* SMC2 Interrupt Mask */ +#define RBIT_IMR_PB8 (1<<1) /* PB8 Interrupt Mask */ + + +/* + * DRAM Refresh + * Section 3.9 + * + * The DRAM refresh memory map replaces the SCC2 Tx BD 6 and Tx BD 7 + * structures in the parameter RAM. + * + * Access to the DRAM registers can be accomplished by + * the following approach: + * + * volatile m302_DRAM_refresh_t *dram; + * dram = (volatile m302_DRAM_refresh_t *) &m302.scc2.bd.tx[6]; + * + * Then simply use pointer references (e.g. dram->count = 3). + */ +typedef struct { + rtems_unsigned16 dram_high; /* DRAM high address and FC */ + rtems_unsigned16 dram_low; /* DRAM low address */ + rtems_unsigned16 increment; /* increment step (bytes/row) */ + rtems_unsigned16 count; /* RAM refresh cycle count (#rows) */ + rtems_unsigned16 t_ptr_h; /* temporary refresh high addr & FC */ + rtems_unsigned16 t_ptr_l; /* temporary refresh low address */ + rtems_unsigned16 t_count; /* temporary refresh cycles count */ + rtems_unsigned16 res; /* reserved */ +} m302_DRAM_refresh_t; + + +/* + * TMR - Timer Mode Register (for timers 1 and 2) + * Section 3.5.2.1 + */ +#define RBIT_TMR_ICLK_STOP (0<<1) +#define RBIT_TMR_ICLK_MASTER (1<<1) +#define RBIT_TMR_ICLK_MASTER16 (2<<1) +#define RBIT_TMR_ICLK_TIN (3<<1) + +#define RBIT_TMR_OM (1<<5) +#define RBIT_TMR_ORI (1<<4) +#define RBIT_TMR_FRR (1<<3) +#define RBIT_TMR_RST (1<<0) + + +/* + * TER - Timer Event Register (for timers 1 and 2) + * Section 3.5.2.5 + */ +#define RBIT_TER_REF (1<<1) /* Output Reference Event */ +#define RBIT_TER_CAP (1<<0) /* Capture Event */ + + +/* + * SCC Buffer Descriptors and Buffer Descriptors Table + * Section 4.5.5 + */ +typedef struct m302_SCC_bd { + rtems_unsigned16 status; /* status and control */ + rtems_unsigned16 length; /* data length */ + rtems_unsigned8 *buffer; /* data buffer pointer */ +} m302_SCC_bd_t; + +typedef struct { + m302_SCC_bd_t rx[8]; /* receive buffer descriptors */ + m302_SCC_bd_t tx[8]; /* transmit buffer descriptors */ +} m302_SCC_bd_table_t; + + +/* + * SCC Parameter RAM (offset 0x080 from an SCC Base) + * Section 4.5.6 + * + * Each SCC parameter RAM area begins at offset 0x80 from each SCC base + * area (0x400, 0x500, or 0x600 from the dual-port RAM base). + * + * Offsets 0x9c-0xbf from each SCC base area compose the protocol-specific + * portion of the SCC parameter RAM. + */ +typedef struct { + rtems_unsigned8 rfcr; /* Rx Function Code */ + rtems_unsigned8 tfcr; /* Tx Function Code */ + rtems_unsigned16 mrblr; /* Maximum Rx Buffer Length */ + rtems_unsigned16 _rstate; /* Rx Internal State */ + rtems_unsigned8 res2; + rtems_unsigned8 rbd; /* Rx Internal Buffer Number */ + rtems_unsigned32 _rdptr; /* Rx Internal Data Pointer */ + rtems_unsigned16 _rcount; /* Rx Internal Byte Count */ + rtems_unsigned16 _rtmp; /* Rx Temp */ + rtems_unsigned16 _tstate; /* Tx Internal State */ + rtems_unsigned8 res7; + rtems_unsigned8 tbd; /* Tx Internal Buffer Number */ + rtems_unsigned32 _tdptr; /* Tx Internal Data Pointer */ + rtems_unsigned16 _tcount; /* Tx Internal Byte Count */ + rtems_unsigned16 _ttmp; /* Tx Temp */ +} m302_SCC_parameters_t; + +/* + * UART-Specific SCC Parameter RAM + * Section 4.5.11.3 + */ +typedef struct { + rtems_unsigned16 max_idl; /* Maximum IDLE Characters (rx) */ + rtems_unsigned16 idlc; /* Temporary rx IDLE counter */ + rtems_unsigned16 brkcr; /* Break Count Register (tx) */ + rtems_unsigned16 parec; /* Receive Parity Error Counter */ + rtems_unsigned16 frmec; /* Receive Framing Error Counter */ + rtems_unsigned16 nosec; /* Receive Noise Counter */ + rtems_unsigned16 brkec; /* Receive Break Condition Counter */ + rtems_unsigned16 uaddr1; /* UART ADDRESS Character 1 */ + rtems_unsigned16 uaddr2; /* UART ADDRESS Character 2 */ + rtems_unsigned16 rccr; /* Receive Control Character Register */ + rtems_unsigned16 character[8]; /* Control Characters 1 through 8*/ +} m302_SCC_UartSpecific_t; +/* + * This definition allows for the checking of receive buffers + * for errors. + */ + +#define RCV_ERR 0x003F + +/* + * UART receive buffer descriptor bit definitions. + * Section 4.5.11.14 + */ +#define RBIT_UART_CTRL (1<<11) /* buffer contains a control char */ +#define RBIT_UART_ADDR (1<<10) /* first byte contains an address */ +#define RBIT_UART_MATCH (1<<9) /* indicates which addr char matched */ +#define RBIT_UART_IDLE (1<<8) /* buffer closed due to IDLE sequence */ +#define RBIT_UART_BR (1<<5) /* break sequence was received */ +#define RBIT_UART_FR (1<<4) /* framing error was received */ +#define RBIT_UART_PR (1<<3) /* parity error was received */ +#define RBIT_UART_OV (1<<1) /* receiver overrun occurred */ +#define RBIT_UART_CD (1<<0) /* carrier detect lost */ +#define RBIT_UART_STATUS 0x003B /* all status bits */ + +/* + * UART transmit buffer descriptor bit definitions. + * Section 4.5.11.15 + */ +#define RBIT_UART_CR (1<<11) /* clear-to-send report + * this results in two idle bits + * between back-to-back frames + */ +#define RBIT_UART_A (1<<10) /* buffer contains address characters + * only valid in multidrop mode (UM0=1) + */ +#define RBIT_UART_PREAMBLE (1<<9) /* send preamble before data */ +#define RBIT_UART_CTS_LOST (1<<0) /* CTS lost */ + +/* + * UART event register + * Section 4.5.11.16 + */ +#define M302_UART_EV_CTS (1<<7) /* CTS status changed */ +#define M302_UART_EV_CD (1<<6) /* carrier detect status changed */ +#define M302_UART_EV_IDL (1<<5) /* IDLE sequence status changed */ +#define M302_UART_EV_BRK (1<<4) /* break character was received */ +#define M302_UART_EV_CCR (1<<3) /* control character received */ +#define M302_UART_EV_TX (1<<1) /* buffer has been transmitted */ +#define M302_UART_EV_RX (1<<0) /* buffer has been received */ + + +/* + * HDLC-Specific SCC Parameter RAM + * Section 4.5.12.3 + * + * c_mask_l should be 0xF0B8 for 16-bit CRC, 0xdebb for 32-bit CRC + * c_mask_h is a don't care for 16-bit CRC, 0x20E2 for 32-bit CRC + */ +typedef struct { + rtems_unsigned16 rcrc_l; /* Temp Receive CRC Low */ + rtems_unsigned16 rcrc_h; /* Temp Receive CRC High */ + rtems_unsigned16 c_mask_l; /* CRC Mask Low */ + rtems_unsigned16 c_mask_h; /* CRC Mask High */ + rtems_unsigned16 tcrc_l; /* Temp Transmit CRC Low */ + rtems_unsigned16 tcrc_h; /* Temp Transmit CRC High */ + + rtems_unsigned16 disfc; /* Discard Frame Counter */ + rtems_unsigned16 crcec; /* CRC Error Counter */ + rtems_unsigned16 abtsc; /* Abort Sequence Counter */ + rtems_unsigned16 nmarc; /* Nonmatching Address Received Cntr */ + rtems_unsigned16 retrc; /* Frame Retransmission Counter */ + + rtems_unsigned16 mflr; /* Maximum Frame Length Register */ + rtems_unsigned16 max_cnt; /* Maximum_Length Counter */ + + rtems_unsigned16 hmask; /* User Defined Frame Address Mask */ + rtems_unsigned16 haddr1; /* User Defined Frame Address */ + rtems_unsigned16 haddr2; /* " */ + rtems_unsigned16 haddr3; /* " */ + rtems_unsigned16 haddr4; /* " */ +} m302_SCC_HdlcSpecific_t; +/* + * HDLC receiver buffer descriptor bit definitions + * Section 4.5.12.10 + */ +#define RBIT_HDLC_EMPTY_BIT 0x8000 /* buffer associated with BD is empty */ +#define RBIT_HDLC_LAST_BIT 0x0800 /* buffer is last in a frame */ +#define RBIT_HDLC_FIRST_BIT 0x0400 /* buffer is first in a frame */ +#define RBIT_HDLC_FRAME_LEN 0x0020 /* receiver frame length violation */ +#define RBIT_HDLC_NONOCT_Rx 0x0010 /* received non-octet aligned frame */ +#define RBIT_HDLC_ABORT_SEQ 0x0008 /* received abort sequence */ +#define RBIT_HDLC_CRC_ERROR 0x0004 /* frame contains a CRC error */ +#define RBIT_HDLC_OVERRUN 0x0002 /* receiver overrun occurred */ +#define RBIT_HDLC_CD_LOST 0x0001 /* carrier detect lost */ + +/* + * HDLC transmit buffer descriptor bit definitions + * Section 4.5.12.11 + */ +#define RBIT_HDLC_READY_BIT 0x8000 /* buffer is ready to transmit */ +#define RBIT_HDLC_EXT_BUFFER 0x4000 /* buffer is in external memory */ +#define RBIT_HDLC_WRAP_BIT 0x2000 /* last buffer in bd table, so wrap */ +#define RBIT_HDLC_WAKE_UP 0x1000 /* interrupt when buffer serviced */ +#define RBIT_HDLC_LAST_BIT 0x0800 /* buffer is last in the frame */ +#define RBIT_HDLC_TxCRC_BIT 0x0400 /* transmit a CRC sequence */ +#define RBIT_HDLC_UNDERRUN 0x0002 /* transmitter underrun */ +#define RBIT_HDLC_CTS_LOST 0x0001 /* CTS lost */ + +/* + * HDLC event register bit definitions + * Section 4.5.12.12 + */ +#define RBIT_HDLC_CTS 0x80 /* CTS status changed */ +#define RBIT_HDLC_CD 0x40 /* carrier detect status changed */ +#define RBIT_HDLC_IDL 0x20 /* IDLE sequence status changed */ +#define RBIT_HDLC_TXE 0x10 /* transmit error */ +#define RBIT_HDLC_RXF 0x08 /* received frame */ +#define RBIT_HDLC_BSY 0x04 /* frame rcvd and discarded due to + * lack of buffers + */ +#define RBIT_HDLC_TXB 0x02 /* buffer has been transmitted */ +#define RBIT_HDLC_RXB 0x01 /* received buffer */ + + + +typedef struct { + m302_SCC_bd_table_t bd; /* +000 Buffer Descriptor Table */ + m302_SCC_parameters_t parm; /* +080 Common Parameter RAM */ + union { /* +09C Protocol-Specific Parm RAM */ + m302_SCC_UartSpecific_t uart; + m302_SCC_HdlcSpecific_t hdlc; + } prot; + rtems_unsigned8 res[0x040]; /* +0C0 reserved, (not implemented) */ +} m302_SCC_t; + + +/* + * Common SCC Registers + */ +typedef struct { + rtems_unsigned16 res1; + rtems_unsigned16 scon; /* SCC Configuration Register 4.5.2 */ + rtems_unsigned16 scm; /* SCC Mode Register 4.5.3 */ + rtems_unsigned16 dsr; /* SCC Data Synchronization Register 4.5.4 */ + rtems_unsigned8 scce; /* SCC Event Register 4.5.8.1 */ + rtems_unsigned8 res2; + rtems_unsigned8 sccm; /* SCC Mask Register 4.5.8.2 */ + rtems_unsigned8 res3; + rtems_unsigned8 sccs; /* SCC Status Register 4.5.8.3 */ + rtems_unsigned8 res4; + rtems_unsigned16 res5; +} m302_SCC_Registers_t; + +/* + * SCON - SCC Configuration Register + * Section 4.5.2 + */ +#define RBIT_SCON_WOMS (1<<15) /* Wired-OR Mode Select (NMSI mode only) + * When set, the TXD driver is an + * open-drain output */ +#define RBIT_SCON_EXTC (1<<14) /* External Clock Source */ +#define RBIT_SCON_TCS (1<<13) /* Transmit Clock Source */ +#define RBIT_SCON_RCS (1<<12) /* Receive Clock Source */ + +/* + * SCM - SCC Mode Register bit definitions + * Section 4.5.3 + * The parameter-specific mode bits occupy bits 15 through 6. + */ +#define RBIT_SCM_ENR (1<<3) /* Enable receiver */ +#define RBIT_SCM_ENT (1<<2) /* Enable transmitter */ + + +/* + * Internal MC68302 Registers + * starts at offset 0x800 from dual-port RAM base + * Section 2.8 + */ +typedef struct { + /* offset +800 */ + rtems_unsigned16 res0; + rtems_unsigned16 cmr; /* IDMA Channel Mode Register */ + rtems_unsigned32 sapr; /* IDMA Source Address Pointer */ + rtems_unsigned32 dapr; /* IDMA Destination Address Pointer */ + rtems_unsigned16 bcr; /* IDMA Byte Count Register */ + rtems_unsigned8 csr; /* IDMA Channel Status Register */ + rtems_unsigned8 res1; + rtems_unsigned8 fcr; /* IDMA Function Code Register */ + rtems_unsigned8 res2; + + /* offset +812 */ + rtems_unsigned16 gimr; /* Global Interrupt Mode Register */ + rtems_unsigned16 ipr; /* Interrupt Pending Register */ + rtems_unsigned16 imr; /* Interrupt Mask Register */ + rtems_unsigned16 isr; /* Interrupt In-Service Register */ + rtems_unsigned16 res3; + rtems_unsigned16 res4; + + /* offset +81e */ + rtems_unsigned16 pacnt; /* Port A Control Register */ + rtems_unsigned16 paddr; /* Port A Data Direction Register */ + rtems_unsigned16 padat; /* Port A Data Register */ + rtems_unsigned16 pbcnt; /* Port B Control Register */ + rtems_unsigned16 pbddr; /* Port B Data Direction Register */ + rtems_unsigned16 pbdat; /* Port B Data Register */ + rtems_unsigned16 res5; + + /* offset +82c */ + rtems_unsigned16 res6; + rtems_unsigned16 res7; + rtems_unsigned16 br0; /* Base Register (CS0) */ + rtems_unsigned16 or0; /* Option Register (CS0) */ + rtems_unsigned16 br1; /* Base Register (CS1) */ + rtems_unsigned16 or1; /* Option Register (CS1) */ + rtems_unsigned16 br2; /* Base Register (CS2) */ + rtems_unsigned16 or2; /* Option Register (CS2) */ + rtems_unsigned16 br3; /* Base Register (CS3) */ + rtems_unsigned16 or3; /* Option Register (CS3) */ + + /* offset +840 */ + rtems_unsigned16 tmr1; /* Timer Unit 1 Mode Register */ + rtems_unsigned16 trr1; /* Timer Unit 1 Reference Register */ + rtems_unsigned16 tcr1; /* Timer Unit 1 Capture Register */ + rtems_unsigned16 tcn1; /* Timer Unit 1 Counter */ + rtems_unsigned8 res8; + rtems_unsigned8 ter1; /* Timer Unit 1 Event Register */ + rtems_unsigned16 wrr; /* Watchdog Reference Register */ + rtems_unsigned16 wcn; /* Watchdog Counter */ + rtems_unsigned16 res9; + rtems_unsigned16 tmr2; /* Timer Unit 2 Mode Register */ + rtems_unsigned16 trr2; /* Timer Unit 2 Reference Register */ + rtems_unsigned16 tcr2; /* Timer Unit 2 Capture Register */ + rtems_unsigned16 tcn2; /* Timer Unit 2 Counter */ + rtems_unsigned8 resa; + rtems_unsigned8 ter2; /* Timer Unit 2 Event Register */ + rtems_unsigned16 resb; + rtems_unsigned16 resc; + rtems_unsigned16 resd; + + /* offset +860 */ + rtems_unsigned8 cr; /* Command Register */ + rtems_unsigned8 rese[0x1f]; + + /* offset +880, +890, +8a0 */ + m302_SCC_Registers_t scc[3]; /* SCC1, SCC2, SCC3 Registers */ + + /* offset +8b0 */ + rtems_unsigned16 spmode; /* SCP,SMC Mode and Clock Cntrl Reg */ + rtems_unsigned16 simask; /* Serial Interface Mask Register */ + rtems_unsigned16 simode; /* Serial Interface Mode Register */ +} m302_internalReg_t ; + + +/* + * MC68302 dual-port RAM structure. + * (Includes System RAM, Parameter RAM, and Internal Registers). + * Section 2.8 + */ +typedef struct { + rtems_unsigned8 mem[0x240]; /* +000 User Data Memory */ + rtems_unsigned8 res1[0x1c0]; /* +240 reserved, (not implemented) */ + m302_SCC_t scc1; /* +400 SCC1 */ + m302_SCC_t scc2; /* +500 SCC2 */ + m302_SCC_t scc3; /* +600 SCC3 */ + rtems_unsigned8 res2[0x100]; /* +700 reserved, (not implemented) */ + m302_internalReg_t reg; /* +800 68302 Internal Registers */ +} m302_dualPortRAM_t; + + +/* + * Declare the variable that's used to reference the variables in + * the dual-port RAM. + */ +extern volatile m302_dualPortRAM_t m302; + +#endif +/* end of include file */ diff --git a/cpukit/score/cpu/m68k/rtems/m68k/m68302.h b/cpukit/score/cpu/m68k/rtems/m68k/m68302.h new file mode 100644 index 0000000000..da96478cf3 --- /dev/null +++ b/cpukit/score/cpu/m68k/rtems/m68k/m68302.h @@ -0,0 +1,608 @@ +/* + *------------------------------------------------------------------ + * + * m68302.h - Definitions for Motorola MC68302 processor. + * + * Section references in this file refer to revision 2 of Motorola's + * "MC68302 Integrated Multiprotocol Processor User's Manual". + * (Motorola document MC68302UM/AD REV 2.) + * + * Based on Don Meyer's cpu68302.h that was posted in comp.sys.m68k + * on 17 February, 1993. + * + * Copyright 1995 David W. Glessner. + * + * Redistribution and use in source and binary forms are permitted + * provided that the following conditions are met: + * 1. Redistribution of source code and documentation must retain + * the above copyright notice, this list of conditions and the + * following disclaimer. + * 2. The name of the author may not be used to endorse or promote + * products derived from this software without specific prior + * written permission. + * + * This software is provided "AS IS" without warranty of any kind, + * either expressed or implied, including, but not limited to, the + * implied warranties of merchantability, title and fitness for a + * particular purpose. + * + * + * $Id$ + * + *------------------------------------------------------------------ + */ + +#ifndef __MOTOROLA_MC68302_DEFINITIONS_h +#define __MOTOROLA_MC68302_DEFINITIONS_h + +/* + * BAR - Base Address Register + * Section 2.7 + */ +#define M302_BAR (*((volatile rtems_unsigned16 *) 0xf2)) + +/* + * SCR - System Control Register + * Section 3.8.1 + */ +#define M302_SCR (*((volatile rtems_unsigned32 *) 0xf4)) +/* + * SCR bits + */ +#define RBIT_SCR_IPA 0x08000000 +#define RBIT_SCR_HWT 0x04000000 +#define RBIT_SCR_WPV 0x02000000 +#define RBIT_SCR_ADC 0x01000000 + +#define RBIT_SCR_ERRE 0x00400000 +#define RBIT_SCR_VGE 0x00200000 +#define RBIT_SCR_WPVE 0x00100000 +#define RBIT_SCR_RMCST 0x00080000 +#define RBIT_SCR_EMWS 0x00040000 +#define RBIT_SCR_ADCE 0x00020000 +#define RBIT_SCR_BCLM 0x00010000 + +#define RBIT_SCR_FRZW 0x00008000 +#define RBIT_SCR_FRZ2 0x00004000 +#define RBIT_SCR_FRZ1 0x00002000 +#define RBIT_SCR_SAM 0x00001000 +#define RBIT_SCR_HWDEN 0x00000800 +#define RBIT_SCR_HWDCN2 0x00000400 +#define RBIT_SCR_HWDCN1 0x00000200 +#define RBIT_SCR_HWDCN0 0x00000100 + +#define RBIT_SCR_LPREC 0x00000080 +#define RBIT_SCR_LPP16 0x00000040 +#define RBIT_SCR_LPEN 0x00000020 +#define RBIT_SCR_LPCLKDIV 0x0000001f + + +/* + * 68000 interrupt and trap vector numbers + */ +#define M68K_IVEC_BUS_ERROR 2 +#define M68K_IVEC_ADDRESS_ERROR 3 +#define M68K_IVEC_ILLEGAL_OPCODE 4 +#define M68K_IVEC_ZERO_DIVIDE 5 +#define M68K_IVEC_CHK 6 +#define M68K_IVEC_TRAPV 7 +#define M68K_IVEC_PRIVILEGE 8 +#define M68K_IVEC_TRACE 9 +#define M68K_IVEC_LINE_A 10 +#define M68K_IVEC_LINE_F 11 +/* Unassigned, Reserved 12-14 */ +#define M68K_IVEC_UNINITIALIZED_INT 15 +/* Unassigned, Reserved 16-23 */ +#define M68K_IVEC_SPURIOUS_INT 24 + +#define M68K_IVEC_LEVEL1_AUTOVECTOR 25 +#define M68K_IVEC_LEVEL2_AUTOVECTOR 26 +#define M68K_IVEC_LEVEL3_AUTOVECTOR 27 +#define M68K_IVEC_LEVEL4_AUTOVECTOR 28 +#define M68K_IVEC_LEVEL5_AUTOVECTOR 29 +#define M68K_IVEC_LEVEL6_AUTOVECTOR 30 +#define M68K_IVEC_LEVEL7_AUTOVECTOR 31 + +#define M68K_IVEC_TRAP0 32 +#define M68K_IVEC_TRAP1 33 +#define M68K_IVEC_TRAP2 34 +#define M68K_IVEC_TRAP3 35 +#define M68K_IVEC_TRAP4 36 +#define M68K_IVEC_TRAP5 37 +#define M68K_IVEC_TRAP6 38 +#define M68K_IVEC_TRAP7 39 +#define M68K_IVEC_TRAP8 40 +#define M68K_IVEC_TRAP9 41 +#define M68K_IVEC_TRAP10 42 +#define M68K_IVEC_TRAP11 43 +#define M68K_IVEC_TRAP12 44 +#define M68K_IVEC_TRAP13 45 +#define M68K_IVEC_TRAP14 46 +#define M68K_IVEC_TRAP15 47 +/* + * Unassigned, Reserved 48-59 + * + * Note: Vectors 60-63 are used by the MC68302 (e.g. BAR, SCR). + */ + +/* + * MC68302 Interrupt Vectors + * Section 3.2 + */ +enum m68302_ivec_e { + M302_IVEC_ERR =0, + M302_IVEC_PB8 =1, /* General-Purpose Interrupt 0 */ + M302_IVEC_SMC2 =2, + M302_IVEC_SMC1 =3, + M302_IVEC_TIMER3 =4, + M302_IVEC_SCP =5, + M302_IVEC_TIMER2 =6, + M302_IVEC_PB9 =7, /* General-Purpose Interrupt 1 */ + M302_IVEC_SCC3 =8, + M302_IVEC_TIMER1 =9, + M302_IVEC_SCC2 =10, + M302_IVEC_IDMA =11, + M302_IVEC_SDMA =12, /* SDMA Channels Bus Error */ + M302_IVEC_SCC1 =13, + M302_IVEC_PB10 =14, /* General-Purpose Interrupt 2 */ + M302_IVEC_PB11 =15, /* General-Purpose Interrupt 3 */ + M302_IVEC_IRQ1 =17, /* External Device */ + M302_IVEC_IRQ6 =22, /* External Device */ + M302_IVEC_IRQ7 =23 /* External Device */ +}; + + +/* + * GIMR - Global Interrupt Mode Register + * Section 3.2.5.1 + */ +#define RBIT_GIMR_MOD (1<<15) +#define RBIT_GIMR_IV7 (1<<14) +#define RBIT_GIMR_IV6 (1<<13) +#define RBIT_GIMR_IV1 (1<<12) +#define RBIT_GIMR_ET7 (1<<10) +#define RBIT_GIMR_ET6 (1<<9) +#define RBIT_GIMR_ET1 (1<<8) +#define RBIT_GIMR_VECTOR (7<<5) + +/* + * IPR - Interrupt Pending Register (Section 3.2.5.2) + * IMR - Interrupt Mask Register (Section 3.2.5.3) + * ISR - Interrupt In-Service Register (Section 3.2.5.4) + */ +#define RBIT_IPR_PB11 (1<<15) +#define RBIT_IPR_PB10 (1<<14) +#define RBIT_IPR_SCC1 (1<<13) +#define RBIT_IPR_SDMA (1<<12) +#define RBIT_IPR_IDMA (1<<11) +#define RBIT_IPR_SCC2 (1<<10) +#define RBIT_IPR_TIMER1 (1<<9) +#define RBIT_IPR_SCC3 (1<<8) +#define RBIT_IPR_PB9 (1<<7) +#define RBIT_IPR_TIMER2 (1<<6) +#define RBIT_IPR_SCP (1<<5) +#define RBIT_IPR_TIMER3 (1<<4) +#define RBIT_IPR_SMC1 (1<<3) +#define RBIT_IPR_SMC2 (1<<2) +#define RBIT_IPR_PB8 (1<<1) +#define RBIT_IPR_ERR (1<<0) + +#define RBIT_ISR_PB11 (1<<15) +#define RBIT_ISR_PB10 (1<<14) +#define RBIT_ISR_SCC1 (1<<13) +#define RBIT_ISR_SDMA (1<<12) +#define RBIT_ISR_IDMA (1<<11) +#define RBIT_ISR_SCC2 (1<<10) +#define RBIT_ISR_TIMER1 (1<<9) +#define RBIT_ISR_SCC3 (1<<8) +#define RBIT_ISR_PB9 (1<<7) +#define RBIT_ISR_TIMER2 (1<<6) +#define RBIT_ISR_SCP (1<<5) +#define RBIT_ISR_TIMER3 (1<<4) +#define RBIT_ISR_SMC1 (1<<3) +#define RBIT_ISR_SMC2 (1<<2) +#define RBIT_ISR_PB8 (1<<1) + +#define RBIT_IMR_PB11 (1<<15) /* PB11 Interrupt Mask */ +#define RBIT_IMR_PB10 (1<<14) /* PB10 Interrupt Mask */ +#define RBIT_IMR_SCC1 (1<<13) /* SCC1 Interrupt Mask */ +#define RBIT_IMR_SDMA (1<<12) /* SDMA Interrupt Mask */ +#define RBIT_IMR_IDMA (1<<11) /* IDMA Interrupt Mask */ +#define RBIT_IMR_SCC2 (1<<10) /* SCC2 Interrupt Mask */ +#define RBIT_IMR_TIMER1 (1<<9) /* TIMER1 Interrupt Mask */ +#define RBIT_IMR_SCC3 (1<<8) /* SCC3 Interrupt Mask */ +#define RBIT_IMR_PB9 (1<<7) /* PB9 Interrupt Mask */ +#define RBIT_IMR_TIMER2 (1<<6) /* TIMER2 Interrupt Mask */ +#define RBIT_IMR_SCP (1<<5) /* SCP Interrupt Mask */ +#define RBIT_IMR_TIMER3 (1<<4) /* TIMER3 Interrupt Mask */ +#define RBIT_IMR_SMC1 (1<<3) /* SMC1 Interrupt Mask */ +#define RBIT_IMR_SMC2 (1<<2) /* SMC2 Interrupt Mask */ +#define RBIT_IMR_PB8 (1<<1) /* PB8 Interrupt Mask */ + + +/* + * DRAM Refresh + * Section 3.9 + * + * The DRAM refresh memory map replaces the SCC2 Tx BD 6 and Tx BD 7 + * structures in the parameter RAM. + * + * Access to the DRAM registers can be accomplished by + * the following approach: + * + * volatile m302_DRAM_refresh_t *dram; + * dram = (volatile m302_DRAM_refresh_t *) &m302.scc2.bd.tx[6]; + * + * Then simply use pointer references (e.g. dram->count = 3). + */ +typedef struct { + rtems_unsigned16 dram_high; /* DRAM high address and FC */ + rtems_unsigned16 dram_low; /* DRAM low address */ + rtems_unsigned16 increment; /* increment step (bytes/row) */ + rtems_unsigned16 count; /* RAM refresh cycle count (#rows) */ + rtems_unsigned16 t_ptr_h; /* temporary refresh high addr & FC */ + rtems_unsigned16 t_ptr_l; /* temporary refresh low address */ + rtems_unsigned16 t_count; /* temporary refresh cycles count */ + rtems_unsigned16 res; /* reserved */ +} m302_DRAM_refresh_t; + + +/* + * TMR - Timer Mode Register (for timers 1 and 2) + * Section 3.5.2.1 + */ +#define RBIT_TMR_ICLK_STOP (0<<1) +#define RBIT_TMR_ICLK_MASTER (1<<1) +#define RBIT_TMR_ICLK_MASTER16 (2<<1) +#define RBIT_TMR_ICLK_TIN (3<<1) + +#define RBIT_TMR_OM (1<<5) +#define RBIT_TMR_ORI (1<<4) +#define RBIT_TMR_FRR (1<<3) +#define RBIT_TMR_RST (1<<0) + + +/* + * TER - Timer Event Register (for timers 1 and 2) + * Section 3.5.2.5 + */ +#define RBIT_TER_REF (1<<1) /* Output Reference Event */ +#define RBIT_TER_CAP (1<<0) /* Capture Event */ + + +/* + * SCC Buffer Descriptors and Buffer Descriptors Table + * Section 4.5.5 + */ +typedef struct m302_SCC_bd { + rtems_unsigned16 status; /* status and control */ + rtems_unsigned16 length; /* data length */ + rtems_unsigned8 *buffer; /* data buffer pointer */ +} m302_SCC_bd_t; + +typedef struct { + m302_SCC_bd_t rx[8]; /* receive buffer descriptors */ + m302_SCC_bd_t tx[8]; /* transmit buffer descriptors */ +} m302_SCC_bd_table_t; + + +/* + * SCC Parameter RAM (offset 0x080 from an SCC Base) + * Section 4.5.6 + * + * Each SCC parameter RAM area begins at offset 0x80 from each SCC base + * area (0x400, 0x500, or 0x600 from the dual-port RAM base). + * + * Offsets 0x9c-0xbf from each SCC base area compose the protocol-specific + * portion of the SCC parameter RAM. + */ +typedef struct { + rtems_unsigned8 rfcr; /* Rx Function Code */ + rtems_unsigned8 tfcr; /* Tx Function Code */ + rtems_unsigned16 mrblr; /* Maximum Rx Buffer Length */ + rtems_unsigned16 _rstate; /* Rx Internal State */ + rtems_unsigned8 res2; + rtems_unsigned8 rbd; /* Rx Internal Buffer Number */ + rtems_unsigned32 _rdptr; /* Rx Internal Data Pointer */ + rtems_unsigned16 _rcount; /* Rx Internal Byte Count */ + rtems_unsigned16 _rtmp; /* Rx Temp */ + rtems_unsigned16 _tstate; /* Tx Internal State */ + rtems_unsigned8 res7; + rtems_unsigned8 tbd; /* Tx Internal Buffer Number */ + rtems_unsigned32 _tdptr; /* Tx Internal Data Pointer */ + rtems_unsigned16 _tcount; /* Tx Internal Byte Count */ + rtems_unsigned16 _ttmp; /* Tx Temp */ +} m302_SCC_parameters_t; + +/* + * UART-Specific SCC Parameter RAM + * Section 4.5.11.3 + */ +typedef struct { + rtems_unsigned16 max_idl; /* Maximum IDLE Characters (rx) */ + rtems_unsigned16 idlc; /* Temporary rx IDLE counter */ + rtems_unsigned16 brkcr; /* Break Count Register (tx) */ + rtems_unsigned16 parec; /* Receive Parity Error Counter */ + rtems_unsigned16 frmec; /* Receive Framing Error Counter */ + rtems_unsigned16 nosec; /* Receive Noise Counter */ + rtems_unsigned16 brkec; /* Receive Break Condition Counter */ + rtems_unsigned16 uaddr1; /* UART ADDRESS Character 1 */ + rtems_unsigned16 uaddr2; /* UART ADDRESS Character 2 */ + rtems_unsigned16 rccr; /* Receive Control Character Register */ + rtems_unsigned16 character[8]; /* Control Characters 1 through 8*/ +} m302_SCC_UartSpecific_t; +/* + * This definition allows for the checking of receive buffers + * for errors. + */ + +#define RCV_ERR 0x003F + +/* + * UART receive buffer descriptor bit definitions. + * Section 4.5.11.14 + */ +#define RBIT_UART_CTRL (1<<11) /* buffer contains a control char */ +#define RBIT_UART_ADDR (1<<10) /* first byte contains an address */ +#define RBIT_UART_MATCH (1<<9) /* indicates which addr char matched */ +#define RBIT_UART_IDLE (1<<8) /* buffer closed due to IDLE sequence */ +#define RBIT_UART_BR (1<<5) /* break sequence was received */ +#define RBIT_UART_FR (1<<4) /* framing error was received */ +#define RBIT_UART_PR (1<<3) /* parity error was received */ +#define RBIT_UART_OV (1<<1) /* receiver overrun occurred */ +#define RBIT_UART_CD (1<<0) /* carrier detect lost */ +#define RBIT_UART_STATUS 0x003B /* all status bits */ + +/* + * UART transmit buffer descriptor bit definitions. + * Section 4.5.11.15 + */ +#define RBIT_UART_CR (1<<11) /* clear-to-send report + * this results in two idle bits + * between back-to-back frames + */ +#define RBIT_UART_A (1<<10) /* buffer contains address characters + * only valid in multidrop mode (UM0=1) + */ +#define RBIT_UART_PREAMBLE (1<<9) /* send preamble before data */ +#define RBIT_UART_CTS_LOST (1<<0) /* CTS lost */ + +/* + * UART event register + * Section 4.5.11.16 + */ +#define M302_UART_EV_CTS (1<<7) /* CTS status changed */ +#define M302_UART_EV_CD (1<<6) /* carrier detect status changed */ +#define M302_UART_EV_IDL (1<<5) /* IDLE sequence status changed */ +#define M302_UART_EV_BRK (1<<4) /* break character was received */ +#define M302_UART_EV_CCR (1<<3) /* control character received */ +#define M302_UART_EV_TX (1<<1) /* buffer has been transmitted */ +#define M302_UART_EV_RX (1<<0) /* buffer has been received */ + + +/* + * HDLC-Specific SCC Parameter RAM + * Section 4.5.12.3 + * + * c_mask_l should be 0xF0B8 for 16-bit CRC, 0xdebb for 32-bit CRC + * c_mask_h is a don't care for 16-bit CRC, 0x20E2 for 32-bit CRC + */ +typedef struct { + rtems_unsigned16 rcrc_l; /* Temp Receive CRC Low */ + rtems_unsigned16 rcrc_h; /* Temp Receive CRC High */ + rtems_unsigned16 c_mask_l; /* CRC Mask Low */ + rtems_unsigned16 c_mask_h; /* CRC Mask High */ + rtems_unsigned16 tcrc_l; /* Temp Transmit CRC Low */ + rtems_unsigned16 tcrc_h; /* Temp Transmit CRC High */ + + rtems_unsigned16 disfc; /* Discard Frame Counter */ + rtems_unsigned16 crcec; /* CRC Error Counter */ + rtems_unsigned16 abtsc; /* Abort Sequence Counter */ + rtems_unsigned16 nmarc; /* Nonmatching Address Received Cntr */ + rtems_unsigned16 retrc; /* Frame Retransmission Counter */ + + rtems_unsigned16 mflr; /* Maximum Frame Length Register */ + rtems_unsigned16 max_cnt; /* Maximum_Length Counter */ + + rtems_unsigned16 hmask; /* User Defined Frame Address Mask */ + rtems_unsigned16 haddr1; /* User Defined Frame Address */ + rtems_unsigned16 haddr2; /* " */ + rtems_unsigned16 haddr3; /* " */ + rtems_unsigned16 haddr4; /* " */ +} m302_SCC_HdlcSpecific_t; +/* + * HDLC receiver buffer descriptor bit definitions + * Section 4.5.12.10 + */ +#define RBIT_HDLC_EMPTY_BIT 0x8000 /* buffer associated with BD is empty */ +#define RBIT_HDLC_LAST_BIT 0x0800 /* buffer is last in a frame */ +#define RBIT_HDLC_FIRST_BIT 0x0400 /* buffer is first in a frame */ +#define RBIT_HDLC_FRAME_LEN 0x0020 /* receiver frame length violation */ +#define RBIT_HDLC_NONOCT_Rx 0x0010 /* received non-octet aligned frame */ +#define RBIT_HDLC_ABORT_SEQ 0x0008 /* received abort sequence */ +#define RBIT_HDLC_CRC_ERROR 0x0004 /* frame contains a CRC error */ +#define RBIT_HDLC_OVERRUN 0x0002 /* receiver overrun occurred */ +#define RBIT_HDLC_CD_LOST 0x0001 /* carrier detect lost */ + +/* + * HDLC transmit buffer descriptor bit definitions + * Section 4.5.12.11 + */ +#define RBIT_HDLC_READY_BIT 0x8000 /* buffer is ready to transmit */ +#define RBIT_HDLC_EXT_BUFFER 0x4000 /* buffer is in external memory */ +#define RBIT_HDLC_WRAP_BIT 0x2000 /* last buffer in bd table, so wrap */ +#define RBIT_HDLC_WAKE_UP 0x1000 /* interrupt when buffer serviced */ +#define RBIT_HDLC_LAST_BIT 0x0800 /* buffer is last in the frame */ +#define RBIT_HDLC_TxCRC_BIT 0x0400 /* transmit a CRC sequence */ +#define RBIT_HDLC_UNDERRUN 0x0002 /* transmitter underrun */ +#define RBIT_HDLC_CTS_LOST 0x0001 /* CTS lost */ + +/* + * HDLC event register bit definitions + * Section 4.5.12.12 + */ +#define RBIT_HDLC_CTS 0x80 /* CTS status changed */ +#define RBIT_HDLC_CD 0x40 /* carrier detect status changed */ +#define RBIT_HDLC_IDL 0x20 /* IDLE sequence status changed */ +#define RBIT_HDLC_TXE 0x10 /* transmit error */ +#define RBIT_HDLC_RXF 0x08 /* received frame */ +#define RBIT_HDLC_BSY 0x04 /* frame rcvd and discarded due to + * lack of buffers + */ +#define RBIT_HDLC_TXB 0x02 /* buffer has been transmitted */ +#define RBIT_HDLC_RXB 0x01 /* received buffer */ + + + +typedef struct { + m302_SCC_bd_table_t bd; /* +000 Buffer Descriptor Table */ + m302_SCC_parameters_t parm; /* +080 Common Parameter RAM */ + union { /* +09C Protocol-Specific Parm RAM */ + m302_SCC_UartSpecific_t uart; + m302_SCC_HdlcSpecific_t hdlc; + } prot; + rtems_unsigned8 res[0x040]; /* +0C0 reserved, (not implemented) */ +} m302_SCC_t; + + +/* + * Common SCC Registers + */ +typedef struct { + rtems_unsigned16 res1; + rtems_unsigned16 scon; /* SCC Configuration Register 4.5.2 */ + rtems_unsigned16 scm; /* SCC Mode Register 4.5.3 */ + rtems_unsigned16 dsr; /* SCC Data Synchronization Register 4.5.4 */ + rtems_unsigned8 scce; /* SCC Event Register 4.5.8.1 */ + rtems_unsigned8 res2; + rtems_unsigned8 sccm; /* SCC Mask Register 4.5.8.2 */ + rtems_unsigned8 res3; + rtems_unsigned8 sccs; /* SCC Status Register 4.5.8.3 */ + rtems_unsigned8 res4; + rtems_unsigned16 res5; +} m302_SCC_Registers_t; + +/* + * SCON - SCC Configuration Register + * Section 4.5.2 + */ +#define RBIT_SCON_WOMS (1<<15) /* Wired-OR Mode Select (NMSI mode only) + * When set, the TXD driver is an + * open-drain output */ +#define RBIT_SCON_EXTC (1<<14) /* External Clock Source */ +#define RBIT_SCON_TCS (1<<13) /* Transmit Clock Source */ +#define RBIT_SCON_RCS (1<<12) /* Receive Clock Source */ + +/* + * SCM - SCC Mode Register bit definitions + * Section 4.5.3 + * The parameter-specific mode bits occupy bits 15 through 6. + */ +#define RBIT_SCM_ENR (1<<3) /* Enable receiver */ +#define RBIT_SCM_ENT (1<<2) /* Enable transmitter */ + + +/* + * Internal MC68302 Registers + * starts at offset 0x800 from dual-port RAM base + * Section 2.8 + */ +typedef struct { + /* offset +800 */ + rtems_unsigned16 res0; + rtems_unsigned16 cmr; /* IDMA Channel Mode Register */ + rtems_unsigned32 sapr; /* IDMA Source Address Pointer */ + rtems_unsigned32 dapr; /* IDMA Destination Address Pointer */ + rtems_unsigned16 bcr; /* IDMA Byte Count Register */ + rtems_unsigned8 csr; /* IDMA Channel Status Register */ + rtems_unsigned8 res1; + rtems_unsigned8 fcr; /* IDMA Function Code Register */ + rtems_unsigned8 res2; + + /* offset +812 */ + rtems_unsigned16 gimr; /* Global Interrupt Mode Register */ + rtems_unsigned16 ipr; /* Interrupt Pending Register */ + rtems_unsigned16 imr; /* Interrupt Mask Register */ + rtems_unsigned16 isr; /* Interrupt In-Service Register */ + rtems_unsigned16 res3; + rtems_unsigned16 res4; + + /* offset +81e */ + rtems_unsigned16 pacnt; /* Port A Control Register */ + rtems_unsigned16 paddr; /* Port A Data Direction Register */ + rtems_unsigned16 padat; /* Port A Data Register */ + rtems_unsigned16 pbcnt; /* Port B Control Register */ + rtems_unsigned16 pbddr; /* Port B Data Direction Register */ + rtems_unsigned16 pbdat; /* Port B Data Register */ + rtems_unsigned16 res5; + + /* offset +82c */ + rtems_unsigned16 res6; + rtems_unsigned16 res7; + rtems_unsigned16 br0; /* Base Register (CS0) */ + rtems_unsigned16 or0; /* Option Register (CS0) */ + rtems_unsigned16 br1; /* Base Register (CS1) */ + rtems_unsigned16 or1; /* Option Register (CS1) */ + rtems_unsigned16 br2; /* Base Register (CS2) */ + rtems_unsigned16 or2; /* Option Register (CS2) */ + rtems_unsigned16 br3; /* Base Register (CS3) */ + rtems_unsigned16 or3; /* Option Register (CS3) */ + + /* offset +840 */ + rtems_unsigned16 tmr1; /* Timer Unit 1 Mode Register */ + rtems_unsigned16 trr1; /* Timer Unit 1 Reference Register */ + rtems_unsigned16 tcr1; /* Timer Unit 1 Capture Register */ + rtems_unsigned16 tcn1; /* Timer Unit 1 Counter */ + rtems_unsigned8 res8; + rtems_unsigned8 ter1; /* Timer Unit 1 Event Register */ + rtems_unsigned16 wrr; /* Watchdog Reference Register */ + rtems_unsigned16 wcn; /* Watchdog Counter */ + rtems_unsigned16 res9; + rtems_unsigned16 tmr2; /* Timer Unit 2 Mode Register */ + rtems_unsigned16 trr2; /* Timer Unit 2 Reference Register */ + rtems_unsigned16 tcr2; /* Timer Unit 2 Capture Register */ + rtems_unsigned16 tcn2; /* Timer Unit 2 Counter */ + rtems_unsigned8 resa; + rtems_unsigned8 ter2; /* Timer Unit 2 Event Register */ + rtems_unsigned16 resb; + rtems_unsigned16 resc; + rtems_unsigned16 resd; + + /* offset +860 */ + rtems_unsigned8 cr; /* Command Register */ + rtems_unsigned8 rese[0x1f]; + + /* offset +880, +890, +8a0 */ + m302_SCC_Registers_t scc[3]; /* SCC1, SCC2, SCC3 Registers */ + + /* offset +8b0 */ + rtems_unsigned16 spmode; /* SCP,SMC Mode and Clock Cntrl Reg */ + rtems_unsigned16 simask; /* Serial Interface Mask Register */ + rtems_unsigned16 simode; /* Serial Interface Mode Register */ +} m302_internalReg_t ; + + +/* + * MC68302 dual-port RAM structure. + * (Includes System RAM, Parameter RAM, and Internal Registers). + * Section 2.8 + */ +typedef struct { + rtems_unsigned8 mem[0x240]; /* +000 User Data Memory */ + rtems_unsigned8 res1[0x1c0]; /* +240 reserved, (not implemented) */ + m302_SCC_t scc1; /* +400 SCC1 */ + m302_SCC_t scc2; /* +500 SCC2 */ + m302_SCC_t scc3; /* +600 SCC3 */ + rtems_unsigned8 res2[0x100]; /* +700 reserved, (not implemented) */ + m302_internalReg_t reg; /* +800 68302 Internal Registers */ +} m302_dualPortRAM_t; + + +/* + * Declare the variable that's used to reference the variables in + * the dual-port RAM. + */ +extern volatile m302_dualPortRAM_t m302; + +#endif +/* end of include file */ |