diff options
| -rw-r--r-- | doc/supplements/mips64orion/ChangeLog | 4 | ||||
| -rw-r--r-- | doc/supplements/mips64orion/intr_NOTIMES.t | 4 | ||||
| -rw-r--r-- | doc/supplements/mips64orion/timeBSP.t | 14 | ||||
| -rw-r--r-- | doc/supplements/sh/ChangeLog | 4 | ||||
| -rw-r--r-- | doc/supplements/sh/intr_NOTIMES.t | 8 | ||||
| -rw-r--r-- | doc/supplements/sh/timeBSP.t | 20 | ||||
| -rw-r--r-- | doc/supplements/template/ChangeLog | 4 | ||||
| -rw-r--r-- | doc/supplements/template/intr_NOTIMES.t | 2 | ||||
| -rw-r--r-- | doc/supplements/template/timeBSP.t | 18 |
9 files changed, 51 insertions, 27 deletions
diff --git a/doc/supplements/mips64orion/ChangeLog b/doc/supplements/mips64orion/ChangeLog index e869715868..43f3af133f 100644 --- a/doc/supplements/mips64orion/ChangeLog +++ b/doc/supplements/mips64orion/ChangeLog @@ -1,3 +1,7 @@ +2002-07-30 Joel Sherrill <joel@OARcorp.com> + + * intr_NOTIMES.t, timeBSP.t: Replaced XXX's with real info. + 2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> * Makefile.am: Remove AUTOMAKE_OPTIONS. diff --git a/doc/supplements/mips64orion/intr_NOTIMES.t b/doc/supplements/mips64orion/intr_NOTIMES.t index 04e4dff717..fd4ca3aa9c 100644 --- a/doc/supplements/mips64orion/intr_NOTIMES.t +++ b/doc/supplements/mips64orion/intr_NOTIMES.t @@ -167,7 +167,7 @@ the execution of this section and restores them to the previous level upon completion of the section. RTEMS has been optimized to insure that interrupts are disabled for less than RTEMS_MAXIMUM_DISABLE_PERIOD microseconds on a -RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ Mhz XXX with +RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ Mhz processor with zero wait states. These numbers will vary based the number of wait states and processor speed present on the target board. [NOTE: The maximum period with interrupts disabled is hand calculated. This @@ -189,7 +189,7 @@ interrupt stack is determined by the interrupt_stack_size field in the CPU Configuration Table. During the initialization process, RTEMS will install its interrupt stack. -The XXX port of RTEMS supports a software managed +The mips64orion port of RTEMS supports a software managed dedicated interrupt stack on those CPU models which do not support a separate interrupt stack in hardware. diff --git a/doc/supplements/mips64orion/timeBSP.t b/doc/supplements/mips64orion/timeBSP.t index 63877b8de3..efce892858 100644 --- a/doc/supplements/mips64orion/timeBSP.t +++ b/doc/supplements/mips64orion/timeBSP.t @@ -27,7 +27,8 @@ times as they pertain to the XXX version of RTEMS. All times reported except for the maximum period interrupts are disabled by RTEMS were measured using a Motorola -BSP_FOR_TIMES CPU board. The BSP_FOR_TIMES is a 20Mhz board with one wait +BSP_FOR_TIMES CPU board. The BSP_FOR_TIMES is a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ +Mhz board with one wait state dynamic memory and a XXX numeric coprocessor. The Zilog 8036 countdown timer on this board was used to measure elapsed time with a one-half microsecond resolution. All @@ -41,7 +42,8 @@ disabled. The worst case times of the XXX microprocessor were used for each instruction. Zero wait state memory was assumed. The total CPU cycles executed with interrupts disabled, including the instructions to disable and enable -interrupts, was divided by 20 to simulate a 20Mhz XXX. It +interrupts, was divided by 20 to simulate a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ +Mhz processor. It should be noted that the worst case instruction times for the XXX assume that the internal cache is disabled and that no instructions overlap. @@ -52,20 +54,22 @@ The maximum period with interrupts disabled within RTEMS is less than RTEMS_MAXIMUM_DISABLE_PERIOD microseconds including the instructions which disable and re-enable interrupts. The time required for -the XXX to vector an interrupt and for the RTEMS entry +the mips64orion to vector an interrupt and for the RTEMS entry overhead before invoking the user's interrupt handler are a total of RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK microseconds. These combine to yield a worst case interrupt latency of less than RTEMS_MAXIMUM_DISABLE_PERIOD + RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK -microseconds at 20Mhz. [NOTE: The maximum period with interrupts +microseconds at RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ +Mhz. [NOTE: The maximum period with interrupts disabled was last determined for Release RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.] It should be noted again that the maximum period with interrupts disabled within RTEMS is hand-timed and based upon worst case (i.e. CPU cache disabled and no instruction overlap) -times for a 20Mhz XXX. The interrupt vector and entry +times for a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ +Mhz processor. The interrupt vector and entry overhead time was generated on an BSP_FOR_TIMES benchmark platform using the Multiprocessing Communications registers to generate as the interrupt source. diff --git a/doc/supplements/sh/ChangeLog b/doc/supplements/sh/ChangeLog index e869715868..43f3af133f 100644 --- a/doc/supplements/sh/ChangeLog +++ b/doc/supplements/sh/ChangeLog @@ -1,3 +1,7 @@ +2002-07-30 Joel Sherrill <joel@OARcorp.com> + + * intr_NOTIMES.t, timeBSP.t: Replaced XXX's with real info. + 2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> * Makefile.am: Remove AUTOMAKE_OPTIONS. diff --git a/doc/supplements/sh/intr_NOTIMES.t b/doc/supplements/sh/intr_NOTIMES.t index 04e4dff717..d642ce1ddf 100644 --- a/doc/supplements/sh/intr_NOTIMES.t +++ b/doc/supplements/sh/intr_NOTIMES.t @@ -23,19 +23,19 @@ special control mechanisms to return to the normal processing stream. Although RTEMS hides many of the processor dependent details of interrupt processing, it is important to understand how the RTEMS interrupt manager is mapped onto the processor's -unique architecture. Discussed in this chapter are the XXX's +unique architecture. Discussed in this chapter are the SH's interrupt response and control mechanisms as they pertain to RTEMS. @section Vectoring of an Interrupt Handler Depending on whether or not the particular CPU -supports a separate interrupt stack, the XXX family has two +supports a separate interrupt stack, the SH family has two different interrupt handling models. @subsection Models Without Separate Interrupt Stacks -Upon receipt of an interrupt the XXX family +Upon receipt of an interrupt the SH family members without separate interrupt stacks automatically perform the following actions: @@ -45,7 +45,7 @@ the following actions: @subsection Models With Separate Interrupt Stacks -Upon receipt of an interrupt the XXX family +Upon receipt of an interrupt the SH family members with separate interrupt stacks automatically perform the following actions: diff --git a/doc/supplements/sh/timeBSP.t b/doc/supplements/sh/timeBSP.t index 63877b8de3..1439bb56bf 100644 --- a/doc/supplements/sh/timeBSP.t +++ b/doc/supplements/sh/timeBSP.t @@ -15,19 +15,20 @@ @section Introduction -The timing data for the XXX version of RTEMS is +The timing data for the SH version of RTEMS is provided along with the target dependent aspects concerning the gathering of the timing data. The hardware platform used to gather the times is described to give the reader a better understanding of each directive time provided. Also, provided is a description of the interrupt latency and the context switch -times as they pertain to the XXX version of RTEMS. +times as they pertain to the SH version of RTEMS. @section Hardware Platform All times reported except for the maximum period interrupts are disabled by RTEMS were measured using a Motorola -BSP_FOR_TIMES CPU board. The BSP_FOR_TIMES is a 20Mhz board with one wait +BSP_FOR_TIMES CPU board. The BSP_FOR_TIMES is a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ +Mhz board with one wait state dynamic memory and a XXX numeric coprocessor. The Zilog 8036 countdown timer on this board was used to measure elapsed time with a one-half microsecond resolution. All @@ -41,9 +42,10 @@ disabled. The worst case times of the XXX microprocessor were used for each instruction. Zero wait state memory was assumed. The total CPU cycles executed with interrupts disabled, including the instructions to disable and enable -interrupts, was divided by 20 to simulate a 20Mhz XXX. It +interrupts, was divided by 20 to simulate a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ +Mhz processor. It should be noted that the worst case instruction times for the -XXX assume that the internal cache is disabled and that no +processor assume that the internal cache is disabled and that no instructions overlap. @section Interrupt Latency @@ -52,20 +54,22 @@ The maximum period with interrupts disabled within RTEMS is less than RTEMS_MAXIMUM_DISABLE_PERIOD microseconds including the instructions which disable and re-enable interrupts. The time required for -the XXX to vector an interrupt and for the RTEMS entry +the processor to vector an interrupt and for the RTEMS entry overhead before invoking the user's interrupt handler are a total of RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK microseconds. These combine to yield a worst case interrupt latency of less than RTEMS_MAXIMUM_DISABLE_PERIOD + RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK -microseconds at 20Mhz. [NOTE: The maximum period with interrupts +microseconds at RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ +Mhz. [NOTE: The maximum period with interrupts disabled was last determined for Release RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.] It should be noted again that the maximum period with interrupts disabled within RTEMS is hand-timed and based upon worst case (i.e. CPU cache disabled and no instruction overlap) -times for a 20Mhz XXX. The interrupt vector and entry +times for a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ +Mhz processor. The interrupt vector and entry overhead time was generated on an BSP_FOR_TIMES benchmark platform using the Multiprocessing Communications registers to generate as the interrupt source. diff --git a/doc/supplements/template/ChangeLog b/doc/supplements/template/ChangeLog index e869715868..43f3af133f 100644 --- a/doc/supplements/template/ChangeLog +++ b/doc/supplements/template/ChangeLog @@ -1,3 +1,7 @@ +2002-07-30 Joel Sherrill <joel@OARcorp.com> + + * intr_NOTIMES.t, timeBSP.t: Replaced XXX's with real info. + 2002-03-27 Ralf Corsepius <corsepiu@faw.uni-ulm.de> * Makefile.am: Remove AUTOMAKE_OPTIONS. diff --git a/doc/supplements/template/intr_NOTIMES.t b/doc/supplements/template/intr_NOTIMES.t index 04e4dff717..13e4921ea9 100644 --- a/doc/supplements/template/intr_NOTIMES.t +++ b/doc/supplements/template/intr_NOTIMES.t @@ -23,7 +23,7 @@ special control mechanisms to return to the normal processing stream. Although RTEMS hides many of the processor dependent details of interrupt processing, it is important to understand how the RTEMS interrupt manager is mapped onto the processor's -unique architecture. Discussed in this chapter are the XXX's +unique architecture. Discussed in this chapter are the processor's interrupt response and control mechanisms as they pertain to RTEMS. diff --git a/doc/supplements/template/timeBSP.t b/doc/supplements/template/timeBSP.t index 153aa8ffaf..85e5ea44aa 100644 --- a/doc/supplements/template/timeBSP.t +++ b/doc/supplements/template/timeBSP.t @@ -27,12 +27,13 @@ times as they pertain to the XXX version of RTEMS. All times reported except for the maximum period interrupts are disabled by RTEMS were measured using a Motorola -MYBSP CPU board. The MYBSP is a 20Mhz board with one wait +MYBSP CPU board. The MYBSP is a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ +Mhz board with one wait state dynamic memory and a XXX numeric coprocessor. The Zilog 8036 countdown timer on this board was used to measure elapsed time with a one-half microsecond resolution. All sources of hardware interrupts were disabled, although the -interrupt level of the XXX allows all interrupts. +interrupt level of the processor allows all interrupts. The maximum period interrupts are disabled was measured by summing the number of CPU cycles required by each @@ -41,9 +42,10 @@ disabled. The worst case times of the XXX microprocessor were used for each instruction. Zero wait state memory was assumed. The total CPU cycles executed with interrupts disabled, including the instructions to disable and enable -interrupts, was divided by 20 to simulate a 20Mhz XXX. It +interrupts, was divided by 20 to simulate a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ +Mhz processor. It should be noted that the worst case instruction times for the -XXX assume that the internal cache is disabled and that no +processor assume that the internal cache is disabled and that no instructions overlap. @section Interrupt Latency @@ -52,20 +54,22 @@ The maximum period with interrupts disabled within RTEMS is less than RTEMS_MAXIMUM_DISABLE_PERIOD microseconds including the instructions which disable and re-enable interrupts. The time required for -the XXX to vector an interrupt and for the RTEMS entry +the processor to vector an interrupt and for the RTEMS entry overhead before invoking the user's interrupt handler are a total of RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK microseconds. These combine to yield a worst case interrupt latency of less than RTEMS_MAXIMUM_DISABLE_PERIOD + RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK -microseconds at 20Mhz. [NOTE: The maximum period with interrupts +microseconds at RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ +Mhz. [NOTE: The maximum period with interrupts disabled was last determined for Release RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.] It should be noted again that the maximum period with interrupts disabled within RTEMS is hand-timed and based upon worst case (i.e. CPU cache disabled and no instruction overlap) -times for a 20Mhz XXX. The interrupt vector and entry +times for a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ +Mhz processor. The interrupt vector and entry overhead time was generated on an MYBSP benchmark platform using the Multiprocessing Communications registers to generate as the interrupt source. |