diff options
-rw-r--r-- | c/src/lib/libchip/Makefile.in | 14 | ||||
-rw-r--r-- | c/src/lib/libchip/serial/Makefile.in | 59 | ||||
-rw-r--r-- | c/src/lib/libchip/serial/ns16550.c | 608 | ||||
-rw-r--r-- | c/src/lib/libchip/serial/ns16550.h | 40 | ||||
-rw-r--r-- | c/src/lib/libchip/serial/ns16550_p.h | 208 | ||||
-rw-r--r-- | c/src/lib/libchip/serial/z85c30.c | 830 | ||||
-rw-r--r-- | c/src/lib/libchip/serial/z85c30.h | 54 | ||||
-rw-r--r-- | c/src/lib/libchip/serial/z85c30_p.h | 385 | ||||
-rw-r--r-- | c/src/libchip/serial/Makefile.in | 59 | ||||
-rw-r--r-- | c/src/libchip/serial/ns16550.c | 608 | ||||
-rw-r--r-- | c/src/libchip/serial/ns16550.h | 40 | ||||
-rw-r--r-- | c/src/libchip/serial/ns16550_p.h | 208 | ||||
-rw-r--r-- | c/src/libchip/serial/z85c30.c | 830 | ||||
-rw-r--r-- | c/src/libchip/serial/z85c30.h | 54 | ||||
-rw-r--r-- | c/src/libchip/serial/z85c30_p.h | 385 |
15 files changed, 4382 insertions, 0 deletions
diff --git a/c/src/lib/libchip/Makefile.in b/c/src/lib/libchip/Makefile.in new file mode 100644 index 0000000000..5f61d06870 --- /dev/null +++ b/c/src/lib/libchip/Makefile.in @@ -0,0 +1,14 @@ +# +# $Id$ +# + +@SET_MAKE@ +srcdir = @srcdir@ +VPATH = @srcdir@ +RTEMS_ROOT = @top_srcdir@ +PROJECT_ROOT = @PROJECT_ROOT@ + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/directory.cfg + +SUB_DIRS=serial diff --git a/c/src/lib/libchip/serial/Makefile.in b/c/src/lib/libchip/serial/Makefile.in new file mode 100644 index 0000000000..0cc8924ea6 --- /dev/null +++ b/c/src/lib/libchip/serial/Makefile.in @@ -0,0 +1,59 @@ +# +# $Id$ +# + +@SET_MAKE@ +srcdir = @srcdir@ +VPATH = @srcdir@ +RTEMS_ROOT = @top_srcdir@ +PROJECT_ROOT = @PROJECT_ROOT@ + +LIBNAME=libserialio.a +LIB=${ARCH}/${LIBNAME} + +C_PIECES=ns16550 z85c30 +C_FILES=$(C_PIECES:%=%.c) +C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) + +H_FILES=$(srcdir)/libcsupport.h +SYS_H_FILES= +RTEMS_H_FILES=$(srcdir)/libio.h +PRIVATE_H_FILES=$(srcdir)/internal.h + +INSTALLED_H_FILES=$(srcdir)/ns16550.h $(srcdir)/z8530.h +SRCS=$(C_FILES) $(H_FILES) $(SYS_H_FILES) $(RTEMS_H_FILES) $(PRIVATE_H_FILES) +OBJS=$(C_O_FILES) + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/lib.cfg + +# +# Add local stuff here using += +# + +DEFINES += +CPPFLAGS += +CFLAGS += $(LIBC_DEFINES) + +# +# Add your list of files to delete here. The config files +# already know how to delete some stuff, so you may want +# to just run 'make clean' first to see what gets missed. +# 'make clobber' already includes 'make clean' +# + +CLEAN_ADDITIONS += $(LIB) +CLOBBER_ADDITIONS += + +all: ${ARCH} preinstall $(LIB) + $(INSTALL_VARIANT) -m 644 ${LIB} ${PROJECT_RELEASE}/lib + +$(LIB): $(SRCS) ${OBJS} + $(make-library) + +# Install the library, appending _g or _p as appropriate. +# for include files, just use $(INSTALL) +preinstall: + $(INSTALL) -m 444 $(H_FILES) $(PROJECT_INCLUDE)/libchip + + diff --git a/c/src/lib/libchip/serial/ns16550.c b/c/src/lib/libchip/serial/ns16550.c new file mode 100644 index 0000000000..dff820bb70 --- /dev/null +++ b/c/src/lib/libchip/serial/ns16550.c @@ -0,0 +1,608 @@ +/* + * This file contains the TTY driver for the NS16550 + * + * COPYRIGHT (c) 1998 by Radstone Technology + * + * + * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY + * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK + * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU. + * + * You are hereby granted permission to use, copy, modify, and distribute + * this file, provided that this notice, plus the above copyright notice + * and disclaimer, appears in all copies. Radstone Technology will provide + * no support for this code. + * + * This driver uses the termios pseudo driver. + */ + +#include <rtems.h> +#include <rtems/libio.h> +#include <stdlib.h> + +#include "console.h" +#include "ns16550_p.h" + +/* + * Flow control is only supported when using interrupts + */ +console_flow ns16550_flow_RTSCTS = +{ + ns16550_negate_RTS, /* deviceStopRemoteTx */ + ns16550_assert_RTS /* deviceStartRemoteTx */ +}; + +console_flow ns16550_flow_DTRCTS = +{ + ns16550_negate_DTR, /* deviceStopRemoteTx */ + ns16550_assert_DTR /* deviceStartRemoteTx */ +}; + +console_fns ns16550_fns = +{ + ns16550_probe, /* deviceProbe */ + ns16550_open, /* deviceFirstOpen */ + ns16550_flush, /* deviceLastClose */ + NULL, /* deviceRead */ + ns16550_write_support_int, /* deviceWrite */ + ns16550_initialize_interrupts, /* deviceInitialize */ + ns16550_write_polled, /* deviceWritePolled */ + FALSE, /* deviceOutputUsesInterrupts */ +}; + +console_fns ns16550_fns_polled = +{ + ns16550_probe, /* deviceProbe */ + ns16550_open, /* deviceFirstOpen */ + ns16550_close, /* deviceLastClose */ + ns16550_inbyte_nonblocking_polled, /* deviceRead */ + ns16550_write_support_polled, /* deviceWrite */ + ns16550_init, /* deviceInitialize */ + ns16550_write_polled, /* deviceWritePolled */ + FALSE, /* deviceOutputUsesInterrupts */ +}; + +extern void set_vector( rtems_isr_entry, rtems_vector_number, int ); + +/* + * Types for get and set register routines + */ + +typedef unsigned8 (*getRegister_f)(unsigned32 port, unsigned8 register); +typedef void (*setRegister_f)( + unsigned32 port, unsigned8 reg, unsigned8 value); +/* + * Console Device Driver Entry Points + */ +static boolean ns16550_probe(int minor) +{ + /* + * If the configuration dependant probe has located the device then + * assume it is there + */ + return(TRUE); +} + +static void ns16550_init(int minor) +{ + unsigned32 pNS16550; + unsigned8 ucTrash; + unsigned8 ucDataByte; + unsigned32 ulBaudDivisor; + ns16550_context *pns16550Context; + setRegister_f setReg; + getRegister_f getReg; + + pns16550Context=(ns16550_context *)malloc(sizeof(ns16550_context)); + + Console_Port_Data[minor].pDeviceContext=(void *)pns16550Context; + pns16550Context->ucModemCtrl=SP_MODEM_IRQ; + + pNS16550 = Console_Port_Tbl[minor].ulCtrlPort1; + setReg = Console_Port_Tbl[minor].setRegister; + getReg = Console_Port_Tbl[minor].getRegister; + + /* Clear the divisor latch, clear all interrupt enables, + * and reset and + * disable the FIFO's. + */ + + (*setReg)(pNS16550, NS16550_LINE_CONTROL, 0x0); + (*setReg)(pNS16550, NS16550_INTERRUPT_ENABLE, 0x0); + + /* Set the divisor latch and set the baud rate. */ + + ulBaudDivisor=NS16550_Baud((unsigned32)Console_Port_Tbl[minor].pDeviceParams); + ucDataByte = SP_LINE_DLAB; + (*setReg)(pNS16550, NS16550_LINE_CONTROL, ucDataByte); + (*setReg)(pNS16550, NS16550_TRANSMIT_BUFFER, ulBaudDivisor&0xff); + (*setReg)(pNS16550, NS16550_INTERRUPT_ENABLE, (ulBaudDivisor>>8)&0xff); + + /* Clear the divisor latch and set the character size to eight bits */ + /* with one stop bit and no parity checking. */ + ucDataByte = EIGHT_BITS; + (*setReg)(pNS16550, NS16550_LINE_CONTROL, ucDataByte); + + /* Enable and reset transmit and receive FIFOs. TJA */ + ucDataByte = SP_FIFO_ENABLE; + (*setReg)(pNS16550, NS16550_FIFO_CONTROL, ucDataByte); + + ucDataByte = SP_FIFO_ENABLE | SP_FIFO_RXRST | SP_FIFO_TXRST; + (*setReg)(pNS16550, NS16550_FIFO_CONTROL, ucDataByte); + + /* + * Disable interrupts + */ + ucDataByte = 0; + (*setReg)(pNS16550, NS16550_INTERRUPT_ENABLE, ucDataByte); + + /* Set data terminal ready. */ + /* And open interrupt tristate line */ + (*setReg)(pNS16550, NS16550_MODEM_CONTROL,pns16550Context->ucModemCtrl); + + ucTrash = (*getReg)(pNS16550, NS16550_LINE_STATUS ); + ucTrash = (*getReg)(pNS16550, NS16550_RECEIVE_BUFFER ); +} + +static int ns16550_open( + int major, + int minor, + void * arg +) +{ + /* + * Assert DTR + */ + + if(Console_Port_Tbl[minor].pDeviceFlow != &ns16550_flow_DTRCTS) { + ns16550_assert_DTR(minor); + } + + return(RTEMS_SUCCESSFUL); +} + +static int ns16550_close( + int major, + int minor, + void * arg +) +{ + /* + * Negate DTR + */ + if(Console_Port_Tbl[minor].pDeviceFlow != &ns16550_flow_DTRCTS) { + ns16550_negate_DTR(minor); + } + + return(RTEMS_SUCCESSFUL); +} + +/* + * ns16550_write_polled + */ +static void ns16550_write_polled( + int minor, + char cChar +) +{ + unsigned32 pNS16550; + unsigned char ucLineStatus; + int iTimeout; + getRegister_f getReg; + setRegister_f setReg; + + pNS16550 = Console_Port_Tbl[minor].ulCtrlPort1; + getReg = Console_Port_Tbl[minor].getRegister; + setReg = Console_Port_Tbl[minor].setRegister; + + /* + * wait for transmitter holding register to be empty + */ + iTimeout=1000; + ucLineStatus = (*getReg)(pNS16550, NS16550_LINE_STATUS); + while ((ucLineStatus & SP_LSR_THOLD) == 0) { + /* + * Yield while we wait + */ + if(_System_state_Is_up(_System_state_Get())) { + rtems_task_wake_after(RTEMS_YIELD_PROCESSOR); + } + ucLineStatus = (*getReg)(pNS16550, NS16550_LINE_STATUS); + if(!--iTimeout) { + break; + } + } + + /* + * transmit character + */ + (*setReg)(pNS16550, NS16550_TRANSMIT_BUFFER, cChar); +} + +/* + * These routines provide control of the RTS and DTR lines + */ +/* + * ns16550_assert_RTS + */ +static int ns16550_assert_RTS(int minor) +{ + unsigned32 pNS16550; + unsigned32 Irql; + ns16550_context *pns16550Context; + setRegister_f setReg; + + pns16550Context=(ns16550_context *) Console_Port_Data[minor].pDeviceContext; + + pNS16550 = Console_Port_Tbl[minor].ulCtrlPort1; + setReg = Console_Port_Tbl[minor].setRegister; + + /* + * Assert RTS + */ + rtems_interrupt_disable(Irql); + pns16550Context->ucModemCtrl|=SP_MODEM_RTS; + (*setReg)(pNS16550, NS16550_MODEM_CONTROL, pns16550Context->ucModemCtrl); + rtems_interrupt_enable(Irql); + return 0; +} + +/* + * ns16550_negate_RTS + */ +static int ns16550_negate_RTS(int minor) +{ + unsigned32 pNS16550; + unsigned32 Irql; + ns16550_context *pns16550Context; + setRegister_f setReg; + + pns16550Context=(ns16550_context *) Console_Port_Data[minor].pDeviceContext; + + pNS16550 = Console_Port_Tbl[minor].ulCtrlPort1; + setReg = Console_Port_Tbl[minor].setRegister; + + /* + * Negate RTS + */ + rtems_interrupt_disable(Irql); + pns16550Context->ucModemCtrl&=~SP_MODEM_RTS; + (*setReg)(pNS16550, NS16550_MODEM_CONTROL, pns16550Context->ucModemCtrl); + rtems_interrupt_enable(Irql); + return 0; +} + +/* + * These flow control routines utilise a connection from the local DTR + * line to the remote CTS line + */ +/* + * ns16550_assert_DTR + */ +static int ns16550_assert_DTR(int minor) +{ + unsigned32 pNS16550; + unsigned32 Irql; + ns16550_context *pns16550Context; + setRegister_f setReg; + + pns16550Context=(ns16550_context *) Console_Port_Data[minor].pDeviceContext; + + pNS16550 = Console_Port_Tbl[minor].ulCtrlPort1; + setReg = Console_Port_Tbl[minor].setRegister; + + /* + * Assert DTR + */ + rtems_interrupt_disable(Irql); + pns16550Context->ucModemCtrl|=SP_MODEM_DTR; + (*setReg)(pNS16550, NS16550_MODEM_CONTROL, pns16550Context->ucModemCtrl); + rtems_interrupt_enable(Irql); + return 0; +} + +/* + * ns16550_negate_DTR + */ +static int ns16550_negate_DTR(int minor) +{ + unsigned32 pNS16550; + unsigned32 Irql; + ns16550_context *pns16550Context; + setRegister_f setReg; + + pns16550Context=(ns16550_context *) Console_Port_Data[minor].pDeviceContext; + + pNS16550 = Console_Port_Tbl[minor].ulCtrlPort1; + setReg = Console_Port_Tbl[minor].setRegister; + + /* + * Negate DTR + */ + rtems_interrupt_disable(Irql); + pns16550Context->ucModemCtrl&=~SP_MODEM_DTR; + (*setReg)(pNS16550, NS16550_MODEM_CONTROL,pns16550Context->ucModemCtrl); + rtems_interrupt_enable(Irql); + return 0; +} + +/* + * ns16550_isr + * + * This routine is the console interrupt handler for COM1 and COM2 + * + * Input parameters: + * vector - vector number + * + * Output parameters: NONE + * + * Return values: NONE + */ + +static void ns16550_process( + int minor +) +{ + unsigned32 pNS16550; + volatile unsigned8 ucLineStatus; + volatile unsigned8 ucInterruptId; + char cChar; + getRegister_f getReg; + setRegister_f setReg; + + pNS16550 = Console_Port_Tbl[minor].ulCtrlPort1; + getReg = Console_Port_Tbl[minor].getRegister; + setReg = Console_Port_Tbl[minor].setRegister; + + do { + /* + * Deal with any received characters + */ + while(TRUE) { + ucLineStatus = (*getReg)(pNS16550, NS16550_LINE_STATUS); + if(~ucLineStatus & SP_LSR_RDY) { + break; + } + cChar = (*getReg)(pNS16550, NS16550_RECEIVE_BUFFER); + rtems_termios_enqueue_raw_characters( + Console_Port_Data[minor].termios_data, + &cChar, + 1 + ); + } + + while(TRUE) { + if(Ring_buffer_Is_empty(&Console_Port_Data[minor].TxBuffer)) { + Console_Port_Data[minor].bActive=FALSE; + if(Console_Port_Tbl[minor].pDeviceFlow !=&ns16550_flow_RTSCTS) { + ns16550_negate_RTS(minor); + } + + /* + * There is no data to transmit + */ + break; + } + + ucLineStatus = (*getReg)(pNS16550, NS16550_LINE_STATUS); + if(~ucLineStatus & SP_LSR_THOLD) { + /* + * We'll get another interrupt when + * the transmitter holding reg. becomes + * free again + */ + break; + } + + Ring_buffer_Remove_character( &Console_Port_Data[minor].TxBuffer, cChar); + /* + * transmit character + */ + (*setReg)(pNS16550, NS16550_TRANSMIT_BUFFER, cChar); + } + + ucInterruptId = (*getReg)(pNS16550, NS16550_INTERRUPT_ID); + } + while((ucInterruptId&0xf)!=0x1); +} + +static rtems_isr ns16550_isr( + rtems_vector_number vector +) +{ + int minor; + + for(minor=0;minor<Console_Port_Count;minor++) { + if(vector==Console_Port_Tbl[minor].ulIntVector) { + ns16550_process(minor); + } + } +} + +/* + * ns16550_flush + */ +static int ns16550_flush(int major, int minor, void *arg) +{ + while(!Ring_buffer_Is_empty(&Console_Port_Data[minor].TxBuffer)) { + /* + * Yield while we wait + */ + if(_System_state_Is_up(_System_state_Get())) { + rtems_task_wake_after(RTEMS_YIELD_PROCESSOR); + } + } + + ns16550_close(major, minor, arg); + + return(RTEMS_SUCCESSFUL); +} + +/* + * ns16550_initialize_interrupts + * + * This routine initializes the console's receive and transmit + * ring buffers and loads the appropriate vectors to handle the interrupts. + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * Return values: NONE + */ + +static void ns16550_enable_interrupts( + int minor +) +{ + unsigned32 pNS16550; + unsigned8 ucDataByte; + setRegister_f setReg; + + pNS16550 = Console_Port_Tbl[minor].ulCtrlPort1; + setReg = Console_Port_Tbl[minor].setRegister; + + /* + * Enable interrupts + */ + ucDataByte = SP_INT_RX_ENABLE | SP_INT_TX_ENABLE; + (*setReg)(pNS16550, NS16550_INTERRUPT_ENABLE, ucDataByte); + +} + +static void ns16550_initialize_interrupts(int minor) +{ + ns16550_init(minor); + + Ring_buffer_Initialize(&Console_Port_Data[minor].TxBuffer); + + Console_Port_Data[minor].bActive = FALSE; + + set_vector(ns16550_isr, Console_Port_Tbl[minor].ulIntVector, 1); + + ns16550_enable_interrupts(minor); +} + +/* + * ns16550_write_support_int + * + * Console Termios output entry point. + * + */ +static int ns16550_write_support_int( + int minor, + const char *buf, + int len +) +{ + int i; + unsigned32 Irql; + + for(i=0; i<len;) { + if(Ring_buffer_Is_full(&Console_Port_Data[minor].TxBuffer)) { + if(!Console_Port_Data[minor].bActive) { + /* + * Wake up the device + */ + rtems_interrupt_disable(Irql); + Console_Port_Data[minor].bActive = TRUE; + if(Console_Port_Tbl[minor].pDeviceFlow != &ns16550_flow_RTSCTS) { + ns16550_assert_RTS(minor); + } + ns16550_process(minor); + rtems_interrupt_enable(Irql); + } else { + /* + * Yield + */ + rtems_task_wake_after(RTEMS_YIELD_PROCESSOR); + } + + /* + * Wait for ring buffer to empty + */ + continue; + } + else { + Ring_buffer_Add_character( &Console_Port_Data[minor].TxBuffer, buf[i]); + i++; + } + } + + /* + * Ensure that characters are on the way + */ + if(!Console_Port_Data[minor].bActive) { + /* + * Wake up the device + */ + rtems_interrupt_disable(Irql); + Console_Port_Data[minor].bActive = TRUE; + if(Console_Port_Tbl[minor].pDeviceFlow !=&ns16550_flow_RTSCTS) { + ns16550_assert_RTS(minor); + } + ns16550_process(minor); + rtems_interrupt_enable(Irql); + } + + return (len); +} + +/* + * ns16550_write_support_polled + * + * Console Termios output entry point. + * + */ +static int ns16550_write_support_polled( + int minor, + const char *buf, + int len +) +{ + int nwrite = 0; + + /* + * poll each byte in the string out of the port. + */ + while (nwrite < len) { + /* + * transmit character + */ + ns16550_write_polled(minor, *buf++); + nwrite++; + } + + /* + * return the number of bytes written. + */ + return nwrite; +} + +/* + * ns16550_inbyte_nonblocking_polled + * + * Console Termios polling input entry point. + */ + +static int ns16550_inbyte_nonblocking_polled( + int minor +) +{ + unsigned32 pNS16550; + unsigned char ucLineStatus; + char cChar; + getRegister_f getReg; + + pNS16550 = Console_Port_Tbl[minor].ulCtrlPort1; + getReg = Console_Port_Tbl[minor].getRegister; + + ucLineStatus = (*getReg)(pNS16550, NS16550_LINE_STATUS); + if(ucLineStatus & SP_LSR_RDY) { + cChar = (*getReg)(pNS16550, NS16550_RECEIVE_BUFFER); + return((int)cChar); + } else { + return(-1); + } +} diff --git a/c/src/lib/libchip/serial/ns16550.h b/c/src/lib/libchip/serial/ns16550.h new file mode 100644 index 0000000000..e797ba2244 --- /dev/null +++ b/c/src/lib/libchip/serial/ns16550.h @@ -0,0 +1,40 @@ +/* + * COPYRIGHT (c) 1998 by Radstone Technology + * + * + * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY + * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK + * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU. + * + * You are hereby granted permission to use, copy, modify, and distribute + * this file, provided that this notice, plus the above copyright notice + * and disclaimer, appears in all copies. Radstone Technology will provide + * no support for this code. + * + */ + +#ifndef _NS16550_H_ +#define _NS16550_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Driver function table + */ +extern console_fns ns16550_fns; +extern console_fns ns16550_fns_polled; + +/* + * Flow control function tables + */ +extern console_flow ns16550_flow_RTSCTS; +extern console_flow ns16550_flow_DTRCTS; + +#ifdef __cplusplus +} +#endif + +#endif /* _NS16550_H_ */ diff --git a/c/src/lib/libchip/serial/ns16550_p.h b/c/src/lib/libchip/serial/ns16550_p.h new file mode 100644 index 0000000000..9e610119e0 --- /dev/null +++ b/c/src/lib/libchip/serial/ns16550_p.h @@ -0,0 +1,208 @@ +/* + * COPYRIGHT (c) 1998 by Radstone Technology + * + * + * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY + * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK + * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU. + * + * You are hereby granted permission to use, copy, modify, and distribute + * this file, provided that this notice, plus the above copyright notice + * and disclaimer, appears in all copies. Radstone Technology will provide + * no support for this code. + * + */ + +#ifndef _NS16550_P_H_ +#define _NS16550_P_H_ + +#ifdef __cplusplus +extern "C" { +#endif +/* + * Define serial port read registers structure. + */ + +typedef volatile struct _SP_READ_REGISTERS { + unsigned char ReceiveBuffer; + unsigned char InterruptEnable; + unsigned char InterruptId; + unsigned char LineControl; + unsigned char ModemControl; + unsigned char LineStatus; + unsigned char ModemStatus; + unsigned char ScratchPad; +} SP_READ_REGISTERS, *PSP_READ_REGISTERS; + + +#define NS16550_RECEIVE_BUFFER 0 +#define NS16550_INTERRUPT_ENABLE 1 +#define NS16550_INTERRUPT_ID 2 +#define NS16550_LINE_CONTROL 3 +#define NS16550_MODEM_CONTROL 4 +#define NS16550_LINE_STATUS 5 +#define NS16550_MODEM_STATUS 6 +#define NS16550_SCRATCH_PAD 7 +/* + * Define serial port write registers structure. + */ + +typedef volatile struct _SP_WRITE_REGISTERS { + unsigned char TransmitBuffer; + unsigned char InterruptEnable; + unsigned char FifoControl; + unsigned char LineControl; + unsigned char ModemControl; + unsigned char Reserved1; + unsigned char ModemStatus; + unsigned char ScratchPad; +} SP_WRITE_REGISTERS, *PSP_WRITE_REGISTERS; + +#define NS16550_TRANSMIT_BUFFER 0 +#define NS16550_FIFO_CONTROL 2 + +/* + * Define serial port interrupt enable register structure. + */ + +#define SP_INT_RX_ENABLE 0x01 +#define SP_INT_TX_ENABLE 0x02 +#define SP_INT_LS_ENABLE 0x04 +#define SP_INT_MS_ENABLE 0x08 + +/* + * Define serial port interrupt id register structure. + */ + +typedef struct _SP_INTERRUPT_ID { + unsigned char InterruptPending : 1; + unsigned char Identification : 3; + unsigned char Reserved1 : 2; + unsigned char FifoEnabled : 2; +} SP_INTERRUPT_ID, *PSP_INTERRUPT_ID; + +/* + * Define serial port fifo control register structure. + */ +#define SP_FIFO_ENABLE 0x01 +#define SP_FIFO_RXRST 0x02 +#define SP_FIFO_TXRST 0x04 +#define SP_FIFO_DMA 0x08 +#define SP_FIFO_RXLEVEL 0xc0 + +/* + * Define serial port line control register structure. + */ +#define SP_LINE_SIZE 0x03 +#define SP_LINE_STOP 0x04 +#define SP_LINE_PAR 0x08 +#define SP_LINE_ODD 0x10 +#define SP_LINE_STICK 0x20 +#define SP_LINE_BREAK 0x40 +#define SP_LINE_DLAB 0x80 + +/* + * Line status register character size definitions. + */ +#define FIVE_BITS 0x0 /* five bits per character */ +#define SIX_BITS 0x1 /* six bits per character */ +#define SEVEN_BITS 0x2 /* seven bits per character */ +#define EIGHT_BITS 0x3 /* eight bits per character */ + +/* + * Line speed divisor definition. + */ +#define NS16550_Baud(baud_rate) (115200/baud_rate) + +/* + * Define serial port modem control register structure. + */ +#define SP_MODEM_DTR 0x01 +#define SP_MODEM_RTS 0x02 +#define SP_MODEM_IRQ 0x08 +#define SP_MODEM_LOOP 0x10 +#define SP_MODEM_DIV4 0x80 + +/* + * Define serial port line status register structure. + */ +#define SP_LSR_RDY 0x01 +#define SP_LSR_EOVRUN 0x02 +#define SP_LSR_EPAR 0x04 +#define SP_LSR_EFRAME 0x08 +#define SP_LSR_BREAK 0x10 +#define SP_LSR_THOLD 0x20 +#define SP_LSR_TX 0x40 +#define SP_LSR_EFIFO 0x80 + +typedef struct _ns16550_context +{ + unsigned8 ucModemCtrl; +} ns16550_context; + +/* + * Driver functions + */ +static boolean ns16550_probe(int minor); + +static void ns16550_init(int minor); + +static int ns16550_open( + int major, + int minor, + void * arg +); + +static int ns16550_close( + int major, + int minor, + void * arg +); + +static void ns16550_write_polled( + int minor, + char cChar +); + +static int ns16550_assert_RTS( + int minor +); + +static int ns16550_negate_RTS( + int minor +); + +static int ns16550_assert_DTR( + int minor +); + +static int ns16550_negate_DTR( + int minor +); + +static void ns16550_initialize_interrupts(int minor); + +static int ns16550_flush(int major, int minor, void *arg); + +static int ns16550_write_support_int( + int minor, + const char *buf, + int len +); + +static int ns16550_write_support_polled( + int minor, + const char *buf, + int len + ); + +static int ns16550_inbyte_nonblocking_polled( + int minor +); + +#ifdef __cplusplus +} +#endif + +#endif /* _NS16550_P_H_ */ diff --git a/c/src/lib/libchip/serial/z85c30.c b/c/src/lib/libchip/serial/z85c30.c new file mode 100644 index 0000000000..9fc629938a --- /dev/null +++ b/c/src/lib/libchip/serial/z85c30.c @@ -0,0 +1,830 @@ +/* + * This file contains the console driver chip level routines for the + * z85c30 chip. + * + * COPYRIGHT (c) 1998 by Radstone Technology + * + * + * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY + * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK + * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU. + * + * You are hereby granted permission to use, copy, modify, and distribute + * this file, provided that this notice, plus the above copyright notice + * and disclaimer, appears in all copies. Radstone Technology will provide + * no support for this code. + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include <rtems.h> +#include <rtems/libio.h> +#include <stdlib.h> + +#include "console.h" +#include "z85c30_p.h" + +/* + * Flow control is only supported when using interrupts + */ +console_flow z85c30_flow_RTSCTS = +{ + z85c30_negate_RTS, /* deviceStopRemoteTx */ + z85c30_assert_RTS /* deviceStartRemoteTx */ +}; + +console_flow z85c30_flow_DTRCTS = +{ + z85c30_negate_DTR, /* deviceStopRemoteTx */ + z85c30_assert_DTR /* deviceStartRemoteTx */ +}; + +/* + * Exported driver function table + */ +console_fns z85c30_fns = +{ + z85c30_probe, /* deviceProbe */ + z85c30_open, /* deviceFirstOpen */ + z85c30_flush, /* deviceLastClose */ + NULL, /* deviceRead */ + z85c30_write_support_int, /* deviceWrite */ + z85c30_initialize_interrupts, /* deviceInitialize */ + z85c30_write_polled, /* deviceWritePolled */ + FALSE, /* deviceOutputUsesInterrupts */ +}; + +console_fns z85c30_fns_polled = +{ + z85c30_probe, /* deviceProbe */ + z85c30_open, /* deviceFirstOpen */ + z85c30_close, /* deviceLastClose */ + z85c30_inbyte_nonblocking_polled, /* deviceRead */ + z85c30_write_support_polled, /* deviceWrite */ + z85c30_init, /* deviceInitialize */ + z85c30_write_polled, /* deviceWritePolled */ + FALSE, /* deviceOutputUsesInterrupts */ +}; + +extern void set_vector( rtems_isr_entry, rtems_vector_number, int ); + +/* + * Types for get and set register routines + */ + +typedef unsigned8 (*getRegister_f)(unsigned32 port, unsigned8 register); +typedef void (*setRegister_f)( + unsigned32 port, unsigned8 reg, unsigned8 value); +typedef unsigned8 (*getData_f)(unsigned32 port); +typedef void (*setData_f)(unsigned32 port, unsigned8 value); + + +/* + * z85c30_initialize_port + * + * initialize a z85c30 Port + */ + +static void z85c30_initialize_port( + int minor +) +{ + unsigned32 ulCtrlPort; + unsigned32 ulBaudDivisor; + setRegister_f setReg; + + ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; + setReg = Console_Port_Tbl[minor].setRegister; + + /* + * Using register 4 + * Set up the clock rate is 16 times the data + * rate, 8 bit sync char, 1 stop bit, no parity + */ + + (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR4, SCC_WR4_1_STOP | SCC_WR4_16_CLOCK ); + + /* + * Set up for 8 bits/character on receive with + * receiver disable via register 3 + */ + (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR3, SCC_WR3_RX_8_BITS ); + + /* + * Set up for 8 bits/character on transmit + * with transmitter disable via register 5 + */ + (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR5, SCC_WR5_TX_8_BITS ); + + /* + * Clear misc control bits + */ + (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR10, 0x00 ); + + /* + * Setup the source of the receive and xmit + * clock as BRG output and the transmit clock + * as the output source for TRxC pin via register 11 + */ + (*setReg)( + ulCtrlPort, + SCC_WR0_SEL_WR11, + SCC_WR11_OUT_BR_GEN | SCC_WR11_TRXC_OI | + SCC_WR11_TX_BR_GEN | SCC_WR11_RX_BR_GEN + ); + + ulBaudDivisor = Z85C30_Baud( + (unsigned32) Console_Port_Tbl[minor].ulClock, + (unsigned32) Console_Port_Tbl[minor].pDeviceParams + ); + + /* + * Setup the lower 8 bits time constants=1E. + * If the time constans=1E, then the desire + * baud rate will be equilvalent to 9600, via register 12. + */ + (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR12, ulBaudDivisor & 0xff ); + + /* + * using register 13 + * Setup the upper 8 bits time constant + */ + (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR13, (ulBaudDivisor>>8) & 0xff ); + + /* + * Enable the baud rate generator enable with clock from the + * SCC's PCLK input via register 14. + */ + (*setReg)( + ulCtrlPort, + SCC_WR0_SEL_WR14, + SCC_WR14_BR_EN | SCC_WR14_BR_SRC | SCC_WR14_NULL + ); + + /* + * We are only interested in CTS state changes + */ + (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR15, SCC_WR15_CTS_IE ); + + /* + * Reset errors + */ + (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT ); + + (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_ERR_RST ); + + /* + * Enable the receiver via register 3 + */ + (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR3, SCC_WR3_RX_8_BITS | SCC_WR3_RX_EN ); + + /* + * Enable the transmitter pins set via register 5. + */ + (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR5, SCC_WR5_TX_8_BITS | SCC_WR5_TX_EN ); + + /* + * Disable interrupts + */ + (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR1, 0 ); + + /* + * Reset TX CRC + */ + (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_CRC ); + + /* + * Reset interrupts + */ + (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT ); +} + +static int z85c30_open( + int major, + int minor, + void *arg +) +{ + /* + * Assert DTR + */ + + if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_DTRCTS) { + z85c30_assert_DTR(minor); + } + + return(RTEMS_SUCCESSFUL); +} + +static int z85c30_close( + int major, + int minor, + void *arg +) +{ + /* + * Negate DTR + */ + + if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_DTRCTS) { + z85c30_negate_DTR(minor); + } + + return(RTEMS_SUCCESSFUL); +} + +/* + * z85c30_write_polled + * + * This routine transmits a character using polling. + */ + +static void z85c30_write_polled( + int minor, + char cChar +) +{ + volatile unsigned8 z85c30_status; + unsigned32 ulCtrlPort; + getRegister_f getReg; + setData_f setData; + + ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; + getReg = Console_Port_Tbl[minor].getRegister; + setData = Console_Port_Tbl[minor].setData; + + /* + * Wait for the Transmit buffer to indicate that it is empty. + */ + + z85c30_status = (*getReg)( ulCtrlPort, SCC_WR0_SEL_RD0 ); + + while (!Z85C30_Status_Is_TX_buffer_empty(z85c30_status)) { + /* + * Yield while we wait + */ + if (_System_state_Is_up(_System_state_Get())) { + rtems_task_wake_after(RTEMS_YIELD_PROCESSOR); + } + z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); + } + + /* + * Write the character. + */ + + (*setData)(Console_Port_Tbl[minor].ulDataPort, cChar); +} + +/* + * Console Device Driver Entry Points + */ + +static boolean z85c30_probe(int minor) +{ + /* + * If the configuration dependant probe has located the device then + * assume it is there + */ + + return(TRUE); +} + +static void z85c30_init(int minor) +{ + unsigned32 ulCtrlPort; + unsigned8 dummy; + z85c30_context *pz85c30Context; + setRegister_f setReg; + getRegister_f getReg; + + setReg = Console_Port_Tbl[minor].setRegister; + getReg = Console_Port_Tbl[minor].getRegister; + + pz85c30Context = (z85c30_context *)malloc(sizeof(z85c30_context)); + + Console_Port_Data[minor].pDeviceContext=(void *)pz85c30Context; + + pz85c30Context->ucModemCtrl = SCC_WR5_TX_8_BITS | SCC_WR5_TX_EN; + + ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; + if (ulCtrlPort == Console_Port_Tbl[minor].ulCtrlPort2) { + /* + * This is channel A + */ + /* + * Ensure port state machine is reset + */ + dummy = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); + + (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR9, SCC_WR9_CH_A_RST); + + } else { + /* + * This is channel B + */ + /* + * Ensure port state machine is reset + */ + dummy = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); + + (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR9, SCC_WR9_CH_B_RST); + } + + z85c30_initialize_port(minor); +} + +/* + * These routines provide control of the RTS and DTR lines + */ +/* + * z85c30_assert_RTS + */ +static int z85c30_assert_RTS(int minor) +{ + rtems_interrupt_level Irql; + z85c30_context *pz85c30Context; + setRegister_f setReg; + + setReg = Console_Port_Tbl[minor].setRegister; + + pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext; + + /* + * Assert RTS + */ + + rtems_interrupt_disable(Irql); + pz85c30Context->ucModemCtrl|=SCC_WR5_RTS; + (*setReg)( + Console_Port_Tbl[minor].ulCtrlPort1, + SCC_WR0_SEL_WR5, + pz85c30Context->ucModemCtrl + ); + rtems_interrupt_enable(Irql); + return 0; +} + +/* + * z85c30_negate_RTS + */ +static int z85c30_negate_RTS(int minor) +{ + rtems_interrupt_level Irql; + z85c30_context *pz85c30Context; + setRegister_f setReg; + + setReg = Console_Port_Tbl[minor].setRegister; + + pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext; + + /* + * Negate RTS + */ + + rtems_interrupt_disable(Irql); + pz85c30Context->ucModemCtrl&=~SCC_WR5_RTS; + (*setReg)( + Console_Port_Tbl[minor].ulCtrlPort1, + SCC_WR0_SEL_WR5, + pz85c30Context->ucModemCtrl + ); + rtems_interrupt_enable(Irql); + return 0; +} + +/* + * These flow control routines utilise a connection from the local DTR + * line to the remote CTS line + */ +/* + * z85c30_assert_DTR + */ +static int z85c30_assert_DTR(int minor) +{ + rtems_interrupt_level Irql; + z85c30_context *pz85c30Context; + setRegister_f setReg; + + setReg = Console_Port_Tbl[minor].setRegister; + + pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext; + + /* + * Assert DTR + */ + + rtems_interrupt_disable(Irql); + pz85c30Context->ucModemCtrl|=SCC_WR5_DTR; + (*setReg)( + Console_Port_Tbl[minor].ulCtrlPort1, + SCC_WR0_SEL_WR5, + pz85c30Context->ucModemCtrl + ); + rtems_interrupt_enable(Irql); + return 0; +} + +/* + * z85c30_negate_DTR + */ +static int z85c30_negate_DTR(int minor) +{ + rtems_interrupt_level Irql; + z85c30_context *pz85c30Context; + setRegister_f setReg; + + setReg = Console_Port_Tbl[minor].setRegister; + + pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext; + + /* + * Negate DTR + */ + + rtems_interrupt_disable(Irql); + pz85c30Context->ucModemCtrl&=~SCC_WR5_DTR; + (*setReg)( + Console_Port_Tbl[minor].ulCtrlPort1, + SCC_WR0_SEL_WR5, + pz85c30Context->ucModemCtrl + ); + rtems_interrupt_enable(Irql); + return 0; +} + +/* + * z85c30_isr + * + * This routine is the console interrupt handler for COM3 and COM4 + * + * Input parameters: + * vector - vector number + * + * Output parameters: NONE + * + * Return values: NONE + */ + +static void z85c30_process( + int minor, + unsigned8 ucIntPend +) +{ + unsigned32 ulCtrlPort; + unsigned32 ulDataPort; + volatile unsigned8 z85c30_status; + char cChar; + setRegister_f setReg; + getRegister_f getReg; + getData_f getData; + setData_f setData; + + ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; + ulDataPort = Console_Port_Tbl[minor].ulDataPort; + setReg = Console_Port_Tbl[minor].setRegister; + getReg = Console_Port_Tbl[minor].getRegister; + getData = Console_Port_Tbl[minor].getData; + getData = Console_Port_Tbl[minor].getData; + + /* + * Deal with any received characters + */ + while (ucIntPend&SCC_RR3_B_RX_IP) + { + z85c30_status=(*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); + if (!Z85C30_Status_Is_RX_character_available(z85c30_status)) { + break; + } + + /* + * Return the character read. + */ + + cChar = (*getData)(ulDataPort); + + rtems_termios_enqueue_raw_characters( + Console_Port_Data[minor].termios_data, + &cChar, + 1 + ); + } + + while (TRUE) + { + z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); + if (!Z85C30_Status_Is_TX_buffer_empty(z85c30_status)) { + /* + * We'll get another interrupt when + * the transmitter holding reg. becomes + * free again and we are clear to send + */ + break; + } + + if (!Z85C30_Status_Is_CTS_asserted(z85c30_status)) { + /* + * We can't transmit yet + */ + (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_INT); + /* + * The next state change of CTS will wake us up + */ + break; + } + + if (Ring_buffer_Is_empty(&Console_Port_Data[minor].TxBuffer)) { + Console_Port_Data[minor].bActive=FALSE; + if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_RTSCTS) { + z85c30_negate_RTS(minor); + } + /* + * There is no data to transmit + */ + (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_INT); + break; + } + + Ring_buffer_Remove_character( &Console_Port_Data[minor].TxBuffer, cChar); + + /* + * transmit character + */ + (*setData)(ulDataPort, cChar); + + /* + * Interrupt once FIFO has room + */ + (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_INT); + break; + } + + if (ucIntPend&SCC_RR3_B_EXT_IP) { + /* + * Clear the external status interrupt + */ + (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT); + z85c30_status=(*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); + } + + /* + * Reset interrupts + */ + (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_HI_IUS); +} + +static rtems_isr z85c30_isr( + rtems_vector_number vector +) +{ + int minor; + unsigned32 ulCtrlPort; + volatile unsigned8 ucIntPend; + volatile unsigned8 ucIntPendPort; + getRegister_f getReg; + + for (minor=0;minor<Console_Port_Count;minor++) { + if (vector==Console_Port_Tbl[minor].ulIntVector) { + ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort2; + getReg = Console_Port_Tbl[minor].getRegister; + do { + ucIntPend=(*getReg)(ulCtrlPort, SCC_WR0_SEL_RD3); + + /* + * If this is channel A select channel A status + */ + + if (ulCtrlPort == Console_Port_Tbl[minor].ulCtrlPort1) { + ucIntPendPort = ucIntPend>>3; + ucIntPendPort = ucIntPendPort&=7; + } else { + ucIntPendPort = ucIntPend &= 7; + } + + if (ucIntPendPort) { + z85c30_process(minor, ucIntPendPort); + } + } while (ucIntPendPort); + } + } +} + +/* + * z85c30_flush + */ + +static int z85c30_flush( + int major, + int minor, + void *arg +) +{ + while (!Ring_buffer_Is_empty(&Console_Port_Data[minor].TxBuffer)) { + /* + * Yield while we wait + */ + if (_System_state_Is_up(_System_state_Get())) { + rtems_task_wake_after(RTEMS_YIELD_PROCESSOR); + } + } + + z85c30_close(major, minor, arg); + + return(RTEMS_SUCCESSFUL); +} + +/* + * z85c30_initialize_interrupts + * + * This routine initializes the console's receive and transmit + * ring buffers and loads the appropriate vectors to handle the interrupts. + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * Return values: NONE + */ + +static void z85c30_enable_interrupts( + int minor +) +{ + unsigned32 ulCtrlPort; + setRegister_f setReg; + + ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; + setReg = Console_Port_Tbl[minor].setRegister; + + /* + * Enable interrupts + */ + (*setReg)( + ulCtrlPort, + SCC_WR0_SEL_WR1, + SCC_WR1_EXT_INT_EN | SCC_WR1_TX_INT_EN | SCC_WR1_INT_ALL_RX + ); + (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR2, 0); + (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR9, SCC_WR9_MIE); + + /* + * Reset interrupts + */ + (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT); +} + +static void z85c30_initialize_interrupts( + int minor +) +{ + z85c30_init(minor); + + Ring_buffer_Initialize(&Console_Port_Data[minor].TxBuffer); + + Console_Port_Data[minor].bActive=FALSE; + if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_RTSCTS) { + z85c30_negate_RTS(minor); + } + + if (Console_Port_Tbl[minor].ulCtrlPort1== Console_Port_Tbl[minor].ulCtrlPort2) { + /* + * Only do this for Channel A + */ + + set_vector(z85c30_isr, Console_Port_Tbl[minor].ulIntVector, 1); + } + + z85c30_enable_interrupts(minor); +} + +/* + * z85c30_write_support_int + * + * Console Termios output entry point. + * + */ +static int z85c30_write_support_int( + int minor, + const char *buf, + int len) +{ + int i; + unsigned32 Irql; + + for (i=0; i<len;) { + if (Ring_buffer_Is_full(&Console_Port_Data[minor].TxBuffer)) { + if (!Console_Port_Data[minor].bActive) { + /* + * Wake up the device + */ + if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_RTSCTS) { + z85c30_assert_RTS(minor); + } + rtems_interrupt_disable(Irql); + Console_Port_Data[minor].bActive=TRUE; + z85c30_process(minor, SCC_RR3_B_TX_IP); + rtems_interrupt_enable(Irql); + } else { + /* + * Yield while we await an interrupt + */ + rtems_task_wake_after(RTEMS_YIELD_PROCESSOR); + } + + /* + * Wait for ring buffer to empty + */ + continue; + } else { + Ring_buffer_Add_character( &Console_Port_Data[minor].TxBuffer, buf[i]); + i++; + } + } + + /* + * Ensure that characters are on the way + */ + if (!Console_Port_Data[minor].bActive) { + /* + * Wake up the device + */ + if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_RTSCTS) { + z85c30_assert_RTS(minor); + } + rtems_interrupt_disable(Irql); + Console_Port_Data[minor].bActive=TRUE; + z85c30_process(minor, SCC_RR3_B_TX_IP); + rtems_interrupt_enable(Irql); + } + + return (len); +} + +/* + * z85c30_inbyte_nonblocking_polled + * + * This routine polls for a character. + */ +static int z85c30_inbyte_nonblocking_polled( + int minor +) +{ + volatile unsigned8 z85c30_status; + unsigned32 ulCtrlPort; + getRegister_f getReg; + getData_f getData; + + ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; + getData = Console_Port_Tbl[minor].getData; + getReg = Console_Port_Tbl[minor].getRegister; + + /* + * return -1 if a character is not available. + */ + z85c30_status=(*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); + if (!Z85C30_Status_Is_RX_character_available(z85c30_status)) { + return -1; + } + + /* + * Return the character read. + */ + return (*getData)(Console_Port_Tbl[minor].ulDataPort); +} + +/* + * z85c30_write_support_polled + * + * Console Termios output entry point. + * + */ + +static int z85c30_write_support_polled( + int minor, + const char *buf, + int len) +{ + int nwrite=0; + + /* + * poll each byte in the string out of the port. + */ + while (nwrite < len) { + z85c30_write_polled(minor, *buf++); + nwrite++; + } + + /* + * return the number of bytes written. + */ + return nwrite; +} diff --git a/c/src/lib/libchip/serial/z85c30.h b/c/src/lib/libchip/serial/z85c30.h new file mode 100644 index 0000000000..2eed03d1e3 --- /dev/null +++ b/c/src/lib/libchip/serial/z85c30.h @@ -0,0 +1,54 @@ +/* z85c30.h + * + * This include file contains all console driver definations for the z85c30 + * + * COPYRIGHT (c) 1998 by Radstone Technology + * + * + * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY + * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK + * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU. + * + * You are hereby granted permission to use, copy, modify, and distribute + * this file, provided that this notice, plus the above copyright notice + * and disclaimer, appears in all copies. Radstone Technology will provide + * no support for this code. + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id: + */ + +#ifndef __Z85C30_H +#define __Z85C30_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Driver function table + */ + +extern console_fns z85c30_fns; +extern console_fns z85c30_fns_polled; + +/* + * Flow control function tables + */ + +extern console_flow z85c30_flow_RTSCTS; +extern console_flow z85c30_flow_DTRCTS; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/c/src/lib/libchip/serial/z85c30_p.h b/c/src/lib/libchip/serial/z85c30_p.h new file mode 100644 index 0000000000..29f1aa7624 --- /dev/null +++ b/c/src/lib/libchip/serial/z85c30_p.h @@ -0,0 +1,385 @@ +/* z85c30_p.h + * + * This include file contains all private driver definations for the z85c30 + * + * COPYRIGHT (c) 1998 by Radstone Technology + * + * + * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY + * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK + * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU. + * + * You are hereby granted permission to use, copy, modify, and distribute + * this file, provided that this notice, plus the above copyright notice + * and disclaimer, appears in all copies. Radstone Technology will provide + * no support for this code. + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id: + */ + +#ifndef __Z85C30_P_H +#define __Z85C30_P_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* bit values for write register 0 */ +/* command register */ + +#define SCC_WR0_SEL_WR0 0x00 +#define SCC_WR0_SEL_WR1 0x01 +#define SCC_WR0_SEL_WR2 0x02 +#define SCC_WR0_SEL_WR3 0x03 +#define SCC_WR0_SEL_WR4 0x04 +#define SCC_WR0_SEL_WR5 0x05 +#define SCC_WR0_SEL_WR6 0x06 +#define SCC_WR0_SEL_WR7 0x07 +#define SCC_WR0_SEL_WR8 0x08 +#define SCC_WR0_SEL_WR9 0x09 +#define SCC_WR0_SEL_WR10 0x0a +#define SCC_WR0_SEL_WR11 0x0b +#define SCC_WR0_SEL_WR12 0x0c +#define SCC_WR0_SEL_WR13 0x0d +#define SCC_WR0_SEL_WR14 0x0e +#define SCC_WR0_SEL_WR15 0x0f +#define SCC_WR0_SEL_RD0 0x00 +#define SCC_WR0_SEL_RD1 0x01 +#define SCC_WR0_SEL_RD2 0x02 +#define SCC_WR0_SEL_RD3 0x03 +#define SCC_WR0_SEL_RD4 0x04 +#define SCC_WR0_SEL_RD5 0x05 +#define SCC_WR0_SEL_RD6 0x06 +#define SCC_WR0_SEL_RD7 0x07 +#define SCC_WR0_SEL_RD8 0x08 +#define SCC_WR0_SEL_RD9 0x09 +#define SCC_WR0_SEL_RD10 0x0a +#define SCC_WR0_SEL_RD11 0x0b +#define SCC_WR0_SEL_RD12 0x0c +#define SCC_WR0_SEL_RD13 0x0d +#define SCC_WR0_SEL_RD14 0x0e +#define SCC_WR0_SEL_RD15 0x0f +#define SCC_WR0_NULL_CODE 0x00 +#define SCC_WR0_RST_INT 0x10 +#define SCC_WR0_SEND_ABORT 0x18 +#define SCC_WR0_EN_INT_RX 0x20 +#define SCC_WR0_RST_TX_INT 0x28 +#define SCC_WR0_ERR_RST 0x30 +#define SCC_WR0_RST_HI_IUS 0x38 +#define SCC_WR0_RST_RX_CRC 0x40 +#define SCC_WR0_RST_TX_CRC 0x80 +#define SCC_WR0_RST_TX_UND 0xc0 + +/* write register 2 */ +/* interrupt vector */ + +/* bit values for write register 1 */ +/* tx/rx interrupt and data transfer mode definition */ + +#define SCC_WR1_EXT_INT_EN 0x01 +#define SCC_WR1_TX_INT_EN 0x02 +#define SCC_WR1_PARITY 0x04 +#define SCC_WR1_RX_INT_DIS 0x00 +#define SCC_WR1_RX_INT_FIR 0x08 +#define SCC_WR1_INT_ALL_RX 0x10 +#define SCC_WR1_RX_INT_SPE 0x18 +#define SCC_WR1_RDMA_RECTR 0x20 +#define SCC_WR1_RDMA_FUNC 0x40 +#define SCC_WR1_RDMA_EN 0x80 + +/* bit values for write register 3 */ +/* receive parameters and control */ + +#define SCC_WR3_RX_EN 0x01 +#define SCC_WR3_SYNC_CHAR 0x02 +#define SCC_WR3_ADR_SEARCH 0x04 +#define SCC_WR3_RX_CRC_EN 0x08 +#define SCC_WR3_ENTER_HUNT 0x10 +#define SCC_WR3_AUTO_EN 0x20 +#define SCC_WR3_RX_5_BITS 0x00 +#define SCC_WR3_RX_7_BITS 0x40 +#define SCC_WR3_RX_6_BITS 0x80 +#define SCC_WR3_RX_8_BITS 0xc0 + +/* bit values for write register 4 */ +/* tx/rx misc parameters and modes */ + +#define SCC_WR4_PAR_EN 0x01 +#define SCC_WR4_PAR_EVEN 0x02 +#define SCC_WR4_SYNC_EN 0x00 +#define SCC_WR4_1_STOP 0x04 +#define SCC_WR4_2_STOP 0x0c +#define SCC_WR4_8_SYNC 0x00 +#define SCC_WR4_16_SYNC 0x10 +#define SCC_WR4_SDLC 0x20 +#define SCC_WR4_EXT_SYNC 0x30 +#define SCC_WR4_1_CLOCK 0x00 +#define SCC_WR4_16_CLOCK 0x40 +#define SCC_WR4_32_CLOCK 0x80 +#define SCC_WR4_64_CLOCK 0xc0 + +/* bit values for write register 5 */ +/* transmit parameter and controls */ + +#define SCC_WR5_TX_CRC_EN 0x01 +#define SCC_WR5_RTS 0x02 +#define SCC_WR5_SDLC 0x04 +#define SCC_WR5_TX_EN 0x08 +#define SCC_WR5_SEND_BRK 0x10 + +#define SCC_WR5_TX_5_BITS 0x00 +#define SCC_WR5_TX_7_BITS 0x20 +#define SCC_WR5_TX_6_BITS 0x40 +#define SCC_WR5_TX_8_BITS 0x60 +#define SCC_WR5_DTR 0x80 + +/* write register 6 */ +/* sync chars or sdlc address field */ + +/* write register 7 */ +/* sync char or sdlc flag */ + +/* write register 8 */ +/* transmit buffer */ + +/* bit values for write register 9 */ +/* master interrupt control */ + +#define SCC_WR9_VIS 0x01 +#define SCC_WR9_NV 0x02 +#define SCC_WR9_DLC 0x04 +#define SCC_WR9_MIE 0x08 +#define SCC_WR9_STATUS_HI 0x10 +#define SCC_WR9_NO_RST 0x00 +#define SCC_WR9_CH_B_RST 0x40 +#define SCC_WR9_CH_A_RST 0x80 +#define SCC_WR9_HDWR_RST 0xc0 + +/* bit values for write register 10 */ +/* misc tx/rx control bits */ + +#define SCC_WR10_6_BIT_SYNC 0x01 +#define SCC_WR10_LOOP_MODE 0x02 +#define SCC_WR10_ABORT_UND 0x04 +#define SCC_WR10_MARK_IDLE 0x08 +#define SCC_WR10_ACT_POLL 0x10 +#define SCC_WR10_NRZ 0x00 +#define SCC_WR10_NRZI 0x20 +#define SCC_WR10_FM1 0x40 +#define SCC_WR10_FM0 0x60 +#define SCC_WR10_CRC_PRESET 0x80 + +/* bit values for write register 11 */ +/* clock mode control */ + +#define SCC_WR11_OUT_XTAL 0x00 +#define SCC_WR11_OUT_TX_CLK 0x01 +#define SCC_WR11_OUT_BR_GEN 0x02 +#define SCC_WR11_OUT_DPLL 0x03 +#define SCC_WR11_TRXC_OI 0x04 +#define SCC_WR11_TX_RTXC 0x00 +#define SCC_WR11_TX_TRXC 0x08 +#define SCC_WR11_TX_BR_GEN 0x10 +#define SCC_WR11_TX_DPLL 0x18 +#define SCC_WR11_RX_RTXC 0x00 +#define SCC_WR11_RX_TRXC 0x20 +#define SCC_WR11_RX_BR_GEN 0x40 +#define SCC_WR11_RX_DPLL 0x60 +#define SCC_WR11_RTXC_XTAL 0x80 + +/* write register 12 */ +/* lower byte of baud rate generator time constant */ + +/* write register 13 */ +/* upper byte of baud rate generator time constant */ + +/* bit values for write register 14 */ +/* misc control bits */ + +#define SCC_WR14_BR_EN 0x01 +#define SCC_WR14_BR_SRC 0x02 +#define SCC_WR14_DTR_FUNC 0x04 +#define SCC_WR14_AUTO_ECHO 0x08 +#define SCC_WR14_LCL_LOOP 0x10 +#define SCC_WR14_NULL 0x00 +#define SCC_WR14_SEARCH 0x20 +#define SCC_WR14_RST_CLK 0x40 +#define SCC_WR14_DIS_DPLL 0x60 +#define SCC_WR14_SRC_BR 0x80 +#define SCC_WR14_SRC_RTXC 0xa0 +#define SCC_WR14_FM_MODE 0xc0 +#define SCC_WR14_NRZI 0xe0 + +/* bit values for write register 15 */ +/* external/status interrupt control */ + +#define SCC_WR15_ZERO_CNT 0x02 +#define SCC_WR15_CD_IE 0x08 +#define SCC_WR15_SYNC_IE 0x10 +#define SCC_WR15_CTS_IE 0x20 +#define SCC_WR15_TX_UND_IE 0x40 +#define SCC_WR15_BREAK_IE 0x80 + +/* bit values for read register 0 */ +/* tx/rx buffer status and external status */ + +#define SCC_RR0_RX_AVAIL 0x01 +#define SCC_RR0_ZERO_CNT 0x02 +#define SCC_RR0_TX_EMPTY 0x04 +#define SCC_RR0_CD 0x08 +#define SCC_RR0_SYNC 0x10 +#define SCC_RR0_CTS 0x20 +#define SCC_RR0_TX_UND 0x40 +#define SCC_RR0_BREAK 0x80 + +/* bit values for read register 1 */ + +#define SCC_RR1_ALL_SENT 0x01 +#define SCC_RR1_RES_CD_2 0x02 +#define SCC_RR1_RES_CD_1 0x01 +#define SCC_RR1_RES_CD_0 0x08 +#define SCC_RR1_PAR_ERR 0x10 +#define SCC_RR1_RX_OV_ERR 0x20 +#define SCC_RR1_CRC_ERR 0x40 +#define SCC_RR1_END_FRAME 0x80 + +/* read register 2 */ +/* interrupt vector */ + +/* bit values for read register 3 */ +/* interrupt pending register */ + +#define SCC_RR3_B_EXT_IP 0x01 +#define SCC_RR3_B_TX_IP 0x02 +#define SCC_RR3_B_RX_IP 0x04 +#define SCC_RR3_A_EXT_IP 0x08 +#define SCC_RR3_A_TX_IP 0x10 +#define SCC_RR3_A_RX_IP 0x20 + +/* read register 8 */ +/* receive data register */ + +/* bit values for read register 10 */ +/* misc status bits */ + +#define SCC_RR10_ON_LOOP 0x02 +#define SCC_RR10_LOOP_SEND 0x10 +#define SCC_RR10_2_CLK_MIS 0x40 +#define SCC_RR10_1_CLK_MIS 0x80 + +/* read register 12 */ +/* lower byte of time constant */ + +/* read register 13 */ +/* upper byte of time constant */ + +/* bit values for read register 15 */ +/* external/status ie bits */ + +#define SCC_RR15_ZERO_CNT 0x02 +#define SCC_RR15_CD_IE 0x08 +#define SCC_RR15_SYNC_IE 0x10 +#define SCC_RR15_CTS_IE 0x20 +#define SCC_RR15_TX_UND_IE 0x40 +#define SCC_RR15_BREAK_IE 0x80 + +typedef struct _z85c30_context +{ + unsigned8 ucModemCtrl; +} z85c30_context; + +/* + * The following macro calculates the Baud constant. For the Z85C30 chip. + * + * Note: baud constant = ((clock frequency / Clock_X) / (2 * Baud Rate)) - 2 + * eg ((10,000,000 / 16) / (2 * Baud Rate)) - 2 + */ +#define Z85C30_Baud( _clock, _baud_rate ) \ + ( ((_clock) /( 16 * 2 * _baud_rate)) - 2) + +#define Z85C30_Status_Is_RX_character_available(_status) \ + ((_status) & SCC_RR0_RX_AVAIL) + +#define Z85C30_Status_Is_TX_buffer_empty(_status) \ + ((_status) & SCC_RR0_TX_EMPTY) + +#define Z85C30_Status_Is_CTS_asserted(_status) \ + ((_status) & SCC_RR0_CTS) + +#define Z85C30_Status_Is_break_abort(_status) \ + ((_status) & SCC_RR0_BREAK) + +/* + * Private routines + */ +static boolean z85c30_probe(int minor); + +static void z85c30_init(int minor); + +static int z85c30_open( + int major, + int minor, + void * arg +); + +static int z85c30_close( + int major, + int minor, + void * arg +); + +static void z85c30_write_polled( + int minor, + char cChar +); + +static int z85c30_assert_RTS( + int minor +); + +static int z85c30_negate_RTS( + int minor +); + +static int z85c30_assert_DTR( + int minor +); + +static int z85c30_negate_DTR( + int minor +); + +static void z85c30_initialize_interrupts(int minor); + +static int z85c30_flush(int major, int minor, void *arg); + +static int z85c30_write_support_int( + int minor, + const char *buf, + int len +); + +static int z85c30_write_support_polled( + int minor, + const char *buf, + int len +); + +static int z85c30_inbyte_nonblocking_polled( + int minor +); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/c/src/libchip/serial/Makefile.in b/c/src/libchip/serial/Makefile.in new file mode 100644 index 0000000000..0cc8924ea6 --- /dev/null +++ b/c/src/libchip/serial/Makefile.in @@ -0,0 +1,59 @@ +# +# $Id$ +# + +@SET_MAKE@ +srcdir = @srcdir@ +VPATH = @srcdir@ +RTEMS_ROOT = @top_srcdir@ +PROJECT_ROOT = @PROJECT_ROOT@ + +LIBNAME=libserialio.a +LIB=${ARCH}/${LIBNAME} + +C_PIECES=ns16550 z85c30 +C_FILES=$(C_PIECES:%=%.c) +C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) + +H_FILES=$(srcdir)/libcsupport.h +SYS_H_FILES= +RTEMS_H_FILES=$(srcdir)/libio.h +PRIVATE_H_FILES=$(srcdir)/internal.h + +INSTALLED_H_FILES=$(srcdir)/ns16550.h $(srcdir)/z8530.h +SRCS=$(C_FILES) $(H_FILES) $(SYS_H_FILES) $(RTEMS_H_FILES) $(PRIVATE_H_FILES) +OBJS=$(C_O_FILES) + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/lib.cfg + +# +# Add local stuff here using += +# + +DEFINES += +CPPFLAGS += +CFLAGS += $(LIBC_DEFINES) + +# +# Add your list of files to delete here. The config files +# already know how to delete some stuff, so you may want +# to just run 'make clean' first to see what gets missed. +# 'make clobber' already includes 'make clean' +# + +CLEAN_ADDITIONS += $(LIB) +CLOBBER_ADDITIONS += + +all: ${ARCH} preinstall $(LIB) + $(INSTALL_VARIANT) -m 644 ${LIB} ${PROJECT_RELEASE}/lib + +$(LIB): $(SRCS) ${OBJS} + $(make-library) + +# Install the library, appending _g or _p as appropriate. +# for include files, just use $(INSTALL) +preinstall: + $(INSTALL) -m 444 $(H_FILES) $(PROJECT_INCLUDE)/libchip + + diff --git a/c/src/libchip/serial/ns16550.c b/c/src/libchip/serial/ns16550.c new file mode 100644 index 0000000000..dff820bb70 --- /dev/null +++ b/c/src/libchip/serial/ns16550.c @@ -0,0 +1,608 @@ +/* + * This file contains the TTY driver for the NS16550 + * + * COPYRIGHT (c) 1998 by Radstone Technology + * + * + * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY + * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK + * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU. + * + * You are hereby granted permission to use, copy, modify, and distribute + * this file, provided that this notice, plus the above copyright notice + * and disclaimer, appears in all copies. Radstone Technology will provide + * no support for this code. + * + * This driver uses the termios pseudo driver. + */ + +#include <rtems.h> +#include <rtems/libio.h> +#include <stdlib.h> + +#include "console.h" +#include "ns16550_p.h" + +/* + * Flow control is only supported when using interrupts + */ +console_flow ns16550_flow_RTSCTS = +{ + ns16550_negate_RTS, /* deviceStopRemoteTx */ + ns16550_assert_RTS /* deviceStartRemoteTx */ +}; + +console_flow ns16550_flow_DTRCTS = +{ + ns16550_negate_DTR, /* deviceStopRemoteTx */ + ns16550_assert_DTR /* deviceStartRemoteTx */ +}; + +console_fns ns16550_fns = +{ + ns16550_probe, /* deviceProbe */ + ns16550_open, /* deviceFirstOpen */ + ns16550_flush, /* deviceLastClose */ + NULL, /* deviceRead */ + ns16550_write_support_int, /* deviceWrite */ + ns16550_initialize_interrupts, /* deviceInitialize */ + ns16550_write_polled, /* deviceWritePolled */ + FALSE, /* deviceOutputUsesInterrupts */ +}; + +console_fns ns16550_fns_polled = +{ + ns16550_probe, /* deviceProbe */ + ns16550_open, /* deviceFirstOpen */ + ns16550_close, /* deviceLastClose */ + ns16550_inbyte_nonblocking_polled, /* deviceRead */ + ns16550_write_support_polled, /* deviceWrite */ + ns16550_init, /* deviceInitialize */ + ns16550_write_polled, /* deviceWritePolled */ + FALSE, /* deviceOutputUsesInterrupts */ +}; + +extern void set_vector( rtems_isr_entry, rtems_vector_number, int ); + +/* + * Types for get and set register routines + */ + +typedef unsigned8 (*getRegister_f)(unsigned32 port, unsigned8 register); +typedef void (*setRegister_f)( + unsigned32 port, unsigned8 reg, unsigned8 value); +/* + * Console Device Driver Entry Points + */ +static boolean ns16550_probe(int minor) +{ + /* + * If the configuration dependant probe has located the device then + * assume it is there + */ + return(TRUE); +} + +static void ns16550_init(int minor) +{ + unsigned32 pNS16550; + unsigned8 ucTrash; + unsigned8 ucDataByte; + unsigned32 ulBaudDivisor; + ns16550_context *pns16550Context; + setRegister_f setReg; + getRegister_f getReg; + + pns16550Context=(ns16550_context *)malloc(sizeof(ns16550_context)); + + Console_Port_Data[minor].pDeviceContext=(void *)pns16550Context; + pns16550Context->ucModemCtrl=SP_MODEM_IRQ; + + pNS16550 = Console_Port_Tbl[minor].ulCtrlPort1; + setReg = Console_Port_Tbl[minor].setRegister; + getReg = Console_Port_Tbl[minor].getRegister; + + /* Clear the divisor latch, clear all interrupt enables, + * and reset and + * disable the FIFO's. + */ + + (*setReg)(pNS16550, NS16550_LINE_CONTROL, 0x0); + (*setReg)(pNS16550, NS16550_INTERRUPT_ENABLE, 0x0); + + /* Set the divisor latch and set the baud rate. */ + + ulBaudDivisor=NS16550_Baud((unsigned32)Console_Port_Tbl[minor].pDeviceParams); + ucDataByte = SP_LINE_DLAB; + (*setReg)(pNS16550, NS16550_LINE_CONTROL, ucDataByte); + (*setReg)(pNS16550, NS16550_TRANSMIT_BUFFER, ulBaudDivisor&0xff); + (*setReg)(pNS16550, NS16550_INTERRUPT_ENABLE, (ulBaudDivisor>>8)&0xff); + + /* Clear the divisor latch and set the character size to eight bits */ + /* with one stop bit and no parity checking. */ + ucDataByte = EIGHT_BITS; + (*setReg)(pNS16550, NS16550_LINE_CONTROL, ucDataByte); + + /* Enable and reset transmit and receive FIFOs. TJA */ + ucDataByte = SP_FIFO_ENABLE; + (*setReg)(pNS16550, NS16550_FIFO_CONTROL, ucDataByte); + + ucDataByte = SP_FIFO_ENABLE | SP_FIFO_RXRST | SP_FIFO_TXRST; + (*setReg)(pNS16550, NS16550_FIFO_CONTROL, ucDataByte); + + /* + * Disable interrupts + */ + ucDataByte = 0; + (*setReg)(pNS16550, NS16550_INTERRUPT_ENABLE, ucDataByte); + + /* Set data terminal ready. */ + /* And open interrupt tristate line */ + (*setReg)(pNS16550, NS16550_MODEM_CONTROL,pns16550Context->ucModemCtrl); + + ucTrash = (*getReg)(pNS16550, NS16550_LINE_STATUS ); + ucTrash = (*getReg)(pNS16550, NS16550_RECEIVE_BUFFER ); +} + +static int ns16550_open( + int major, + int minor, + void * arg +) +{ + /* + * Assert DTR + */ + + if(Console_Port_Tbl[minor].pDeviceFlow != &ns16550_flow_DTRCTS) { + ns16550_assert_DTR(minor); + } + + return(RTEMS_SUCCESSFUL); +} + +static int ns16550_close( + int major, + int minor, + void * arg +) +{ + /* + * Negate DTR + */ + if(Console_Port_Tbl[minor].pDeviceFlow != &ns16550_flow_DTRCTS) { + ns16550_negate_DTR(minor); + } + + return(RTEMS_SUCCESSFUL); +} + +/* + * ns16550_write_polled + */ +static void ns16550_write_polled( + int minor, + char cChar +) +{ + unsigned32 pNS16550; + unsigned char ucLineStatus; + int iTimeout; + getRegister_f getReg; + setRegister_f setReg; + + pNS16550 = Console_Port_Tbl[minor].ulCtrlPort1; + getReg = Console_Port_Tbl[minor].getRegister; + setReg = Console_Port_Tbl[minor].setRegister; + + /* + * wait for transmitter holding register to be empty + */ + iTimeout=1000; + ucLineStatus = (*getReg)(pNS16550, NS16550_LINE_STATUS); + while ((ucLineStatus & SP_LSR_THOLD) == 0) { + /* + * Yield while we wait + */ + if(_System_state_Is_up(_System_state_Get())) { + rtems_task_wake_after(RTEMS_YIELD_PROCESSOR); + } + ucLineStatus = (*getReg)(pNS16550, NS16550_LINE_STATUS); + if(!--iTimeout) { + break; + } + } + + /* + * transmit character + */ + (*setReg)(pNS16550, NS16550_TRANSMIT_BUFFER, cChar); +} + +/* + * These routines provide control of the RTS and DTR lines + */ +/* + * ns16550_assert_RTS + */ +static int ns16550_assert_RTS(int minor) +{ + unsigned32 pNS16550; + unsigned32 Irql; + ns16550_context *pns16550Context; + setRegister_f setReg; + + pns16550Context=(ns16550_context *) Console_Port_Data[minor].pDeviceContext; + + pNS16550 = Console_Port_Tbl[minor].ulCtrlPort1; + setReg = Console_Port_Tbl[minor].setRegister; + + /* + * Assert RTS + */ + rtems_interrupt_disable(Irql); + pns16550Context->ucModemCtrl|=SP_MODEM_RTS; + (*setReg)(pNS16550, NS16550_MODEM_CONTROL, pns16550Context->ucModemCtrl); + rtems_interrupt_enable(Irql); + return 0; +} + +/* + * ns16550_negate_RTS + */ +static int ns16550_negate_RTS(int minor) +{ + unsigned32 pNS16550; + unsigned32 Irql; + ns16550_context *pns16550Context; + setRegister_f setReg; + + pns16550Context=(ns16550_context *) Console_Port_Data[minor].pDeviceContext; + + pNS16550 = Console_Port_Tbl[minor].ulCtrlPort1; + setReg = Console_Port_Tbl[minor].setRegister; + + /* + * Negate RTS + */ + rtems_interrupt_disable(Irql); + pns16550Context->ucModemCtrl&=~SP_MODEM_RTS; + (*setReg)(pNS16550, NS16550_MODEM_CONTROL, pns16550Context->ucModemCtrl); + rtems_interrupt_enable(Irql); + return 0; +} + +/* + * These flow control routines utilise a connection from the local DTR + * line to the remote CTS line + */ +/* + * ns16550_assert_DTR + */ +static int ns16550_assert_DTR(int minor) +{ + unsigned32 pNS16550; + unsigned32 Irql; + ns16550_context *pns16550Context; + setRegister_f setReg; + + pns16550Context=(ns16550_context *) Console_Port_Data[minor].pDeviceContext; + + pNS16550 = Console_Port_Tbl[minor].ulCtrlPort1; + setReg = Console_Port_Tbl[minor].setRegister; + + /* + * Assert DTR + */ + rtems_interrupt_disable(Irql); + pns16550Context->ucModemCtrl|=SP_MODEM_DTR; + (*setReg)(pNS16550, NS16550_MODEM_CONTROL, pns16550Context->ucModemCtrl); + rtems_interrupt_enable(Irql); + return 0; +} + +/* + * ns16550_negate_DTR + */ +static int ns16550_negate_DTR(int minor) +{ + unsigned32 pNS16550; + unsigned32 Irql; + ns16550_context *pns16550Context; + setRegister_f setReg; + + pns16550Context=(ns16550_context *) Console_Port_Data[minor].pDeviceContext; + + pNS16550 = Console_Port_Tbl[minor].ulCtrlPort1; + setReg = Console_Port_Tbl[minor].setRegister; + + /* + * Negate DTR + */ + rtems_interrupt_disable(Irql); + pns16550Context->ucModemCtrl&=~SP_MODEM_DTR; + (*setReg)(pNS16550, NS16550_MODEM_CONTROL,pns16550Context->ucModemCtrl); + rtems_interrupt_enable(Irql); + return 0; +} + +/* + * ns16550_isr + * + * This routine is the console interrupt handler for COM1 and COM2 + * + * Input parameters: + * vector - vector number + * + * Output parameters: NONE + * + * Return values: NONE + */ + +static void ns16550_process( + int minor +) +{ + unsigned32 pNS16550; + volatile unsigned8 ucLineStatus; + volatile unsigned8 ucInterruptId; + char cChar; + getRegister_f getReg; + setRegister_f setReg; + + pNS16550 = Console_Port_Tbl[minor].ulCtrlPort1; + getReg = Console_Port_Tbl[minor].getRegister; + setReg = Console_Port_Tbl[minor].setRegister; + + do { + /* + * Deal with any received characters + */ + while(TRUE) { + ucLineStatus = (*getReg)(pNS16550, NS16550_LINE_STATUS); + if(~ucLineStatus & SP_LSR_RDY) { + break; + } + cChar = (*getReg)(pNS16550, NS16550_RECEIVE_BUFFER); + rtems_termios_enqueue_raw_characters( + Console_Port_Data[minor].termios_data, + &cChar, + 1 + ); + } + + while(TRUE) { + if(Ring_buffer_Is_empty(&Console_Port_Data[minor].TxBuffer)) { + Console_Port_Data[minor].bActive=FALSE; + if(Console_Port_Tbl[minor].pDeviceFlow !=&ns16550_flow_RTSCTS) { + ns16550_negate_RTS(minor); + } + + /* + * There is no data to transmit + */ + break; + } + + ucLineStatus = (*getReg)(pNS16550, NS16550_LINE_STATUS); + if(~ucLineStatus & SP_LSR_THOLD) { + /* + * We'll get another interrupt when + * the transmitter holding reg. becomes + * free again + */ + break; + } + + Ring_buffer_Remove_character( &Console_Port_Data[minor].TxBuffer, cChar); + /* + * transmit character + */ + (*setReg)(pNS16550, NS16550_TRANSMIT_BUFFER, cChar); + } + + ucInterruptId = (*getReg)(pNS16550, NS16550_INTERRUPT_ID); + } + while((ucInterruptId&0xf)!=0x1); +} + +static rtems_isr ns16550_isr( + rtems_vector_number vector +) +{ + int minor; + + for(minor=0;minor<Console_Port_Count;minor++) { + if(vector==Console_Port_Tbl[minor].ulIntVector) { + ns16550_process(minor); + } + } +} + +/* + * ns16550_flush + */ +static int ns16550_flush(int major, int minor, void *arg) +{ + while(!Ring_buffer_Is_empty(&Console_Port_Data[minor].TxBuffer)) { + /* + * Yield while we wait + */ + if(_System_state_Is_up(_System_state_Get())) { + rtems_task_wake_after(RTEMS_YIELD_PROCESSOR); + } + } + + ns16550_close(major, minor, arg); + + return(RTEMS_SUCCESSFUL); +} + +/* + * ns16550_initialize_interrupts + * + * This routine initializes the console's receive and transmit + * ring buffers and loads the appropriate vectors to handle the interrupts. + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * Return values: NONE + */ + +static void ns16550_enable_interrupts( + int minor +) +{ + unsigned32 pNS16550; + unsigned8 ucDataByte; + setRegister_f setReg; + + pNS16550 = Console_Port_Tbl[minor].ulCtrlPort1; + setReg = Console_Port_Tbl[minor].setRegister; + + /* + * Enable interrupts + */ + ucDataByte = SP_INT_RX_ENABLE | SP_INT_TX_ENABLE; + (*setReg)(pNS16550, NS16550_INTERRUPT_ENABLE, ucDataByte); + +} + +static void ns16550_initialize_interrupts(int minor) +{ + ns16550_init(minor); + + Ring_buffer_Initialize(&Console_Port_Data[minor].TxBuffer); + + Console_Port_Data[minor].bActive = FALSE; + + set_vector(ns16550_isr, Console_Port_Tbl[minor].ulIntVector, 1); + + ns16550_enable_interrupts(minor); +} + +/* + * ns16550_write_support_int + * + * Console Termios output entry point. + * + */ +static int ns16550_write_support_int( + int minor, + const char *buf, + int len +) +{ + int i; + unsigned32 Irql; + + for(i=0; i<len;) { + if(Ring_buffer_Is_full(&Console_Port_Data[minor].TxBuffer)) { + if(!Console_Port_Data[minor].bActive) { + /* + * Wake up the device + */ + rtems_interrupt_disable(Irql); + Console_Port_Data[minor].bActive = TRUE; + if(Console_Port_Tbl[minor].pDeviceFlow != &ns16550_flow_RTSCTS) { + ns16550_assert_RTS(minor); + } + ns16550_process(minor); + rtems_interrupt_enable(Irql); + } else { + /* + * Yield + */ + rtems_task_wake_after(RTEMS_YIELD_PROCESSOR); + } + + /* + * Wait for ring buffer to empty + */ + continue; + } + else { + Ring_buffer_Add_character( &Console_Port_Data[minor].TxBuffer, buf[i]); + i++; + } + } + + /* + * Ensure that characters are on the way + */ + if(!Console_Port_Data[minor].bActive) { + /* + * Wake up the device + */ + rtems_interrupt_disable(Irql); + Console_Port_Data[minor].bActive = TRUE; + if(Console_Port_Tbl[minor].pDeviceFlow !=&ns16550_flow_RTSCTS) { + ns16550_assert_RTS(minor); + } + ns16550_process(minor); + rtems_interrupt_enable(Irql); + } + + return (len); +} + +/* + * ns16550_write_support_polled + * + * Console Termios output entry point. + * + */ +static int ns16550_write_support_polled( + int minor, + const char *buf, + int len +) +{ + int nwrite = 0; + + /* + * poll each byte in the string out of the port. + */ + while (nwrite < len) { + /* + * transmit character + */ + ns16550_write_polled(minor, *buf++); + nwrite++; + } + + /* + * return the number of bytes written. + */ + return nwrite; +} + +/* + * ns16550_inbyte_nonblocking_polled + * + * Console Termios polling input entry point. + */ + +static int ns16550_inbyte_nonblocking_polled( + int minor +) +{ + unsigned32 pNS16550; + unsigned char ucLineStatus; + char cChar; + getRegister_f getReg; + + pNS16550 = Console_Port_Tbl[minor].ulCtrlPort1; + getReg = Console_Port_Tbl[minor].getRegister; + + ucLineStatus = (*getReg)(pNS16550, NS16550_LINE_STATUS); + if(ucLineStatus & SP_LSR_RDY) { + cChar = (*getReg)(pNS16550, NS16550_RECEIVE_BUFFER); + return((int)cChar); + } else { + return(-1); + } +} diff --git a/c/src/libchip/serial/ns16550.h b/c/src/libchip/serial/ns16550.h new file mode 100644 index 0000000000..e797ba2244 --- /dev/null +++ b/c/src/libchip/serial/ns16550.h @@ -0,0 +1,40 @@ +/* + * COPYRIGHT (c) 1998 by Radstone Technology + * + * + * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY + * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK + * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU. + * + * You are hereby granted permission to use, copy, modify, and distribute + * this file, provided that this notice, plus the above copyright notice + * and disclaimer, appears in all copies. Radstone Technology will provide + * no support for this code. + * + */ + +#ifndef _NS16550_H_ +#define _NS16550_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Driver function table + */ +extern console_fns ns16550_fns; +extern console_fns ns16550_fns_polled; + +/* + * Flow control function tables + */ +extern console_flow ns16550_flow_RTSCTS; +extern console_flow ns16550_flow_DTRCTS; + +#ifdef __cplusplus +} +#endif + +#endif /* _NS16550_H_ */ diff --git a/c/src/libchip/serial/ns16550_p.h b/c/src/libchip/serial/ns16550_p.h new file mode 100644 index 0000000000..9e610119e0 --- /dev/null +++ b/c/src/libchip/serial/ns16550_p.h @@ -0,0 +1,208 @@ +/* + * COPYRIGHT (c) 1998 by Radstone Technology + * + * + * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY + * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK + * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU. + * + * You are hereby granted permission to use, copy, modify, and distribute + * this file, provided that this notice, plus the above copyright notice + * and disclaimer, appears in all copies. Radstone Technology will provide + * no support for this code. + * + */ + +#ifndef _NS16550_P_H_ +#define _NS16550_P_H_ + +#ifdef __cplusplus +extern "C" { +#endif +/* + * Define serial port read registers structure. + */ + +typedef volatile struct _SP_READ_REGISTERS { + unsigned char ReceiveBuffer; + unsigned char InterruptEnable; + unsigned char InterruptId; + unsigned char LineControl; + unsigned char ModemControl; + unsigned char LineStatus; + unsigned char ModemStatus; + unsigned char ScratchPad; +} SP_READ_REGISTERS, *PSP_READ_REGISTERS; + + +#define NS16550_RECEIVE_BUFFER 0 +#define NS16550_INTERRUPT_ENABLE 1 +#define NS16550_INTERRUPT_ID 2 +#define NS16550_LINE_CONTROL 3 +#define NS16550_MODEM_CONTROL 4 +#define NS16550_LINE_STATUS 5 +#define NS16550_MODEM_STATUS 6 +#define NS16550_SCRATCH_PAD 7 +/* + * Define serial port write registers structure. + */ + +typedef volatile struct _SP_WRITE_REGISTERS { + unsigned char TransmitBuffer; + unsigned char InterruptEnable; + unsigned char FifoControl; + unsigned char LineControl; + unsigned char ModemControl; + unsigned char Reserved1; + unsigned char ModemStatus; + unsigned char ScratchPad; +} SP_WRITE_REGISTERS, *PSP_WRITE_REGISTERS; + +#define NS16550_TRANSMIT_BUFFER 0 +#define NS16550_FIFO_CONTROL 2 + +/* + * Define serial port interrupt enable register structure. + */ + +#define SP_INT_RX_ENABLE 0x01 +#define SP_INT_TX_ENABLE 0x02 +#define SP_INT_LS_ENABLE 0x04 +#define SP_INT_MS_ENABLE 0x08 + +/* + * Define serial port interrupt id register structure. + */ + +typedef struct _SP_INTERRUPT_ID { + unsigned char InterruptPending : 1; + unsigned char Identification : 3; + unsigned char Reserved1 : 2; + unsigned char FifoEnabled : 2; +} SP_INTERRUPT_ID, *PSP_INTERRUPT_ID; + +/* + * Define serial port fifo control register structure. + */ +#define SP_FIFO_ENABLE 0x01 +#define SP_FIFO_RXRST 0x02 +#define SP_FIFO_TXRST 0x04 +#define SP_FIFO_DMA 0x08 +#define SP_FIFO_RXLEVEL 0xc0 + +/* + * Define serial port line control register structure. + */ +#define SP_LINE_SIZE 0x03 +#define SP_LINE_STOP 0x04 +#define SP_LINE_PAR 0x08 +#define SP_LINE_ODD 0x10 +#define SP_LINE_STICK 0x20 +#define SP_LINE_BREAK 0x40 +#define SP_LINE_DLAB 0x80 + +/* + * Line status register character size definitions. + */ +#define FIVE_BITS 0x0 /* five bits per character */ +#define SIX_BITS 0x1 /* six bits per character */ +#define SEVEN_BITS 0x2 /* seven bits per character */ +#define EIGHT_BITS 0x3 /* eight bits per character */ + +/* + * Line speed divisor definition. + */ +#define NS16550_Baud(baud_rate) (115200/baud_rate) + +/* + * Define serial port modem control register structure. + */ +#define SP_MODEM_DTR 0x01 +#define SP_MODEM_RTS 0x02 +#define SP_MODEM_IRQ 0x08 +#define SP_MODEM_LOOP 0x10 +#define SP_MODEM_DIV4 0x80 + +/* + * Define serial port line status register structure. + */ +#define SP_LSR_RDY 0x01 +#define SP_LSR_EOVRUN 0x02 +#define SP_LSR_EPAR 0x04 +#define SP_LSR_EFRAME 0x08 +#define SP_LSR_BREAK 0x10 +#define SP_LSR_THOLD 0x20 +#define SP_LSR_TX 0x40 +#define SP_LSR_EFIFO 0x80 + +typedef struct _ns16550_context +{ + unsigned8 ucModemCtrl; +} ns16550_context; + +/* + * Driver functions + */ +static boolean ns16550_probe(int minor); + +static void ns16550_init(int minor); + +static int ns16550_open( + int major, + int minor, + void * arg +); + +static int ns16550_close( + int major, + int minor, + void * arg +); + +static void ns16550_write_polled( + int minor, + char cChar +); + +static int ns16550_assert_RTS( + int minor +); + +static int ns16550_negate_RTS( + int minor +); + +static int ns16550_assert_DTR( + int minor +); + +static int ns16550_negate_DTR( + int minor +); + +static void ns16550_initialize_interrupts(int minor); + +static int ns16550_flush(int major, int minor, void *arg); + +static int ns16550_write_support_int( + int minor, + const char *buf, + int len +); + +static int ns16550_write_support_polled( + int minor, + const char *buf, + int len + ); + +static int ns16550_inbyte_nonblocking_polled( + int minor +); + +#ifdef __cplusplus +} +#endif + +#endif /* _NS16550_P_H_ */ diff --git a/c/src/libchip/serial/z85c30.c b/c/src/libchip/serial/z85c30.c new file mode 100644 index 0000000000..9fc629938a --- /dev/null +++ b/c/src/libchip/serial/z85c30.c @@ -0,0 +1,830 @@ +/* + * This file contains the console driver chip level routines for the + * z85c30 chip. + * + * COPYRIGHT (c) 1998 by Radstone Technology + * + * + * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY + * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK + * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU. + * + * You are hereby granted permission to use, copy, modify, and distribute + * this file, provided that this notice, plus the above copyright notice + * and disclaimer, appears in all copies. Radstone Technology will provide + * no support for this code. + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include <rtems.h> +#include <rtems/libio.h> +#include <stdlib.h> + +#include "console.h" +#include "z85c30_p.h" + +/* + * Flow control is only supported when using interrupts + */ +console_flow z85c30_flow_RTSCTS = +{ + z85c30_negate_RTS, /* deviceStopRemoteTx */ + z85c30_assert_RTS /* deviceStartRemoteTx */ +}; + +console_flow z85c30_flow_DTRCTS = +{ + z85c30_negate_DTR, /* deviceStopRemoteTx */ + z85c30_assert_DTR /* deviceStartRemoteTx */ +}; + +/* + * Exported driver function table + */ +console_fns z85c30_fns = +{ + z85c30_probe, /* deviceProbe */ + z85c30_open, /* deviceFirstOpen */ + z85c30_flush, /* deviceLastClose */ + NULL, /* deviceRead */ + z85c30_write_support_int, /* deviceWrite */ + z85c30_initialize_interrupts, /* deviceInitialize */ + z85c30_write_polled, /* deviceWritePolled */ + FALSE, /* deviceOutputUsesInterrupts */ +}; + +console_fns z85c30_fns_polled = +{ + z85c30_probe, /* deviceProbe */ + z85c30_open, /* deviceFirstOpen */ + z85c30_close, /* deviceLastClose */ + z85c30_inbyte_nonblocking_polled, /* deviceRead */ + z85c30_write_support_polled, /* deviceWrite */ + z85c30_init, /* deviceInitialize */ + z85c30_write_polled, /* deviceWritePolled */ + FALSE, /* deviceOutputUsesInterrupts */ +}; + +extern void set_vector( rtems_isr_entry, rtems_vector_number, int ); + +/* + * Types for get and set register routines + */ + +typedef unsigned8 (*getRegister_f)(unsigned32 port, unsigned8 register); +typedef void (*setRegister_f)( + unsigned32 port, unsigned8 reg, unsigned8 value); +typedef unsigned8 (*getData_f)(unsigned32 port); +typedef void (*setData_f)(unsigned32 port, unsigned8 value); + + +/* + * z85c30_initialize_port + * + * initialize a z85c30 Port + */ + +static void z85c30_initialize_port( + int minor +) +{ + unsigned32 ulCtrlPort; + unsigned32 ulBaudDivisor; + setRegister_f setReg; + + ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; + setReg = Console_Port_Tbl[minor].setRegister; + + /* + * Using register 4 + * Set up the clock rate is 16 times the data + * rate, 8 bit sync char, 1 stop bit, no parity + */ + + (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR4, SCC_WR4_1_STOP | SCC_WR4_16_CLOCK ); + + /* + * Set up for 8 bits/character on receive with + * receiver disable via register 3 + */ + (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR3, SCC_WR3_RX_8_BITS ); + + /* + * Set up for 8 bits/character on transmit + * with transmitter disable via register 5 + */ + (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR5, SCC_WR5_TX_8_BITS ); + + /* + * Clear misc control bits + */ + (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR10, 0x00 ); + + /* + * Setup the source of the receive and xmit + * clock as BRG output and the transmit clock + * as the output source for TRxC pin via register 11 + */ + (*setReg)( + ulCtrlPort, + SCC_WR0_SEL_WR11, + SCC_WR11_OUT_BR_GEN | SCC_WR11_TRXC_OI | + SCC_WR11_TX_BR_GEN | SCC_WR11_RX_BR_GEN + ); + + ulBaudDivisor = Z85C30_Baud( + (unsigned32) Console_Port_Tbl[minor].ulClock, + (unsigned32) Console_Port_Tbl[minor].pDeviceParams + ); + + /* + * Setup the lower 8 bits time constants=1E. + * If the time constans=1E, then the desire + * baud rate will be equilvalent to 9600, via register 12. + */ + (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR12, ulBaudDivisor & 0xff ); + + /* + * using register 13 + * Setup the upper 8 bits time constant + */ + (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR13, (ulBaudDivisor>>8) & 0xff ); + + /* + * Enable the baud rate generator enable with clock from the + * SCC's PCLK input via register 14. + */ + (*setReg)( + ulCtrlPort, + SCC_WR0_SEL_WR14, + SCC_WR14_BR_EN | SCC_WR14_BR_SRC | SCC_WR14_NULL + ); + + /* + * We are only interested in CTS state changes + */ + (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR15, SCC_WR15_CTS_IE ); + + /* + * Reset errors + */ + (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT ); + + (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_ERR_RST ); + + /* + * Enable the receiver via register 3 + */ + (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR3, SCC_WR3_RX_8_BITS | SCC_WR3_RX_EN ); + + /* + * Enable the transmitter pins set via register 5. + */ + (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR5, SCC_WR5_TX_8_BITS | SCC_WR5_TX_EN ); + + /* + * Disable interrupts + */ + (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR1, 0 ); + + /* + * Reset TX CRC + */ + (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_CRC ); + + /* + * Reset interrupts + */ + (*setReg)( ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT ); +} + +static int z85c30_open( + int major, + int minor, + void *arg +) +{ + /* + * Assert DTR + */ + + if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_DTRCTS) { + z85c30_assert_DTR(minor); + } + + return(RTEMS_SUCCESSFUL); +} + +static int z85c30_close( + int major, + int minor, + void *arg +) +{ + /* + * Negate DTR + */ + + if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_DTRCTS) { + z85c30_negate_DTR(minor); + } + + return(RTEMS_SUCCESSFUL); +} + +/* + * z85c30_write_polled + * + * This routine transmits a character using polling. + */ + +static void z85c30_write_polled( + int minor, + char cChar +) +{ + volatile unsigned8 z85c30_status; + unsigned32 ulCtrlPort; + getRegister_f getReg; + setData_f setData; + + ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; + getReg = Console_Port_Tbl[minor].getRegister; + setData = Console_Port_Tbl[minor].setData; + + /* + * Wait for the Transmit buffer to indicate that it is empty. + */ + + z85c30_status = (*getReg)( ulCtrlPort, SCC_WR0_SEL_RD0 ); + + while (!Z85C30_Status_Is_TX_buffer_empty(z85c30_status)) { + /* + * Yield while we wait + */ + if (_System_state_Is_up(_System_state_Get())) { + rtems_task_wake_after(RTEMS_YIELD_PROCESSOR); + } + z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); + } + + /* + * Write the character. + */ + + (*setData)(Console_Port_Tbl[minor].ulDataPort, cChar); +} + +/* + * Console Device Driver Entry Points + */ + +static boolean z85c30_probe(int minor) +{ + /* + * If the configuration dependant probe has located the device then + * assume it is there + */ + + return(TRUE); +} + +static void z85c30_init(int minor) +{ + unsigned32 ulCtrlPort; + unsigned8 dummy; + z85c30_context *pz85c30Context; + setRegister_f setReg; + getRegister_f getReg; + + setReg = Console_Port_Tbl[minor].setRegister; + getReg = Console_Port_Tbl[minor].getRegister; + + pz85c30Context = (z85c30_context *)malloc(sizeof(z85c30_context)); + + Console_Port_Data[minor].pDeviceContext=(void *)pz85c30Context; + + pz85c30Context->ucModemCtrl = SCC_WR5_TX_8_BITS | SCC_WR5_TX_EN; + + ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; + if (ulCtrlPort == Console_Port_Tbl[minor].ulCtrlPort2) { + /* + * This is channel A + */ + /* + * Ensure port state machine is reset + */ + dummy = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); + + (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR9, SCC_WR9_CH_A_RST); + + } else { + /* + * This is channel B + */ + /* + * Ensure port state machine is reset + */ + dummy = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); + + (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR9, SCC_WR9_CH_B_RST); + } + + z85c30_initialize_port(minor); +} + +/* + * These routines provide control of the RTS and DTR lines + */ +/* + * z85c30_assert_RTS + */ +static int z85c30_assert_RTS(int minor) +{ + rtems_interrupt_level Irql; + z85c30_context *pz85c30Context; + setRegister_f setReg; + + setReg = Console_Port_Tbl[minor].setRegister; + + pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext; + + /* + * Assert RTS + */ + + rtems_interrupt_disable(Irql); + pz85c30Context->ucModemCtrl|=SCC_WR5_RTS; + (*setReg)( + Console_Port_Tbl[minor].ulCtrlPort1, + SCC_WR0_SEL_WR5, + pz85c30Context->ucModemCtrl + ); + rtems_interrupt_enable(Irql); + return 0; +} + +/* + * z85c30_negate_RTS + */ +static int z85c30_negate_RTS(int minor) +{ + rtems_interrupt_level Irql; + z85c30_context *pz85c30Context; + setRegister_f setReg; + + setReg = Console_Port_Tbl[minor].setRegister; + + pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext; + + /* + * Negate RTS + */ + + rtems_interrupt_disable(Irql); + pz85c30Context->ucModemCtrl&=~SCC_WR5_RTS; + (*setReg)( + Console_Port_Tbl[minor].ulCtrlPort1, + SCC_WR0_SEL_WR5, + pz85c30Context->ucModemCtrl + ); + rtems_interrupt_enable(Irql); + return 0; +} + +/* + * These flow control routines utilise a connection from the local DTR + * line to the remote CTS line + */ +/* + * z85c30_assert_DTR + */ +static int z85c30_assert_DTR(int minor) +{ + rtems_interrupt_level Irql; + z85c30_context *pz85c30Context; + setRegister_f setReg; + + setReg = Console_Port_Tbl[minor].setRegister; + + pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext; + + /* + * Assert DTR + */ + + rtems_interrupt_disable(Irql); + pz85c30Context->ucModemCtrl|=SCC_WR5_DTR; + (*setReg)( + Console_Port_Tbl[minor].ulCtrlPort1, + SCC_WR0_SEL_WR5, + pz85c30Context->ucModemCtrl + ); + rtems_interrupt_enable(Irql); + return 0; +} + +/* + * z85c30_negate_DTR + */ +static int z85c30_negate_DTR(int minor) +{ + rtems_interrupt_level Irql; + z85c30_context *pz85c30Context; + setRegister_f setReg; + + setReg = Console_Port_Tbl[minor].setRegister; + + pz85c30Context = (z85c30_context *) Console_Port_Data[minor].pDeviceContext; + + /* + * Negate DTR + */ + + rtems_interrupt_disable(Irql); + pz85c30Context->ucModemCtrl&=~SCC_WR5_DTR; + (*setReg)( + Console_Port_Tbl[minor].ulCtrlPort1, + SCC_WR0_SEL_WR5, + pz85c30Context->ucModemCtrl + ); + rtems_interrupt_enable(Irql); + return 0; +} + +/* + * z85c30_isr + * + * This routine is the console interrupt handler for COM3 and COM4 + * + * Input parameters: + * vector - vector number + * + * Output parameters: NONE + * + * Return values: NONE + */ + +static void z85c30_process( + int minor, + unsigned8 ucIntPend +) +{ + unsigned32 ulCtrlPort; + unsigned32 ulDataPort; + volatile unsigned8 z85c30_status; + char cChar; + setRegister_f setReg; + getRegister_f getReg; + getData_f getData; + setData_f setData; + + ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; + ulDataPort = Console_Port_Tbl[minor].ulDataPort; + setReg = Console_Port_Tbl[minor].setRegister; + getReg = Console_Port_Tbl[minor].getRegister; + getData = Console_Port_Tbl[minor].getData; + getData = Console_Port_Tbl[minor].getData; + + /* + * Deal with any received characters + */ + while (ucIntPend&SCC_RR3_B_RX_IP) + { + z85c30_status=(*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); + if (!Z85C30_Status_Is_RX_character_available(z85c30_status)) { + break; + } + + /* + * Return the character read. + */ + + cChar = (*getData)(ulDataPort); + + rtems_termios_enqueue_raw_characters( + Console_Port_Data[minor].termios_data, + &cChar, + 1 + ); + } + + while (TRUE) + { + z85c30_status = (*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); + if (!Z85C30_Status_Is_TX_buffer_empty(z85c30_status)) { + /* + * We'll get another interrupt when + * the transmitter holding reg. becomes + * free again and we are clear to send + */ + break; + } + + if (!Z85C30_Status_Is_CTS_asserted(z85c30_status)) { + /* + * We can't transmit yet + */ + (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_INT); + /* + * The next state change of CTS will wake us up + */ + break; + } + + if (Ring_buffer_Is_empty(&Console_Port_Data[minor].TxBuffer)) { + Console_Port_Data[minor].bActive=FALSE; + if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_RTSCTS) { + z85c30_negate_RTS(minor); + } + /* + * There is no data to transmit + */ + (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_INT); + break; + } + + Ring_buffer_Remove_character( &Console_Port_Data[minor].TxBuffer, cChar); + + /* + * transmit character + */ + (*setData)(ulDataPort, cChar); + + /* + * Interrupt once FIFO has room + */ + (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_TX_INT); + break; + } + + if (ucIntPend&SCC_RR3_B_EXT_IP) { + /* + * Clear the external status interrupt + */ + (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT); + z85c30_status=(*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); + } + + /* + * Reset interrupts + */ + (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_HI_IUS); +} + +static rtems_isr z85c30_isr( + rtems_vector_number vector +) +{ + int minor; + unsigned32 ulCtrlPort; + volatile unsigned8 ucIntPend; + volatile unsigned8 ucIntPendPort; + getRegister_f getReg; + + for (minor=0;minor<Console_Port_Count;minor++) { + if (vector==Console_Port_Tbl[minor].ulIntVector) { + ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort2; + getReg = Console_Port_Tbl[minor].getRegister; + do { + ucIntPend=(*getReg)(ulCtrlPort, SCC_WR0_SEL_RD3); + + /* + * If this is channel A select channel A status + */ + + if (ulCtrlPort == Console_Port_Tbl[minor].ulCtrlPort1) { + ucIntPendPort = ucIntPend>>3; + ucIntPendPort = ucIntPendPort&=7; + } else { + ucIntPendPort = ucIntPend &= 7; + } + + if (ucIntPendPort) { + z85c30_process(minor, ucIntPendPort); + } + } while (ucIntPendPort); + } + } +} + +/* + * z85c30_flush + */ + +static int z85c30_flush( + int major, + int minor, + void *arg +) +{ + while (!Ring_buffer_Is_empty(&Console_Port_Data[minor].TxBuffer)) { + /* + * Yield while we wait + */ + if (_System_state_Is_up(_System_state_Get())) { + rtems_task_wake_after(RTEMS_YIELD_PROCESSOR); + } + } + + z85c30_close(major, minor, arg); + + return(RTEMS_SUCCESSFUL); +} + +/* + * z85c30_initialize_interrupts + * + * This routine initializes the console's receive and transmit + * ring buffers and loads the appropriate vectors to handle the interrupts. + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * Return values: NONE + */ + +static void z85c30_enable_interrupts( + int minor +) +{ + unsigned32 ulCtrlPort; + setRegister_f setReg; + + ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; + setReg = Console_Port_Tbl[minor].setRegister; + + /* + * Enable interrupts + */ + (*setReg)( + ulCtrlPort, + SCC_WR0_SEL_WR1, + SCC_WR1_EXT_INT_EN | SCC_WR1_TX_INT_EN | SCC_WR1_INT_ALL_RX + ); + (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR2, 0); + (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR9, SCC_WR9_MIE); + + /* + * Reset interrupts + */ + (*setReg)(ulCtrlPort, SCC_WR0_SEL_WR0, SCC_WR0_RST_INT); +} + +static void z85c30_initialize_interrupts( + int minor +) +{ + z85c30_init(minor); + + Ring_buffer_Initialize(&Console_Port_Data[minor].TxBuffer); + + Console_Port_Data[minor].bActive=FALSE; + if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_RTSCTS) { + z85c30_negate_RTS(minor); + } + + if (Console_Port_Tbl[minor].ulCtrlPort1== Console_Port_Tbl[minor].ulCtrlPort2) { + /* + * Only do this for Channel A + */ + + set_vector(z85c30_isr, Console_Port_Tbl[minor].ulIntVector, 1); + } + + z85c30_enable_interrupts(minor); +} + +/* + * z85c30_write_support_int + * + * Console Termios output entry point. + * + */ +static int z85c30_write_support_int( + int minor, + const char *buf, + int len) +{ + int i; + unsigned32 Irql; + + for (i=0; i<len;) { + if (Ring_buffer_Is_full(&Console_Port_Data[minor].TxBuffer)) { + if (!Console_Port_Data[minor].bActive) { + /* + * Wake up the device + */ + if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_RTSCTS) { + z85c30_assert_RTS(minor); + } + rtems_interrupt_disable(Irql); + Console_Port_Data[minor].bActive=TRUE; + z85c30_process(minor, SCC_RR3_B_TX_IP); + rtems_interrupt_enable(Irql); + } else { + /* + * Yield while we await an interrupt + */ + rtems_task_wake_after(RTEMS_YIELD_PROCESSOR); + } + + /* + * Wait for ring buffer to empty + */ + continue; + } else { + Ring_buffer_Add_character( &Console_Port_Data[minor].TxBuffer, buf[i]); + i++; + } + } + + /* + * Ensure that characters are on the way + */ + if (!Console_Port_Data[minor].bActive) { + /* + * Wake up the device + */ + if (Console_Port_Tbl[minor].pDeviceFlow !=&z85c30_flow_RTSCTS) { + z85c30_assert_RTS(minor); + } + rtems_interrupt_disable(Irql); + Console_Port_Data[minor].bActive=TRUE; + z85c30_process(minor, SCC_RR3_B_TX_IP); + rtems_interrupt_enable(Irql); + } + + return (len); +} + +/* + * z85c30_inbyte_nonblocking_polled + * + * This routine polls for a character. + */ +static int z85c30_inbyte_nonblocking_polled( + int minor +) +{ + volatile unsigned8 z85c30_status; + unsigned32 ulCtrlPort; + getRegister_f getReg; + getData_f getData; + + ulCtrlPort = Console_Port_Tbl[minor].ulCtrlPort1; + getData = Console_Port_Tbl[minor].getData; + getReg = Console_Port_Tbl[minor].getRegister; + + /* + * return -1 if a character is not available. + */ + z85c30_status=(*getReg)(ulCtrlPort, SCC_WR0_SEL_RD0); + if (!Z85C30_Status_Is_RX_character_available(z85c30_status)) { + return -1; + } + + /* + * Return the character read. + */ + return (*getData)(Console_Port_Tbl[minor].ulDataPort); +} + +/* + * z85c30_write_support_polled + * + * Console Termios output entry point. + * + */ + +static int z85c30_write_support_polled( + int minor, + const char *buf, + int len) +{ + int nwrite=0; + + /* + * poll each byte in the string out of the port. + */ + while (nwrite < len) { + z85c30_write_polled(minor, *buf++); + nwrite++; + } + + /* + * return the number of bytes written. + */ + return nwrite; +} diff --git a/c/src/libchip/serial/z85c30.h b/c/src/libchip/serial/z85c30.h new file mode 100644 index 0000000000..2eed03d1e3 --- /dev/null +++ b/c/src/libchip/serial/z85c30.h @@ -0,0 +1,54 @@ +/* z85c30.h + * + * This include file contains all console driver definations for the z85c30 + * + * COPYRIGHT (c) 1998 by Radstone Technology + * + * + * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY + * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK + * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU. + * + * You are hereby granted permission to use, copy, modify, and distribute + * this file, provided that this notice, plus the above copyright notice + * and disclaimer, appears in all copies. Radstone Technology will provide + * no support for this code. + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id: + */ + +#ifndef __Z85C30_H +#define __Z85C30_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * Driver function table + */ + +extern console_fns z85c30_fns; +extern console_fns z85c30_fns_polled; + +/* + * Flow control function tables + */ + +extern console_flow z85c30_flow_RTSCTS; +extern console_flow z85c30_flow_DTRCTS; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/c/src/libchip/serial/z85c30_p.h b/c/src/libchip/serial/z85c30_p.h new file mode 100644 index 0000000000..29f1aa7624 --- /dev/null +++ b/c/src/libchip/serial/z85c30_p.h @@ -0,0 +1,385 @@ +/* z85c30_p.h + * + * This include file contains all private driver definations for the z85c30 + * + * COPYRIGHT (c) 1998 by Radstone Technology + * + * + * THIS FILE IS PROVIDED TO YOU, THE USER, "AS IS", WITHOUT WARRANTY OF ANY + * KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK + * AS TO THE QUALITY AND PERFORMANCE OF ALL CODE IN THIS FILE IS WITH YOU. + * + * You are hereby granted permission to use, copy, modify, and distribute + * this file, provided that this notice, plus the above copyright notice + * and disclaimer, appears in all copies. Radstone Technology will provide + * no support for this code. + * + * COPYRIGHT (c) 1989-1997. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may in + * the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id: + */ + +#ifndef __Z85C30_P_H +#define __Z85C30_P_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* bit values for write register 0 */ +/* command register */ + +#define SCC_WR0_SEL_WR0 0x00 +#define SCC_WR0_SEL_WR1 0x01 +#define SCC_WR0_SEL_WR2 0x02 +#define SCC_WR0_SEL_WR3 0x03 +#define SCC_WR0_SEL_WR4 0x04 +#define SCC_WR0_SEL_WR5 0x05 +#define SCC_WR0_SEL_WR6 0x06 +#define SCC_WR0_SEL_WR7 0x07 +#define SCC_WR0_SEL_WR8 0x08 +#define SCC_WR0_SEL_WR9 0x09 +#define SCC_WR0_SEL_WR10 0x0a +#define SCC_WR0_SEL_WR11 0x0b +#define SCC_WR0_SEL_WR12 0x0c +#define SCC_WR0_SEL_WR13 0x0d +#define SCC_WR0_SEL_WR14 0x0e +#define SCC_WR0_SEL_WR15 0x0f +#define SCC_WR0_SEL_RD0 0x00 +#define SCC_WR0_SEL_RD1 0x01 +#define SCC_WR0_SEL_RD2 0x02 +#define SCC_WR0_SEL_RD3 0x03 +#define SCC_WR0_SEL_RD4 0x04 +#define SCC_WR0_SEL_RD5 0x05 +#define SCC_WR0_SEL_RD6 0x06 +#define SCC_WR0_SEL_RD7 0x07 +#define SCC_WR0_SEL_RD8 0x08 +#define SCC_WR0_SEL_RD9 0x09 +#define SCC_WR0_SEL_RD10 0x0a +#define SCC_WR0_SEL_RD11 0x0b +#define SCC_WR0_SEL_RD12 0x0c +#define SCC_WR0_SEL_RD13 0x0d +#define SCC_WR0_SEL_RD14 0x0e +#define SCC_WR0_SEL_RD15 0x0f +#define SCC_WR0_NULL_CODE 0x00 +#define SCC_WR0_RST_INT 0x10 +#define SCC_WR0_SEND_ABORT 0x18 +#define SCC_WR0_EN_INT_RX 0x20 +#define SCC_WR0_RST_TX_INT 0x28 +#define SCC_WR0_ERR_RST 0x30 +#define SCC_WR0_RST_HI_IUS 0x38 +#define SCC_WR0_RST_RX_CRC 0x40 +#define SCC_WR0_RST_TX_CRC 0x80 +#define SCC_WR0_RST_TX_UND 0xc0 + +/* write register 2 */ +/* interrupt vector */ + +/* bit values for write register 1 */ +/* tx/rx interrupt and data transfer mode definition */ + +#define SCC_WR1_EXT_INT_EN 0x01 +#define SCC_WR1_TX_INT_EN 0x02 +#define SCC_WR1_PARITY 0x04 +#define SCC_WR1_RX_INT_DIS 0x00 +#define SCC_WR1_RX_INT_FIR 0x08 +#define SCC_WR1_INT_ALL_RX 0x10 +#define SCC_WR1_RX_INT_SPE 0x18 +#define SCC_WR1_RDMA_RECTR 0x20 +#define SCC_WR1_RDMA_FUNC 0x40 +#define SCC_WR1_RDMA_EN 0x80 + +/* bit values for write register 3 */ +/* receive parameters and control */ + +#define SCC_WR3_RX_EN 0x01 +#define SCC_WR3_SYNC_CHAR 0x02 +#define SCC_WR3_ADR_SEARCH 0x04 +#define SCC_WR3_RX_CRC_EN 0x08 +#define SCC_WR3_ENTER_HUNT 0x10 +#define SCC_WR3_AUTO_EN 0x20 +#define SCC_WR3_RX_5_BITS 0x00 +#define SCC_WR3_RX_7_BITS 0x40 +#define SCC_WR3_RX_6_BITS 0x80 +#define SCC_WR3_RX_8_BITS 0xc0 + +/* bit values for write register 4 */ +/* tx/rx misc parameters and modes */ + +#define SCC_WR4_PAR_EN 0x01 +#define SCC_WR4_PAR_EVEN 0x02 +#define SCC_WR4_SYNC_EN 0x00 +#define SCC_WR4_1_STOP 0x04 +#define SCC_WR4_2_STOP 0x0c +#define SCC_WR4_8_SYNC 0x00 +#define SCC_WR4_16_SYNC 0x10 +#define SCC_WR4_SDLC 0x20 +#define SCC_WR4_EXT_SYNC 0x30 +#define SCC_WR4_1_CLOCK 0x00 +#define SCC_WR4_16_CLOCK 0x40 +#define SCC_WR4_32_CLOCK 0x80 +#define SCC_WR4_64_CLOCK 0xc0 + +/* bit values for write register 5 */ +/* transmit parameter and controls */ + +#define SCC_WR5_TX_CRC_EN 0x01 +#define SCC_WR5_RTS 0x02 +#define SCC_WR5_SDLC 0x04 +#define SCC_WR5_TX_EN 0x08 +#define SCC_WR5_SEND_BRK 0x10 + +#define SCC_WR5_TX_5_BITS 0x00 +#define SCC_WR5_TX_7_BITS 0x20 +#define SCC_WR5_TX_6_BITS 0x40 +#define SCC_WR5_TX_8_BITS 0x60 +#define SCC_WR5_DTR 0x80 + +/* write register 6 */ +/* sync chars or sdlc address field */ + +/* write register 7 */ +/* sync char or sdlc flag */ + +/* write register 8 */ +/* transmit buffer */ + +/* bit values for write register 9 */ +/* master interrupt control */ + +#define SCC_WR9_VIS 0x01 +#define SCC_WR9_NV 0x02 +#define SCC_WR9_DLC 0x04 +#define SCC_WR9_MIE 0x08 +#define SCC_WR9_STATUS_HI 0x10 +#define SCC_WR9_NO_RST 0x00 +#define SCC_WR9_CH_B_RST 0x40 +#define SCC_WR9_CH_A_RST 0x80 +#define SCC_WR9_HDWR_RST 0xc0 + +/* bit values for write register 10 */ +/* misc tx/rx control bits */ + +#define SCC_WR10_6_BIT_SYNC 0x01 +#define SCC_WR10_LOOP_MODE 0x02 +#define SCC_WR10_ABORT_UND 0x04 +#define SCC_WR10_MARK_IDLE 0x08 +#define SCC_WR10_ACT_POLL 0x10 +#define SCC_WR10_NRZ 0x00 +#define SCC_WR10_NRZI 0x20 +#define SCC_WR10_FM1 0x40 +#define SCC_WR10_FM0 0x60 +#define SCC_WR10_CRC_PRESET 0x80 + +/* bit values for write register 11 */ +/* clock mode control */ + +#define SCC_WR11_OUT_XTAL 0x00 +#define SCC_WR11_OUT_TX_CLK 0x01 +#define SCC_WR11_OUT_BR_GEN 0x02 +#define SCC_WR11_OUT_DPLL 0x03 +#define SCC_WR11_TRXC_OI 0x04 +#define SCC_WR11_TX_RTXC 0x00 +#define SCC_WR11_TX_TRXC 0x08 +#define SCC_WR11_TX_BR_GEN 0x10 +#define SCC_WR11_TX_DPLL 0x18 +#define SCC_WR11_RX_RTXC 0x00 +#define SCC_WR11_RX_TRXC 0x20 +#define SCC_WR11_RX_BR_GEN 0x40 +#define SCC_WR11_RX_DPLL 0x60 +#define SCC_WR11_RTXC_XTAL 0x80 + +/* write register 12 */ +/* lower byte of baud rate generator time constant */ + +/* write register 13 */ +/* upper byte of baud rate generator time constant */ + +/* bit values for write register 14 */ +/* misc control bits */ + +#define SCC_WR14_BR_EN 0x01 +#define SCC_WR14_BR_SRC 0x02 +#define SCC_WR14_DTR_FUNC 0x04 +#define SCC_WR14_AUTO_ECHO 0x08 +#define SCC_WR14_LCL_LOOP 0x10 +#define SCC_WR14_NULL 0x00 +#define SCC_WR14_SEARCH 0x20 +#define SCC_WR14_RST_CLK 0x40 +#define SCC_WR14_DIS_DPLL 0x60 +#define SCC_WR14_SRC_BR 0x80 +#define SCC_WR14_SRC_RTXC 0xa0 +#define SCC_WR14_FM_MODE 0xc0 +#define SCC_WR14_NRZI 0xe0 + +/* bit values for write register 15 */ +/* external/status interrupt control */ + +#define SCC_WR15_ZERO_CNT 0x02 +#define SCC_WR15_CD_IE 0x08 +#define SCC_WR15_SYNC_IE 0x10 +#define SCC_WR15_CTS_IE 0x20 +#define SCC_WR15_TX_UND_IE 0x40 +#define SCC_WR15_BREAK_IE 0x80 + +/* bit values for read register 0 */ +/* tx/rx buffer status and external status */ + +#define SCC_RR0_RX_AVAIL 0x01 +#define SCC_RR0_ZERO_CNT 0x02 +#define SCC_RR0_TX_EMPTY 0x04 +#define SCC_RR0_CD 0x08 +#define SCC_RR0_SYNC 0x10 +#define SCC_RR0_CTS 0x20 +#define SCC_RR0_TX_UND 0x40 +#define SCC_RR0_BREAK 0x80 + +/* bit values for read register 1 */ + +#define SCC_RR1_ALL_SENT 0x01 +#define SCC_RR1_RES_CD_2 0x02 +#define SCC_RR1_RES_CD_1 0x01 +#define SCC_RR1_RES_CD_0 0x08 +#define SCC_RR1_PAR_ERR 0x10 +#define SCC_RR1_RX_OV_ERR 0x20 +#define SCC_RR1_CRC_ERR 0x40 +#define SCC_RR1_END_FRAME 0x80 + +/* read register 2 */ +/* interrupt vector */ + +/* bit values for read register 3 */ +/* interrupt pending register */ + +#define SCC_RR3_B_EXT_IP 0x01 +#define SCC_RR3_B_TX_IP 0x02 +#define SCC_RR3_B_RX_IP 0x04 +#define SCC_RR3_A_EXT_IP 0x08 +#define SCC_RR3_A_TX_IP 0x10 +#define SCC_RR3_A_RX_IP 0x20 + +/* read register 8 */ +/* receive data register */ + +/* bit values for read register 10 */ +/* misc status bits */ + +#define SCC_RR10_ON_LOOP 0x02 +#define SCC_RR10_LOOP_SEND 0x10 +#define SCC_RR10_2_CLK_MIS 0x40 +#define SCC_RR10_1_CLK_MIS 0x80 + +/* read register 12 */ +/* lower byte of time constant */ + +/* read register 13 */ +/* upper byte of time constant */ + +/* bit values for read register 15 */ +/* external/status ie bits */ + +#define SCC_RR15_ZERO_CNT 0x02 +#define SCC_RR15_CD_IE 0x08 +#define SCC_RR15_SYNC_IE 0x10 +#define SCC_RR15_CTS_IE 0x20 +#define SCC_RR15_TX_UND_IE 0x40 +#define SCC_RR15_BREAK_IE 0x80 + +typedef struct _z85c30_context +{ + unsigned8 ucModemCtrl; +} z85c30_context; + +/* + * The following macro calculates the Baud constant. For the Z85C30 chip. + * + * Note: baud constant = ((clock frequency / Clock_X) / (2 * Baud Rate)) - 2 + * eg ((10,000,000 / 16) / (2 * Baud Rate)) - 2 + */ +#define Z85C30_Baud( _clock, _baud_rate ) \ + ( ((_clock) /( 16 * 2 * _baud_rate)) - 2) + +#define Z85C30_Status_Is_RX_character_available(_status) \ + ((_status) & SCC_RR0_RX_AVAIL) + +#define Z85C30_Status_Is_TX_buffer_empty(_status) \ + ((_status) & SCC_RR0_TX_EMPTY) + +#define Z85C30_Status_Is_CTS_asserted(_status) \ + ((_status) & SCC_RR0_CTS) + +#define Z85C30_Status_Is_break_abort(_status) \ + ((_status) & SCC_RR0_BREAK) + +/* + * Private routines + */ +static boolean z85c30_probe(int minor); + +static void z85c30_init(int minor); + +static int z85c30_open( + int major, + int minor, + void * arg +); + +static int z85c30_close( + int major, + int minor, + void * arg +); + +static void z85c30_write_polled( + int minor, + char cChar +); + +static int z85c30_assert_RTS( + int minor +); + +static int z85c30_negate_RTS( + int minor +); + +static int z85c30_assert_DTR( + int minor +); + +static int z85c30_negate_DTR( + int minor +); + +static void z85c30_initialize_interrupts(int minor); + +static int z85c30_flush(int major, int minor, void *arg); + +static int z85c30_write_support_int( + int minor, + const char *buf, + int len +); + +static int z85c30_write_support_polled( + int minor, + const char *buf, + int len +); + +static int z85c30_inbyte_nonblocking_polled( + int minor +); + +#ifdef __cplusplus +} +#endif + +#endif |