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-rw-r--r--bsps/aarch64/include/bsp/aarch64-mmu.h23
-rw-r--r--bsps/aarch64/raspberrypi/console/console.c69
-rw-r--r--bsps/aarch64/raspberrypi/include/bsp.h76
-rw-r--r--bsps/aarch64/raspberrypi/include/bsp/irq.h109
-rw-r--r--bsps/aarch64/raspberrypi/include/bsp/raspberrypi.h471
-rw-r--r--bsps/aarch64/raspberrypi/include/tm27.h46
-rw-r--r--bsps/aarch64/raspberrypi/start/bspstart.c49
-rw-r--r--bsps/aarch64/raspberrypi/start/bspstarthooks.c53
-rw-r--r--bsps/aarch64/raspberrypi/start/bspstartmmu.c84
-rw-r--r--bsps/aarch64/shared/start/linkcmds.base2
-rw-r--r--bsps/aarch64/shared/start/start.S6
-rw-r--r--bsps/aarch64/xilinx-versal/dev/serial/versal-uart-polled.c37
-rw-r--r--bsps/aarch64/xilinx-versal/dev/serial/versal-uart.c321
-rw-r--r--bsps/aarch64/xilinx-versal/include/bsp.h4
-rw-r--r--bsps/aarch64/xilinx-versal/include/bsp/i2c.h64
-rw-r--r--bsps/aarch64/xilinx-versal/include/bsp/irq.h2
-rw-r--r--bsps/aarch64/xilinx-versal/include/dev/serial/versal-uart-regs.h1
-rw-r--r--bsps/aarch64/xilinx-versal/include/dev/serial/versal-uart.h4
-rw-r--r--bsps/aarch64/xilinx-versal/start/bspstart.c12
-rw-r--r--bsps/aarch64/xilinx-versal/start/bspstartmmu.c6
-rw-r--r--bsps/aarch64/xilinx-zynqmp/console/console.c151
-rw-r--r--bsps/aarch64/xilinx-zynqmp/fdt/bsp_fdt.c51
-rw-r--r--bsps/aarch64/xilinx-zynqmp/fdt/cfc400x.dts110
-rw-r--r--bsps/aarch64/xilinx-zynqmp/fdt/cfc400x_dtb.c124
-rw-r--r--bsps/aarch64/xilinx-zynqmp/fdt/zynqmp.dts94
-rw-r--r--bsps/aarch64/xilinx-zynqmp/fdt/zynqmp_dtb.c97
-rw-r--r--bsps/aarch64/xilinx-zynqmp/include/bsp.h15
-rw-r--r--bsps/aarch64/xilinx-zynqmp/start/bspstartmmu.c4
-rw-r--r--bsps/arm/beagle/dcan/am335x-dcan.c104
-rw-r--r--bsps/arm/beagle/dcan/dcan.c646
-rwxr-xr-xbsps/arm/beagle/dcan/hw_cm_per.h1407
-rwxr-xr-xbsps/arm/beagle/dcan/hw_dcan.h1289
-rw-r--r--bsps/arm/beagle/include/bsp/am335x_dcan.h106
-rwxr-xr-xbsps/arm/beagle/include/bsp/hw_control_AM335x.h7794
-rwxr-xr-xbsps/arm/beagle/include/bsp/soc_AM335x.h206
-rw-r--r--bsps/arm/include/bsp/start.h6
-rw-r--r--bsps/arm/shared/clock/clock-armv7m.c2
-rw-r--r--bsps/arm/shared/start/linkcmds.base2
-rw-r--r--bsps/arm/shared/start/start.S3
-rw-r--r--bsps/arm/tms570/include/bsp/tms570_selftest_parity.h8
-rw-r--r--bsps/arm/tms570/start/bspstarthooks-hwinit.c2
-rw-r--r--bsps/i386/pc386/include/edid.h2
-rw-r--r--bsps/i386/pc386/start/linkcmds2
-rw-r--r--bsps/include/bsp/fatal.h5
-rw-r--r--bsps/include/bsp/irq-generic.h29
-rw-r--r--bsps/include/grlib/ahbstat.h25
-rw-r--r--bsps/include/grlib/ambapp.h25
-rw-r--r--bsps/include/grlib/ambapp_bus.h25
-rw-r--r--bsps/include/grlib/ambapp_bus_grlib.h25
-rw-r--r--bsps/include/grlib/ambapp_ids.h25
-rw-r--r--bsps/include/grlib/apbuart.h25
-rw-r--r--bsps/include/grlib/apbuart_cons.h25
-rw-r--r--bsps/include/grlib/apbuart_termios.h25
-rw-r--r--bsps/include/grlib/b1553brm.h25
-rw-r--r--bsps/include/grlib/b1553rt.h25
-rw-r--r--bsps/include/grlib/bspcommon.h25
-rw-r--r--bsps/include/grlib/canmux.h25
-rw-r--r--bsps/include/grlib/cons.h25
-rw-r--r--bsps/include/grlib/debug_defs.h29
-rw-r--r--bsps/include/grlib/genirq.h25
-rw-r--r--bsps/include/grlib/gpiolib.h25
-rw-r--r--bsps/include/grlib/gptimer.h25
-rw-r--r--bsps/include/grlib/gr1553b.h25
-rw-r--r--bsps/include/grlib/gr1553bc.h25
-rw-r--r--bsps/include/grlib/gr1553bc_list.h25
-rw-r--r--bsps/include/grlib/gr1553bm.h25
-rw-r--r--bsps/include/grlib/gr1553rt.h25
-rw-r--r--bsps/include/grlib/gr_701.h25
-rw-r--r--bsps/include/grlib/gr_cpci_gr740.h25
-rw-r--r--bsps/include/grlib/gr_rasta_adcdac.h25
-rw-r--r--bsps/include/grlib/gr_rasta_io.h25
-rw-r--r--bsps/include/grlib/gr_rasta_spw_router.h25
-rw-r--r--bsps/include/grlib/gr_rasta_tmtc.h25
-rw-r--r--bsps/include/grlib/gr_tmtc_1553.h25
-rw-r--r--bsps/include/grlib/gradcdac.h25
-rw-r--r--bsps/include/grlib/grascs.h25
-rw-r--r--bsps/include/grlib/grcan.h25
-rw-r--r--bsps/include/grlib/grctm.h25
-rw-r--r--bsps/include/grlib/grgpio.h25
-rw-r--r--bsps/include/grlib/griommu.h25
-rw-r--r--bsps/include/grlib/grlib.h25
-rw-r--r--bsps/include/grlib/grlib_impl.h43
-rw-r--r--bsps/include/grlib/grpci.h29
-rw-r--r--bsps/include/grlib/grpci2.h25
-rw-r--r--bsps/include/grlib/grpci2dma.h25
-rw-r--r--bsps/include/grlib/grpwm.h25
-rw-r--r--bsps/include/grlib/grslink.h25
-rw-r--r--bsps/include/grlib/grspw.h25
-rw-r--r--bsps/include/grlib/grspw_pkt.h25
-rw-r--r--bsps/include/grlib/grspw_router.h25
-rw-r--r--bsps/include/grlib/grtc.h25
-rw-r--r--bsps/include/grlib/grtm.h25
-rw-r--r--bsps/include/grlib/i2cmst.h25
-rw-r--r--bsps/include/grlib/l2c.h25
-rw-r--r--bsps/include/grlib/l4stat.h25
-rw-r--r--bsps/include/grlib/mctrl.h25
-rw-r--r--bsps/include/grlib/memscrub.h25
-rw-r--r--bsps/include/grlib/occan.h25
-rw-r--r--bsps/include/grlib/pcif.h29
-rw-r--r--bsps/include/grlib/satcan.h25
-rw-r--r--bsps/include/grlib/spictrl.h25
-rw-r--r--bsps/include/grlib/spwcuc.h25
-rw-r--r--bsps/include/grlib/spwtdp.h25
-rw-r--r--bsps/include/grlib/tlib.h25
-rw-r--r--bsps/include/libchip/greth.h152
-rw-r--r--bsps/m68k/shared/cache/cache.h56
-rw-r--r--bsps/m68k/shared/start/linkcmds.base2
-rw-r--r--bsps/or1k/shared/start/linkcmds.base2
-rw-r--r--bsps/powerpc/gen5200/include/tm27.h2
-rw-r--r--bsps/powerpc/gen5200/start/linkcmds.gen5200_base2
-rw-r--r--bsps/powerpc/motorola_powerpc/include/bsp.h2
-rw-r--r--bsps/powerpc/mvme5500/include/tm27.h2
-rw-r--r--bsps/powerpc/psim/include/tm27.h2
-rw-r--r--bsps/powerpc/qoriq/include/tm27.h10
-rw-r--r--bsps/powerpc/shared/cpu.c2
-rw-r--r--bsps/powerpc/shared/cpu_asm.S156
-rw-r--r--bsps/powerpc/shared/exceptions/ppc_exc_async_normal.S189
-rw-r--r--bsps/powerpc/shared/start/linkcmds.base2
-rw-r--r--bsps/powerpc/t32mppc/include/bsp/irq.h4
-rw-r--r--bsps/powerpc/virtex/console/consolelite.c8
-rw-r--r--bsps/riscv/griscv/clock/clockdrv.c25
-rw-r--r--bsps/riscv/griscv/console/console.c25
-rw-r--r--bsps/riscv/griscv/console/printk_support.c25
-rw-r--r--bsps/riscv/griscv/include/amba.h25
-rw-r--r--bsps/riscv/noel/console/console-config.c208
-rw-r--r--bsps/riscv/noel/include/bsp.h78
-rw-r--r--bsps/riscv/noel/include/bsp/irq.h75
-rw-r--r--bsps/riscv/noel/include/bsp/riscv.h61
-rw-r--r--bsps/riscv/noel/include/tm27.h1
-rw-r--r--bsps/riscv/noel/start/bsp_fatal_halt.c46
-rw-r--r--bsps/riscv/riscv/clock/clockdrv.c6
-rw-r--r--bsps/riscv/riscv/config/mpfs64imafdc.cfg9
-rw-r--r--bsps/riscv/riscv/console/console-config.c14
-rw-r--r--bsps/riscv/riscv/console/fe310-uart.c7
-rw-r--r--bsps/riscv/riscv/dts/mpfs.dts365
-rw-r--r--bsps/riscv/riscv/include/bsp.h2
-rw-r--r--bsps/riscv/riscv/include/bsp/irq.h4
-rw-r--r--bsps/riscv/riscv/include/bsp/mpfs-dtb.h602
-rw-r--r--bsps/riscv/riscv/include/bsp/riscv.h4
-rw-r--r--bsps/riscv/riscv/include/tm27.h137
-rw-r--r--bsps/riscv/riscv/irq/irq.c344
-rw-r--r--bsps/riscv/riscv/start/bsp_fatal_halt.c3
-rw-r--r--bsps/riscv/riscv/start/bspsmp.c2
-rw-r--r--bsps/riscv/riscv/start/bspstart.c21
-rw-r--r--bsps/riscv/shared/start/bspgetworkarea.c144
-rw-r--r--bsps/riscv/shared/start/start.S9
-rw-r--r--bsps/sh/gensh1/start/linkcmds12
-rw-r--r--bsps/sh/gensh2/start/linkcmds12
-rw-r--r--bsps/shared/cache/cacheimpl.h43
-rw-r--r--bsps/shared/grlib/1553/b1553brm.c25
-rw-r--r--bsps/shared/grlib/1553/b1553rt.c25
-rw-r--r--bsps/shared/grlib/1553/gr1553b.c25
-rw-r--r--bsps/shared/grlib/1553/gr1553bc.c25
-rw-r--r--bsps/shared/grlib/1553/gr1553bm.c25
-rw-r--r--bsps/shared/grlib/1553/gr1553rt.c25
-rw-r--r--bsps/shared/grlib/amba/ahbstat.c25
-rw-r--r--bsps/shared/grlib/amba/ambapp.c25
-rw-r--r--bsps/shared/grlib/amba/ambapp_alloc.c25
-rw-r--r--bsps/shared/grlib/amba/ambapp_count.c25
-rw-r--r--bsps/shared/grlib/amba/ambapp_depth.c25
-rw-r--r--bsps/shared/grlib/amba/ambapp_find_by_idx.c25
-rw-r--r--bsps/shared/grlib/amba/ambapp_freq.c25
-rw-r--r--bsps/shared/grlib/amba/ambapp_names.c25
-rw-r--r--bsps/shared/grlib/amba/ambapp_old.c25
-rw-r--r--bsps/shared/grlib/amba/ambapp_parent.c25
-rw-r--r--bsps/shared/grlib/amba/ambapp_show.c25
-rw-r--r--bsps/shared/grlib/analog/gradcdac.c25
-rw-r--r--bsps/shared/grlib/ascs/grascs.c25
-rw-r--r--bsps/shared/grlib/btimer/gptimer.c25
-rw-r--r--bsps/shared/grlib/btimer/tlib.c25
-rw-r--r--bsps/shared/grlib/btimer/tlib_ckinit.c25
-rw-r--r--bsps/shared/grlib/can/canbtrs.c2
-rw-r--r--bsps/shared/grlib/can/canmux.c25
-rw-r--r--bsps/shared/grlib/can/grcan.c25
-rw-r--r--bsps/shared/grlib/can/grcan_internal.h25
-rw-r--r--bsps/shared/grlib/can/grcanfd.c25
-rw-r--r--bsps/shared/grlib/can/grcanstd.c25
-rw-r--r--bsps/shared/grlib/can/occan.c25
-rw-r--r--bsps/shared/grlib/can/satcan.c25
-rw-r--r--bsps/shared/grlib/drvmgr/ambapp_bus.c25
-rw-r--r--bsps/shared/grlib/drvmgr/ambapp_bus_grlib.c25
-rw-r--r--bsps/shared/grlib/drvmgr/get_resarray_count.c25
-rw-r--r--bsps/shared/grlib/gpio/gpiolib.c25
-rw-r--r--bsps/shared/grlib/gpio/grgpio.c25
-rw-r--r--bsps/shared/grlib/i2c/i2cmst.c25
-rw-r--r--bsps/shared/grlib/iommu/griommu.c25
-rw-r--r--bsps/shared/grlib/irq/genirq.c25
-rw-r--r--bsps/shared/grlib/l2c/l2c.c25
-rw-r--r--bsps/shared/grlib/mem/mctrl.c25
-rw-r--r--bsps/shared/grlib/pci/gr_701.c25
-rw-r--r--bsps/shared/grlib/pci/gr_rasta_adcdac.c25
-rw-r--r--bsps/shared/grlib/pci/gr_rasta_io.c25
-rw-r--r--bsps/shared/grlib/pci/gr_rasta_spw_router.c25
-rw-r--r--bsps/shared/grlib/pci/gr_rasta_tmtc.c25
-rw-r--r--bsps/shared/grlib/pci/gr_tmtc_1553.c25
-rw-r--r--bsps/shared/grlib/pci/grpci.c25
-rw-r--r--bsps/shared/grlib/pci/grpci2.c25
-rw-r--r--bsps/shared/grlib/pci/grpci2dma.c25
-rw-r--r--bsps/shared/grlib/pci/pcif.c25
-rw-r--r--bsps/shared/grlib/pwm/grpwm.c25
-rw-r--r--bsps/shared/grlib/scrub/memscrub.c25
-rw-r--r--bsps/shared/grlib/slink/grslink.c25
-rw-r--r--bsps/shared/grlib/spi/spictrl.c25
-rw-r--r--bsps/shared/grlib/spw/grspw.c25
-rw-r--r--bsps/shared/grlib/spw/grspw_pkt.c25
-rw-r--r--bsps/shared/grlib/spw/grspw_router.c25
-rw-r--r--bsps/shared/grlib/spw/spwtdp.c25
-rw-r--r--bsps/shared/grlib/stat/l4stat.c25
-rw-r--r--bsps/shared/grlib/time/grctm.c25
-rw-r--r--bsps/shared/grlib/time/spwcuc.c25
-rw-r--r--bsps/shared/grlib/tmtc/grtc.c25
-rw-r--r--bsps/shared/grlib/tmtc/grtm.c25
-rw-r--r--bsps/shared/grlib/uart/apbuart_cons.c25
-rw-r--r--bsps/shared/grlib/uart/apbuart_polled.c25
-rw-r--r--bsps/shared/grlib/uart/apbuart_termios.c25
-rw-r--r--bsps/shared/grlib/uart/cons.c25
-rw-r--r--bsps/shared/start/bsp-fdt.c8
-rw-r--r--bsps/shared/start/bspfatal-default.c2
-rw-r--r--bsps/sparc/erc32/include/bsp/irq.h29
-rw-r--r--bsps/sparc/erc32/include/tm27.h25
-rw-r--r--bsps/sparc/erc32/start/bspstart.c25
-rw-r--r--bsps/sparc/include/bsp/gr_leon4_n2x.h25
-rw-r--r--bsps/sparc/include/drvmgr/leon2_amba_bus.h25
-rw-r--r--bsps/sparc/leon2/clock/ckinit.c25
-rw-r--r--bsps/sparc/leon2/include/bsp/at697_pci.h25
-rw-r--r--bsps/sparc/leon2/include/bsp/irq.h25
-rw-r--r--bsps/sparc/leon2/include/leon.h25
-rw-r--r--bsps/sparc/leon2/include/tm27.h25
-rw-r--r--bsps/sparc/leon2/pci/at697_pci.c25
-rw-r--r--bsps/sparc/leon2/start/bspstart.c25
-rw-r--r--bsps/sparc/leon3/btimer/watchdog.c25
-rw-r--r--bsps/sparc/leon3/clock/ckinit.c25
-rw-r--r--bsps/sparc/leon3/console/console.c25
-rw-r--r--bsps/sparc/leon3/console/printk_support.c25
-rw-r--r--bsps/sparc/leon3/include/amba.h25
-rw-r--r--bsps/sparc/leon3/include/bsp/irq.h25
-rw-r--r--bsps/sparc/leon3/include/bsp/watchdog.h25
-rw-r--r--bsps/sparc/leon3/include/leon.h25
-rw-r--r--bsps/sparc/leon3/include/tm27.h25
-rw-r--r--bsps/sparc/leon3/start/amba.c25
-rw-r--r--bsps/sparc/leon3/start/bsp_fatal_halt.c25
-rw-r--r--bsps/sparc/leon3/start/bspclean.c25
-rw-r--r--bsps/sparc/leon3/start/bspidle.S25
-rw-r--r--bsps/sparc/leon3/start/bspstart.c25
-rw-r--r--bsps/sparc/leon3/start/cpucounter.c25
-rw-r--r--bsps/sparc/leon3/start/drvmgr_def_drivers.c25
-rw-r--r--bsps/sparc/leon3/start/eirq.c25
-rw-r--r--bsps/sparc/shared/drvmgr/ambapp_bus_leon2.c25
-rw-r--r--bsps/sparc/shared/drvmgr/leon2_amba_bus.c25
-rw-r--r--bsps/sparc/shared/irq/bsp_isr_handler.c35
-rw-r--r--bsps/sparc/shared/irq/irq-shared.c35
-rw-r--r--bsps/sparc/shared/pci/gr_cpci_gr740.c25
-rw-r--r--bsps/sparc/shared/pci/gr_leon4_n2x.c31
-rw-r--r--bsps/sparc/shared/pci/pci_memreg_sparc_be.c25
-rw-r--r--bsps/sparc/shared/pci/pci_memreg_sparc_le.c25
-rw-r--r--bsps/sparc/shared/start/bsp_fatal_exit.c25
-rw-r--r--bsps/sparc/shared/start/bsp_fatal_halt.c25
-rw-r--r--bsps/sparc/shared/start/start.S25
-rw-r--r--bsps/x86_64/amd64/config/amd64.cfg1
-rw-r--r--bsps/x86_64/amd64/start/page.c2
-rw-r--r--cpukit/dev/can/can.c505
-rw-r--r--cpukit/doxygen/appl-config.h239
-rw-r--r--cpukit/include/adainclude/rtems-io.adb21
-rw-r--r--cpukit/include/dev/can/can-msg.h105
-rw-r--r--cpukit/include/dev/can/can.h284
-rw-r--r--cpukit/include/dev/can/canqueueimpl.h231
-rw-r--r--cpukit/include/drvmgr/drvmgr.h29
-rw-r--r--cpukit/include/drvmgr/drvmgr_confdefs.h25
-rw-r--r--cpukit/include/drvmgr/drvmgr_list.h25
-rw-r--r--cpukit/include/drvmgr/pci_bus.h25
-rw-r--r--cpukit/include/link_elf.h8
-rw-r--r--cpukit/include/linux/rbtree.h10
-rw-r--r--cpukit/include/pci.h25
-rw-r--r--cpukit/include/pci/access.h45
-rw-r--r--cpukit/include/pci/cfg.h25
-rw-r--r--cpukit/include/pci/cfg_auto.h25
-rw-r--r--cpukit/include/pci/cfg_peripheral.h25
-rw-r--r--cpukit/include/pci/cfg_read.h25
-rw-r--r--cpukit/include/pci/cfg_static.h25
-rw-r--r--cpukit/include/pci/ids_extra.h30
-rw-r--r--cpukit/include/pci/irq.h35
-rw-r--r--cpukit/include/rtems/bsd.h24
-rw-r--r--cpukit/include/rtems/capture.h4
-rw-r--r--cpukit/include/rtems/cbs.h24
-rw-r--r--cpukit/include/rtems/chain.h64
-rw-r--r--cpukit/include/rtems/confdefs.h1
-rw-r--r--cpukit/include/rtems/confdefs/face.h82
-rw-r--r--cpukit/include/rtems/confdefs/inittask.h3
-rw-r--r--cpukit/include/rtems/confdefs/libpci.h25
-rw-r--r--cpukit/include/rtems/confdefs/percpu.h14
-rw-r--r--cpukit/include/rtems/confdefs/scheduler.h10
-rw-r--r--cpukit/include/rtems/confdefs/threads.h19
-rw-r--r--cpukit/include/rtems/confdefs/wkspace.h50
-rw-r--r--cpukit/include/rtems/config.h631
-rw-r--r--cpukit/include/rtems/counter.h8
-rw-r--r--cpukit/include/rtems/debugger/rtems-debugger-server.h1
-rw-r--r--cpukit/include/rtems/extensionimpl.h6
-rw-r--r--cpukit/include/rtems/fatal.h2
-rw-r--r--cpukit/include/rtems/init.h2
-rw-r--r--cpukit/include/rtems/ioimpl.h4
-rw-r--r--cpukit/include/rtems/libio.h2
-rw-r--r--cpukit/include/rtems/linkersets.h2
-rw-r--r--cpukit/include/rtems/malloc.h60
-rw-r--r--cpukit/include/rtems/mallocinitmulti.h2
-rw-r--r--cpukit/include/rtems/mallocinitone.h2
-rw-r--r--cpukit/include/rtems/media.h2
-rw-r--r--cpukit/include/rtems/posix/condimpl.h10
-rw-r--r--cpukit/include/rtems/posix/keyimpl.h22
-rw-r--r--cpukit/include/rtems/posix/mqueueimpl.h14
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-rw-r--r--spec/build/bsps/nios2/nios2_iss/bspnios2iss.yml1
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-rw-r--r--spec/build/bsps/optdtbheaderpath.yml20
-rw-r--r--spec/build/bsps/or1k/generic_or1k/bspgenericor1k.yml1
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-rw-r--r--spec/build/bsps/powerpc/gen5200/obj.yml1
-rw-r--r--spec/build/bsps/powerpc/gen83xx/obj.yml1
-rw-r--r--spec/build/bsps/powerpc/motorola_powerpc/obj.yml1
-rw-r--r--spec/build/bsps/powerpc/mpc55xxevb/obj.yml1
-rw-r--r--spec/build/bsps/powerpc/mpc8260ads/bspmpc8260ads.yml1
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-rw-r--r--spec/build/bsps/powerpc/psim/bsppsim.yml1
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-rw-r--r--spec/build/bsps/powerpc/qoriq/obj.yml1
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-rw-r--r--spec/build/bsps/powerpc/tqm8xx/obj.yml1
-rw-r--r--spec/build/bsps/powerpc/virtex/bspvirtex.yml1
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-rw-r--r--spec/build/bsps/riscv/griscv/obj.yml1
-rw-r--r--spec/build/bsps/riscv/noel/abi.yml48
-rw-r--r--spec/build/bsps/riscv/noel/bspnoel32im.yml (renamed from spec/build/bsps/aarch64/xilinx-versal/bspvck190ilp32.yml)12
-rw-r--r--spec/build/bsps/riscv/noel/bspnoel32imafd.yml19
-rw-r--r--spec/build/bsps/riscv/noel/bspnoel64imac.yml19
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-rw-r--r--spec/build/bsps/riscv/noel/grp.yml61
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-rw-r--r--spec/build/bsps/riscv/noel/objsmp.yml15
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-rw-r--r--spec/build/bsps/riscv/optextirqmax.yml9
-rw-r--r--spec/build/bsps/riscv/optrambegin.yml8
-rw-r--r--spec/build/bsps/riscv/optramsize.yml5
-rw-r--r--spec/build/bsps/riscv/riscv/abi.yml6
-rw-r--r--spec/build/bsps/riscv/riscv/bspmpfs64imafdc.yml19
-rw-r--r--spec/build/bsps/riscv/riscv/grp.yml6
-rw-r--r--spec/build/bsps/riscv/riscv/obj.yml2
-rw-r--r--spec/build/bsps/riscv/riscv/optmpfs.yml18
-rw-r--r--spec/build/bsps/riscv/riscv/optns16550max.yml3
-rw-r--r--spec/build/bsps/sh/gensh1/bspgensh1.yml1
-rw-r--r--spec/build/bsps/sh/gensh2/bspgensh2.yml1
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-rw-r--r--spec/build/bsps/sh/shsim/obj.yml1
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-rw-r--r--spec/build/bsps/sparc/leon2/obj.yml1
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-rw-r--r--spec/build/cpukit/optsmp.yml6
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-rw-r--r--spec/build/testsuites/libtests/grp.yml2
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-rw-r--r--spec/build/testsuites/validation/validation-one-cpu-1.yml1
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-rw-r--r--testsuites/libtests/sha/init.c215
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-rw-r--r--testsuites/libtests/stackchk01/stackchk01.doc12
-rw-r--r--testsuites/psxtests/psxclock/init.c2
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-rw-r--r--testsuites/samples/minimum/init.c15
-rw-r--r--testsuites/smptests/smpcapture02/init.c25
-rw-r--r--testsuites/sptests/sp07/system.h2
-rw-r--r--testsuites/sptests/sp21/sp21.scn3
-rw-r--r--testsuites/sptests/spclock_err01/init.c1
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-rw-r--r--testsuites/sptests/spfatal36/init.c63
-rw-r--r--testsuites/sptests/spfatal36/spfatal36.doc11
-rw-r--r--testsuites/sptests/spinternalerror02/init.c2
-rw-r--r--testsuites/sptests/spstkalloc02/init.c13
-rw-r--r--testsuites/sptests/spstkalloc03/init.c4
-rw-r--r--testsuites/sptests/spstkalloc04/init.c4
-rw-r--r--testsuites/sptests/sptls01/init.c39
-rw-r--r--testsuites/sptests/sptls02/init.cc18
-rw-r--r--testsuites/sptests/sptls03/init.c4
-rw-r--r--testsuites/validation/tc-acfg-default.c12
-rw-r--r--testsuites/validation/tc-acfg-scheduler-table-entries-one-cpu.c102
-rw-r--r--testsuites/validation/tc-basedefs-no-debug.c129
-rw-r--r--testsuites/validation/tc-bsp-interrupt-spurious.c42
-rw-r--r--testsuites/validation/tc-clock.c75
-rw-r--r--testsuites/validation/tc-cpuuse.c17
-rw-r--r--testsuites/validation/tc-futex-wake.c70
-rw-r--r--testsuites/validation/tc-intr-entry-install.c31
-rw-r--r--testsuites/validation/tc-intr-entry-remove.c31
-rw-r--r--testsuites/validation/tc-intr-get-affinity.c10
-rw-r--r--testsuites/validation/tc-intr-handler-iterate.c39
-rw-r--r--testsuites/validation/tc-message-performance.c36
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-rw-r--r--testsuites/validation/tc-score-tq.c190
-rw-r--r--testsuites/validation/tc-sem-flush.c8
-rw-r--r--testsuites/validation/tr-fatal-idle-thread-create-failed.c158
-rw-r--r--testsuites/validation/tr-fatal-idle-thread-create-failed.h84
-rw-r--r--testsuites/validation/tr-fatal-idle-thread-stack-too-small.c175
-rw-r--r--testsuites/validation/tr-fatal-idle-thread-stack-too-small.h84
-rw-r--r--testsuites/validation/tr-io-kernel.c2
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-rw-r--r--testsuites/validation/ts-fatal-idle-thread-create-failed.c (renamed from testsuites/validation/ts-validation-smp-only-1.c)42
-rw-r--r--testsuites/validation/ts-fatal-idle-thread-stack-too-small.c97
-rw-r--r--testsuites/validation/ts-fatal-sysinit.h9
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-rw-r--r--testsuites/validation/tx-thread-queue.h50
-rwxr-xr-xwscript311
762 files changed, 30513 insertions, 4459 deletions
diff --git a/bsps/aarch64/include/bsp/aarch64-mmu.h b/bsps/aarch64/include/bsp/aarch64-mmu.h
index 1287c67016..ebc224b9e1 100644
--- a/bsps/aarch64/include/bsp/aarch64-mmu.h
+++ b/bsps/aarch64/include/bsp/aarch64-mmu.h
@@ -243,26 +243,29 @@ BSP_START_TEXT_SECTION static inline rtems_status_code aarch64_mmu_map_block(
/* check for perfect block match */
if ( block_bottom == addr ) {
if ( size >= chunk_size ) {
- /* when page_flag is set the last level must be a page descriptor */
- if ( page_flag || ( page_table[index] & MMU_DESC_TYPE_TABLE ) != MMU_DESC_TYPE_TABLE ) {
- /* no sub-table, apply block properties */
- page_table[index] = addr | flags | page_flag;
- size -= chunk_size;
- addr += chunk_size;
- continue;
+ /* level -1 can't contain block descriptors, fall through to subtable */
+ if ( level != -1 ) {
+ /* when page_flag is set the last level must be a page descriptor */
+ if ( page_flag || ( page_table[index] & MMU_DESC_TYPE_TABLE ) != MMU_DESC_TYPE_TABLE ) {
+ /* no sub-table, apply block properties */
+ page_table[index] = addr | flags | page_flag;
+ size -= chunk_size;
+ addr += chunk_size;
+ continue;
+ }
}
} else {
/* block starts on a boundary, but is short */
chunk_size = size;
- /* it isn't possible to go beyond page table level 2 */
- if ( page_flag ) {
+ /* it isn't possible to go beyond page table level 2 */
+ if ( page_flag ) {
/* no sub-table, apply block properties */
page_table[index] = addr | flags | page_flag;
size -= chunk_size;
addr += chunk_size;
continue;
- }
+ }
}
} else {
uintptr_t block_top = RTEMS_ALIGN_UP( addr, granularity );
diff --git a/bsps/aarch64/raspberrypi/console/console.c b/bsps/aarch64/raspberrypi/console/console.c
new file mode 100644
index 0000000000..73bb0036ff
--- /dev/null
+++ b/bsps/aarch64/raspberrypi/console/console.c
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsAArch64Raspberrypi4
+ *
+ * @brief Console Configuration
+ */
+
+/*
+ * Copyright (C) 2022 Mohd Noor Aman
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <rtems/bspIo.h>
+
+#include <bsp.h>
+#include <dev/serial/arm-pl011.h>
+#include <bsp/console-termios.h>
+
+#include <bspopts.h>
+
+arm_pl011_context raspberrypi_4_context = {
+ .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER("PL011"),
+ .regs = (volatile pl011 *) BSP_RPI4_PL011_BASE,
+ .initial_baud = 115200
+};
+
+const console_device console_device_table[] = {
+ {
+ .device_file = "/dev/ttyS0",
+ .probe = console_device_probe_default,
+ .handler = &arm_pl011_fns,
+ .context = &raspberrypi_4_context.base
+ }
+};
+
+const size_t console_device_count = RTEMS_ARRAY_SIZE(console_device_table);
+
+static void output_char( char c )
+{
+ arm_pl011_write_polled(&raspberrypi_4_context.base, c);
+}
+
+BSP_output_char_function_type BSP_output_char = output_char;
+
+BSP_polling_getchar_function_type BSP_poll_char = NULL;
diff --git a/bsps/aarch64/raspberrypi/include/bsp.h b/bsps/aarch64/raspberrypi/include/bsp.h
new file mode 100644
index 0000000000..4fa81edd40
--- /dev/null
+++ b/bsps/aarch64/raspberrypi/include/bsp.h
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsAArch64Raspberrypi4
+ *
+ * @brief Core BSP definitions
+ */
+
+/*
+ * Copyright (C) 2022 Mohd Noor Aman
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_AARCH64_RASPBERRYPI_4_BSP_H
+#define LIBBSP_AARCH64_RASPBERRYPI_4_BSP_H
+
+/**
+ * @addtogroup RTEMSBSPsAArch64
+ *
+ * @{
+ */
+
+#include <bspopts.h>
+
+#ifndef ASM
+
+#include <bsp/default-initial-extension.h>
+#include <bsp/start.h>
+
+#include <rtems.h>
+
+/*Raspberry pi MMU initialization */
+BSP_START_TEXT_SECTION void raspberrypi_4_setup_mmu_and_cache(void);
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#define BSP_ARM_GIC_CPUIF_BASE 0xFF842000
+#define BSP_ARM_GIC_DIST_BASE 0xFF841000
+
+#define BSP_RPI4_PL011_BASE 0xFE201000
+#define BSP_RPI4_PL011_LENGTH 0x200
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* ASM */
+
+/** @} */
+
+#endif /* LIBBSP_AARCH64_RASPBERRYPI_4_BSP_H */
diff --git a/bsps/aarch64/raspberrypi/include/bsp/irq.h b/bsps/aarch64/raspberrypi/include/bsp/irq.h
new file mode 100644
index 0000000000..effec1b040
--- /dev/null
+++ b/bsps/aarch64/raspberrypi/include/bsp/irq.h
@@ -0,0 +1,109 @@
+/**
+ * @file
+ *
+ * @ingroup raspberrypi_interrupt
+ *
+ * @brief Interrupt definitions.
+ */
+
+/**
+ * Copyright (c) 2013 Alan Cudmore
+ * Copyright (c) 2022 Mohd Noor Aman
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ *
+ * http://www.rtems.org/license/LICENSE
+ *
+ */
+
+#ifndef LIBBSP_ARM_RASPBERRYPI_IRQ_H
+#define LIBBSP_ARM_RASPBERRYPI_IRQ_H
+
+#ifndef ASM
+
+#include <rtems.h>
+#include <rtems/irq.h>
+#include <rtems/irq-extension.h>
+#include <dev/irq/arm-gic-irq.h>
+
+#if defined(RTEMS_SMP)
+#include <rtems/score/processormask.h>
+#endif
+
+/**
+ * @defgroup raspberrypi_interrupt Interrrupt Support
+ *
+ * @ingroup RTEMSBSPsARMRaspberryPi
+ *
+ * @brief Interrupt support.
+ */
+
+#define BCM2835_INTC_TOTAL_IRQ (64 + 8)
+
+#define BCM2835_IRQ_SET1_MIN 0
+#define BCM2835_IRQ_SET2_MIN 32
+
+#define BCM2835_IRQ_ID_GPU_TIMER_M0 0
+#define BCM2835_IRQ_ID_GPU_TIMER_M1 1
+#define BCM2835_IRQ_ID_GPU_TIMER_M2 2
+#define BCM2835_IRQ_ID_GPU_TIMER_M3 3
+
+#define BCM2835_IRQ_ID_USB 9
+#define BCM2835_IRQ_ID_AUX 29
+#define BCM2835_IRQ_ID_SPI_SLAVE 43
+#define BCM2835_IRQ_ID_PWA0 45
+#define BCM2835_IRQ_ID_PWA1 46
+#define BCM2835_IRQ_ID_SMI 48
+#define BCM2835_IRQ_ID_GPIO_0 49
+#define BCM2835_IRQ_ID_GPIO_1 50
+#define BCM2835_IRQ_ID_GPIO_2 51
+#define BCM2835_IRQ_ID_GPIO_3 52
+#define BCM2835_IRQ_ID_I2C 53
+#define BCM2835_IRQ_ID_SPI 54
+#define BCM2835_IRQ_ID_PCM 55
+#define BCM2835_IRQ_ID_UART 57
+#define BCM2835_IRQ_ID_SD 62
+
+#define BCM2835_IRQ_ID_BASIC_BASE_ID 64
+#define BCM2835_IRQ_ID_TIMER_0 64
+#define BCM2835_IRQ_ID_MAILBOX_0 65
+#define BCM2835_IRQ_ID_DOORBELL_0 66
+#define BCM2835_IRQ_ID_DOORBELL_1 67
+#define BCM2835_IRQ_ID_GPU0_HALTED 68
+#define BCM2835_IRQ_ID_GPU1_HALTED 69
+#define BCM2835_IRQ_ID_ILL_ACCESS_1 70
+#define BCM2835_IRQ_ID_ILL_ACCESS_0 71
+#define BSP_TIMER_VIRT_PPI 27
+#define BSP_TIMER_PHYS_NS_PPI 30
+#define BSP_VPL011_SPI 32
+
+#define BSP_INTERRUPT_VECTOR_COUNT BCM2835_INTC_TOTAL_IRQ
+#define BSP_INTERRUPT_VECTOR_INVALID (UINT32_MAX)
+
+#define BSP_IRQ_COUNT (BCM2835_INTC_TOTAL_IRQ)
+
+#if defined(RTEMS_SMP)
+static inline rtems_status_code bsp_interrupt_set_affinity(
+ rtems_vector_number vector,
+ const Processor_mask *affinity
+)
+{
+ (void) vector;
+ (void) affinity;
+ return RTEMS_UNSATISFIED;
+}
+
+static inline rtems_status_code bsp_interrupt_get_affinity(
+ rtems_vector_number vector,
+ Processor_mask *affinity
+)
+{
+ (void) vector;
+ _Processor_mask_From_index( affinity, 0 );
+ return RTEMS_UNSATISFIED;
+}
+#endif
+
+#endif /* ASM */
+#endif /* LIBBSP_ARM_RASPBERRYPI_IRQ_H */
diff --git a/bsps/aarch64/raspberrypi/include/bsp/raspberrypi.h b/bsps/aarch64/raspberrypi/include/bsp/raspberrypi.h
new file mode 100644
index 0000000000..55dd9ed1e9
--- /dev/null
+++ b/bsps/aarch64/raspberrypi/include/bsp/raspberrypi.h
@@ -0,0 +1,471 @@
+/**
+ * @file
+ *
+ * @ingroup raspberrypi_4_regs
+ *
+ * @brief Register definitions.
+ */
+
+/*
+ * Copyright (c) 2022 Mohd Noor Aman
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ *
+ * http://www.rtems.org/license/LICENSE
+ *
+ */
+
+
+#ifndef LIBBSP_AARCH64_RASPBERRYPI_RASPBERRYPI_4_H
+#define LIBBSP_AARCH64_RASPBERRYPI_RASPBERRYPI_4_H
+
+
+#include <bspopts.h>
+#include <stdint.h>
+#include <bsp/utility.h>
+
+
+/**
+ * @defgroup raspberrypi_reg Register Definitions
+ *
+ * @ingroup RTEMSBSPsARMRaspberryPi
+ *
+ * @brief Register Definitions
+ *
+ * @{
+ */
+
+/**
+ * @name Register Macros
+ *
+ * @{
+ */
+
+#define BCM2711_REG(x) (*(volatile uint64_t *)(x))
+#define BCM2711_BIT(n) (1 << (n))
+
+/** @} */
+
+/**
+ * @name Peripheral Base Register Address
+ *
+ * @{
+ */
+
+#define RPI_PERIPHERAL_BASE 0xFE000000
+#define BASE_OFFSET 0xFE000000
+#define RPI_PERIPHERAL_SIZE 0x01800000
+
+/**
+ * @name Bus to Physical address translation
+ * Macro.
+ * @{
+ */
+#define BUS_TO_PHY(x) ((x) - BASE_OFFSET)
+
+/** @} */
+
+/**
+ * @name Internal ARM Timer Registers
+ *
+ * @{
+ */
+
+#define BCM2711_CLOCK_FREQ 250000000
+
+#define BCM2711_TIMER_BASE (RPI_PERIPHERAL_BASE + 0xB400)
+
+#define BCM2711_TIMER_LOD (BCM2711_TIMER_BASE + 0x00)
+#define BCM2711_TIMER_VAL (BCM2711_TIMER_BASE + 0x04)
+#define BCM2711_TIMER_CTL (BCM2711_TIMER_BASE + 0x08)
+#define BCM2711_TIMER_CLI (BCM2711_TIMER_BASE + 0x0C)
+#define BCM2711_TIMER_RIS (BCM2711_TIMER_BASE + 0x10)
+#define BCM2711_TIMER_MIS (BCM2711_TIMER_BASE + 0x14)
+#define BCM2711_TIMER_RLD (BCM2711_TIMER_BASE + 0x18)
+#define BCM2711_TIMER_DIV (BCM2711_TIMER_BASE + 0x1C)
+#define BCM2711_TIMER_CNT (BCM2711_TIMER_BASE + 0x20)
+
+#define BCM2711_TIMER_PRESCALE 0xF9
+
+/** @} */
+
+/**
+ * @name Power Management and Watchdog Registers
+ *
+ * @{
+ */
+
+#define BCM2711_PM_PASSWD_MAGIC 0x5a000000
+
+#define BCM2711_PM_BASE (RPI_PERIPHERAL_BASE + 0x100000)
+
+#define BCM2711_PM_GNRIC (BCM2711_PM_BASE + 0x00)
+#define BCM2711_PM_GNRIC_POWUP 0x00000001
+#define BCM2711_PM_GNRIC_POWOK 0x00000002
+#define BCM2711_PM_GNRIC_ISPOW 0x00000004
+#define BCM2711_PM_GNRIC_MEMREP 0x00000008
+#define BCM2711_PM_GNRIC_MRDONE 0x00000010
+#define BCM2711_PM_GNRIC_ISFUNC 0x00000020
+#define BCM2711_PM_GNRIC_RSTN 0x00000fc0
+#define BCM2711_PM_GNRIC_ENAB 0x00001000
+#define BCM2711_PM_GNRIC_CFG 0x007f0000
+
+#define BCM2711_PM_AUDIO (BCM2711_PM_BASE + 0x04)
+#define BCM2711_PM_AUDIO_APSM 0x000fffff
+#define BCM2711_PM_AUDIO_CTRLEN 0x00100000
+#define BCM2711_PM_AUDIO_RSTN 0x00200000
+
+#define BCM2711_PM_STATUS (BCM2711_PM_BASE + 0x18)
+
+#define BCM2711_PM_RSTC (BCM2711_PM_BASE + 0x1c)
+#define BCM2711_PM_RSTC_DRCFG 0x00000003
+#define BCM2711_PM_RSTC_WRCFG 0x00000030
+#define BCM2711_PM_RSTC_WRCFG_FULL 0x00000020
+#define BCM2711_PM_RSTC_SRCFG 0x00000300
+#define BCM2711_PM_RSTC_QRCFG 0x00003000
+#define BCM2711_PM_RSTC_FRCFG 0x00030000
+#define BCM2711_PM_RSTC_HRCFG 0x00300000
+
+#define BCM2711_PM_RSTS (BCM2711_PM_BASE + 0x20)
+#define BCM2711_PM_RSTS_HADDRQ 0x00000001
+#define BCM2711_PM_RSTS_HADDRF 0x00000002
+#define BCM2711_PM_RSTS_HADDRH 0x00000004
+#define BCM2711_PM_RSTS_HADWRQ 0x00000010
+#define BCM2711_PM_RSTS_HADWRF 0x0000002
+#define BCM2711_PM_RSTS_HADWRH 0x00000040
+#define BCM2711_PM_RSTS_HADSRQ 0x00000100
+#define BCM2711_PM_RSTS_HADSRF 0x00000200
+#define BCM2711_PM_RSTS_HADSRH 0x00000400
+#define BCM2711_PM_RSTS_HADPOR 0x00001000
+
+#define BCM2711_PM_WDOG (BCM2711_PM_BASE + 0x24)
+
+/** @} */
+
+
+/** @} */
+
+/**
+ * @name AUX Registers
+ *
+ * @{
+ */
+
+#define BCM2711_AUX_BASE (RPI_PERIPHERAL_BASE + 0x215000)
+
+#define AUX_ENABLES (BCM2711_AUX_BASE + 0x04)
+#define AUX_MU_IO_REG (BCM2711_AUX_BASE + 0x40)
+#define AUX_MU_IER_REG (BCM2711_AUX_BASE + 0x44)
+#define AUX_MU_IIR_REG (BCM2711_AUX_BASE + 0x48)
+#define AUX_MU_LCR_REG (BCM2711_AUX_BASE + 0x4C)
+#define AUX_MU_MCR_REG (BCM2711_AUX_BASE + 0x50)
+#define AUX_MU_LSR_REG (BCM2711_AUX_BASE + 0x54)
+#define AUX_MU_MSR_REG (BCM2711_AUX_BASE + 0x58)
+#define AUX_MU_SCRATCH (BCM2711_AUX_BASE + 0x5C)
+#define AUX_MU_CNTL_REG (BCM2711_AUX_BASE + 0x60)
+#define AUX_MU_STAT_REG (BCM2711_AUX_BASE + 0x64)
+#define AUX_MU_BAUD_REG (BCM2711_AUX_BASE + 0x68)
+
+/** @} */
+
+
+
+/** @} */
+
+/**
+ * @name GPU Timer Registers
+ *
+ * @{
+ */
+
+/**
+ * NOTE: The GPU uses Compare registers 0 and 2 for
+ * it's own RTOS. 1 and 3 are available for use in
+ * RTEMS.
+ */
+#define BCM2711_GPU_TIMER_BASE (RPI_PERIPHERAL_BASE + 0x3000)
+
+#define BCM2711_GPU_TIMER_CS (BCM2711_GPU_TIMER_BASE + 0x00)
+#define BCM2711_GPU_TIMER_CS_M0 0x00000001
+#define BCM2711_GPU_TIMER_CS_M1 0x00000002
+#define BCM2711_GPU_TIMER_CS_M2 0x00000004
+#define BCM2711_GPU_TIMER_CS_M3 0x00000008
+#define BCM2711_GPU_TIMER_CLO (BCM2711_GPU_TIMER_BASE + 0x04)
+#define BCM2711_GPU_TIMER_CHI (BCM2711_GPU_TIMER_BASE + 0x08)
+#define BCM2711_GPU_TIMER_C0 (BCM2711_GPU_TIMER_BASE + 0x0C)
+#define BCM2711_GPU_TIMER_C1 (BCM2711_GPU_TIMER_BASE + 0x10)
+#define BCM2711_GPU_TIMER_C2 (BCM2711_GPU_TIMER_BASE + 0x14)
+#define BCM2711_GPU_TIMER_C3 (BCM2711_GPU_TIMER_BASE + 0x18)
+
+/** @} */
+
+/**
+ * @name EMMC Registers
+ *
+ * @{
+ */
+
+/**
+ * NOTE: Since the SD controller follows the SDHCI standard,
+ * the rtems-libbsd tree already provides the remaining registers.
+ */
+
+#define BCM2711_EMMC_BASE (RPI_PERIPHERAL_BASE + 0x300000)
+
+/** @} */
+
+/**
+* @name Mailbox Registers
+*
+* @{
+*/
+
+#define BCM2711_MBOX_BASE (RPI_PERIPHERAL_BASE+0xB880)
+
+#define BCM2711_MBOX_READ (BCM2711_MBOX_BASE+0x00)
+#define BCM2711_MBOX_PEEK (BCM2711_MBOX_BASE+0x10)
+#define BCM2711_MBOX_SENDER (BCM2711_MBOX_BASE+0x14)
+#define BCM2711_MBOX_STATUS (BCM2711_MBOX_BASE+0x18)
+#define BCM2711_MBOX_WRITE (BCM2711_MBOX_BASE+0x20)
+#define BCM2711_MBOX_CONFIG (BCM2711_MBOX_BASE+0x1C)
+
+#define BCM2711_MBOX_RESPONSE 0x80000000
+#define BCM2711_MBOX_FULL 0x80000000
+#define BCM2711_MBOX_EMPTY 0x40000000
+
+/** @} */
+
+/**
+* @name Mailbox Channels
+*
+* @{
+*/
+
+/* Power Manager channel */
+#define BCM2711_MBOX_CHANNEL_PM 0
+/* Framebuffer channel */
+#define BCM2711_MBOX_CHANNEL_FB 1
+ /* Virtual UART channel */
+#define BCM2711_MBOX_CHANNEL_VUART 2
+ /* VCHIQ channel */
+#define BCM2711_MBOX_CHANNEL_VCHIQ 3
+ /* LEDs channel */
+#define BCM2711_MBOX_CHANNEL_LED 4
+ /* Button channel */
+#define BCM2711_MBOX_CHANNEL_BUTTON 5
+ /* Touch screen channel */
+#define BCM2711_MBOX_CHANNEL_TOUCHS 6
+
+#define BCM2711_MBOX_CHANNEL_COUNT 7
+/* Property tags (ARM <-> VC) channel */
+#define BCM2711_MBOX_CHANNEL_PROP_AVC 8
+ /* Property tags (VC <-> ARM) channel */
+#define BCM2711_MBOX_CHANNEL_PROP_VCA 9
+
+/** @} */
+
+
+
+/**
+ * @name Raspberry Pi 2 Interrupt Register Defines
+ *
+ * @{
+ */
+
+/* Timers interrupt control registers */
+#define BCM2711_CORE0_TIMER_IRQ_CTRL_BASE 0xFF800040
+#define BCM2711_CORE1_TIMER_IRQ_CTRL_BASE 0xFF800044
+#define BCM2711_CORE2_TIMER_IRQ_CTRL_BASE 0xFF800048
+#define BCM2711_CORE3_TIMER_IRQ_CTRL_BASE 0xFF80004C
+
+#define BCM2711_CORE_TIMER_IRQ_CTRL(cpuidx) \
+ (BCM2711_CORE0_TIMER_IRQ_CTRL_BASE + 0x4 * (cpuidx))
+
+
+/**
+ * @name Raspberry Pi 4 ARM_LOCAL registers
+ *
+ * @{
+ */
+
+#define BCM2711_LOCAL_REGS_BASE 0x4C0000000
+#define BCM2711_LOCAL_REGS_SIZE 0x100
+
+#define BCM2711_LOCAL_ARM_CONTROL (BCM2711_LOCAL_REGS_BASE + 0x00)
+#define BCM2711_LOCAL_CORE_IRQ_CONTROL (BCM2711_LOCAL_REGS_BASE + 0x0c)
+#define BCM2711_LOCAL_PMU_CONTROL_SET (BCM2711_LOCAL_REGS_BASE + 0x10)
+#define BCM2711_LOCAL_PMU_CONTROL_CLR (BCM2711_LOCAL_REGS_BASE + 0x14)
+#define BCM2711_LOCAL_PERI_IRQ_ROUTE0 (BCM2711_LOCAL_REGS_BASE + 0x24)
+#define BCM2711_LOCAL_AXI_QUIET_TIME (BCM2711_LOCAL_REGS_BASE + 0x30)
+#define BCM2711_LOCAL_LOCAL_TIMER_CONTROL (BCM2711_LOCAL_REGS_BASE + 0x34)
+#define BCM2711_LOCAL_LOCAL_TIMER_IRQ (BCM2711_LOCAL_REGS_BASE + 0x38)
+
+#define BCM2711_LOCAL_TIMER_CNTRL0 (BCM2711_LOCAL_REGS_BASE + 0x40)
+#define BCM2711_LOCAL_TIMER_CNTRL1 (BCM2711_LOCAL_REGS_BASE + 0x44)
+#define BCM2711_LOCAL_TIMER_CNTRL2 (BCM2711_LOCAL_REGS_BASE + 0x48)
+#define BCM2711_LOCAL_TIMER_CNTRL3 (BCM2711_LOCAL_REGS_BASE + 0x4c)
+
+#define BCM2711_LOCAL_MAILBOX_CNTRL0 (BCM2711_LOCAL_REGS_BASE + 0x50)
+#define BCM2711_LOCAL_MAILBOX_CNTRL1 (BCM2711_LOCAL_REGS_BASE + 0x54)
+#define BCM2711_LOCAL_MAILBOX_CNTRL2 (BCM2711_LOCAL_REGS_BASE + 0x58)
+#define BCM2711_LOCAL_MAILBOX_CNTRL3 (BCM2711_LOCAL_REGS_BASE + 0x5c)
+
+#define BCM2711_LOCAL_IRQ_SOURCE0 (BCM2711_LOCAL_REGS_BASE + 0x60)
+#define BCM2711_LOCAL_IRQ_SOURCE1 (BCM2711_LOCAL_REGS_BASE + 0x64)
+#define BCM2711_LOCAL_IRQ_SOURCE2 (BCM2711_LOCAL_REGS_BASE + 0x68)
+#define BCM2711_LOCAL_IRQ_SOURCE3 (BCM2711_LOCAL_REGS_BASE + 0x6c)
+
+#define BCM2711_LOCAL_FIQ_SOURCE0 (BCM2711_LOCAL_REGS_BASE + 0x70)
+#define BCM2711_LOCAL_FIQ_SOURCE1 (BCM2711_LOCAL_REGS_BASE + 0x74)
+#define BCM2711_LOCAL_FIQ_SOURCE2 (BCM2711_LOCAL_REGS_BASE + 0x78)
+#define BCM2711_LOCAL_FIQ_SOURCE3 (BCM2711_LOCAL_REGS_BASE + 0x7c)
+
+/**
+ * @name Raspberry Pi 4 Mailbox registers
+ *
+ * @{
+ */
+
+
+
+#define BCM2711_MAILBOX_00_WRITE_SET_BASE 0x4C000080
+#define BCM2711_MAILBOX_01_WRITE_SET_BASE 0x4C000084
+#define BCM2711_MAILBOX_02_WRITE_SET_BASE 0x4C000088
+#define BCM2711_MAILBOX_03_WRITE_SET_BASE 0x4C00008C
+#define BCM2711_MAILBOX_04_WRITE_SET_BASE 0x4C000090
+#define BCM2711_MAILBOX_05_WRITE_SET_BASE 0x4C000094
+#define BCM2711_MAILBOX_06_WRITE_SET_BASE 0x4C000098
+#define BCM2711_MAILBOX_07_WRITE_SET_BASE 0x4C00009C
+#define BCM2711_MAILBOX_08_WRITE_SET_BASE 0x4C0000A0
+#define BCM2711_MAILBOX_09_WRITE_SET_BASE 0x4C0000A4
+#define BCM2711_MAILBOX_10_WRITE_SET_BASE 0x4C0000A8
+#define BCM2711_MAILBOX_11_WRITE_SET_BASE 0x4C0000AC
+#define BCM2711_MAILBOX_12_WRITE_SET_BASE 0x4C0000B0
+#define BCM2711_MAILBOX_13_WRITE_SET_BASE 0x4C0000B4
+#define BCM2711_MAILBOX_14_WRITE_SET_BASE 0x4C0000B8
+#define BCM2711_MAILBOX_15_WRITE_SET_BASE 0x4C0000BC
+
+#define BCM2711_MAILBOX_00_READ_CLEAR_BASE 0x4C0000C0
+#define BCM2711_MAILBOX_01_READ_CLEAR_BASE 0x4C0000C4
+#define BCM2711_MAILBOX_02_READ_CLEAR_BASE 0x4C0000C8
+#define BCM2711_MAILBOX_03_READ_CLEAR_BASE 0x4C0000CC
+#define BCM2711_MAILBOX_04_READ_CLEAR_BASE 0x4C0000D0
+#define BCM2711_MAILBOX_05_READ_CLEAR_BASE 0x4C0000D4
+#define BCM2711_MAILBOX_06_READ_CLEAR_BASE 0x4C0000D8
+#define BCM2711_MAILBOX_07_READ_CLEAR_BASE 0x4C0000DC
+#define BCM2711_MAILBOX_08_READ_CLEAR_BASE 0x4C0000E0
+#define BCM2711_MAILBOX_09_READ_CLEAR_BASE 0x4C0000E4
+#define BCM2711_MAILBOX_10_READ_CLEAR_BASE 0x4C0000E8
+#define BCM2711_MAILBOX_11_READ_CLEAR_BASE 0x4C0000EC
+#define BCM2711_MAILBOX_12_READ_CLEAR_BASE 0x4C0000F0
+#define BCM2711_MAILBOX_13_READ_CLEAR_BASE 0x4C0000F4
+#define BCM2711_MAILBOX_14_READ_CLEAR_BASE 0x4C0000F8
+#define BCM2711_MAILBOX_15_READ_CLEAR_BASE 0x4C0000FC
+
+
+/**
+ * @name Raspberry Pi 4 ARM_C FIQ and IRQ registers
+ *
+ * @{
+ */
+
+#define BCM2711_ARMC_REGS_BASE (RPI_PERIPHERAL_BASE + 0xB200)
+#define BCM2711_ARMC_REGS_SIZE 0x200
+
+#define BCM2711_ARMC_IRQ0_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x00)
+#define BCM2711_ARMC_IRQ0_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x04)
+#define BCM2711_ARMC_IRQ0_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x08)
+#define BCM2711_ARMC_IRQ0_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x10)
+#define BCM2711_ARMC_IRQ0_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x14)
+#define BCM2711_ARMC_IRQ0_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x18)
+#define BCM2711_ARMC_IRQ0_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x20)
+#define BCM2711_ARMC_IRQ0_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x24)
+#define BCM2711_ARMC_IRQ0_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x28)
+
+#define BCM2711_ARMC_IRQ_STATUS0 (BCM2711_ARMC_REGS_BASE + 0x30)
+#define BCM2711_ARMC_IRQ_STATUS1 (BCM2711_ARMC_REGS_BASE + 0x34)
+#define BCM2711_ARMC_IRQ_STATUS2 (BCM2711_ARMC_REGS_BASE + 0x38)
+
+#define BCM2711_ARMC_IRQ1_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x40)
+#define BCM2711_ARMC_IRQ1_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x44)
+#define BCM2711_ARMC_IRQ1_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x48)
+#define BCM2711_ARMC_IRQ1_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x50)
+#define BCM2711_ARMC_IRQ1_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x54)
+#define BCM2711_ARMC_IRQ1_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x58)
+#define BCM2711_ARMC_IRQ1_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x60)
+#define BCM2711_ARMC_IRQ1_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x64)
+#define BCM2711_ARMC_IRQ1_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x68)
+
+#define BCM2711_ARMC_IRQ2_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x80)
+#define BCM2711_ARMC_IRQ2_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x84)
+#define BCM2711_ARMC_IRQ2_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x88)
+#define BCM2711_ARMC_IRQ2_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x90)
+#define BCM2711_ARMC_IRQ2_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x94)
+#define BCM2711_ARMC_IRQ2_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x98)
+#define BCM2711_ARMC_IRQ2_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0xA0)
+#define BCM2711_ARMC_IRQ2_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0xA4)
+#define BCM2711_ARMC_IRQ2_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0xA8)
+
+#define BCM2711_ARMC_IRQ3_PENDING0 (BCM2711_ARMC_REGS_BASE + 0xC0)
+#define BCM2711_ARMC_IRQ3_PENDING1 (BCM2711_ARMC_REGS_BASE + 0xC4)
+#define BCM2711_ARMC_IRQ3_PENDING2 (BCM2711_ARMC_REGS_BASE + 0xC8)
+#define BCM2711_ARMC_IRQ3_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0xD0)
+#define BCM2711_ARMC_IRQ3_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0xD4)
+#define BCM2711_ARMC_IRQ3_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0xD8)
+#define BCM2711_ARMC_IRQ3_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0xE0)
+#define BCM2711_ARMC_IRQ3_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0xE4)
+#define BCM2711_ARMC_IRQ3_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0xE8)
+
+
+
+#define BCM2711_ARMC_FIQ0_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x100)
+#define BCM2711_ARMC_FIQ0_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x104)
+#define BCM2711_ARMC_FIQ0_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x108)
+#define BCM2711_ARMC_FIQ0_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x110)
+#define BCM2711_ARMC_FIQ0_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x114)
+#define BCM2711_ARMC_FIQ0_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x118)
+#define BCM2711_ARMC_FIQ0_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x120)
+#define BCM2711_ARMC_FIQ0_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x124)
+#define BCM2711_ARMC_FIQ0_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x128)
+
+#define BCM2711_ARMC_FIQ1_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x140)
+#define BCM2711_ARMC_FIQ1_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x144)
+#define BCM2711_ARMC_FIQ1_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x148)
+#define BCM2711_ARMC_FIQ1_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x150)
+#define BCM2711_ARMC_FIQ1_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x154)
+#define BCM2711_ARMC_FIQ1_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x158)
+#define BCM2711_ARMC_FIQ1_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x160)
+#define BCM2711_ARMC_FIQ1_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x164)
+#define BCM2711_ARMC_FIQ1_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x168)
+
+#define BCM2711_ARMC_FIQ2_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x180)
+#define BCM2711_ARMC_FIQ2_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x184)
+#define BCM2711_ARMC_FIQ2_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x188)
+#define BCM2711_ARMC_FIQ2_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x190)
+#define BCM2711_ARMC_FIQ2_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x194)
+#define BCM2711_ARMC_FIQ2_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x198)
+#define BCM2711_ARMC_FIQ2_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x1A0)
+#define BCM2711_ARMC_FIQ2_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x1A4)
+#define BCM2711_ARMC_FIQ2_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x1A8)
+
+#define BCM2711_ARMC_FIQ3_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x1C0)
+#define BCM2711_ARMC_FIQ3_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x1C4)
+#define BCM2711_ARMC_FIQ3_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x1C8)
+#define BCM2711_ARMC_FIQ3_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x1D0)
+#define BCM2711_ARMC_FIQ3_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x1D4)
+#define BCM2711_ARMC_FIQ3_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x1D8)
+#define BCM2711_ARMC_FIQ3_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x1E0)
+#define BCM2711_ARMC_FIQ3_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x1E4)
+#define BCM2711_ARMC_FIQ3_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x1E8)
+
+#define BCM2711_ARMC_SWIRQ_SET (BCM2711_ARMC_REGS_BASE + 0x1F0)
+#define BCM2711_ARMC_SWIRQ_CLEAR (BCM2711_ARMC_REGS_BASE + 0x1F4)
+
+
+
+
+
+/** @} */
+
+#endif /* LIBBSP_ARM_RASPBERRYPI_RASPBERRYPI_H */
diff --git a/bsps/aarch64/raspberrypi/include/tm27.h b/bsps/aarch64/raspberrypi/include/tm27.h
new file mode 100644
index 0000000000..653f88ed01
--- /dev/null
+++ b/bsps/aarch64/raspberrypi/include/tm27.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsAArch64Raspberrypi4
+ *
+ * @brief BSP tm27 header
+ */
+
+/*
+ * Copyright (C) 2022 Mohd Noor Aman
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTEMS_TMTEST27
+#error "This is an RTEMS internal file you must not include directly."
+#endif
+
+#ifndef __tm27_h
+#define __tm27_h
+
+#include <dev/irq/arm-gic-tm27.h>
+
+#endif /* __tm27_h */ \ No newline at end of file
diff --git a/bsps/aarch64/raspberrypi/start/bspstart.c b/bsps/aarch64/raspberrypi/start/bspstart.c
new file mode 100644
index 0000000000..368c5d0d08
--- /dev/null
+++ b/bsps/aarch64/raspberrypi/start/bspstart.c
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsAArch64Raspberrypi4
+ *
+ * @brief BSP Startup
+ */
+
+/*
+ * Copyright (C) 2022 Mohd Noor Aman
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <bsp.h>
+#include <bsp/bootcard.h>
+#include <bsp/irq-generic.h>
+#include <bsp/linker-symbols.h>
+
+void bsp_start( void )
+{
+ bsp_interrupt_initialize();
+ rtems_cache_coherent_add_area(
+ bsp_section_nocacheheap_begin,
+ (uintptr_t) bsp_section_nocacheheap_size
+ );
+}
diff --git a/bsps/aarch64/raspberrypi/start/bspstarthooks.c b/bsps/aarch64/raspberrypi/start/bspstarthooks.c
new file mode 100644
index 0000000000..fe0fe77c09
--- /dev/null
+++ b/bsps/aarch64/raspberrypi/start/bspstarthooks.c
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsAArch64Raspberrypi4
+ *
+ * @brief BSP Startup Hooks
+ */
+
+/*
+ * Copyright (C) 2022 Mohd Noor Aman
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <bsp.h>
+#include <bsp/irq-generic.h>
+#include <bsp/start.h>
+#include <rtems/score/cpu.h>
+
+BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
+{
+ /* Do nothing */
+}
+
+BSP_START_TEXT_SECTION void bsp_start_hook_1(void)
+{
+ AArch64_start_set_vector_base();
+ bsp_start_copy_sections();
+ raspberrypi_4_setup_mmu_and_cache();
+ bsp_start_clear_bss();
+} \ No newline at end of file
diff --git a/bsps/aarch64/raspberrypi/start/bspstartmmu.c b/bsps/aarch64/raspberrypi/start/bspstartmmu.c
new file mode 100644
index 0000000000..18a9a112b0
--- /dev/null
+++ b/bsps/aarch64/raspberrypi/start/bspstartmmu.c
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsAArch64Raspberrypi4
+ *
+ * @brief This source file contains the default MMU tables and setup.
+ */
+
+/*
+ * Copyright (C) 2022 Mohd Noor Aman
+ *
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <bsp.h>
+#include <bsp/start.h>
+#include <bsp/aarch64-mmu.h>
+#include <bsp/raspberrypi.h>
+#include <libcpu/mmu-vmsav8-64.h>
+
+
+BSP_START_DATA_SECTION static const aarch64_mmu_config_entry
+raspberrypi_4_mmu_config_table[] = {
+ AARCH64_MMU_DEFAULT_SECTIONS,
+
+ { /* RPI peripheral address */
+ .begin = (unsigned)RPI_PERIPHERAL_BASE,
+ .end = (unsigned)RPI_PERIPHERAL_BASE + (unsigned)RPI_PERIPHERAL_SIZE,
+ .flags = AARCH64_MMU_DEVICE
+ },
+
+ { /* RPI ARM local registers */
+ .begin = (unsigned)BCM2711_LOCAL_REGS_BASE,
+ .end = (unsigned)BCM2711_LOCAL_REGS_BASE + (unsigned)BCM2711_LOCAL_REGS_SIZE,
+ .flags = AARCH64_MMU_DEVICE
+ },
+
+ { /* RPI GIC Interface address */
+ .begin = 0xFF800000U,
+ .end = 0xFFA00000U,
+ .flags = AARCH64_MMU_DEVICE
+ }
+
+};
+/*
+ * Make weak and let the user override.
+ */
+BSP_START_TEXT_SECTION void
+raspberrypi_4_setup_mmu_and_cache( void ) __attribute__ ((weak));
+
+BSP_START_TEXT_SECTION void
+raspberrypi_4_setup_mmu_and_cache( void )
+{
+ aarch64_mmu_setup();
+
+ aarch64_mmu_setup_translation_table(
+ &raspberrypi_4_mmu_config_table[ 0 ],
+ RTEMS_ARRAY_SIZE( raspberrypi_4_mmu_config_table )
+ );
+
+ aarch64_mmu_enable();
+} \ No newline at end of file
diff --git a/bsps/aarch64/shared/start/linkcmds.base b/bsps/aarch64/shared/start/linkcmds.base
index f4639bd990..d442dbea28 100644
--- a/bsps/aarch64/shared/start/linkcmds.base
+++ b/bsps/aarch64/shared/start/linkcmds.base
@@ -151,7 +151,7 @@ SECTIONS {
} > REGION_RODATA AT > REGION_RODATA_LOAD
.data.rel.ro : ALIGN_WITH_INPUT {
*(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*)
- *(.data.rel.ro* .gnu.linkonce.d.rel.ro.*)
+ *(.data.rel.ro .data.rel.ro.* .gnu.linkonce.d.rel.ro.*)
} > REGION_RODATA AT > REGION_RODATA_LOAD
.jcr : ALIGN_WITH_INPUT {
KEEP (*(.jcr))
diff --git a/bsps/aarch64/shared/start/start.S b/bsps/aarch64/shared/start/start.S
index 8bd4f86f4e..0237583463 100644
--- a/bsps/aarch64/shared/start/start.S
+++ b/bsps/aarch64/shared/start/start.S
@@ -307,6 +307,12 @@ _el1_start:
/* FPU does not need to be enabled on AArch64 */
+ /* Ensure FPU traps are disabled by default */
+ mrs x0, FPCR
+ bic x0, x0, #((1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) | (1 << 12))
+ bic x0, x0, #(1 << 15)
+ msr FPCR, x0
+
#endif /* AARCH64_MULTILIB_VFP */
/* Branch to start hook 1 */
diff --git a/bsps/aarch64/xilinx-versal/dev/serial/versal-uart-polled.c b/bsps/aarch64/xilinx-versal/dev/serial/versal-uart-polled.c
index 83493db909..9453dc248b 100644
--- a/bsps/aarch64/xilinx-versal/dev/serial/versal-uart-polled.c
+++ b/bsps/aarch64/xilinx-versal/dev/serial/versal-uart-polled.c
@@ -152,23 +152,6 @@ int versal_uart_initialize(rtems_termios_device_context *base)
return 0;
}
-static bool versal_uart_first_open(
- struct rtems_termios_tty *tty,
- rtems_termios_device_context *base,
- struct termios *term,
- rtems_libio_open_close_args_t *args
-)
-{
- int rc = versal_uart_initialize(base);
- if ( rc < 0 ) {
- return false;
- }
-
- rtems_termios_set_initial_baud(tty, VERSAL_UART_DEFAULT_BAUD);
-
- return true;
-}
-
int versal_uart_read_polled(rtems_termios_device_context *base)
{
volatile versal_uart *regs = versal_uart_get_regs(base);
@@ -209,23 +192,3 @@ void versal_uart_reset_tx_flush(rtems_termios_device_context *base)
/* Wait for empty */
}
}
-
-static void versal_uart_write_support(
- rtems_termios_device_context *base,
- const char *s,
- size_t n
-)
-{
- size_t i;
-
- for (i = 0; i < n; i++) {
- versal_uart_write_polled(base, s[i]);
- }
-}
-
-const rtems_termios_device_handler versal_uart_handler = {
- .first_open = versal_uart_first_open,
- .write = versal_uart_write_support,
- .poll_read = versal_uart_read_polled,
- .mode = TERMIOS_POLLED
-};
diff --git a/bsps/aarch64/xilinx-versal/dev/serial/versal-uart.c b/bsps/aarch64/xilinx-versal/dev/serial/versal-uart.c
new file mode 100644
index 0000000000..b009f83c37
--- /dev/null
+++ b/bsps/aarch64/xilinx-versal/dev/serial/versal-uart.c
@@ -0,0 +1,321 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (C) 2022 Chris Johns <chris@contemporary.software>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <dev/serial/versal-uart.h>
+#include <dev/serial/versal-uart-regs.h>
+#include <bsp/irq.h>
+
+#include <bspopts.h>
+
+#ifdef VERSAL_CONSOLE_USE_INTERRUPTS
+static uint32_t versal_uart_intr_all(void)
+{
+ return VERSAL_UARTI_OEI |
+ VERSAL_UARTI_BEI |
+ VERSAL_UARTI_PEI |
+ VERSAL_UARTI_FEI |
+ VERSAL_UARTI_RTI |
+ VERSAL_UARTI_TXI |
+ VERSAL_UARTI_RXI |
+ VERSAL_UARTI_DSRMI |
+ VERSAL_UARTI_DCDMI |
+ VERSAL_UARTI_CTSMI |
+ VERSAL_UARTI_RIMI;
+}
+
+static void versal_uart_intr_clear(volatile versal_uart *regs, uint32_t ints)
+{
+ regs->uarticr = ints;
+}
+
+static void versal_uart_intr_clearall(volatile versal_uart *regs)
+{
+ versal_uart_intr_clear(regs, versal_uart_intr_all());
+}
+
+static void versal_uart_intr_enable(volatile versal_uart *regs, uint32_t ints)
+{
+ regs->uartimsc |= ints;
+}
+
+static void versal_uart_intr_disable(volatile versal_uart *regs, uint32_t ints)
+{
+ regs->uartimsc &= ~ints;
+}
+
+static void versal_uart_intr_disableall(volatile versal_uart *regs)
+{
+ versal_uart_intr_disable(regs, versal_uart_intr_all());
+}
+
+static bool versal_uart_flags_clear(volatile versal_uart *regs, uint32_t flags)
+{
+ return (regs->uartfr & flags) == 0;
+}
+
+static void versal_uart_interrupt(void *arg)
+{
+ rtems_termios_tty *tty = arg;
+ versal_uart_context *ctx = rtems_termios_get_device_context(tty);
+ volatile versal_uart *regs = ctx->regs;
+ uint32_t uartmis = regs->uartmis;
+
+ versal_uart_intr_clear(regs, uartmis);
+
+ if ((uartmis & (VERSAL_UARTI_RTI | VERSAL_UARTI_RXI)) != 0) {
+ char buf[32];
+ int c = 0;
+ while (c < sizeof(buf) &&
+ versal_uart_flags_clear(regs, VERSAL_UARTFR_RXFE)) {
+ buf[c++] = (char) VERSAL_UARTDR_DATA_GET(regs->uartdr);
+ }
+ rtems_termios_enqueue_raw_characters(tty, buf, c);
+ }
+
+ if (ctx->transmitting) {
+ int sent = ctx->tx_queued;
+ ctx->transmitting = false;
+ ctx->tx_queued = 0;
+ versal_uart_intr_disable(regs, VERSAL_UARTI_TXI);
+ rtems_termios_dequeue_characters(tty, sent);
+ }
+}
+#endif
+
+static bool versal_uart_first_open(
+ rtems_termios_tty *tty,
+ rtems_termios_device_context *base,
+ struct termios *term,
+ rtems_libio_open_close_args_t *args
+)
+{
+#ifdef VERSAL_CONSOLE_USE_INTERRUPTS
+ versal_uart_context *ctx = (versal_uart_context *) base;
+ volatile versal_uart *regs = ctx->regs;
+ rtems_status_code sc;
+
+ ctx->transmitting = false;
+ ctx->tx_queued = 0;
+ ctx->first_send = true;
+#endif
+
+ rtems_termios_set_initial_baud(tty, VERSAL_UART_DEFAULT_BAUD);
+ versal_uart_initialize(base);
+
+#ifdef VERSAL_CONSOLE_USE_INTERRUPTS
+ regs->uartifls = VERSAL_UARTIFLS_RXIFLSEL(2) | VERSAL_UARTIFLS_TXIFLSEL(2);
+ regs->uartlcr_h |= VERSAL_UARTLCR_H_FEN;
+ versal_uart_intr_disableall(regs);
+ sc = rtems_interrupt_handler_install(
+ ctx->irq,
+ "UART",
+ RTEMS_INTERRUPT_SHARED,
+ versal_uart_interrupt,
+ tty
+ );
+ if (sc != RTEMS_SUCCESSFUL) {
+ return false;
+ }
+ versal_uart_intr_clearall(regs);
+ versal_uart_intr_enable(regs, VERSAL_UARTI_RTI | VERSAL_UARTI_RXI);
+#endif
+
+ return true;
+}
+
+#ifdef VERSAL_CONSOLE_USE_INTERRUPTS
+static void versal_uart_last_close(
+ rtems_termios_tty *tty,
+ rtems_termios_device_context *base,
+ rtems_libio_open_close_args_t *args
+)
+{
+ versal_uart_context *ctx = (versal_uart_context *) base;
+ rtems_interrupt_handler_remove(ctx->irq, versal_uart_interrupt, tty);
+}
+#endif
+
+static void versal_uart_write_support(
+ rtems_termios_device_context *base,
+ const char *buf,
+ size_t len
+)
+{
+#ifdef VERSAL_CONSOLE_USE_INTERRUPTS
+ versal_uart_context *ctx = (versal_uart_context *) base;
+ volatile versal_uart *regs = ctx->regs;
+
+ if (len > 0) {
+ size_t len_remaining = len;
+ const char *p = &buf[0];
+ versal_uart_intr_enable(regs, VERSAL_UARTI_TXI);
+ /*
+ * The PL011 IP in the Versal needs preloading the TX FIFO with
+ * exactly 17 characters for the first TX interrupt to be
+ * generated.
+ */
+ if (ctx->first_send) {
+ ctx->first_send = false;
+ for (int i = 0; i < 17; ++i) {
+ regs->uartdr = VERSAL_UARTDR_DATA('\r');
+ }
+ }
+ while (versal_uart_flags_clear(regs, VERSAL_UARTFR_TXFF) &&
+ len_remaining > 0) {
+ regs->uartdr = VERSAL_UARTDR_DATA(*p++);
+ --len_remaining;
+ }
+ ctx->tx_queued = len - len_remaining;
+ ctx->transmitting = true;
+ }
+#else
+ ssize_t i;
+ for (i = 0; i < len; ++i) {
+ versal_uart_write_polled(base, buf[i]);
+ }
+#endif
+}
+
+static bool versal_uart_set_attributes(
+ rtems_termios_device_context *context,
+ const struct termios *term
+)
+{
+ versal_uart_context *ctx = (versal_uart_context *) context;
+ volatile versal_uart *regs = ctx->regs;
+ int32_t baud;
+ uint32_t ibauddiv = 0;
+ uint32_t fbauddiv = 0;
+ uint32_t mode = 0;
+ int rc;
+
+ /*
+ * Determine the baud rate
+ */
+ baud = rtems_termios_baud_to_number(term->c_ospeed);
+
+ if (baud > 0) {
+ uint32_t maxerr = 3;
+
+ rc = versal_cal_baud_rate(
+ VERSAL_UART_DEFAULT_BAUD,
+ maxerr,
+ &ibauddiv,
+ &fbauddiv
+ );
+ if (rc != 0) {
+ return rc;
+ }
+ }
+
+ /*
+ * Configure the mode register
+ */
+ mode = regs->uartlcr_h & VERSAL_UARTLCR_H_FEN;
+
+ /*
+ * Parity
+ */
+ if ((term->c_cflag & PARENB) != 0) {
+ mode |= VERSAL_UARTLCR_H_PEN;
+ if ((term->c_cflag & PARODD) == 0) {
+ mode |= VERSAL_UARTLCR_H_EPS;
+ }
+ }
+
+ /*
+ * Character Size
+ */
+ switch (term->c_cflag & CSIZE)
+ {
+ case CS5:
+ mode = VERSAL_UARTLCR_H_WLEN_SET(mode, VERSAL_UARTLCR_H_WLEN_5);
+ break;
+ case CS6:
+ mode = VERSAL_UARTLCR_H_WLEN_SET(mode, VERSAL_UARTLCR_H_WLEN_6);
+ break;
+ case CS7:
+ mode = VERSAL_UARTLCR_H_WLEN_SET(mode, VERSAL_UARTLCR_H_WLEN_7);
+ break;
+ case CS8:
+ default:
+ mode = VERSAL_UARTLCR_H_WLEN_SET(mode, VERSAL_UARTLCR_H_WLEN_8);
+ break;
+ }
+
+ /*
+ * Stop Bits
+ */
+ if (term->c_cflag & CSTOPB) {
+ /* 2 stop bits */
+ mode |= VERSAL_UARTLCR_H_STP2;
+ }
+
+ versal_uart_intr_disableall(regs);
+
+ /*
+ * Wait for any data in the TXFIFO to be sent then wait while the
+ * transmiter is active.
+ */
+ while ((regs->uartfr & VERSAL_UARTFR_TXFE) == 0 ||
+ (regs->uartfr & VERSAL_UARTFR_BUSY) != 0) {
+ /* Wait */
+ }
+
+ regs->uartcr = VERSAL_UARTCR_UARTEN;
+ /* Ignore baud rate of B0. There are no modem control lines to de-assert */
+ if (baud > 0) {
+ regs->uartibrd = VERSAL_UARTIBRD_BAUD_DIVINT(ibauddiv);
+ regs->uartfbrd = VERSAL_UARTFBRD_BAUD_DIVFRAC(fbauddiv);
+ }
+ regs->uartlcr_h = mode;
+
+ /* Control: receive, transmit, uart enable, no CTS, no RTS, no loopback */
+ regs->uartcr = VERSAL_UARTCR_RXE
+ | VERSAL_UARTCR_TXE
+ | VERSAL_UARTCR_UARTEN;
+
+#ifdef VERSAL_CONSOLE_USE_INTERRUPTS
+ versal_uart_intr_clearall(regs);
+ versal_uart_intr_enable(regs, VERSAL_UARTI_RTI | VERSAL_UARTI_RXI);
+#endif
+
+ return true;
+}
+
+const rtems_termios_device_handler versal_uart_handler = {
+ .first_open = versal_uart_first_open,
+ .set_attributes = versal_uart_set_attributes,
+ .write = versal_uart_write_support,
+#ifdef VERSAL_CONSOLE_USE_INTERRUPTS
+ .last_close = versal_uart_last_close,
+ .mode = TERMIOS_IRQ_DRIVEN
+#else
+ .poll_read = versal_uart_read_polled,
+ .mode = TERMIOS_POLLED
+#endif
+};
diff --git a/bsps/aarch64/xilinx-versal/include/bsp.h b/bsps/aarch64/xilinx-versal/include/bsp.h
index 0bd93f28bc..5b01637786 100644
--- a/bsps/aarch64/xilinx-versal/include/bsp.h
+++ b/bsps/aarch64/xilinx-versal/include/bsp.h
@@ -79,6 +79,10 @@ BSP_START_TEXT_SECTION void versal_setup_mmu_and_cache(void);
void versal_debug_console_flush(void);
+uint32_t versal_clock_i2c0(void);
+
+uint32_t versal_clock_i2c1(void);
+
#ifdef __cplusplus
}
#endif /* __cplusplus */
diff --git a/bsps/aarch64/xilinx-versal/include/bsp/i2c.h b/bsps/aarch64/xilinx-versal/include/bsp/i2c.h
new file mode 100644
index 0000000000..e76ae6cc9a
--- /dev/null
+++ b/bsps/aarch64/xilinx-versal/include/bsp/i2c.h
@@ -0,0 +1,64 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (C) 2022 Chris Johns <chris@contemporary.software>
+ * Copyright (C) 2014 embedded brains GmbH
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBBSP_ARM_XILINX_VERSAL_I2C_H
+#define LIBBSP_ARM_XILINX_VERSAL_I2C_H
+
+#include <dev/i2c/cadence-i2c.h>
+#include <bsp/irq.h>
+#include <bsp.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+static inline int versal_register_i2c_0(void)
+{
+ return i2c_bus_register_cadence(
+ "/dev/i2c-0",
+ 0x00FF020000,
+ versal_clock_i2c0(),
+ VERSAL_IRQ_I2C_0
+ );
+}
+
+static inline int versal_register_i2c_1(void)
+{
+ return i2c_bus_register_cadence(
+ "/dev/i2c-1",
+ 0x00FF030000,
+ versal_clock_i2c1(),
+ VERSAL_IRQ_I2C_1
+ );
+}
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_XILINX_VERSAL_I2C_H */
diff --git a/bsps/aarch64/xilinx-versal/include/bsp/irq.h b/bsps/aarch64/xilinx-versal/include/bsp/irq.h
index c5f199a9ae..b34bdfd345 100644
--- a/bsps/aarch64/xilinx-versal/include/bsp/irq.h
+++ b/bsps/aarch64/xilinx-versal/include/bsp/irq.h
@@ -53,6 +53,8 @@ extern "C" {
#define BSP_TIMER_VIRT_PPI 27
#define BSP_TIMER_PHYS_S_PPI 29
#define BSP_TIMER_PHYS_NS_PPI 30
+#define VERSAL_IRQ_I2C_0 46
+#define VERSAL_IRQ_I2C_1 47
#define VERSAL_IRQ_UART_0 50
#define VERSAL_IRQ_UART_1 51
#define VERSAL_IRQ_ETHERNET_0 88
diff --git a/bsps/aarch64/xilinx-versal/include/dev/serial/versal-uart-regs.h b/bsps/aarch64/xilinx-versal/include/dev/serial/versal-uart-regs.h
index 59db8f950a..30f918bc60 100644
--- a/bsps/aarch64/xilinx-versal/include/dev/serial/versal-uart-regs.h
+++ b/bsps/aarch64/xilinx-versal/include/dev/serial/versal-uart-regs.h
@@ -110,7 +110,6 @@ typedef struct versal_uart {
#define VERSAL_UARTCR_RXE BSP_BIT32(9)
#define VERSAL_UARTCR_TXE BSP_BIT32(8)
#define VERSAL_UARTCR_LBE BSP_BIT32(7)
-//#define VERSAL_UARTCR_SIREN BSP_BIT32()?
#define VERSAL_UARTCR_UARTEN BSP_BIT32(0)
uint32_t uartifls;
#define VERSAL_UARTIFLS_RXIFLSEL(val) BSP_FLD32(val, 3, 5)
diff --git a/bsps/aarch64/xilinx-versal/include/dev/serial/versal-uart.h b/bsps/aarch64/xilinx-versal/include/dev/serial/versal-uart.h
index 95b5172218..cc6b60b77c 100644
--- a/bsps/aarch64/xilinx-versal/include/dev/serial/versal-uart.h
+++ b/bsps/aarch64/xilinx-versal/include/dev/serial/versal-uart.h
@@ -54,7 +54,9 @@ extern "C" {
typedef struct {
rtems_termios_device_context base;
volatile struct versal_uart *regs;
- bool transmitting; /* Currently unused */
+ volatile size_t tx_queued;
+ volatile bool transmitting;
+ bool first_send;
rtems_vector_number irq;
} versal_uart_context;
diff --git a/bsps/aarch64/xilinx-versal/start/bspstart.c b/bsps/aarch64/xilinx-versal/start/bspstart.c
index 2f0048ddf3..89b06a0ff4 100644
--- a/bsps/aarch64/xilinx-versal/start/bspstart.c
+++ b/bsps/aarch64/xilinx-versal/start/bspstart.c
@@ -38,6 +38,18 @@
#include <bsp/irq-generic.h>
#include <bsp/linker-symbols.h>
+#include <rtems/score/basedefs.h>
+
+RTEMS_WEAK uint32_t versal_clock_i2c0(void)
+{
+ return VERSAL_CLOCK_I2C0;
+}
+
+RTEMS_WEAK uint32_t versal_clock_i2c1(void)
+{
+ return VERSAL_CLOCK_I2C1;
+}
+
void bsp_start( void )
{
bsp_interrupt_initialize();
diff --git a/bsps/aarch64/xilinx-versal/start/bspstartmmu.c b/bsps/aarch64/xilinx-versal/start/bspstartmmu.c
index b2da3bc60d..ee87890293 100644
--- a/bsps/aarch64/xilinx-versal/start/bspstartmmu.c
+++ b/bsps/aarch64/xilinx-versal/start/bspstartmmu.c
@@ -44,7 +44,11 @@
BSP_START_DATA_SECTION static const aarch64_mmu_config_entry
versal_mmu_config_table[] = {
AARCH64_MMU_DEFAULT_SECTIONS,
- { /* APU GIC */
+ { /* Devices */
+ .begin = 0xf1000000U,
+ .end = 0xf2000000U,
+ .flags = AARCH64_MMU_DEVICE
+ }, { /* APU GIC */
.begin = 0xf9000000U,
.end = 0xf90c0000U,
.flags = AARCH64_MMU_DEVICE
diff --git a/bsps/aarch64/xilinx-zynqmp/console/console.c b/bsps/aarch64/xilinx-zynqmp/console/console.c
index d1948f1a0c..992b8a62da 100644
--- a/bsps/aarch64/xilinx-zynqmp/console/console.c
+++ b/bsps/aarch64/xilinx-zynqmp/console/console.c
@@ -9,7 +9,7 @@
*/
/*
- * Copyright (C) 2020 On-Line Applications Research Corporation (OAR)
+ * Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
* Written by Kinsey Moore <kinsey.moore@oarcorp.com>
*
* Redistribution and use in source and binary forms, with or without
@@ -36,12 +36,152 @@
#include <rtems/console.h>
#include <rtems/bspIo.h>
+#include <rtems/endian.h>
#include <rtems/sysinit.h>
+#include <bsp/aarch64-mmu.h>
+#include <bsp/fdt.h>
#include <bsp/irq.h>
+
#include <dev/serial/zynq-uart.h>
#include <bspopts.h>
+#include <libfdt.h>
+
+#include <libchip/ns16550.h>
+
+uint32_t mgmt_uart_reg_shift = 0;
+static uint8_t get_register(uintptr_t addr, uint8_t i)
+{
+ volatile uint8_t *reg = (uint8_t *) addr;
+
+ i <<= mgmt_uart_reg_shift;
+ return reg [i];
+}
+
+static void set_register(uintptr_t addr, uint8_t i, uint8_t val)
+{
+ volatile uint8_t *reg = (uint8_t *) addr;
+
+ i <<= mgmt_uart_reg_shift;
+ reg [i] = val;
+}
+
+static ns16550_context zynqmp_mgmt_uart_context = {
+ .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER("Management UART 0"),
+ .get_reg = get_register,
+ .set_reg = set_register,
+ .port = 0,
+ .irq = 0,
+ .clock = 0,
+ .initial_baud = 0,
+};
+
+__attribute__ ((weak)) void zynqmp_configure_management_console(rtems_termios_device_context *base)
+{
+ /* This SLIP-encoded watchdog command sets timeouts to 0xFFFFFFFF seconds. */
+ const char mgmt_watchdog_cmd[] =
+ "\xc0\xda\x00\x00\xff\xff\xff\xff\xff\x00\xff\xff\xff\xffM#\xc0";
+
+ /* Send the system watchdog configuration command */
+ for (int i = 0; i < sizeof(mgmt_watchdog_cmd); i++) {
+ ns16550_polled_putchar(base, mgmt_watchdog_cmd[i]);
+ }
+}
+
+static void zynqmp_management_console_init(void)
+{
+ /* Find the management console in the device tree */
+ const void *fdt = bsp_fdt_get();
+ const uint32_t *prop;
+ uint32_t outprop[4];
+ int proplen;
+ int node;
+
+ const char *alias = fdt_get_alias(fdt, "mgmtport");
+ if (alias == NULL) {
+ return;
+ }
+ node = fdt_path_offset(fdt, alias);
+
+ prop = fdt_getprop(fdt, node, "clock-frequency", &proplen);
+ if ( prop == NULL || proplen != 4 ) {
+ zynqmp_mgmt_uart_context.port = 0;
+ return;
+ }
+ outprop[0] = rtems_uint32_from_big_endian((const uint8_t *) &prop[0]);
+ zynqmp_mgmt_uart_context.clock = outprop[0];
+
+ prop = fdt_getprop(fdt, node, "current-speed", &proplen);
+ if ( prop == NULL || proplen != 4 ) {
+ zynqmp_mgmt_uart_context.port = 0;
+ return;
+ }
+ outprop[0] = rtems_uint32_from_big_endian((const uint8_t *) &prop[0]);
+ zynqmp_mgmt_uart_context.initial_baud = outprop[0];
+
+ prop = fdt_getprop(fdt, node, "interrupts", &proplen);
+ if ( prop == NULL || proplen != 12 ) {
+ zynqmp_mgmt_uart_context.port = 0;
+ return;
+ }
+ outprop[0] = rtems_uint32_from_big_endian((const uint8_t *) &prop[0]);
+ outprop[1] = rtems_uint32_from_big_endian((const uint8_t *) &prop[1]);
+ outprop[2] = rtems_uint32_from_big_endian((const uint8_t *) &prop[2]);
+ /* proplen is in bytes, interrupt mapping expects a length in 32-bit cells */
+ zynqmp_mgmt_uart_context.irq = bsp_fdt_map_intr(outprop, proplen / 4);
+ if ( zynqmp_mgmt_uart_context.irq == 0 ) {
+ zynqmp_mgmt_uart_context.port = 0;
+ return;
+ }
+
+ prop = fdt_getprop(fdt, node, "reg", &proplen);
+ if ( prop == NULL || proplen != 16 ) {
+ zynqmp_mgmt_uart_context.port = 0;
+ return;
+ }
+ outprop[0] = rtems_uint32_from_big_endian((const uint8_t *) &prop[0]);
+ outprop[1] = rtems_uint32_from_big_endian((const uint8_t *) &prop[1]);
+ outprop[2] = rtems_uint32_from_big_endian((const uint8_t *) &prop[2]);
+ outprop[3] = rtems_uint32_from_big_endian((const uint8_t *) &prop[3]);
+ zynqmp_mgmt_uart_context.port = ( ( (uint64_t) outprop[0] ) << 32 ) | outprop[1];
+ uintptr_t uart_base = zynqmp_mgmt_uart_context.port;
+ size_t uart_size = ( ( (uint64_t) outprop[2] ) << 32 ) | outprop[3];
+
+ rtems_status_code sc = aarch64_mmu_map( uart_base,
+ uart_size,
+ AARCH64_MMU_DEVICE);
+ if ( sc != RTEMS_SUCCESSFUL ) {
+ zynqmp_mgmt_uart_context.port = 0;
+ return;
+ }
+
+ prop = fdt_getprop(fdt, node, "reg-offset", &proplen);
+ if ( prop == NULL || proplen != 4 ) {
+ zynqmp_mgmt_uart_context.port = 0;
+ return;
+ }
+ outprop[0] = rtems_uint32_from_big_endian((const uint8_t *) &prop[0]);
+ zynqmp_mgmt_uart_context.port += outprop[0];
+
+ prop = fdt_getprop(fdt, node, "reg-shift", &proplen);
+ if ( prop == NULL || proplen != 4 ) {
+ zynqmp_mgmt_uart_context.port = 0;
+ return;
+ }
+ outprop[0] = rtems_uint32_from_big_endian((const uint8_t *) &prop[0]);
+ mgmt_uart_reg_shift = outprop[0];
+
+ ns16550_probe(&zynqmp_mgmt_uart_context.base);
+
+ zynqmp_configure_management_console(&zynqmp_mgmt_uart_context.base);
+}
+
+RTEMS_SYSINIT_ITEM(
+ zynqmp_management_console_init,
+ RTEMS_SYSINIT_BSP_START,
+ RTEMS_SYSINIT_ORDER_FIRST
+);
static zynq_uart_context zynqmp_uart_instances[2] = {
{
@@ -81,6 +221,15 @@ rtems_status_code console_initialize(
}
}
+ if ( zynqmp_mgmt_uart_context.port != 0 ) {
+ rtems_termios_device_install(
+ "/dev/ttyMGMT0",
+ &ns16550_handler_polled,
+ NULL,
+ &zynqmp_mgmt_uart_context.base
+ );
+ }
+
return RTEMS_SUCCESSFUL;
}
diff --git a/bsps/aarch64/xilinx-zynqmp/fdt/bsp_fdt.c b/bsps/aarch64/xilinx-zynqmp/fdt/bsp_fdt.c
new file mode 100644
index 0000000000..0748639256
--- /dev/null
+++ b/bsps/aarch64/xilinx-zynqmp/fdt/bsp_fdt.c
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsAArch64XilinxZynqMP
+ *
+ * @brief This source file contains the implementatin of bsp_fdt_get().
+ */
+
+/*
+ * Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore <kinsey.moore@oarcorp.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <bsp.h>
+#include <bsp/fdt.h>
+
+const void *bsp_fdt_get(void)
+{
+ return zynqmp_dtb;
+}
+
+uint32_t bsp_fdt_map_intr(const uint32_t *intr, size_t icells)
+{
+ if (icells != 3) {
+ return 0;
+ }
+ return (intr[0] == 0 ? 32 : 16) + intr[1];
+}
diff --git a/bsps/aarch64/xilinx-zynqmp/fdt/cfc400x.dts b/bsps/aarch64/xilinx-zynqmp/fdt/cfc400x.dts
new file mode 100644
index 0000000000..763a668a5c
--- /dev/null
+++ b/bsps/aarch64/xilinx-zynqmp/fdt/cfc400x.dts
@@ -0,0 +1,110 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsAArch64XilinxZynqMP
+ *
+ * @brief This file provides the CFC-400X device tree
+ */
+
+/*
+ * Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore <kinsey.moore@oarcorp.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+/ {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+
+ amba {
+ compatible = "simple-bus";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+
+ interrupt-controller@f9010000 {
+ compatible = "arm,gic-400";
+ #address-cells = <0x02>;
+ #interrupt-cells = <0x03>;
+ reg = <0x00 0xf9010000 0x00 0x10000>;
+ interrupt-controller;
+ phandle = <0x01>;
+ };
+
+ ethernet@ff0b0000 {
+ compatible = "cdns,gem";
+ status = "okay";
+ interrupt-parent = <0x01>;
+ interrupts = <0x00 0x39 0x04>;
+ reg = <0x00 0xff0b0000 0x00 0x1000>;
+ phy-mode = "sgmii";
+ };
+
+ ethernet@ff0c0000 {
+ compatible = "cdns,gem";
+ status = "okay";
+ interrupt-parent = <0x01>;
+ interrupts = <0x00 0x3b 0x04>;
+ reg = <0x00 0xff0c0000 0x00 0x1000>;
+ phy-mode = "sgmii";
+ };
+
+ ethernet@ff0d0000 {
+ compatible = "cdns,gem";
+ status = "okay";
+ interrupt-parent = <0x01>;
+ interrupts = <0x00 0x3d 0x04>;
+ reg = <0x00 0xff0d0000 0x00 0x1000>;
+ phy-mode = "sgmii";
+ };
+
+ ethernet@ff0e0000 {
+ compatible = "cdns,gem";
+ status = "okay";
+ interrupt-parent = <0x01>;
+ interrupts = <0x00 0x3f 0x04>;
+ reg = <0x00 0xff0e0000 0x00 0x1000>;
+ phy-mode = "sgmii";
+ };
+
+ serial@800a0000 {
+ clock-frequency = <0x189c000>;
+ compatible = "ns16550a";
+ current-speed = <0x1c200>;
+ device_type = "serial";
+ interrupt-parent = <0x01>;
+ interrupts = <0x00 0x6e 0x04>;
+ reg = <0x00 0x800a0000 0x00 0x10000>;
+ reg-offset = <0x1000>;
+ reg-shift = <0x02>;
+ };
+ };
+
+ aliases {
+ mgmtport = "/amba/serial@800a0000";
+ };
+};
diff --git a/bsps/aarch64/xilinx-zynqmp/fdt/cfc400x_dtb.c b/bsps/aarch64/xilinx-zynqmp/fdt/cfc400x_dtb.c
new file mode 100644
index 0000000000..2d0078678e
--- /dev/null
+++ b/bsps/aarch64/xilinx-zynqmp/fdt/cfc400x_dtb.c
@@ -0,0 +1,124 @@
+unsigned char zynqmp_dtb[] = {
+ 0xd0, 0x0d, 0xfe, 0xed, 0x00, 0x00, 0x05, 0xa3, 0x00, 0x00, 0x00, 0x38,
+ 0x00, 0x00, 0x04, 0xd0, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x11,
+ 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd3,
+ 0x00, 0x00, 0x04, 0x98, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x02,
+ 0x00, 0x00, 0x00, 0x01, 0x61, 0x6d, 0x62, 0x61, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00, 0x1b,
+ 0x73, 0x69, 0x6d, 0x70, 0x6c, 0x65, 0x2d, 0x62, 0x75, 0x73, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
+ 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x26, 0x00, 0x00, 0x00, 0x01,
+ 0x69, 0x6e, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70, 0x74, 0x2d, 0x63, 0x6f,
+ 0x6e, 0x74, 0x72, 0x6f, 0x6c, 0x6c, 0x65, 0x72, 0x40, 0x66, 0x39, 0x30,
+ 0x31, 0x30, 0x30, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x1b, 0x61, 0x72, 0x6d, 0x2c,
+ 0x67, 0x69, 0x63, 0x2d, 0x34, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x2d,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x10,
+ 0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00, 0xf9, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x42, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x57, 0x00, 0x00, 0x00, 0x01,
+ 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x65, 0x74, 0x68, 0x65,
+ 0x72, 0x6e, 0x65, 0x74, 0x40, 0x66, 0x66, 0x30, 0x62, 0x30, 0x30, 0x30,
+ 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x09,
+ 0x00, 0x00, 0x00, 0x1b, 0x63, 0x64, 0x6e, 0x73, 0x2c, 0x67, 0x65, 0x6d,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x05,
+ 0x00, 0x00, 0x00, 0x5f, 0x6f, 0x6b, 0x61, 0x79, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x66,
+ 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0c,
+ 0x00, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x39,
+ 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x10,
+ 0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00, 0xff, 0x0b, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x82, 0x73, 0x67, 0x6d, 0x69,
+ 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01,
+ 0x65, 0x74, 0x68, 0x65, 0x72, 0x6e, 0x65, 0x74, 0x40, 0x66, 0x66, 0x30,
+ 0x63, 0x30, 0x30, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x1b, 0x63, 0x64, 0x6e, 0x73,
+ 0x2c, 0x67, 0x65, 0x6d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x5f, 0x6f, 0x6b, 0x61, 0x79,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
+ 0x00, 0x00, 0x00, 0x66, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x3b, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00,
+ 0xff, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x82,
+ 0x73, 0x67, 0x6d, 0x69, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
+ 0x00, 0x00, 0x00, 0x01, 0x65, 0x74, 0x68, 0x65, 0x72, 0x6e, 0x65, 0x74,
+ 0x40, 0x66, 0x66, 0x30, 0x64, 0x30, 0x30, 0x30, 0x30, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x1b,
+ 0x63, 0x64, 0x6e, 0x73, 0x2c, 0x67, 0x65, 0x6d, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x5f,
+ 0x6f, 0x6b, 0x61, 0x79, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x66, 0x00, 0x00, 0x00, 0x01,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x77,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3d, 0x00, 0x00, 0x00, 0x04,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x3e,
+ 0x00, 0x00, 0x00, 0x00, 0xff, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x06,
+ 0x00, 0x00, 0x00, 0x82, 0x73, 0x67, 0x6d, 0x69, 0x69, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x65, 0x74, 0x68, 0x65,
+ 0x72, 0x6e, 0x65, 0x74, 0x40, 0x66, 0x66, 0x30, 0x65, 0x30, 0x30, 0x30,
+ 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x09,
+ 0x00, 0x00, 0x00, 0x1b, 0x63, 0x64, 0x6e, 0x73, 0x2c, 0x67, 0x65, 0x6d,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x05,
+ 0x00, 0x00, 0x00, 0x5f, 0x6f, 0x6b, 0x61, 0x79, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x66,
+ 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0c,
+ 0x00, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f,
+ 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x10,
+ 0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00, 0xff, 0x0e, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x82, 0x73, 0x67, 0x6d, 0x69,
+ 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01,
+ 0x73, 0x65, 0x72, 0x69, 0x61, 0x6c, 0x40, 0x38, 0x30, 0x30, 0x61, 0x30,
+ 0x30, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
+ 0x00, 0x00, 0x00, 0x8b, 0x01, 0x89, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x1b, 0x6e, 0x73, 0x31, 0x36,
+ 0x35, 0x35, 0x30, 0x61, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x9b, 0x00, 0x01, 0xc2, 0x00,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0xa9,
+ 0x73, 0x65, 0x72, 0x69, 0x61, 0x6c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x66, 0x00, 0x00, 0x00, 0x01,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x77,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6e, 0x00, 0x00, 0x00, 0x04,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x3e,
+ 0x00, 0x00, 0x00, 0x00, 0x80, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
+ 0x00, 0x00, 0x00, 0xb5, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x02,
+ 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01,
+ 0x61, 0x6c, 0x69, 0x61, 0x73, 0x65, 0x73, 0x00, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00, 0xca, 0x2f, 0x61, 0x6d, 0x62,
+ 0x61, 0x2f, 0x73, 0x65, 0x72, 0x69, 0x61, 0x6c, 0x40, 0x38, 0x30, 0x30,
+ 0x61, 0x30, 0x30, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
+ 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x09, 0x23, 0x61, 0x64, 0x64,
+ 0x72, 0x65, 0x73, 0x73, 0x2d, 0x63, 0x65, 0x6c, 0x6c, 0x73, 0x00, 0x23,
+ 0x73, 0x69, 0x7a, 0x65, 0x2d, 0x63, 0x65, 0x6c, 0x6c, 0x73, 0x00, 0x63,
+ 0x6f, 0x6d, 0x70, 0x61, 0x74, 0x69, 0x62, 0x6c, 0x65, 0x00, 0x72, 0x61,
+ 0x6e, 0x67, 0x65, 0x73, 0x00, 0x23, 0x69, 0x6e, 0x74, 0x65, 0x72, 0x72,
+ 0x75, 0x70, 0x74, 0x2d, 0x63, 0x65, 0x6c, 0x6c, 0x73, 0x00, 0x72, 0x65,
+ 0x67, 0x00, 0x69, 0x6e, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70, 0x74, 0x2d,
+ 0x63, 0x6f, 0x6e, 0x74, 0x72, 0x6f, 0x6c, 0x6c, 0x65, 0x72, 0x00, 0x70,
+ 0x68, 0x61, 0x6e, 0x64, 0x6c, 0x65, 0x00, 0x73, 0x74, 0x61, 0x74, 0x75,
+ 0x73, 0x00, 0x69, 0x6e, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70, 0x74, 0x2d,
+ 0x70, 0x61, 0x72, 0x65, 0x6e, 0x74, 0x00, 0x69, 0x6e, 0x74, 0x65, 0x72,
+ 0x72, 0x75, 0x70, 0x74, 0x73, 0x00, 0x70, 0x68, 0x79, 0x2d, 0x6d, 0x6f,
+ 0x64, 0x65, 0x00, 0x63, 0x6c, 0x6f, 0x63, 0x6b, 0x2d, 0x66, 0x72, 0x65,
+ 0x71, 0x75, 0x65, 0x6e, 0x63, 0x79, 0x00, 0x63, 0x75, 0x72, 0x72, 0x65,
+ 0x6e, 0x74, 0x2d, 0x73, 0x70, 0x65, 0x65, 0x64, 0x00, 0x64, 0x65, 0x76,
+ 0x69, 0x63, 0x65, 0x5f, 0x74, 0x79, 0x70, 0x65, 0x00, 0x72, 0x65, 0x67,
+ 0x2d, 0x6f, 0x66, 0x66, 0x73, 0x65, 0x74, 0x00, 0x72, 0x65, 0x67, 0x2d,
+ 0x73, 0x68, 0x69, 0x66, 0x74, 0x00, 0x6d, 0x67, 0x6d, 0x74, 0x70, 0x6f,
+ 0x72, 0x74, 0x00
+};
+unsigned int zynqmp_dtb_len = 1443;
diff --git a/bsps/aarch64/xilinx-zynqmp/fdt/zynqmp.dts b/bsps/aarch64/xilinx-zynqmp/fdt/zynqmp.dts
new file mode 100644
index 0000000000..65c7dcbba8
--- /dev/null
+++ b/bsps/aarch64/xilinx-zynqmp/fdt/zynqmp.dts
@@ -0,0 +1,94 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSBSPsAArch64XilinxZynqMP
+ *
+ * @brief This file provides the base ZynqMP device tree
+ */
+
+/*
+ * Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
+ * Written by Kinsey Moore <kinsey.moore@oarcorp.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+/ {
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+
+ amba {
+ compatible = "simple-bus";
+ #address-cells = <0x02>;
+ #size-cells = <0x02>;
+ ranges;
+
+ interrupt-controller@f9010000 {
+ compatible = "arm,gic-400";
+ #address-cells = <0x02>;
+ #interrupt-cells = <0x03>;
+ reg = <0x00 0xf9010000 0x00 0x10000>;
+ interrupt-controller;
+ phandle = <0x01>;
+ };
+
+ ethernet@ff0b0000 {
+ compatible = "cdns,gem";
+ status = "okay";
+ interrupt-parent = <0x01>;
+ interrupts = <0x00 0x39 0x04>;
+ reg = <0x00 0xff0b0000 0x00 0x1000>;
+ phy-mode = "sgmii";
+ };
+
+ ethernet@ff0c0000 {
+ compatible = "cdns,gem";
+ status = "okay";
+ interrupt-parent = <0x01>;
+ interrupts = <0x00 0x3b 0x04>;
+ reg = <0x00 0xff0c0000 0x00 0x1000>;
+ phy-mode = "sgmii";
+ };
+
+ ethernet@ff0d0000 {
+ compatible = "cdns,gem";
+ status = "okay";
+ interrupt-parent = <0x01>;
+ interrupts = <0x00 0x3d 0x04>;
+ reg = <0x00 0xff0d0000 0x00 0x1000>;
+ phy-mode = "sgmii";
+ };
+
+ ethernet@ff0e0000 {
+ compatible = "cdns,gem";
+ status = "okay";
+ interrupt-parent = <0x01>;
+ interrupts = <0x00 0x3f 0x04>;
+ reg = <0x00 0xff0e0000 0x00 0x1000>;
+ phy-mode = "sgmii";
+ };
+ };
+};
diff --git a/bsps/aarch64/xilinx-zynqmp/fdt/zynqmp_dtb.c b/bsps/aarch64/xilinx-zynqmp/fdt/zynqmp_dtb.c
new file mode 100644
index 0000000000..955bc5f154
--- /dev/null
+++ b/bsps/aarch64/xilinx-zynqmp/fdt/zynqmp_dtb.c
@@ -0,0 +1,97 @@
+unsigned char zynqmp_dtb[] = {
+ 0xd0, 0x0d, 0xfe, 0xed, 0x00, 0x00, 0x04, 0x5f, 0x00, 0x00, 0x00, 0x38,
+ 0x00, 0x00, 0x03, 0xd4, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x11,
+ 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8b,
+ 0x00, 0x00, 0x03, 0x9c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x02,
+ 0x00, 0x00, 0x00, 0x01, 0x61, 0x6d, 0x62, 0x61, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00, 0x1b,
+ 0x73, 0x69, 0x6d, 0x70, 0x6c, 0x65, 0x2d, 0x62, 0x75, 0x73, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
+ 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x26, 0x00, 0x00, 0x00, 0x01,
+ 0x69, 0x6e, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70, 0x74, 0x2d, 0x63, 0x6f,
+ 0x6e, 0x74, 0x72, 0x6f, 0x6c, 0x6c, 0x65, 0x72, 0x40, 0x66, 0x39, 0x30,
+ 0x31, 0x30, 0x30, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x1b, 0x61, 0x72, 0x6d, 0x2c,
+ 0x67, 0x69, 0x63, 0x2d, 0x34, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x2d,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x10,
+ 0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00, 0xf9, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x42, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x57, 0x00, 0x00, 0x00, 0x01,
+ 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x65, 0x74, 0x68, 0x65,
+ 0x72, 0x6e, 0x65, 0x74, 0x40, 0x66, 0x66, 0x30, 0x62, 0x30, 0x30, 0x30,
+ 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x09,
+ 0x00, 0x00, 0x00, 0x1b, 0x63, 0x64, 0x6e, 0x73, 0x2c, 0x67, 0x65, 0x6d,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x05,
+ 0x00, 0x00, 0x00, 0x5f, 0x6f, 0x6b, 0x61, 0x79, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x66,
+ 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0c,
+ 0x00, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x39,
+ 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x10,
+ 0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00, 0xff, 0x0b, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x82, 0x73, 0x67, 0x6d, 0x69,
+ 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01,
+ 0x65, 0x74, 0x68, 0x65, 0x72, 0x6e, 0x65, 0x74, 0x40, 0x66, 0x66, 0x30,
+ 0x63, 0x30, 0x30, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x1b, 0x63, 0x64, 0x6e, 0x73,
+ 0x2c, 0x67, 0x65, 0x6d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x5f, 0x6f, 0x6b, 0x61, 0x79,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
+ 0x00, 0x00, 0x00, 0x66, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x3b, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00,
+ 0xff, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x82,
+ 0x73, 0x67, 0x6d, 0x69, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
+ 0x00, 0x00, 0x00, 0x01, 0x65, 0x74, 0x68, 0x65, 0x72, 0x6e, 0x65, 0x74,
+ 0x40, 0x66, 0x66, 0x30, 0x64, 0x30, 0x30, 0x30, 0x30, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x1b,
+ 0x63, 0x64, 0x6e, 0x73, 0x2c, 0x67, 0x65, 0x6d, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x5f,
+ 0x6f, 0x6b, 0x61, 0x79, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x66, 0x00, 0x00, 0x00, 0x01,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x77,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3d, 0x00, 0x00, 0x00, 0x04,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x3e,
+ 0x00, 0x00, 0x00, 0x00, 0xff, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x06,
+ 0x00, 0x00, 0x00, 0x82, 0x73, 0x67, 0x6d, 0x69, 0x69, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x65, 0x74, 0x68, 0x65,
+ 0x72, 0x6e, 0x65, 0x74, 0x40, 0x66, 0x66, 0x30, 0x65, 0x30, 0x30, 0x30,
+ 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x09,
+ 0x00, 0x00, 0x00, 0x1b, 0x63, 0x64, 0x6e, 0x73, 0x2c, 0x67, 0x65, 0x6d,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x05,
+ 0x00, 0x00, 0x00, 0x5f, 0x6f, 0x6b, 0x61, 0x79, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x66,
+ 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0c,
+ 0x00, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f,
+ 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x10,
+ 0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x00, 0xff, 0x0e, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x03,
+ 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x82, 0x73, 0x67, 0x6d, 0x69,
+ 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02,
+ 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x09, 0x23, 0x61, 0x64, 0x64,
+ 0x72, 0x65, 0x73, 0x73, 0x2d, 0x63, 0x65, 0x6c, 0x6c, 0x73, 0x00, 0x23,
+ 0x73, 0x69, 0x7a, 0x65, 0x2d, 0x63, 0x65, 0x6c, 0x6c, 0x73, 0x00, 0x63,
+ 0x6f, 0x6d, 0x70, 0x61, 0x74, 0x69, 0x62, 0x6c, 0x65, 0x00, 0x72, 0x61,
+ 0x6e, 0x67, 0x65, 0x73, 0x00, 0x23, 0x69, 0x6e, 0x74, 0x65, 0x72, 0x72,
+ 0x75, 0x70, 0x74, 0x2d, 0x63, 0x65, 0x6c, 0x6c, 0x73, 0x00, 0x72, 0x65,
+ 0x67, 0x00, 0x69, 0x6e, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70, 0x74, 0x2d,
+ 0x63, 0x6f, 0x6e, 0x74, 0x72, 0x6f, 0x6c, 0x6c, 0x65, 0x72, 0x00, 0x70,
+ 0x68, 0x61, 0x6e, 0x64, 0x6c, 0x65, 0x00, 0x73, 0x74, 0x61, 0x74, 0x75,
+ 0x73, 0x00, 0x69, 0x6e, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70, 0x74, 0x2d,
+ 0x70, 0x61, 0x72, 0x65, 0x6e, 0x74, 0x00, 0x69, 0x6e, 0x74, 0x65, 0x72,
+ 0x72, 0x75, 0x70, 0x74, 0x73, 0x00, 0x70, 0x68, 0x79, 0x2d, 0x6d, 0x6f,
+ 0x64, 0x65, 0x00
+};
+unsigned int zynqmp_dtb_len = 1119;
diff --git a/bsps/aarch64/xilinx-zynqmp/include/bsp.h b/bsps/aarch64/xilinx-zynqmp/include/bsp.h
index d937a313f2..bb7df94fd1 100644
--- a/bsps/aarch64/xilinx-zynqmp/include/bsp.h
+++ b/bsps/aarch64/xilinx-zynqmp/include/bsp.h
@@ -51,6 +51,7 @@
#include <bsp/start.h>
#include <rtems.h>
+#include <rtems/termiostypes.h>
#ifdef __cplusplus
extern "C" {
@@ -62,6 +63,10 @@ extern "C" {
#define BSP_RESET_SMC
#define BSP_CPU_ON_USES_SMC
+#define BSP_FDT_IS_SUPPORTED
+extern unsigned int zynqmp_dtb_len;
+extern unsigned char zynqmp_dtb[];
+
/**
* @brief Zynq UltraScale+ MPSoC specific set up of the MMU.
*
@@ -83,6 +88,16 @@ uint32_t zynqmp_clock_i2c0(void);
uint32_t zynqmp_clock_i2c1(void);
+/**
+ * @brief Zynq UltraScale+ MPSoC specific set up of a management console.
+ *
+ * Some systems may have a management interface which needs special
+ * initialization. Provide in the application to override the defaults in the
+ * BSP. This will only be called if the interface is found in the device tree.
+ */
+__attribute__ ((weak))
+void zynqmp_configure_management_console(rtems_termios_device_context *base);
+
#ifdef __cplusplus
}
#endif /* __cplusplus */
diff --git a/bsps/aarch64/xilinx-zynqmp/start/bspstartmmu.c b/bsps/aarch64/xilinx-zynqmp/start/bspstartmmu.c
index 33ca1eafab..e727f9b1de 100644
--- a/bsps/aarch64/xilinx-zynqmp/start/bspstartmmu.c
+++ b/bsps/aarch64/xilinx-zynqmp/start/bspstartmmu.c
@@ -50,6 +50,10 @@ zynqmp_mmu_config_table[] = {
.begin = 0xfd000000U,
.end = 0xffc00000U,
.flags = AARCH64_MMU_DEVICE
+ }, {
+ .begin = 0x80000000U,
+ .end = 0x80100000U,
+ .flags = 0
}
};
diff --git a/bsps/arm/beagle/dcan/am335x-dcan.c b/bsps/arm/beagle/dcan/am335x-dcan.c
new file mode 100644
index 0000000000..f4bb717e1d
--- /dev/null
+++ b/bsps/arm/beagle/dcan/am335x-dcan.c
@@ -0,0 +1,104 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup CANBus
+ *
+ * @brief Controller Area Network (CAN) Bus Implementation
+ *
+ */
+
+/*
+ * Copyright (C) 2022 Prashanth S (fishesprashanth@gmail.com)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <dev/can/can.h>
+
+#include <bsp/am335x_dcan.h>
+#include <bsp/soc_AM335x.h>
+
+#define IF_NAME_SIZE_MAX (12)
+
+void beagle_can_init(void *node)
+{
+ /* FIXME: Remove this method, Check if the device node belongs to CAN
+ * Will be removed once device tree support is added
+ */
+ static int init = 0;
+
+ if (init != 0) {
+ return;
+ }
+
+ init = 1;
+
+ CAN_DEBUG("beagle_can_init\n");
+
+ char if_name[IF_NAME_SIZE_MAX];
+
+ struct am335x_dcan_priv *priv = NULL;
+
+ /* FIXME: Get hardware specific information from device tree */
+ struct am335x_dcan_irq dcan_irq_nums[2] = {{52, 53, 54}, {55, 56, 57}};
+ uint32_t dcan_base_reg_addr[] = {SOC_DCAN_0_REGS, SOC_DCAN_1_REGS};
+
+ for (int i = 0; i < CAN_NODES; i++) {
+ priv = (struct am335x_dcan_priv *)calloc(1, sizeof(struct am335x_dcan_priv));
+
+ if (priv == NULL) {
+ CAN_ERR("beagle_can_init: calloc failed: cannot allocate memory\n");
+ return;
+ }
+
+ /* FIXME: Get hardware specific information from device tree */
+ priv->node = i;
+ priv->base_reg = dcan_base_reg_addr[i];
+ priv->irq = dcan_irq_nums[i];
+ priv->baudrate = 1000000;
+
+ if (dcan_init(priv) < 0) {
+ CAN_ERR("beagle_can_init: CAN controller %d initialization failed\n", priv->node);
+ free(priv);
+ continue;
+ }
+
+ struct can_bus *bus = can_bus_alloc_and_init(sizeof(struct can_bus));
+
+ priv->bus = bus;
+
+ snprintf(if_name, IF_NAME_SIZE_MAX, "/dev/can%d", i);
+
+ bus->priv = priv;
+ dcan_init_ops(priv);
+
+ if (can_bus_register(bus, if_name) != 0) {
+ CAN_ERR("beagle_can_init: bus register failed\n");
+ free(priv);
+ return;
+ }
+
+ CAN_DEBUG("beagle_can_init: can_bus_registered %s\n", if_name);
+ }
+}
diff --git a/bsps/arm/beagle/dcan/dcan.c b/bsps/arm/beagle/dcan/dcan.c
new file mode 100644
index 0000000000..9fee40a340
--- /dev/null
+++ b/bsps/arm/beagle/dcan/dcan.c
@@ -0,0 +1,646 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup CANBus
+ *
+ * @brief Controller Area Network (DCAN) Controller Implementation
+ *
+ */
+
+/*
+ * Copyright (C) 2022 Prashanth S (fishesprashanth@gmail.com)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <bsp.h>
+#include <bsp/am335x_dcan.h>
+#include <bsp/soc_AM335x.h>
+#include <bsp/hw_control_AM335x.h>
+
+#include <bsp/irq.h>
+#include <bsp/irq-generic.h>
+
+#include <dev/can/can.h>
+
+#include "hw_dcan.h"
+#include "hw_cm_per.h"
+
+/*
+ * Pin configurations.
+ */
+#define AM335x_PIN_IN_OFFSET (0x138)
+#define AM335x_PIN_SLEW_FAST (0 << 6)
+#define AM335x_PIN_SLEW_SLOW (1 << 6)
+#define AM335x_PIN_RX_DISABLE (0 << 5)
+#define AM335x_PIN_RX_ENABLE (1 << 5)
+#define AM335x_PIN_PULL_DIS (1 << 3)
+#define AM335x_PIN_PULL_EN (0 << 3)
+#define AM335x_PIN_PULL_UP ((1 << 4) | AM335x_PIN_PULL_EN)
+#define AM335x_PIN_PULL_DOWN ((0 << 4) | AM335x_PIN_PULL_EN)
+
+#define AM335x_PIN_MODE_0 (0)
+#define AM335x_PIN_MODE_1 (1)
+#define AM335x_PIN_MODE_2 (2)
+
+static int dcan_tx(void *, struct can_msg *);
+static bool dcan_tx_ready(void *);
+static void dcan_int_enable(struct am335x_dcan_priv *);
+static void dcan_int_disable(struct am335x_dcan_priv *);
+static void dcan_reset(struct am335x_dcan_priv *priv);
+static void dcan_clk_config(uint32_t node);
+static void dcan_isr(void *data);
+static void dcan_int(void *, bool);
+static int dcan_intr_init(struct am335x_dcan_priv *priv);
+static void dcan_inval_obj(struct am335x_dcan_priv *priv, uint32_t index);
+static void dcan_init_rxobj(struct am335x_dcan_priv *priv);
+static void dcan_save_msg(struct am335x_dcan_priv *priv, struct can_msg *msg);
+static void dcan_read_obj(struct am335x_dcan_priv *priv, uint32_t index);
+static void dcan_bittiming(struct am335x_dcan_priv *priv);
+static void am335x_dcan_pinmux(uint32_t index);
+
+/* FIXME: Should be moved to shared beagle */
+uint32_t am335x_get_sysclk(void);
+
+static struct can_dev_ops dev_ops = {
+ .dev_tx = dcan_tx,
+ .dev_tx_ready = dcan_tx_ready,
+ .dev_int = dcan_int,
+};
+
+void dcan_init_ops(struct am335x_dcan_priv *priv)
+{
+ CAN_DEBUG("dcan_init_ops\n");
+ priv->bus->can_dev_ops = &dev_ops;
+}
+
+/**
+ * @brief Convert Data Length Code (CAN specific) to length
+ * of the CAN message.
+ *
+ * @param[in] Data Length Code for the CAN message.
+ *
+ * @retval Corresponding length for the DLC.
+ */
+static uint16_t can_dlc_to_len(uint16_t dlc)
+{
+ if (dlc > 8) {
+ switch(dlc) {
+ case 9:
+ dlc = 12;
+ case 10:
+ dlc = 16;
+ case 11:
+ dlc = 20;
+ case 12:
+ dlc = 24;
+ case 13:
+ dlc = 32;
+ case 14:
+ dlc = 48;
+ default:
+ dlc = 64;
+ }
+ }
+ return dlc;
+}
+
+/**
+ * @brief Convert Length to Data Length Code (CAN specific).
+ *
+ * @param[in] Length of the CAN message.
+ *
+ * @retval Corresponding DLC for the length.
+ */
+static uint16_t can_len_to_dlc(uint16_t len)
+{
+ if (len > 8) {
+ switch(len) {
+ case 12:
+ len = 9;
+ case 16:
+ len = 10;
+ case 20:
+ len = 11;
+ case 24:
+ len = 12;
+ case 32:
+ len = 13;
+ case 48:
+ len = 14;
+ default:
+ len = 64;
+ }
+ }
+ return len;
+}
+
+/* FIXME: Make DCAN_TXRQ dynamic */
+static bool dcan_tx_ready(void *data)
+{
+ struct am335x_dcan_priv *priv = (struct am335x_dcan_priv *)data;
+
+ CAN_DEBUG("dcan_tx_ready %08x = %08x\n", priv->base_reg + DCAN_TXRQ(1),
+ can_getreg(priv, DCAN_TXRQ(1)));
+
+ if (can_getreg(priv, DCAN_TXRQ(1)) == 0xffffffff)
+ {
+ return false;
+ }
+
+ return true;
+}
+
+static void dcan_inval_obj(struct am335x_dcan_priv *priv, uint32_t index)
+{
+ while (can_getreg(priv, DCAN_IFCMD(2)) & DCAN_IFCMD_BUSY) {
+ /* busy wait */
+ }
+
+ can_putreg(priv, DCAN_IFARB(2), 0);
+
+ /* Disable rx and tx interrupts, clear transmit request */
+
+ can_putreg(priv, DCAN_IFMCTL(2), DCAN_IFMCTL_EOB & (~DCAN_IFMCTL_INTPND));
+ can_putreg(priv, DCAN_IFCMD(2), DCAN_IFCMD_WR_RD |
+ DCAN_IFCMD_CLRINTPND | DCAN_IFCMD_CONTROL | DCAN_IFCMD_ARB |
+ DCAN_IFCMD_MSG_NUM(index));
+}
+
+static void dcan_init_rxobj(struct am335x_dcan_priv *priv)
+{
+ while (can_getreg(priv, DCAN_IFCMD(2)) & DCAN_IFCMD_BUSY) {
+ /* busy wait */
+ }
+
+ can_putreg(priv, DCAN_IFMSK(2), DCAN_IFMSK_MXTD | DCAN_IFMSK_MDIR);
+ can_putreg(priv, DCAN_IFMCTL(2), DCAN_IFMCTL_DATALENGTHCODE |
+ DCAN_IFMCTL_EOB | DCAN_IFMCTL_RXIE | DCAN_IFMCTL_UMASK);
+
+#ifdef CONFIG_CAN_EXTID
+ can_putreg(priv, DCAN_IFARB(2),
+ DCAN_IFARB_MSGVAL | DCAN_IFARB_XTD);
+#else
+ can_putreg(priv, DCAN_IFARB(2), DCAN_IFARB_MSGVAL);
+#endif
+
+ for (int i = CAN_RX_MSG_OBJ_START_NUM; i <= CAN_RX_MSG_OBJ_END_NUM; i++)
+ {
+ while (can_getreg(priv, DCAN_IFCMD(2)) & DCAN_IFCMD_BUSY) {
+ /* busy wait */
+ }
+ can_putreg(priv, DCAN_IFCMD(2),
+ DCAN_IFCMD_WR_RD | DCAN_IFCMD_MASK |
+ DCAN_IFCMD_ARB | DCAN_IFCMD_CONTROL |
+ DCAN_IFCMD_CLRINTPND |
+ DCAN_IFCMD_DATAA | DCAN_IFCMD_DATAB |
+ DCAN_IFCMD_MSG_NUM(i));
+ }
+}
+
+static void dcan_save_msg(struct am335x_dcan_priv *priv, struct can_msg *msg)
+{
+ uint32_t regval;
+
+ regval = can_getreg(priv, DCAN_IFARB(2));
+ CAN_DEBUG("IFARB = %08X\n", regval);
+
+ /* FIXME: Add extid support in ifdefs */
+ msg->id = (regval >> 18) & DCAN_IFARB_MSK;
+
+ /* FIXME: This is to handle RTR feature not implemented yet */
+ /* msg->rtr = ((regval & DCAN_IFARB_DIR) != 0); */
+
+#ifdef CONFIG_CAN_EXTID
+ msg->flags |= ((regval & DCAN_IFARB_XTD) != 0) ? DCAN_XTD : 0;
+#endif
+
+ regval = can_getreg(priv, DCAN_IFMCTL(2));
+ msg->len = can_dlc_to_len((regval >> DCAN_IFMCTL_DATALENGTHCODE_SHIFT) & DCAN_IFMCTL_DATALENGTHCODE);
+
+ ((uint32_t *)msg->data)[0] = can_getreg(priv, DCAN_IFDATA(2));
+ ((uint32_t *)msg->data)[1] = can_getreg(priv, DCAN_IFDATB(2));
+}
+
+static void dcan_read_obj(struct am335x_dcan_priv *priv, uint32_t index)
+{
+ while (can_getreg(priv, DCAN_IFCMD(2)) & DCAN_IFCMD_BUSY) {
+ /* busy wait */
+ }
+
+ can_putreg(priv, DCAN_IFCMD(2),
+ DCAN_IFCMD_MASK | DCAN_IFCMD_ARB |
+ DCAN_IFCMD_CONTROL | DCAN_IFCMD_CLRINTPND | DCAN_IFCMD_DATAA |
+ DCAN_IFCMD_DATAB | DCAN_IFCMD_MSG_NUM(index));
+}
+
+static void dcan_isr(void *data)
+{
+ struct am335x_dcan_priv *priv = data;
+ CAN_DEBUG(">>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> dcan_isr entry node = %d\n", priv->node);
+
+ uint32_t interrupt = can_getreg(priv, DCAN_INT) & DCAN_INT_INT0ID;
+ uint32_t stat = can_getreg(priv, DCAN_ES);
+ uint32_t regval;
+
+ CAN_DEBUG("DCAN_INT = %08x DCAN_ES = %08x\n", interrupt, stat);
+
+ if (interrupt & 0x8000) {
+ /* Clear all warning/error states except RXOK/TXOK */
+
+ regval = can_getreg(priv, DCAN_ES);
+ regval &= DCAN_ES_RXOK | DCAN_ES_TXOK;
+ can_putreg(priv, DCAN_ES, regval);
+
+ if (stat & (DCAN_ES_BOFF | DCAN_ES_EPASS | DCAN_ES_EWARN)) {
+ CAN_ERR("CAN: dcan_isr: Error state\n");
+ REG(priv->base_reg + DCAN_CTL) |= (DCAN_CTL_ABO);
+ dcan_reset(priv);
+ }
+ }
+
+ do {
+ if (interrupt != 0 && (interrupt & 0x8000) == 0) {
+ uint32_t msgindex = interrupt & 0x7fff;
+ CAN_DEBUG("msgindex %d\n", msgindex);
+
+ /* if no error detected */
+
+ if (((stat & DCAN_ES_LEC) == 0) ||
+ ((stat & DCAN_ES_LEC) == DCAN_ES_LEC)) {
+ if (msgindex <= CAN_RX_MSG_OBJ_END_NUM) {
+ CAN_DEBUG("rx interrupt msgobj = %u\n", msgindex);
+ struct can_msg msg;
+
+ regval = can_getreg(priv, DCAN_ES);
+ regval &= ~DCAN_ES_RXOK;
+ can_putreg(priv, DCAN_ES, regval);
+
+ dcan_read_obj(priv, msgindex);
+ dcan_save_msg(priv, &msg);
+#ifdef CAN_DEBUG_ISR
+ can_print_msg(&msg);
+#endif /* CAN_DEBUG_ISR */
+ dcan_inval_obj(priv, msgindex);
+
+ can_receive(priv->bus, &msg);
+ } else {
+ CAN_DEBUG("tx interrupt msgobj = %u\n", msgindex);
+
+ regval = can_getreg(priv, DCAN_ES);
+ regval &= ~DCAN_ES_TXOK;
+ can_putreg(priv, DCAN_ES, regval);
+
+ dcan_inval_obj(priv, msgindex);
+ }
+ } else {
+ dcan_inval_obj(priv, msgindex);
+ }
+
+ can_putreg(priv, DCAN_ES, 0);
+
+ if (msgindex == CAN_RX_MSG_OBJ_END_NUM) {
+ dcan_init_rxobj(priv);
+ }
+ }
+
+ interrupt = can_getreg(priv, DCAN_INT);
+ CAN_DEBUG("DCAN_INT = %08x\n", interrupt);
+ } while (interrupt != 0);
+
+ can_tx_done(priv->bus);
+
+ CAN_DEBUG(">>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> dcan_isr exit\n");
+}
+
+static void dcan_int_enable(struct am335x_dcan_priv *priv)
+{
+ CAN_DEBUG("dcan_int_enable\n");
+ bsp_interrupt_vector_enable(priv->irq.dcan_intr0);
+ bsp_interrupt_vector_enable(priv->irq.dcan_intr1);
+ bsp_interrupt_vector_enable(priv->irq.dcan_parity);
+
+ REG(priv->base_reg + DCAN_CTL) |= DCAN_CTL_EIE | DCAN_CTL_SIE;
+ REG(priv->base_reg + DCAN_CTL) |= DCAN_CTL_IE1 | DCAN_CTL_IE0;
+
+ CAN_DEBUG("DCAN_CTL = 0x%08X\n", can_getreg(priv, DCAN_CTL));
+}
+
+static void dcan_int_disable(struct am335x_dcan_priv *priv)
+{
+ CAN_DEBUG("dcan_int_disable\n");
+ bsp_interrupt_vector_disable(priv->irq.dcan_intr0);
+ bsp_interrupt_vector_disable(priv->irq.dcan_intr1);
+ bsp_interrupt_vector_disable(priv->irq.dcan_parity);
+
+ REG(priv->base_reg + DCAN_CTL) &= (~(DCAN_CTL_EIE | DCAN_CTL_SIE));
+ REG(priv->base_reg + DCAN_CTL) &= (~(DCAN_CTL_IE1 | DCAN_CTL_IE0));
+
+ CAN_DEBUG("DCAN_CTL = 0x%08X\n", can_getreg(priv, DCAN_CTL));
+}
+
+static void dcan_int(void *data, bool flag)
+{
+ if (flag == true) {
+ dcan_int_enable(data);
+ } else {
+ dcan_int_disable(data);
+ }
+}
+
+static int dcan_tx(void *data, struct can_msg *msg)
+{
+ uint32_t regval;
+ uint32_t num;
+ uint32_t id;
+ uint32_t dlc;
+ uint8_t txobj;
+
+ struct am335x_dcan_priv *priv = (struct am335x_dcan_priv *)data;
+
+ CAN_DEBUG("dcan_tx Entry\n");
+
+ regval = can_getreg(priv, DCAN_TXRQ(1));
+ CAN_DEBUG("DCAN_TXRQ = 0x%08X\n", regval);
+
+ for (num = 0; num < 32; num++) {
+ if ((regval & (1 << num)) == 0) {
+ break;
+ }
+ }
+
+ if (num == 32) {
+ return RTEMS_NO_MEMORY;
+ }
+
+ txobj = CAN_TX_MSG_OBJ_START_NUM + num;
+ if (txobj > CAN_TX_MSG_OBJ_END_NUM) {
+ CAN_DEBUG("dcan_tx Calculated txobj num exceeds the CAN_TX_MSG_OBJ_END_NUM\n")
+ return RTEMS_INTERNAL_ERROR;
+ }
+ CAN_DEBUG("msgobj num = %u\n", txobj);
+
+ id = msg->id;
+ dlc = can_len_to_dlc(msg->len);
+
+ CAN_DEBUG("CAN-%d ID: %d LEN: %d\n",
+ priv->node, msg->id, msg->len);
+
+ /* FIXME: Add support for EXT ID */
+ can_putreg(priv, DCAN_IFMSK(1), 0xffff);
+
+ regval = ((dlc & DCAN_IFMCTL_DATALENGTHCODE) |
+ DCAN_IFMCTL_EOB | DCAN_IFMCTL_TXRQST |
+ DCAN_IFMCTL_TXIE);
+ can_putreg(priv, DCAN_IFMCTL(1), regval);
+
+ /* Write data to IF1 data registers */
+ regval = msg->data[0] + (msg->data[1] << 8) +
+ (msg->data[2] << 16) + (msg->data[3] << 24);
+ can_putreg(priv, DCAN_IFDATA(1), regval);
+
+ regval = msg->data[4] + (msg->data[5] << 8) +
+ (msg->data[6] << 16) + (msg->data[7] << 24);
+ can_putreg(priv, DCAN_IFDATB(1), regval);
+
+#ifdef CONFIG_CAN_EXTID
+ can_putreg(priv,
+ DCAN_IFARB(1),
+ DCAN_IFARB_DIR | DCAN_IFARB_MSGVAL |
+ DCAN_IFARB_XTD | (id << DCAN_IFARB_MSK_SHIFT));
+#else
+ can_putreg(priv,
+ DCAN_IFARB(1),
+ DCAN_IFARB_DIR | DCAN_IFARB_MSGVAL |
+ (id << 18));
+#endif
+
+ /* Write to Message RAM */
+ regval = (DCAN_IFCMD_WR_RD | DCAN_IFCMD_MASK |
+ DCAN_IFCMD_ARB | DCAN_IFCMD_CONTROL |
+ DCAN_IFCMD_CLRINTPND | DCAN_IFCMD_TXRQST_NEWDAT |
+ DCAN_IFCMD_DATAA | DCAN_IFCMD_DATAB |
+ DCAN_IFCMD_MSG_NUM(txobj));
+ can_putreg(priv, DCAN_IFCMD(1), regval);
+
+ regval = can_getreg(priv, DCAN_TXRQ(1));
+
+ CAN_DEBUG("msgobj = %u DCAN_TXRQ(1) = 0x%08X\n", txobj, regval);
+
+ CAN_DEBUG("dcan_tx Exit\n");
+
+ return RTEMS_SUCCESSFUL;
+}
+
+static void am335x_dcan_pinmux(uint32_t index)
+{
+ CAN_DEBUG("am335x_dcan_pinmux for node = 0x%08X\n", index);
+
+ /* FIXME: Add a common way of configuring control module */
+ if (index == 1) {
+ REG(AM335X_PADCONF_BASE + AM335X_CONF_UART1_RXD) = AM335x_PIN_PULL_UP
+ | AM335x_PIN_RX_DISABLE | AM335x_PIN_MODE_2;
+ REG(AM335X_PADCONF_BASE + AM335X_CONF_UART1_TXD) = AM335x_PIN_PULL_UP
+ | AM335x_PIN_RX_ENABLE | AM335x_PIN_MODE_2;
+ } else if (index == 0) {
+ REG(AM335X_PADCONF_BASE + AM335X_CONF_UART1_CTSN) = AM335x_PIN_PULL_UP
+ | AM335x_PIN_RX_DISABLE | AM335x_PIN_MODE_2;
+ REG(AM335X_PADCONF_BASE + AM335X_CONF_UART1_RTSN) = AM335x_PIN_PULL_UP
+ | AM335x_PIN_RX_ENABLE | AM335x_PIN_MODE_2;
+ }
+}
+
+uint32_t am335x_get_sysclk(void)
+{
+ uint32_t reg_val = REG(SOC_CONTROL_REGS + CONTROL_STATUS);
+
+ switch(reg_val & CONTROL_STATUS_SYSBOOT1_MASK) {
+ case CONTROL_STATUS_SYSBOOT1_19p2MHZ:
+ return 19200000;
+ case CONTROL_STATUS_SYSBOOT1_24MHZ:
+ return 24000000;
+ case CONTROL_STATUS_SYSBOOT1_25MHZ:
+ return 25000000;
+ case CONTROL_STATUS_SYSBOOT1_26MHZ:
+ return 26000000;
+ default:
+ CAN_ERR("DCANGetSysCLK: failed\n");
+ }
+ return 0;
+}
+
+static void dcan_bittiming(struct am335x_dcan_priv *priv)
+{
+ uint32_t ts1 = CONFIG_AM335X_CAN_TSEG1;
+ uint32_t ts2 = CONFIG_AM335X_CAN_TSEG2;
+ uint32_t sjw = 1;
+ uint32_t brp = CAN_CLOCK_FREQUENCY / (priv->baudrate * CAN_BIT_QUANTA);
+
+ uint32_t regval;
+
+ CAN_DEBUG("CAN%d PCLK: %d baud: %d\n",
+ priv->node, CAN_CLOCK_FREQUENCY, priv->baudrate);
+ CAN_DEBUG("TS1: %d TS2: %d BRP: %d SJW= %d\n", ts1, ts2, brp, sjw);
+ /* Start configuring bit timing */
+
+ regval = REG(priv->base_reg + DCAN_CTL);
+ regval |= DCAN_CTL_CCE;
+ can_putreg(priv, DCAN_CTL, regval);
+
+ regval = (((brp - 1) << DCAN_BTR_BRP_SHIFT)
+ | ((ts1 - 1) << DCAN_BTR_TSEG1_SHIFT)
+ | ((ts2 - 1) << DCAN_BTR_TSEG2_SHIFT)
+ | ((sjw - 1) << DCAN_BTR_SJW_SHIFT));
+
+ CAN_DEBUG("Setting CANxBTR= 0x%08x\n", regval);
+
+ /* Set bit timing */
+ can_putreg(priv, DCAN_BTR, regval);
+
+ /* Stop configuring bit timing */
+ regval = can_getreg(priv, DCAN_CTL);
+ regval &= ~DCAN_CTL_CCE;
+ can_putreg(priv, DCAN_CTL, regval);
+}
+
+static int dcan_intr_init(struct am335x_dcan_priv *priv)
+{
+ int ret;
+
+ if ((ret = rtems_interrupt_handler_install(priv->irq.dcan_intr0, "can-intr-0",
+ RTEMS_INTERRUPT_UNIQUE, dcan_isr, (void *)priv)) != RTEMS_SUCCESSFUL) {
+ CAN_ERR("interrupt registration failed irq = %u\n", priv->irq.dcan_intr0);
+ return ret;
+ }
+
+ CAN_DEBUG("Interrupt registration successful intr 0 = %u\n", priv->irq.dcan_intr0);
+
+ if ((ret = rtems_interrupt_handler_install(priv->irq.dcan_intr1, "can-intr-1",
+ RTEMS_INTERRUPT_UNIQUE, dcan_isr, (void *)priv)) != RTEMS_SUCCESSFUL) {
+ CAN_ERR("interrupt registration failed irq = %u\n", priv->irq.dcan_intr1);
+ return ret;
+ }
+
+ CAN_DEBUG("Interrupt registration successful intr 1 = %u\n", priv->irq.dcan_intr1);
+
+ if ((ret = rtems_interrupt_handler_install(priv->irq.dcan_parity, "can-intr-parity",
+ RTEMS_INTERRUPT_UNIQUE, dcan_isr, (void *)priv)) != RTEMS_SUCCESSFUL) {
+ CAN_ERR("interrupt registration failed irq = %u\n", priv->irq.dcan_parity);
+ return ret;
+ }
+
+ CAN_DEBUG("Interrupt registration successful intr parity = %u\n", priv->irq.dcan_parity);
+
+ return ret;
+}
+
+static void dcan_clk_config(uint32_t node)
+{
+ if (node == 1) {
+ CAN_DEBUG("CLK for DCAN1\n");
+ REG(SOC_CM_PER_REGS + CM_PER_DCAN1_CLKCTRL) =
+ CM_PER_DCAN1_CLKCTRL_MODULEMODE_ENABLE;
+
+ while((REG(SOC_CM_PER_REGS + CM_PER_DCAN1_CLKCTRL) &
+ CM_PER_DCAN1_CLKCTRL_MODULEMODE) !=
+ CM_PER_DCAN1_CLKCTRL_MODULEMODE_ENABLE);
+ } else if (node == 0) {
+ CAN_DEBUG("CLK for DCAN0\n");
+ REG(SOC_CM_PER_REGS + CM_PER_DCAN0_CLKCTRL) =
+ CM_PER_DCAN0_CLKCTRL_MODULEMODE_ENABLE;
+
+ while((REG(SOC_CM_PER_REGS + CM_PER_DCAN0_CLKCTRL) &
+ CM_PER_DCAN0_CLKCTRL_MODULEMODE) !=
+ CM_PER_DCAN0_CLKCTRL_MODULEMODE_ENABLE);
+ } else {
+ CAN_ERR("dcan_clk_config: unsupported node\n");
+ }
+}
+
+int dcan_init(struct am335x_dcan_priv *priv)
+{
+ uint32_t regval;
+ int ret;
+
+ CAN_DEBUG("DCAN Node %d\n", priv->node);
+
+ dcan_clk_config(priv->node);
+
+ am335x_dcan_pinmux(priv->node);
+
+ REG(SOC_CONTROL_REGS + CONTROL_DCAN_RAMINIT) |=
+ CONTROL_DCAN_RAMINIT_DCAN1_RAMINIT_START;
+ while ((REG(SOC_CONTROL_REGS + CONTROL_DCAN_RAMINIT) &
+ CONTROL_DCAN_RAMINIT_DCAN1_RAMINIT_START) == 0);
+
+ dcan_reset(priv);
+
+ dcan_bittiming(priv);
+
+#ifdef CAN_DEBUG
+ dcan_tx_ready(priv);
+#endif /* CAN_DEBUG */
+
+ for (int i = 0; i < CAN_NUM_OF_MSG_OBJS; i++) {
+ dcan_inval_obj(priv, i);
+ }
+
+#ifdef CAN_DEBUG
+ dcan_tx_ready(priv);
+
+ /* FIXME: This is for Enabling loopback and ABO, configure it from ioctl. */
+ REG(priv->base_reg + DCAN_CTL) |= DCAN_CTL_ABO | DCAN_CTL_TEST;
+#endif /* CAN_DEBUG */
+
+ regval = can_getreg(priv, DCAN_CTL);
+ regval &= ~DCAN_CTL_INIT;
+ can_putreg(priv, DCAN_CTL, regval);
+
+ while (can_getreg(priv, DCAN_CTL) & DCAN_CTL_INIT);
+
+/* FIXME: This is for enabling Loopback, should be configured from ioctl */
+/*
+ CAN_DEBUG("Enabling Loopback\n");
+ REG(priv->base_reg + DCAN_CTL) |= DCAN_CTL_TEST;
+ REG(priv->base_reg + DCAN_TEST) |= DCAN_TEST_LBACK;
+*/
+
+ dcan_init_rxobj(priv);
+
+ if ((ret = dcan_intr_init(priv)) != RTEMS_SUCCESSFUL) {
+ return ret;
+ }
+
+ regval = can_getreg(priv, DCAN_CTL);
+ regval |= (DCAN_CTL_IE0 | DCAN_CTL_SIE | DCAN_CTL_EIE);
+ can_putreg(priv, DCAN_CTL, regval);
+
+ return ret;
+}
+
+static void dcan_reset(struct am335x_dcan_priv *priv)
+{
+ can_putreg(priv, DCAN_CTL, DCAN_CTL_INIT | DCAN_CTL_SWR);
+ while (can_getreg(priv, DCAN_CTL) & DCAN_CTL_SWR);
+}
diff --git a/bsps/arm/beagle/dcan/hw_cm_per.h b/bsps/arm/beagle/dcan/hw_cm_per.h
new file mode 100755
index 0000000000..bb23fa3d4f
--- /dev/null
+++ b/bsps/arm/beagle/dcan/hw_cm_per.h
@@ -0,0 +1,1407 @@
+
+
+/**
+ * @Component: CM
+ *
+ * @Filename: ../../CredDataBase/prcmCRED/cm_per_cred.h
+ *
+ ============================================================================ */
+/*
+* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+*/
+/*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+
+#ifndef _HW_CM_PER_H_
+#define _HW_CM_PER_H_
+
+
+/***********************************************************************\
+ * Register arrays Definition
+\***********************************************************************/
+
+
+/***********************************************************************\
+ * Bundle arrays Definition
+\***********************************************************************/
+
+
+/***********************************************************************\
+ * Bundles Definition
+\***********************************************************************/
+
+
+
+/*************************************************************************\
+ * Registers Definition
+\*************************************************************************/
+
+#define CM_PER_L4LS_CLKSTCTRL (0x0)
+#define CM_PER_L3S_CLKSTCTRL (0x4)
+#define CM_PER_L4FW_CLKSTCTRL (0x8)
+#define CM_PER_L3_CLKSTCTRL (0xc)
+#define CM_PER_CPGMAC0_CLKCTRL (0x14)
+#define CM_PER_LCDC_CLKCTRL (0x18)
+#define CM_PER_USB0_CLKCTRL (0x1c)
+#define CM_PER_MLB_CLKCTRL (0x20)
+#define CM_PER_TPTC0_CLKCTRL (0x24)
+#define CM_PER_EMIF_CLKCTRL (0x28)
+#define CM_PER_OCMCRAM_CLKCTRL (0x2c)
+#define CM_PER_GPMC_CLKCTRL (0x30)
+#define CM_PER_MCASP0_CLKCTRL (0x34)
+#define CM_PER_UART5_CLKCTRL (0x38)
+#define CM_PER_MMC0_CLKCTRL (0x3c)
+#define CM_PER_ELM_CLKCTRL (0x40)
+#define CM_PER_I2C2_CLKCTRL (0x44)
+#define CM_PER_I2C1_CLKCTRL (0x48)
+#define CM_PER_SPI0_CLKCTRL (0x4c)
+#define CM_PER_SPI1_CLKCTRL (0x50)
+#define CM_PER_L4LS_CLKCTRL (0x60)
+#define CM_PER_L4FW_CLKCTRL (0x64)
+#define CM_PER_MCASP1_CLKCTRL (0x68)
+#define CM_PER_UART1_CLKCTRL (0x6c)
+#define CM_PER_UART2_CLKCTRL (0x70)
+#define CM_PER_UART3_CLKCTRL (0x74)
+#define CM_PER_UART4_CLKCTRL (0x78)
+//#define CM_PER_TIMER7_CLKCTRL (0x7c)
+#define CM_PER_TIMER2_CLKCTRL (0x80)
+#define CM_PER_TIMER3_CLKCTRL (0x84)
+#define CM_PER_TIMER4_CLKCTRL (0x88)
+#define CM_PER_RNG_CLKCTRL (0x90)
+#define CM_PER_AES0_CLKCTRL (0x94)
+#define CM_PER_SHA0_CLKCTRL (0xa0)
+#define CM_PER_PKA_CLKCTRL (0xa4)
+#define CM_PER_GPIO6_CLKCTRL (0xa8)
+#define CM_PER_GPIO1_CLKCTRL (0xac)
+#define CM_PER_GPIO2_CLKCTRL (0xb0)
+#define CM_PER_GPIO3_CLKCTRL (0xb4)
+#define CM_PER_TPCC_CLKCTRL (0xbc)
+#define CM_PER_DCAN0_CLKCTRL (0xc0)
+#define CM_PER_DCAN1_CLKCTRL (0xc4)
+#define CM_PER_EPWMSS1_CLKCTRL (0xcc)
+#define CM_PER_EMIF_FW_CLKCTRL (0xd0)
+#define CM_PER_EPWMSS0_CLKCTRL (0xd4)
+#define CM_PER_EPWMSS2_CLKCTRL (0xd8)
+#define CM_PER_L3_INSTR_CLKCTRL (0xdc)
+#define CM_PER_L3_CLKCTRL (0xe0)
+#define CM_PER_IEEE5000_CLKCTRL (0xe4)
+#define CM_PER_ICSS_CLKCTRL (0xe8)
+#define CM_PER_TIMER5_CLKCTRL (0xec)
+#define CM_PER_TIMER6_CLKCTRL (0xf0)
+#define CM_PER_MMC1_CLKCTRL (0xf4)
+#define CM_PER_MMC2_CLKCTRL (0xf8)
+#define CM_PER_TPTC1_CLKCTRL (0xfc)
+#define CM_PER_TPTC2_CLKCTRL (0x100)
+#define CM_PER_SPINLOCK_CLKCTRL (0x10c)
+#define CM_PER_MAILBOX0_CLKCTRL (0x110)
+#define CM_PER_L4HS_CLKSTCTRL (0x11c)
+#define CM_PER_L4HS_CLKCTRL (0x120)
+#define CM_PER_MSTR_EXPS_CLKCTRL (0x124)
+#define CM_PER_SLV_EXPS_CLKCTRL (0x128)
+#define CM_PER_OCPWP_L3_CLKSTCTRL (0x12c)
+#define CM_PER_OCPWP_CLKCTRL (0x130)
+#define CM_PER_ICSS_CLKSTCTRL (0x140)
+#define CM_PER_CPSW_CLKSTCTRL (0x144)
+#define CM_PER_LCDC_CLKSTCTRL (0x148)
+#define CM_PER_CLKDIV32K_CLKCTRL (0x14c)
+#define CM_PER_CLK_24MHZ_CLKSTCTRL (0x150)
+
+/**************************************************************************\
+ * Field Definition Macros
+\**************************************************************************/
+
+/* L4LS_CLKSTCTRL */
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_CAN_CLK (0x00000800u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_CAN_CLK_SHIFT (0x0000000Bu)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_CAN_CLK_ACT (0x1u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_CAN_CLK_INACT (0x0u)
+
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO_1_GDBCLK (0x00080000u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT (0x00000013u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO_1_GDBCLK_ACT (0x1u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO_1_GDBCLK_INACT (0x0u)
+
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO_2_GDBCLK (0x00100000u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT (0x00000014u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO_2_GDBCLK_ACT (0x1u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO_2_GDBCLK_INACT (0x0u)
+
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO_3_GDBCLK (0x00200000u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT (0x00000015u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO_3_GDBCLK_ACT (0x1u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO_3_GDBCLK_INACT (0x0u)
+
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_I2C_FCLK (0x01000000u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_I2C_FCLK_SHIFT (0x00000018u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_I2C_FCLK_ACT (0x1u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_I2C_FCLK_INACT (0x0u)
+
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK (0x00000100u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK_SHIFT (0x00000008u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK_ACT (0x1u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK_INACT (0x0u)
+
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_LCDC_GCLK (0x00020000u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_LCDC_GCLK_SHIFT (0x00000011u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_LCDC_GCLK_ACT (0x1u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_LCDC_GCLK_INACT (0x0u)
+
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_SPI_GCLK (0x02000000u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_SPI_GCLK_SHIFT (0x00000019u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_SPI_GCLK_ACT (0x1u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_SPI_GCLK_INACT (0x0u)
+
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER2_GCLK (0x00004000u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER2_GCLK_SHIFT (0x0000000Eu)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER2_GCLK_ACT (0x1u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER2_GCLK_INACT (0x0u)
+
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER3_GCLK (0x00008000u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER3_GCLK_SHIFT (0x0000000Fu)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER3_GCLK_ACT (0x1u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER3_GCLK_INACT (0x0u)
+
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER4_GCLK (0x00010000u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER4_GCLK_SHIFT (0x00000010u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER4_GCLK_ACT (0x1u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER4_GCLK_INACT (0x0u)
+
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER5_GCLK (0x08000000u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER5_GCLK_SHIFT (0x0000001Bu)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER5_GCLK_ACT (0x1u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER5_GCLK_INACT (0x0u)
+
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER6_GCLK (0x10000000u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER6_GCLK_SHIFT (0x0000001Cu)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER6_GCLK_ACT (0x1u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER6_GCLK_INACT (0x0u)
+
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER7_GCLK (0x00002000u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER7_GCLK_SHIFT (0x0000000Du)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER7_GCLK_ACT (0x1u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER7_GCLK_INACT (0x0u)
+
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_UART_GFCLK (0x00000400u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_UART_GFCLK_SHIFT (0x0000000Au)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_UART_GFCLK_ACT (0x1u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_UART_GFCLK_INACT (0x0u)
+
+#define CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL (0x00000003u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SHIFT (0x00000000u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_HW_AUTO (0x3u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_NO_SLEEP (0x0u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SW_SLEEP (0x1u)
+#define CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SW_WKUP (0x2u)
+
+
+/* L3S_CLKSTCTRL */
+#define CM_PER_L3S_CLKSTCTRL_CLKACTIVITY_L3S_GCLK (0x00000008u)
+#define CM_PER_L3S_CLKSTCTRL_CLKACTIVITY_L3S_GCLK_SHIFT (0x00000003u)
+#define CM_PER_L3S_CLKSTCTRL_CLKACTIVITY_L3S_GCLK_ACT (0x1u)
+#define CM_PER_L3S_CLKSTCTRL_CLKACTIVITY_L3S_GCLK_INACT (0x0u)
+
+#define CM_PER_L3S_CLKSTCTRL_CLKTRCTRL (0x00000003u)
+#define CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SHIFT (0x00000000u)
+#define CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_HW_AUTO (0x3u)
+#define CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_NO_SLEEP (0x0u)
+#define CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SW_SLEEP (0x1u)
+#define CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SW_WKUP (0x2u)
+
+
+/* L4FW_CLKSTCTRL */
+#define CM_PER_L4FW_CLKSTCTRL_CLKACTIVITY_L4FW_GCLK (0x00000100u)
+#define CM_PER_L4FW_CLKSTCTRL_CLKACTIVITY_L4FW_GCLK_SHIFT (0x00000008u)
+#define CM_PER_L4FW_CLKSTCTRL_CLKACTIVITY_L4FW_GCLK_ACT (0x1u)
+#define CM_PER_L4FW_CLKSTCTRL_CLKACTIVITY_L4FW_GCLK_INACT (0x0u)
+
+#define CM_PER_L4FW_CLKSTCTRL_CLKTRCTRL (0x00000003u)
+#define CM_PER_L4FW_CLKSTCTRL_CLKTRCTRL_SHIFT (0x00000000u)
+#define CM_PER_L4FW_CLKSTCTRL_CLKTRCTRL_HW_AUTO (0x3u)
+#define CM_PER_L4FW_CLKSTCTRL_CLKTRCTRL_NO_SLEEP (0x0u)
+#define CM_PER_L4FW_CLKSTCTRL_CLKTRCTRL_SW_SLEEP (0x1u)
+#define CM_PER_L4FW_CLKSTCTRL_CLKTRCTRL_SW_WKUP (0x2u)
+
+
+/* L3_CLKSTCTRL */
+#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_CPTS_RFT_GCLK (0x00000040u)
+#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT (0x00000006u)
+#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_CPTS_RFT_GCLK_ACT (0x1u)
+#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_CPTS_RFT_GCLK_INACT (0x0u)
+
+#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_EMIF_GCLK (0x00000004u)
+#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_EMIF_GCLK_SHIFT (0x00000002u)
+#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_EMIF_GCLK_ACT (0x1u)
+#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_EMIF_GCLK_INACT (0x0u)
+
+#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK (0x00000010u)
+#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK_SHIFT (0x00000004u)
+#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK_ACT (0x1u)
+#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK_INACT (0x0u)
+
+#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_MCASP_GCLK (0x00000080u)
+#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_MCASP_GCLK_SHIFT (0x00000007u)
+#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_MCASP_GCLK_ACT (0x1u)
+#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_MCASP_GCLK_INACT (0x0u)
+
+#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_MMC_FCLK (0x00000008u)
+#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_MMC_FCLK_SHIFT (0x00000003u)
+#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_MMC_FCLK_ACT (0x1u)
+#define CM_PER_L3_CLKSTCTRL_CLKACTIVITY_MMC_FCLK_INACT (0x0u)
+
+#define CM_PER_L3_CLKSTCTRL_CLKTRCTRL (0x00000003u)
+#define CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SHIFT (0x00000000u)
+#define CM_PER_L3_CLKSTCTRL_CLKTRCTRL_HW_AUTO (0x3u)
+#define CM_PER_L3_CLKSTCTRL_CLKTRCTRL_NO_SLEEP (0x0u)
+#define CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SW_SLEEP (0x1u)
+#define CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP (0x2u)
+
+
+/* CPGMAC0_CLKCTRL */
+#define CM_PER_CPGMAC0_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_CPGMAC0_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_CPGMAC0_CLKCTRL_IDLEST_DISABLED (0x3u)
+#define CM_PER_CPGMAC0_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_CPGMAC0_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_CPGMAC0_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_CPGMAC0_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_CPGMAC0_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_CPGMAC0_CLKCTRL_MODULEMODE_DISABLE (0x0u)
+#define CM_PER_CPGMAC0_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_CPGMAC0_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_CPGMAC0_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+#define CM_PER_CPGMAC0_CLKCTRL_STBYST (0x00040000u)
+#define CM_PER_CPGMAC0_CLKCTRL_STBYST_SHIFT (0x00000012u)
+#define CM_PER_CPGMAC0_CLKCTRL_STBYST_FUNC (0x0u)
+#define CM_PER_CPGMAC0_CLKCTRL_STBYST_STANDBY (0x1u)
+
+
+/* LCDC_CLKCTRL */
+#define CM_PER_LCDC_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_LCDC_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_LCDC_CLKCTRL_IDLEST_DISABLE (0x3u)
+#define CM_PER_LCDC_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_LCDC_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_LCDC_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_LCDC_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_LCDC_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_LCDC_CLKCTRL_MODULEMODE_DISABLED (0x0u)
+#define CM_PER_LCDC_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_LCDC_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_LCDC_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+#define CM_PER_LCDC_CLKCTRL_STBYST (0x00040000u)
+#define CM_PER_LCDC_CLKCTRL_STBYST_SHIFT (0x00000012u)
+#define CM_PER_LCDC_CLKCTRL_STBYST_FUNC (0x0u)
+#define CM_PER_LCDC_CLKCTRL_STBYST_STANDBY (0x1u)
+
+
+/* USB0_CLKCTRL */
+#define CM_PER_USB0_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_USB0_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_USB0_CLKCTRL_IDLEST_DISABLED (0x3u)
+#define CM_PER_USB0_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_USB0_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_USB0_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_USB0_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_USB0_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_USB0_CLKCTRL_MODULEMODE_DISABLE (0x0u)
+#define CM_PER_USB0_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_USB0_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_USB0_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+#define CM_PER_USB0_CLKCTRL_STBYST (0x00040000u)
+#define CM_PER_USB0_CLKCTRL_STBYST_SHIFT (0x00000012u)
+#define CM_PER_USB0_CLKCTRL_STBYST_FUNC (0x0u)
+#define CM_PER_USB0_CLKCTRL_STBYST_STANDBY (0x1u)
+
+
+/* MLB_CLKCTRL */
+#define CM_PER_MLB_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_MLB_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_MLB_CLKCTRL_IDLEST_DISABLE (0x3u)
+#define CM_PER_MLB_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_MLB_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_MLB_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_MLB_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_MLB_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_MLB_CLKCTRL_MODULEMODE_DISABLED (0x0u)
+#define CM_PER_MLB_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_MLB_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_MLB_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+#define CM_PER_MLB_CLKCTRL_STBYST (0x00040000u)
+#define CM_PER_MLB_CLKCTRL_STBYST_SHIFT (0x00000012u)
+#define CM_PER_MLB_CLKCTRL_STBYST_FUNC (0x0u)
+#define CM_PER_MLB_CLKCTRL_STBYST_STANDBY (0x1u)
+
+
+/* TPTC0_CLKCTRL */
+#define CM_PER_TPTC0_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_TPTC0_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_TPTC0_CLKCTRL_IDLEST_DISABLED (0x3u)
+#define CM_PER_TPTC0_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_TPTC0_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_TPTC0_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_TPTC0_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_TPTC0_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_TPTC0_CLKCTRL_MODULEMODE_DISABLE (0x0u)
+#define CM_PER_TPTC0_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_TPTC0_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_TPTC0_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+#define CM_PER_TPTC0_CLKCTRL_STBYST (0x00040000u)
+#define CM_PER_TPTC0_CLKCTRL_STBYST_SHIFT (0x00000012u)
+#define CM_PER_TPTC0_CLKCTRL_STBYST_FUNC (0x0u)
+#define CM_PER_TPTC0_CLKCTRL_STBYST_STANDBY (0x1u)
+
+
+/* EMIF_CLKCTRL */
+#define CM_PER_EMIF_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_EMIF_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_EMIF_CLKCTRL_IDLEST_DISABLE (0x3u)
+#define CM_PER_EMIF_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_EMIF_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_EMIF_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_EMIF_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_EMIF_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_EMIF_CLKCTRL_MODULEMODE_DISABLED (0x0u)
+#define CM_PER_EMIF_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_EMIF_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_EMIF_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* OCMCRAM_CLKCTRL */
+#define CM_PER_OCMCRAM_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_OCMCRAM_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_OCMCRAM_CLKCTRL_IDLEST_DISABLE (0x3u)
+#define CM_PER_OCMCRAM_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_OCMCRAM_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_OCMCRAM_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_OCMCRAM_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_OCMCRAM_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_OCMCRAM_CLKCTRL_MODULEMODE_DISABLED (0x0u)
+#define CM_PER_OCMCRAM_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_OCMCRAM_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_OCMCRAM_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* GPMC_CLKCTRL */
+#define CM_PER_GPMC_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_GPMC_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_GPMC_CLKCTRL_IDLEST_DISABLED (0x3u)
+#define CM_PER_GPMC_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_GPMC_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_GPMC_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_GPMC_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_GPMC_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_GPMC_CLKCTRL_MODULEMODE_DISABLE (0x0u)
+#define CM_PER_GPMC_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_GPMC_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_GPMC_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* MCASP0_CLKCTRL */
+#define CM_PER_MCASP0_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_MCASP0_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_MCASP0_CLKCTRL_IDLEST_DISABLE (0x3u)
+#define CM_PER_MCASP0_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_MCASP0_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_MCASP0_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_MCASP0_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_MCASP0_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_MCASP0_CLKCTRL_MODULEMODE_DISABLED (0x0u)
+#define CM_PER_MCASP0_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_MCASP0_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_MCASP0_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* UART5_CLKCTRL */
+#define CM_PER_UART5_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_UART5_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_UART5_CLKCTRL_IDLEST_DISABLE (0x3u)
+#define CM_PER_UART5_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_UART5_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_UART5_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_UART5_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_UART5_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_UART5_CLKCTRL_MODULEMODE_DISABLED (0x0u)
+#define CM_PER_UART5_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_UART5_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_UART5_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* MMC0_CLKCTRL */
+#define CM_PER_MMC0_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_MMC0_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_MMC0_CLKCTRL_IDLEST_DISABLED (0x3u)
+#define CM_PER_MMC0_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_MMC0_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_MMC0_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_MMC0_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_MMC0_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_MMC0_CLKCTRL_MODULEMODE_DISABLE (0x0u)
+#define CM_PER_MMC0_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_MMC0_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_MMC0_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* ELM_CLKCTRL */
+#define CM_PER_ELM_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_ELM_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_ELM_CLKCTRL_IDLEST_DISABLE (0x3u)
+#define CM_PER_ELM_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_ELM_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_ELM_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_ELM_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_ELM_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_ELM_CLKCTRL_MODULEMODE_DISABLED (0x0u)
+#define CM_PER_ELM_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_ELM_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_ELM_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* I2C2_CLKCTRL */
+#define CM_PER_I2C2_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_I2C2_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_I2C2_CLKCTRL_IDLEST_DISABLE (0x3u)
+#define CM_PER_I2C2_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_I2C2_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_I2C2_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_I2C2_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_I2C2_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_I2C2_CLKCTRL_MODULEMODE_DISABLED (0x0u)
+#define CM_PER_I2C2_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_I2C2_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_I2C2_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* I2C1_CLKCTRL */
+#define CM_PER_I2C1_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_I2C1_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_I2C1_CLKCTRL_IDLEST_DISABLE (0x3u)
+#define CM_PER_I2C1_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_I2C1_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_I2C1_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_I2C1_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_I2C1_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_I2C1_CLKCTRL_MODULEMODE_DISABLED (0x0u)
+#define CM_PER_I2C1_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_I2C1_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_I2C1_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* SPI0_CLKCTRL */
+#define CM_PER_SPI0_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_SPI0_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_SPI0_CLKCTRL_IDLEST_DISABLE (0x3u)
+#define CM_PER_SPI0_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_SPI0_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_SPI0_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_SPI0_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_SPI0_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_SPI0_CLKCTRL_MODULEMODE_DISABLED (0x0u)
+#define CM_PER_SPI0_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_SPI0_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_SPI0_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* SPI1_CLKCTRL */
+#define CM_PER_SPI1_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_SPI1_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_SPI1_CLKCTRL_IDLEST_DISABLE (0x3u)
+#define CM_PER_SPI1_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_SPI1_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_SPI1_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_SPI1_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_SPI1_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_SPI1_CLKCTRL_MODULEMODE_DISABLED (0x0u)
+#define CM_PER_SPI1_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_SPI1_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_SPI1_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* L4LS_CLKCTRL */
+#define CM_PER_L4LS_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_L4LS_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_L4LS_CLKCTRL_IDLEST_DISABLE (0x3u)
+#define CM_PER_L4LS_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_L4LS_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_L4LS_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_L4LS_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_L4LS_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_L4LS_CLKCTRL_MODULEMODE_DISABLED (0x0u)
+#define CM_PER_L4LS_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_L4LS_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_L4LS_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* L4FW_CLKCTRL */
+#define CM_PER_L4FW_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_L4FW_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_L4FW_CLKCTRL_IDLEST_DISABLE (0x3u)
+#define CM_PER_L4FW_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_L4FW_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_L4FW_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_L4FW_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_L4FW_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_L4FW_CLKCTRL_MODULEMODE_DISABLED (0x0u)
+#define CM_PER_L4FW_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_L4FW_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_L4FW_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* MCASP1_CLKCTRL */
+#define CM_PER_MCASP1_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_MCASP1_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_MCASP1_CLKCTRL_IDLEST_DISABLE (0x3u)
+#define CM_PER_MCASP1_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_MCASP1_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_MCASP1_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_MCASP1_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_MCASP1_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_MCASP1_CLKCTRL_MODULEMODE_DISABLED (0x0u)
+#define CM_PER_MCASP1_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_MCASP1_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_MCASP1_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* UART1_CLKCTRL */
+#define CM_PER_UART1_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_UART1_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_UART1_CLKCTRL_IDLEST_DISABLE (0x3u)
+#define CM_PER_UART1_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_UART1_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_UART1_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_UART1_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_UART1_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_UART1_CLKCTRL_MODULEMODE_DISABLED (0x0u)
+#define CM_PER_UART1_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_UART1_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_UART1_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* UART2_CLKCTRL */
+#define CM_PER_UART2_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_UART2_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_UART2_CLKCTRL_IDLEST_DISABLE (0x3u)
+#define CM_PER_UART2_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_UART2_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_UART2_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_UART2_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_UART2_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_UART2_CLKCTRL_MODULEMODE_DISABLED (0x0u)
+#define CM_PER_UART2_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_UART2_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_UART2_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* UART3_CLKCTRL */
+#define CM_PER_UART3_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_UART3_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_UART3_CLKCTRL_IDLEST_DISABLE (0x3u)
+#define CM_PER_UART3_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_UART3_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_UART3_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_UART3_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_UART3_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_UART3_CLKCTRL_MODULEMODE_DISABLED (0x0u)
+#define CM_PER_UART3_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_UART3_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_UART3_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* UART4_CLKCTRL */
+#define CM_PER_UART4_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_UART4_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_UART4_CLKCTRL_IDLEST_DISABLED (0x3u)
+#define CM_PER_UART4_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_UART4_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_UART4_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_UART4_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_UART4_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_UART4_CLKCTRL_MODULEMODE_DISABLE (0x0u)
+#define CM_PER_UART4_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_UART4_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_UART4_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* TIMER7_CLKCTRL */
+#define CM_PER_TIMER7_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_TIMER7_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_TIMER7_CLKCTRL_IDLEST_DISABLED (0x3u)
+#define CM_PER_TIMER7_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_TIMER7_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_TIMER7_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_TIMER7_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_TIMER7_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_TIMER7_CLKCTRL_MODULEMODE_DISABLE (0x0u)
+#define CM_PER_TIMER7_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_TIMER7_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_TIMER7_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* TIMER2_CLKCTRL */
+#define CM_PER_TIMER2_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_TIMER2_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_TIMER2_CLKCTRL_IDLEST_DISABLDED (0x3u)
+#define CM_PER_TIMER2_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_TIMER2_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_TIMER2_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_TIMER2_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_TIMER2_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_TIMER2_CLKCTRL_MODULEMODE_DISABLE (0x0u)
+#define CM_PER_TIMER2_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_TIMER2_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_TIMER2_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* TIMER3_CLKCTRL */
+#define CM_PER_TIMER3_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_TIMER3_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_TIMER3_CLKCTRL_IDLEST_DISABLED (0x3u)
+#define CM_PER_TIMER3_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_TIMER3_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_TIMER3_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_TIMER3_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_TIMER3_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_TIMER3_CLKCTRL_MODULEMODE_DISABLE (0x0u)
+#define CM_PER_TIMER3_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_TIMER3_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_TIMER3_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* TIMER4_CLKCTRL */
+#define CM_PER_TIMER4_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_TIMER4_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_TIMER4_CLKCTRL_IDLEST_DISABLED (0x3u)
+#define CM_PER_TIMER4_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_TIMER4_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_TIMER4_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_TIMER4_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_TIMER4_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_TIMER4_CLKCTRL_MODULEMODE_DISABLE (0x0u)
+#define CM_PER_TIMER4_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_TIMER4_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_TIMER4_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* RNG_CLKCTRL */
+#define CM_PER_RNG_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_RNG_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_RNG_CLKCTRL_IDLEST_DISABLED (0x3u)
+#define CM_PER_RNG_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_RNG_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_RNG_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_RNG_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_RNG_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_RNG_CLKCTRL_MODULEMODE_DISABLE (0x0u)
+#define CM_PER_RNG_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_RNG_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_RNG_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* AES0_CLKCTRL */
+#define CM_PER_AES0_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_AES0_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_AES0_CLKCTRL_IDLEST_DISABLE (0x3u)
+#define CM_PER_AES0_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_AES0_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_AES0_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_AES0_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_AES0_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_AES0_CLKCTRL_MODULEMODE_DISABLED (0x0u)
+#define CM_PER_AES0_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_AES0_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_AES0_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* SHA0_CLKCTRL */
+#define CM_PER_SHA0_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_SHA0_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_SHA0_CLKCTRL_IDLEST_DISABLE (0x3u)
+#define CM_PER_SHA0_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_SHA0_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_SHA0_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_SHA0_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_SHA0_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_SHA0_CLKCTRL_MODULEMODE_DISABLED (0x0u)
+#define CM_PER_SHA0_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_SHA0_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_SHA0_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* PKA_CLKCTRL */
+#define CM_PER_PKA_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_PKA_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_PKA_CLKCTRL_IDLEST_DISABLE (0x3u)
+#define CM_PER_PKA_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_PKA_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_PKA_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_PKA_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_PKA_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_PKA_CLKCTRL_MODULEMODE_DISABLED (0x0u)
+#define CM_PER_PKA_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_PKA_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_PKA_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* GPIO1_CLKCTRL */
+#define CM_PER_GPIO1_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_GPIO1_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_GPIO1_CLKCTRL_IDLEST_DISABLED (0x3u)
+#define CM_PER_GPIO1_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_GPIO1_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_GPIO1_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_GPIO1_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_GPIO1_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_GPIO1_CLKCTRL_MODULEMODE_DISABLE (0x0u)
+#define CM_PER_GPIO1_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_GPIO1_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_GPIO1_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+#define CM_PER_GPIO1_CLKCTRL_OPTFCLKEN_GPIO_1_GDBCLK (0x00040000u)
+#define CM_PER_GPIO1_CLKCTRL_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT (0x00000012u)
+#define CM_PER_GPIO1_CLKCTRL_OPTFCLKEN_GPIO_1_GDBCLK_FCLK_DIS (0x0u)
+#define CM_PER_GPIO1_CLKCTRL_OPTFCLKEN_GPIO_1_GDBCLK_FCLK_EN (0x1u)
+
+
+/* GPIO2_CLKCTRL */
+#define CM_PER_GPIO2_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_GPIO2_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_GPIO2_CLKCTRL_IDLEST_DISABLE (0x3u)
+#define CM_PER_GPIO2_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_GPIO2_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_GPIO2_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_GPIO2_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_GPIO2_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_GPIO2_CLKCTRL_MODULEMODE_DISABLED (0x0u)
+#define CM_PER_GPIO2_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_GPIO2_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_GPIO2_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+#define CM_PER_GPIO2_CLKCTRL_OPTFCLKEN_GPIO_2_GDBCLK (0x00040000u)
+#define CM_PER_GPIO2_CLKCTRL_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT (0x00000012u)
+#define CM_PER_GPIO2_CLKCTRL_OPTFCLKEN_GPIO_2_GDBCLK_FCLK_DIS (0x0u)
+#define CM_PER_GPIO2_CLKCTRL_OPTFCLKEN_GPIO_2_GDBCLK_FCLK_EN (0x1u)
+
+
+/* GPIO3_CLKCTRL */
+#define CM_PER_GPIO3_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_GPIO3_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_GPIO3_CLKCTRL_IDLEST_DISABLED (0x3u)
+#define CM_PER_GPIO3_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_GPIO3_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_GPIO3_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_GPIO3_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_GPIO3_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_GPIO3_CLKCTRL_MODULEMODE_DISABLE (0x0u)
+#define CM_PER_GPIO3_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_GPIO3_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_GPIO3_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+#define CM_PER_GPIO3_CLKCTRL_OPTFCLKEN_GPIO_3_GDBCLK (0x00040000u)
+#define CM_PER_GPIO3_CLKCTRL_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT (0x00000012u)
+#define CM_PER_GPIO3_CLKCTRL_OPTFCLKEN_GPIO_3_GDBCLK_FCLK_DIS (0x0u)
+#define CM_PER_GPIO3_CLKCTRL_OPTFCLKEN_GPIO_3_GDBCLK_FCLK_EN (0x1u)
+
+
+/* TPCC_CLKCTRL */
+#define CM_PER_TPCC_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_TPCC_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_TPCC_CLKCTRL_IDLEST_DISABLED (0x3u)
+#define CM_PER_TPCC_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_TPCC_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_TPCC_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_TPCC_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_TPCC_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_TPCC_CLKCTRL_MODULEMODE_DISABLE (0x0u)
+#define CM_PER_TPCC_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_TPCC_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_TPCC_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* DCAN0_CLKCTRL */
+#define CM_PER_DCAN0_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_DCAN0_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_DCAN0_CLKCTRL_IDLEST_DISABLE (0x3u)
+#define CM_PER_DCAN0_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_DCAN0_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_DCAN0_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_DCAN0_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_DCAN0_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_DCAN0_CLKCTRL_MODULEMODE_DISABLED (0x0u)
+#define CM_PER_DCAN0_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_DCAN0_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_DCAN0_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* DCAN1_CLKCTRL */
+#define CM_PER_DCAN1_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_DCAN1_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_DCAN1_CLKCTRL_IDLEST_DISABLE (0x3u)
+#define CM_PER_DCAN1_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_DCAN1_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_DCAN1_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_DCAN1_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_DCAN1_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_DCAN1_CLKCTRL_MODULEMODE_DISABLED (0x0u)
+#define CM_PER_DCAN1_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_DCAN1_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_DCAN1_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* EPWMSS1_CLKCTRL */
+#define CM_PER_EPWMSS1_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_EPWMSS1_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_EPWMSS1_CLKCTRL_IDLEST_DISABLE (0x3u)
+#define CM_PER_EPWMSS1_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_EPWMSS1_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_EPWMSS1_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_EPWMSS1_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_EPWMSS1_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_EPWMSS1_CLKCTRL_MODULEMODE_DISABLED (0x0u)
+#define CM_PER_EPWMSS1_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_EPWMSS1_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_EPWMSS1_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* EMIF_FW_CLKCTRL */
+#define CM_PER_EMIF_FW_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_EMIF_FW_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_EMIF_FW_CLKCTRL_IDLEST_DISABLE (0x3u)
+#define CM_PER_EMIF_FW_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_EMIF_FW_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_EMIF_FW_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_EMIF_FW_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_EMIF_FW_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_EMIF_FW_CLKCTRL_MODULEMODE_DISABLED (0x0u)
+#define CM_PER_EMIF_FW_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_EMIF_FW_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_EMIF_FW_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* EPWMSS0_CLKCTRL */
+#define CM_PER_EPWMSS0_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_EPWMSS0_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_EPWMSS0_CLKCTRL_IDLEST_DISABLED (0x3u)
+#define CM_PER_EPWMSS0_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_EPWMSS0_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_EPWMSS0_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_EPWMSS0_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_EPWMSS0_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_EPWMSS0_CLKCTRL_MODULEMODE_DISABLE (0x0u)
+#define CM_PER_EPWMSS0_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_EPWMSS0_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_EPWMSS0_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* EPWMSS2_CLKCTRL */
+#define CM_PER_EPWMSS2_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_EPWMSS2_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_EPWMSS2_CLKCTRL_IDLEST_DISABLE (0x3u)
+#define CM_PER_EPWMSS2_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_EPWMSS2_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_EPWMSS2_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_EPWMSS2_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_EPWMSS2_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_EPWMSS2_CLKCTRL_MODULEMODE_DISABLED (0x0u)
+#define CM_PER_EPWMSS2_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_EPWMSS2_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_EPWMSS2_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* L3_INSTR_CLKCTRL */
+#define CM_PER_L3_INSTR_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_L3_INSTR_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_L3_INSTR_CLKCTRL_IDLEST_DISABLE (0x3u)
+#define CM_PER_L3_INSTR_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_L3_INSTR_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_L3_INSTR_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_L3_INSTR_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_DISABLED (0x0u)
+#define CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* L3_CLKCTRL */
+#define CM_PER_L3_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_L3_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_L3_CLKCTRL_IDLEST_DISABLE (0x3u)
+#define CM_PER_L3_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_L3_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_L3_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_L3_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_L3_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_L3_CLKCTRL_MODULEMODE_DISABLED (0x0u)
+#define CM_PER_L3_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_L3_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_L3_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* IEEE5000_CLKCTRL */
+#define CM_PER_IEEE5000_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_IEEE5000_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_IEEE5000_CLKCTRL_IDLEST_DISABLE (0x3u)
+#define CM_PER_IEEE5000_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_IEEE5000_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_IEEE5000_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_IEEE5000_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_IEEE5000_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_IEEE5000_CLKCTRL_MODULEMODE_DISABLED (0x0u)
+#define CM_PER_IEEE5000_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_IEEE5000_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_IEEE5000_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+#define CM_PER_IEEE5000_CLKCTRL_STBYST (0x00040000u)
+#define CM_PER_IEEE5000_CLKCTRL_STBYST_SHIFT (0x00000012u)
+#define CM_PER_IEEE5000_CLKCTRL_STBYST_FUNC (0x0u)
+#define CM_PER_IEEE5000_CLKCTRL_STBYST_STANDBY (0x1u)
+
+
+/* ICSS_CLKCTRL */
+#define CM_PER_ICSS_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_ICSS_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_ICSS_CLKCTRL_IDLEST_DISABLE (0x3u)
+#define CM_PER_ICSS_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_ICSS_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_ICSS_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_ICSS_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_ICSS_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_ICSS_CLKCTRL_MODULEMODE_DISABLED (0x0u)
+#define CM_PER_ICSS_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_ICSS_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_ICSS_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+#define CM_PER_ICSS_CLKCTRL_STBYST (0x00040000u)
+#define CM_PER_ICSS_CLKCTRL_STBYST_SHIFT (0x00000012u)
+#define CM_PER_ICSS_CLKCTRL_STBYST_FUNC (0x0u)
+#define CM_PER_ICSS_CLKCTRL_STBYST_STANDBY (0x1u)
+
+
+/* TIMER5_CLKCTRL */
+#define CM_PER_TIMER5_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_TIMER5_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_TIMER5_CLKCTRL_IDLEST_DISABLE (0x3u)
+#define CM_PER_TIMER5_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_TIMER5_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_TIMER5_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_TIMER5_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_TIMER5_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_TIMER5_CLKCTRL_MODULEMODE_DISABLED (0x0u)
+#define CM_PER_TIMER5_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_TIMER5_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_TIMER5_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* TIMER6_CLKCTRL */
+#define CM_PER_TIMER6_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_TIMER6_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_TIMER6_CLKCTRL_IDLEST_DISABLE (0x3u)
+#define CM_PER_TIMER6_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_TIMER6_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_TIMER6_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_TIMER6_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_TIMER6_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_TIMER6_CLKCTRL_MODULEMODE_DISABLED (0x0u)
+#define CM_PER_TIMER6_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_TIMER6_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_TIMER6_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* MMC1_CLKCTRL */
+#define CM_PER_MMC1_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_MMC1_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_MMC1_CLKCTRL_IDLEST_DISABLE (0x3u)
+#define CM_PER_MMC1_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_MMC1_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_MMC1_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_MMC1_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_MMC1_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_MMC1_CLKCTRL_MODULEMODE_DISABLED (0x0u)
+#define CM_PER_MMC1_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_MMC1_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_MMC1_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* MMC2_CLKCTRL */
+#define CM_PER_MMC2_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_MMC2_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_MMC2_CLKCTRL_IDLEST_DISABLE (0x3u)
+#define CM_PER_MMC2_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_MMC2_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_MMC2_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_MMC2_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_MMC2_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_MMC2_CLKCTRL_MODULEMODE_DISABLED (0x0u)
+#define CM_PER_MMC2_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_MMC2_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_MMC2_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* TPTC1_CLKCTRL */
+#define CM_PER_TPTC1_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_TPTC1_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_TPTC1_CLKCTRL_IDLEST_DISABLED (0x3u)
+#define CM_PER_TPTC1_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_TPTC1_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_TPTC1_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_TPTC1_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_TPTC1_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_TPTC1_CLKCTRL_MODULEMODE_DISABLE (0x0u)
+#define CM_PER_TPTC1_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_TPTC1_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_TPTC1_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+#define CM_PER_TPTC1_CLKCTRL_STBYST (0x00040000u)
+#define CM_PER_TPTC1_CLKCTRL_STBYST_SHIFT (0x00000012u)
+#define CM_PER_TPTC1_CLKCTRL_STBYST_FUNC (0x0u)
+#define CM_PER_TPTC1_CLKCTRL_STBYST_STANDBY (0x1u)
+
+
+/* TPTC2_CLKCTRL */
+#define CM_PER_TPTC2_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_TPTC2_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_TPTC2_CLKCTRL_IDLEST_DISABLED (0x3u)
+#define CM_PER_TPTC2_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_TPTC2_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_TPTC2_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_TPTC2_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_TPTC2_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_TPTC2_CLKCTRL_MODULEMODE_DISABLE (0x0u)
+#define CM_PER_TPTC2_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_TPTC2_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_TPTC2_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+#define CM_PER_TPTC2_CLKCTRL_STBYST (0x00040000u)
+#define CM_PER_TPTC2_CLKCTRL_STBYST_SHIFT (0x00000012u)
+#define CM_PER_TPTC2_CLKCTRL_STBYST_FUNC (0x0u)
+#define CM_PER_TPTC2_CLKCTRL_STBYST_STANDBY (0x1u)
+
+
+/* SPINLOCK_CLKCTRL */
+#define CM_PER_SPINLOCK_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_SPINLOCK_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_SPINLOCK_CLKCTRL_IDLEST_DISABLE (0x3u)
+#define CM_PER_SPINLOCK_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_SPINLOCK_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_SPINLOCK_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_SPINLOCK_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_SPINLOCK_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_SPINLOCK_CLKCTRL_MODULEMODE_DISABLED (0x0u)
+#define CM_PER_SPINLOCK_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_SPINLOCK_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_SPINLOCK_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* MAILBOX0_CLKCTRL */
+#define CM_PER_MAILBOX0_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_MAILBOX0_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_MAILBOX0_CLKCTRL_IDLEST_DISABLE (0x3u)
+#define CM_PER_MAILBOX0_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_MAILBOX0_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_MAILBOX0_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_MAILBOX0_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_MAILBOX0_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_MAILBOX0_CLKCTRL_MODULEMODE_DISABLED (0x0u)
+#define CM_PER_MAILBOX0_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_MAILBOX0_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_MAILBOX0_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* L4HS_CLKSTCTRL */
+#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_CPSW_250MHZ_GCLK (0x00000010u)
+#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT (0x00000004u)
+#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_CPSW_250MHZ_GCLK_ACT (0x1u)
+#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_CPSW_250MHZ_GCLK_INACT (0x0u)
+
+#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_CPSW_50MHZ_GCLK (0x00000020u)
+#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT (0x00000005u)
+#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_CPSW_50MHZ_GCLK_ACT (0x1u)
+#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_CPSW_50MHZ_GCLK_INACT (0x0u)
+
+#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_CPSW_5MHZ_GCLK (0x00000040u)
+#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT (0x00000006u)
+#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_CPSW_5MHZ_GCLK_ACT (0x1u)
+#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_CPSW_5MHZ_GCLK_INACT (0x0u)
+
+#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_L4HS_GCLK (0x00000008u)
+#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_L4HS_GCLK_SHIFT (0x00000003u)
+#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_L4HS_GCLK_ACT (0x1u)
+#define CM_PER_L4HS_CLKSTCTRL_CLKACTIVITY_L4HS_GCLK_INACT (0x0u)
+
+#define CM_PER_L4HS_CLKSTCTRL_CLKTRCTRL (0x00000003u)
+#define CM_PER_L4HS_CLKSTCTRL_CLKTRCTRL_SHIFT (0x00000000u)
+#define CM_PER_L4HS_CLKSTCTRL_CLKTRCTRL_HW_AUTO (0x3u)
+#define CM_PER_L4HS_CLKSTCTRL_CLKTRCTRL_NO_SLEEP (0x0u)
+#define CM_PER_L4HS_CLKSTCTRL_CLKTRCTRL_SW_SLEEP (0x1u)
+#define CM_PER_L4HS_CLKSTCTRL_CLKTRCTRL_SW_WKUP (0x2u)
+
+
+/* L4HS_CLKCTRL */
+#define CM_PER_L4HS_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_L4HS_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_L4HS_CLKCTRL_IDLEST_DISABLE (0x3u)
+#define CM_PER_L4HS_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_L4HS_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_L4HS_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_L4HS_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_L4HS_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_L4HS_CLKCTRL_MODULEMODE_DISABLED (0x0u)
+#define CM_PER_L4HS_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_L4HS_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_L4HS_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* MSTR_EXPS_CLKCTRL */
+#define CM_PER_MSTR_EXPS_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_MSTR_EXPS_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_MSTR_EXPS_CLKCTRL_IDLEST_DISABLE (0x3u)
+#define CM_PER_MSTR_EXPS_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_MSTR_EXPS_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_MSTR_EXPS_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_MSTR_EXPS_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_MSTR_EXPS_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_MSTR_EXPS_CLKCTRL_MODULEMODE_DISABLED (0x0u)
+#define CM_PER_MSTR_EXPS_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_MSTR_EXPS_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_MSTR_EXPS_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+#define CM_PER_MSTR_EXPS_CLKCTRL_STBYST (0x00040000u)
+#define CM_PER_MSTR_EXPS_CLKCTRL_STBYST_SHIFT (0x00000012u)
+#define CM_PER_MSTR_EXPS_CLKCTRL_STBYST_FUNC (0x0u)
+#define CM_PER_MSTR_EXPS_CLKCTRL_STBYST_STANDBY (0x1u)
+
+
+/* SLV_EXPS_CLKCTRL */
+#define CM_PER_SLV_EXPS_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_SLV_EXPS_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_SLV_EXPS_CLKCTRL_IDLEST_DISABLE (0x3u)
+#define CM_PER_SLV_EXPS_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_SLV_EXPS_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_SLV_EXPS_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_SLV_EXPS_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_SLV_EXPS_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_SLV_EXPS_CLKCTRL_MODULEMODE_DISABLED (0x0u)
+#define CM_PER_SLV_EXPS_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_SLV_EXPS_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_SLV_EXPS_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* OCPWP_L3_CLKSTCTRL */
+#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_GCLK (0x00000010u)
+#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT (0x00000004u)
+#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_GCLK_ACT (0x1u)
+#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_GCLK_INACT (0x0u)
+
+#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L4_GCLK (0x00000020u)
+#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT (0x00000005u)
+#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L4_GCLK_ACT (0x1u)
+#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L4_GCLK_INACT (0x0u)
+
+#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL (0x00000003u)
+#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SHIFT (0x00000000u)
+#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_HW_AUTO (0x3u)
+#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_NO_SLEEP (0x0u)
+#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_SLEEP (0x1u)
+#define CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP (0x2u)
+
+
+/* OCPWP_CLKCTRL */
+#define CM_PER_OCPWP_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_OCPWP_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_OCPWP_CLKCTRL_IDLEST_DISABLE (0x3u)
+#define CM_PER_OCPWP_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_OCPWP_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_OCPWP_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_OCPWP_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_OCPWP_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_OCPWP_CLKCTRL_MODULEMODE_DISABLED (0x0u)
+#define CM_PER_OCPWP_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_OCPWP_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_OCPWP_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+#define CM_PER_OCPWP_CLKCTRL_STBYST (0x00040000u)
+#define CM_PER_OCPWP_CLKCTRL_STBYST_SHIFT (0x00000012u)
+#define CM_PER_OCPWP_CLKCTRL_STBYST_FUNC (0x0u)
+#define CM_PER_OCPWP_CLKCTRL_STBYST_STANDBY (0x1u)
+
+
+/* ICSS_CLKSTCTRL */
+#define CM_PER_ICSS_CLKSTCTRL_CLKACTIVITY_ICSS_IEP_GCLK (0x00000020u)
+#define CM_PER_ICSS_CLKSTCTRL_CLKACTIVITY_ICSS_IEP_GCLK_SHIFT (0x00000005u)
+#define CM_PER_ICSS_CLKSTCTRL_CLKACTIVITY_ICSS_IEP_GCLK_ACT (0x1u)
+#define CM_PER_ICSS_CLKSTCTRL_CLKACTIVITY_ICSS_IEP_GCLK_INACT (0x0u)
+
+#define CM_PER_ICSS_CLKSTCTRL_CLKACTIVITY_ICSS_OCP_GCLK (0x00000010u)
+#define CM_PER_ICSS_CLKSTCTRL_CLKACTIVITY_ICSS_OCP_GCLK_SHIFT (0x00000004u)
+#define CM_PER_ICSS_CLKSTCTRL_CLKACTIVITY_ICSS_OCP_GCLK_ACT (0x1u)
+#define CM_PER_ICSS_CLKSTCTRL_CLKACTIVITY_ICSS_OCP_GCLK_INACT (0x0u)
+
+#define CM_PER_ICSS_CLKSTCTRL_CLKACTIVITY_ICSS_UART_GCLK (0x00000040u)
+#define CM_PER_ICSS_CLKSTCTRL_CLKACTIVITY_ICSS_UART_GCLK_SHIFT (0x00000006u)
+#define CM_PER_ICSS_CLKSTCTRL_CLKACTIVITY_ICSS_UART_GCLK_ACT (0x1u)
+#define CM_PER_ICSS_CLKSTCTRL_CLKACTIVITY_ICSS_UART_GCLK_INACT (0x0u)
+
+#define CM_PER_ICSS_CLKSTCTRL_CLKTRCTRL (0x00000003u)
+#define CM_PER_ICSS_CLKSTCTRL_CLKTRCTRL_SHIFT (0x00000000u)
+#define CM_PER_ICSS_CLKSTCTRL_CLKTRCTRL_HW_AUTO (0x3u)
+#define CM_PER_ICSS_CLKSTCTRL_CLKTRCTRL_NO_SLEEP (0x0u)
+#define CM_PER_ICSS_CLKSTCTRL_CLKTRCTRL_SW_SLEEP (0x1u)
+#define CM_PER_ICSS_CLKSTCTRL_CLKTRCTRL_SW_WKUP (0x2u)
+
+
+/* CPSW_CLKSTCTRL */
+#define CM_PER_CPSW_CLKSTCTRL_CLKACTIVITY_CPSW_125MHZ_GCLK (0x00000010u)
+#define CM_PER_CPSW_CLKSTCTRL_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT (0x00000004u)
+#define CM_PER_CPSW_CLKSTCTRL_CLKACTIVITY_CPSW_125MHZ_GCLK_ACT (0x1u)
+#define CM_PER_CPSW_CLKSTCTRL_CLKACTIVITY_CPSW_125MHZ_GCLK_INACT (0x0u)
+
+#define CM_PER_CPSW_CLKSTCTRL_CLKTRCTRL (0x00000003u)
+#define CM_PER_CPSW_CLKSTCTRL_CLKTRCTRL_SHIFT (0x00000000u)
+#define CM_PER_CPSW_CLKSTCTRL_CLKTRCTRL_HW_AUTO (0x3u)
+#define CM_PER_CPSW_CLKSTCTRL_CLKTRCTRL_NO_SLEEP (0x0u)
+#define CM_PER_CPSW_CLKSTCTRL_CLKTRCTRL_SW_SLEEP (0x1u)
+#define CM_PER_CPSW_CLKSTCTRL_CLKTRCTRL_SW_WKUP (0x2u)
+
+
+/* LCDC_CLKSTCTRL */
+#define CM_PER_LCDC_CLKSTCTRL_CLKACTIVITY_LCDC_L3_OCP_GCLK (0x00000010u)
+#define CM_PER_LCDC_CLKSTCTRL_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT (0x00000004u)
+#define CM_PER_LCDC_CLKSTCTRL_CLKACTIVITY_LCDC_L3_OCP_GCLK_ACT (0x1u)
+#define CM_PER_LCDC_CLKSTCTRL_CLKACTIVITY_LCDC_L3_OCP_GCLK_INACT (0x0u)
+
+#define CM_PER_LCDC_CLKSTCTRL_CLKACTIVITY_LCDC_L4_OCP_GCLK (0x00000020u)
+#define CM_PER_LCDC_CLKSTCTRL_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT (0x00000005u)
+#define CM_PER_LCDC_CLKSTCTRL_CLKACTIVITY_LCDC_L4_OCP_GCLK_ACT (0x1u)
+#define CM_PER_LCDC_CLKSTCTRL_CLKACTIVITY_LCDC_L4_OCP_GCLK_INACT (0x0u)
+
+#define CM_PER_LCDC_CLKSTCTRL_CLKTRCTRL (0x00000003u)
+#define CM_PER_LCDC_CLKSTCTRL_CLKTRCTRL_SHIFT (0x00000000u)
+#define CM_PER_LCDC_CLKSTCTRL_CLKTRCTRL_HW_AUTO (0x3u)
+#define CM_PER_LCDC_CLKSTCTRL_CLKTRCTRL_NO_SLEEP (0x0u)
+#define CM_PER_LCDC_CLKSTCTRL_CLKTRCTRL_SW_SLEEP (0x1u)
+#define CM_PER_LCDC_CLKSTCTRL_CLKTRCTRL_SW_WKUP (0x2u)
+
+
+/* CLKDIV32K_CLKCTRL */
+#define CM_PER_CLKDIV32K_CLKCTRL_IDLEST (0x00030000u)
+#define CM_PER_CLKDIV32K_CLKCTRL_IDLEST_SHIFT (0x00000010u)
+#define CM_PER_CLKDIV32K_CLKCTRL_IDLEST_DISABLE (0x3u)
+#define CM_PER_CLKDIV32K_CLKCTRL_IDLEST_FUNC (0x0u)
+#define CM_PER_CLKDIV32K_CLKCTRL_IDLEST_IDLE (0x2u)
+#define CM_PER_CLKDIV32K_CLKCTRL_IDLEST_TRANS (0x1u)
+
+#define CM_PER_CLKDIV32K_CLKCTRL_MODULEMODE (0x00000003u)
+#define CM_PER_CLKDIV32K_CLKCTRL_MODULEMODE_SHIFT (0x00000000u)
+#define CM_PER_CLKDIV32K_CLKCTRL_MODULEMODE_DISABLED (0x0u)
+#define CM_PER_CLKDIV32K_CLKCTRL_MODULEMODE_ENABLE (0x2u)
+#define CM_PER_CLKDIV32K_CLKCTRL_MODULEMODE_RESERVED (0x3u)
+#define CM_PER_CLKDIV32K_CLKCTRL_MODULEMODE_RESERVED_1 (0x1u)
+
+
+/* CLK_24MHZ_CLKSTCTRL */
+#define CM_PER_CLK_24MHZ_CLKSTCTRL_CLKACTIVITY_CLK_24MHZ_GCLK (0x00000010u)
+#define CM_PER_CLK_24MHZ_CLKSTCTRL_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT (0x00000004u)
+#define CM_PER_CLK_24MHZ_CLKSTCTRL_CLKACTIVITY_CLK_24MHZ_GCLK_ACT (0x1u)
+#define CM_PER_CLK_24MHZ_CLKSTCTRL_CLKACTIVITY_CLK_24MHZ_GCLK_INACT (0x0u)
+
+#define CM_PER_CLK_24MHZ_CLKSTCTRL_CLKTRCTRL (0x00000003u)
+#define CM_PER_CLK_24MHZ_CLKSTCTRL_CLKTRCTRL_SHIFT (0x00000000u)
+#define CM_PER_CLK_24MHZ_CLKSTCTRL_CLKTRCTRL_HW_AUTO (0x3u)
+#define CM_PER_CLK_24MHZ_CLKSTCTRL_CLKTRCTRL_NO_SLEEP (0x0u)
+#define CM_PER_CLK_24MHZ_CLKSTCTRL_CLKTRCTRL_SW_SLEEP (0x1u)
+#define CM_PER_CLK_24MHZ_CLKSTCTRL_CLKTRCTRL_SW_WKUP (0x2u)
+
+
+
+#endif
diff --git a/bsps/arm/beagle/dcan/hw_dcan.h b/bsps/arm/beagle/dcan/hw_dcan.h
new file mode 100755
index 0000000000..24a8b7aed5
--- /dev/null
+++ b/bsps/arm/beagle/dcan/hw_dcan.h
@@ -0,0 +1,1289 @@
+
+
+/**
+ * @Component: DCAN
+ *
+ * @Filename: ../../CredDataBase/dcan_cred.h
+ *
+ ============================================================================ */
+/*
+* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+*/
+/*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+
+#ifndef _HW_DCAN_H_
+#define _HW_DCAN_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***********************************************************************\
+ * Register arrays Definition
+\***********************************************************************/
+
+
+/***********************************************************************\
+ * Bundle arrays Definition
+\***********************************************************************/
+
+
+/***********************************************************************\
+ * Bundles Definition
+\***********************************************************************/
+
+
+
+/*************************************************************************\
+ * Registers Definition
+\*************************************************************************/
+
+#define DCAN_CTL (0x0)
+#define DCAN_PARITYERR_EOI (0x04)
+#define DCAN_ES (0x4)
+#define DCAN_ERRC (0x8)
+#define DCAN_BTR (0xc)
+#define DCAN_INT (0x10)
+#define DCAN_TEST (0x14)
+#define DCAN_PERR (0x1c)
+#define DCAN_ABOTR (0x80)
+#define DCAN_TXRQ_X (0x84)
+#define DCAN_TXRQ(n) (0x88 + (n * 4))
+#define DCAN_NWDAT_X (0x98)
+#define DCAN_NWDAT(n) (0x9c + (n * 4))
+#define DCAN_INTPND_X (0xac)
+#define DCAN_INTPND(n) (0xB0 + (n * 4))
+#define DCAN_MSGVAL_X (0xc0)
+#define DCAN_MSGVAL(n) (0xC4 + (n * 4))
+#define DCAN_INTMUX(n) (0xD8 + (n * 4))
+#define DCAN_IFCMD(n) (0x100 + (((n) - 1) * 0x20))
+#define DCAN_IFMSK(n) (0x104 + (((n) - 1) * 0x20))
+#define DCAN_IFARB(n) (0x108 + (((n) - 1) * 0x20))
+#define DCAN_IFMCTL(n) (0x10c + (((n) - 1) * 0x20))
+#define DCAN_IFDATA(n) (0x110 + (((n) - 1) * 0x20))
+#define DCAN_IFDATB(n) (0x114 + (((n) - 1) * 0x20))
+#define DCAN_IF3OBS (0x140)
+#define DCAN_IF3UPD(n) (0x160 + (n * 4))
+#define DCAN_TIOC (0x1e0)
+#define DCAN_RIOC (0x1e4)
+
+/**************************************************************************\
+ * Field Definition Macros
+\**************************************************************************/
+
+/* CTL */
+#define DCAN_CTL_ABO (0x00000200u)
+#define DCAN_CTL_ABO_SHIFT (0x00000009u)
+#define DCAN_CTL_ABO_DISABLED (0x0u)
+#define DCAN_CTL_ABO_ENABLED (0x1u)
+
+#define DCAN_CTL_CCE (0x00000040u)
+#define DCAN_CTL_CCE_SHIFT (0x00000006u)
+#define DCAN_CTL_CCE_ACCESS (0x1u)
+#define DCAN_CTL_CCE_NOACCESS (0x0u)
+
+#define DCAN_CTL_DAR (0x00000020u)
+#define DCAN_CTL_DAR_SHIFT (0x00000005u)
+#define DCAN_CTL_DAR_DISABLED (0x1u)
+#define DCAN_CTL_DAR_ENABLED (0x0u)
+
+#define DCAN_CTL_DE1 (0x00040000u)
+#define DCAN_CTL_DE1_SHIFT (0x00000012u)
+#define DCAN_CTL_DE1_DISABLED (0x0u)
+#define DCAN_CTL_DE1_ENABLED (0x1u)
+
+#define DCAN_CTL_DE2 (0x00080000u)
+#define DCAN_CTL_DE2_SHIFT (0x00000013u)
+#define DCAN_CTL_DE2_DISABLED (0x0u)
+#define DCAN_CTL_DE2_ENABLED (0x1u)
+
+#define DCAN_CTL_DE3 (0x00100000u)
+#define DCAN_CTL_DE3_SHIFT (0x00000014u)
+#define DCAN_CTL_DE3_DISABLED (0x0u)
+#define DCAN_CTL_DE3_ENABLED (0x1u)
+
+#define DCAN_CTL_EIE (0x00000008u)
+#define DCAN_CTL_EIE_SHIFT (0x00000003u)
+#define DCAN_CTL_EIE_DISABLED (0x0u)
+#define DCAN_CTL_EIE_ENABLED (0x1u)
+
+#define DCAN_CTL_IDS (0x00000100u)
+#define DCAN_CTL_IDS_SHIFT (0x00000008u)
+#define DCAN_CTL_IDS_INTERRUPT (0x1u)
+#define DCAN_CTL_IDS_WAIT (0x0u)
+
+#define DCAN_CTL_IE0 (0x00000002u)
+#define DCAN_CTL_IE0_SHIFT (0x00000001u)
+#define DCAN_CTL_IE0_DISABLED (0x0u)
+#define DCAN_CTL_IE0_ENABLED (0x1u)
+
+#define DCAN_CTL_IE1 (0x00020000u)
+#define DCAN_CTL_IE1_SHIFT (0x00000011u)
+#define DCAN_CTL_IE1_DISABLED (0x0u)
+#define DCAN_CTL_IE1_ENABLED (0x1u)
+
+#define DCAN_CTL_INIT (0x00000001u)
+#define DCAN_CTL_INIT_SHIFT (0x00000000u)
+#define DCAN_CTL_INIT_INITMODE (0x1u)
+#define DCAN_CTL_INIT_NORMAL (0x0u)
+
+#define DCAN_CTL_INITDBG (0x00010000u)
+#define DCAN_CTL_INITDBG_SHIFT (0x00000010u)
+#define DCAN_CTL_INITDBG_DISABLED (0x0u)
+#define DCAN_CTL_INITDBG_ENABLED (0x1u)
+
+#define DCAN_CTL_PDR (0x01000000u)
+#define DCAN_CTL_PDR_SHIFT (0x00000018u)
+#define DCAN_CTL_PDR_NOTPOWERDOWN (0x0u)
+#define DCAN_CTL_PDR_POWERDOWN (0x1u)
+
+#define DCAN_CTL_PMD (0x00003C00u)
+#define DCAN_CTL_PMD_SHIFT (0x0000000Au)
+#define DCAN_CTL_PMD_DISABLED (0x5u)
+#define DCAN_CTL_PMD_ENABLED (0x1u)
+
+#define DCAN_CTL_SIE (0x00000004u)
+#define DCAN_CTL_SIE_SHIFT (0x00000002u)
+#define DCAN_CTL_SIE_DISABLED (0x0u)
+#define DCAN_CTL_SIE_ENABLED (0x1u)
+
+#define DCAN_CTL_SWR (0x00008000u)
+#define DCAN_CTL_SWR_SHIFT (0x0000000Fu)
+#define DCAN_CTL_SWR_NORMAL (0x0u)
+#define DCAN_CTL_SWR_RESET (0x1u)
+
+#define DCAN_CTL_TEST (0x00000080u)
+#define DCAN_CTL_TEST_SHIFT (0x00000007u)
+#define DCAN_CTL_TEST_NORMALMODE (0x0u)
+#define DCAN_CTL_TEST_TESTMODE (0x1u)
+
+#define DCAN_CTL_WUBA (0x02000000u)
+#define DCAN_CTL_WUBA_SHIFT (0x00000019u)
+#define DCAN_CTL_WUBA_DETECTION (0x1u)
+#define DCAN_CTL_WUBA_NODETECTION (0x0u)
+
+
+/* PARITYERR_EOI */
+#define DCAN_PARITYERR_EOI_PARITYERR_EOI (0x00000100u)
+#define DCAN_PARITYERR_EOI_PARITYERR_EOI_SHIFT (0x00000008u)
+#define DCAN_PARITYERR_EOI_PARITYERR_EOI_ENDOFINTERRUPT (0x1u)
+#define DCAN_PARITYERR_EOI_PARITYERR_EOI_NOEFFECT (0x0u)
+
+
+/* ES */
+#define DCAN_ES_BOFF (0x00000080u)
+#define DCAN_ES_BOFF_SHIFT (0x00000007u)
+#define DCAN_ES_BOFF_ERROR (0x1u)
+#define DCAN_ES_BOFF_NOERROR (0x0u)
+
+#define DCAN_ES_EPASS (0x00000020u)
+#define DCAN_ES_EPASS_SHIFT (0x00000005u)
+#define DCAN_ES_EPASS_NOPASSIVE (0x0u)
+#define DCAN_ES_EPASS_PASSIVEERROR (0x1u)
+
+#define DCAN_ES_EWARN (0x00000040u)
+#define DCAN_ES_EWARN_SHIFT (0x00000006u)
+#define DCAN_ES_EWARN_ATLEAST1ERRORABOVE_96 (0x1u)
+#define DCAN_ES_EWARN_ERRENCOUNTERBELOW_96 (0x0u)
+
+#define DCAN_ES_LEC (0x00000007u)
+#define DCAN_ES_LEC_SHIFT (0x00000000u)
+#define DCAN_ES_LEC_ACKERROR (0x3u)
+#define DCAN_ES_LEC_BIT0ERROR (0x5u)
+#define DCAN_ES_LEC_BIT1ERROR (0x4u)
+#define DCAN_ES_LEC_CRCERROR (0x6u)
+#define DCAN_ES_LEC_FORMERROR (0x2u)
+#define DCAN_ES_LEC_NOERROR (0x0u)
+#define DCAN_ES_LEC_NOEVENT (0x7u)
+#define DCAN_ES_LEC_STUFFERROR (0x1u)
+
+#define DCAN_ES_PDA (0x00000400u)
+#define DCAN_ES_PDA_SHIFT (0x0000000Au)
+#define DCAN_ES_PDA_NOTPOWERDOWN (0x0u)
+#define DCAN_ES_PDA_POWERDOWN (0x1u)
+
+#define DCAN_ES_PER (0x00000100u)
+#define DCAN_ES_PER_SHIFT (0x00000008u)
+#define DCAN_ES_PER_ERROR (0x1u)
+#define DCAN_ES_PER_NOERROR (0x0u)
+
+#define DCAN_ES_RXOK (0x00000010u)
+#define DCAN_ES_RXOK_SHIFT (0x00000004u)
+#define DCAN_ES_RXOK_MESSAGERECIEVED (0x1u)
+#define DCAN_ES_RXOK_NOMESSAGE (0x0u)
+
+#define DCAN_ES_TXOK (0x00000008u)
+#define DCAN_ES_TXOK_SHIFT (0x00000003u)
+#define DCAN_ES_TXOK_MESSAGETRANSMITTED (0x1u)
+#define DCAN_ES_TXOK_NOMESSAGE (0x0u)
+
+#define DCAN_ES_WAKEUPPND (0x00000200u)
+#define DCAN_ES_WAKEUPPND_SHIFT (0x00000009u)
+#define DCAN_ES_WAKEUPPND_INITWAKEUP (0x1u)
+#define DCAN_ES_WAKEUPPND_NOWAKEUP (0x0u)
+
+
+/* ERRC */
+#define DCAN_ERRC_REC (0x00007F00u)
+#define DCAN_ERRC_REC_SHIFT (0x00000008u)
+
+#define DCAN_ERRC_RP (0x00008000u)
+#define DCAN_ERRC_RP_SHIFT (0x0000000Fu)
+#define DCAN_ERRC_RP_BELOWERRORPASSIVELEVEL (0x0u)
+#define DCAN_ERRC_RP_REACHEDERRORPASSIVELEVEL (0x1u)
+
+#define DCAN_ERRC_TEC (0x000000FFu)
+#define DCAN_ERRC_TEC_SHIFT (0x00000000u)
+
+
+/* BTR */
+#define DCAN_BTR_BRP (0x0000003Fu)
+#define DCAN_BTR_BRP_SHIFT (0x00000000u)
+
+#define DCAN_BTR_BRPE (0x000F0000u)
+#define DCAN_BTR_BRPE_SHIFT (0x00000010u)
+
+#define DCAN_BTR_DCAN_BTR (0xFFFFFFFFu)
+#define DCAN_BTR_DCAN_BTR_SHIFT (0x00000000u)
+
+#define DCAN_BTR_SJW (0x000000C0u)
+#define DCAN_BTR_SJW_SHIFT (0x00000006u)
+
+#define DCAN_BTR_TSEG1 (0x00000F00u)
+#define DCAN_BTR_TSEG1_SHIFT (0x00000008u)
+
+#define DCAN_BTR_TSEG2 (0x00007000u)
+#define DCAN_BTR_TSEG2_SHIFT (0x0000000Cu)
+
+
+/* INT */
+#define DCAN_INT_INT0ID (0x0000FFFFu)
+#define DCAN_INT_INT0ID_SHIFT (0x00000000u)
+
+#define DCAN_INT_INT1ID (0x00FF0000u)
+#define DCAN_INT_INT1ID_SHIFT (0x00000010u)
+
+
+/* TEST */
+#define DCAN_TEST_EXL (0x00000100u)
+#define DCAN_TEST_EXL_SHIFT (0x00000008u)
+#define DCAN_TEST_EXL_DISABLED (0x0u)
+#define DCAN_TEST_EXL_ENABLED (0x1u)
+
+#define DCAN_TEST_LBACK (0x00000010u)
+#define DCAN_TEST_LBACK_SHIFT (0x00000004u)
+#define DCAN_TEST_LBACK_DISABLED (0x0u)
+#define DCAN_TEST_LBACK_ENABLED (0x1u)
+
+#define DCAN_TEST_RDA (0x00000200u)
+#define DCAN_TEST_RDA_SHIFT (0x00000009u)
+#define DCAN_TEST_RDA_ACCESS (0x1u)
+#define DCAN_TEST_RDA_NORMAL (0x0u)
+
+#define DCAN_TEST_RX (0x00000080u)
+#define DCAN_TEST_RX_SHIFT (0x00000007u)
+#define DCAN_TEST_RX_DOMINANT (0x0u)
+#define DCAN_TEST_RX_RECESSIVE (0x1u)
+
+#define DCAN_TEST_TX (0x00000060u)
+#define DCAN_TEST_TX_SHIFT (0x00000005u)
+#define DCAN_TEST_TX_DOMINANT (0x2u)
+#define DCAN_TEST_TX_NORMAL (0x0u)
+#define DCAN_TEST_TX_RECESSIVE (0x3u)
+#define DCAN_TEST_TX_SAMPLEPOINT (0x1u)
+
+#define DCAN_TEST_SILENT (0x00000008u)
+#define DCAN_TEST_SILENT_SHIFT (0x00000003u)
+#define DCAN_TEST_SILENT_DISABLED (0x0u)
+#define DCAN_TEST_SILENT_ENABLED (0x1u)
+
+
+/* PERR */
+#define DCAN_PERR_MESSAGE_NUMBER (0x000000FFu)
+#define DCAN_PERR_MESSAGE_NUMBER_SHIFT (0x00000000u)
+
+#define DCAN_PERR_WORD_NUMBER (0x00000700u)
+#define DCAN_PERR_WORD_NUMBER_SHIFT (0x00000008u)
+
+
+/* ABOTR */
+#define DCAN_ABOTR_ABOTIME (0xFFFFFFFFu)
+#define DCAN_ABOTR_ABOTIME_SHIFT (0x00000000u)
+
+
+/* TXRQ_X */
+#define DCAN_TXRQ_X_TXRQSTREG1 (0x00000003u)
+#define DCAN_TXRQ_X_TXRQSTREG1_SHIFT (0x00000000u)
+
+#define DCAN_TXRQ_X_TXRQSTREG2 (0x0000000Cu)
+#define DCAN_TXRQ_X_TXRQSTREG2_SHIFT (0x00000002u)
+
+#define DCAN_TXRQ_X_TXRQSTREG3 (0x00000030u)
+#define DCAN_TXRQ_X_TXRQSTREG3_SHIFT (0x00000004u)
+
+#define DCAN_TXRQ_X_TXRQSTREG4 (0x000000C0u)
+#define DCAN_TXRQ_X_TXRQSTREG4_SHIFT (0x00000006u)
+
+#define DCAN_TXRQ_X_TXRQSTREG5 (0x00000300u)
+#define DCAN_TXRQ_X_TXRQSTREG5_SHIFT (0x00000008u)
+
+#define DCAN_TXRQ_X_TXRQSTREG6 (0x00000C00u)
+#define DCAN_TXRQ_X_TXRQSTREG6_SHIFT (0x0000000Au)
+
+#define DCAN_TXRQ_X_TXRQSTREG7 (0x00003000u)
+#define DCAN_TXRQ_X_TXRQSTREG7_SHIFT (0x0000000Cu)
+
+#define DCAN_TXRQ_X_TXRQSTREG8 (0x0000C000u)
+#define DCAN_TXRQ_X_TXRQSTREG8_SHIFT (0x0000000Eu)
+
+
+/* TXRQ12 */
+#define DCAN_TXRQ12_TXRQST_16_1 (0x0000FFFFu)
+#define DCAN_TXRQ12_TXRQST_16_1_SHIFT (0x00000000u)
+
+#define DCAN_TXRQ12_TXRQST_32_17 (0xFFFF0000u)
+#define DCAN_TXRQ12_TXRQST_32_17_SHIFT (0x00000010u)
+
+
+/* TXRQ34 */
+#define DCAN_TXRQ34_TXRQST_48_33 (0x0000FFFFu)
+#define DCAN_TXRQ34_TXRQST_48_33_SHIFT (0x00000000u)
+
+#define DCAN_TXRQ34_TXRQST_64_49 (0xFFFF0000u)
+#define DCAN_TXRQ34_TXRQST_64_49_SHIFT (0x00000010u)
+
+
+/* TXRQ56 */
+#define DCAN_TXRQ56_TXRQST_80_65 (0x0000FFFFu)
+#define DCAN_TXRQ56_TXRQST_80_65_SHIFT (0x00000000u)
+
+#define DCAN_TXRQ56_TXRQST_96_81 (0xFFFF0000u)
+#define DCAN_TXRQ56_TXRQST_96_81_SHIFT (0x00000010u)
+
+
+/* TXRQ78 */
+#define DCAN_TXRQ78_TXRQST_112_97 (0x0000FFFFu)
+#define DCAN_TXRQ78_TXRQST_112_97_SHIFT (0x00000000u)
+
+#define DCAN_TXRQ78_TXRQST_128_113 (0xFFFF0000u)
+#define DCAN_TXRQ78_TXRQST_128_113_SHIFT (0x00000010u)
+
+
+/* NWDAT_X */
+#define DCAN_NWDAT_X_NEWDATREG1 (0x00000003u)
+#define DCAN_NWDAT_X_NEWDATREG1_SHIFT (0x00000000u)
+
+#define DCAN_NWDAT_X_NEWDATREG2 (0x0000000Cu)
+#define DCAN_NWDAT_X_NEWDATREG2_SHIFT (0x00000002u)
+
+#define DCAN_NWDAT_X_NEWDATREG3 (0x00000030u)
+#define DCAN_NWDAT_X_NEWDATREG3_SHIFT (0x00000004u)
+
+#define DCAN_NWDAT_X_NEWDATREG4 (0x000000C0u)
+#define DCAN_NWDAT_X_NEWDATREG4_SHIFT (0x00000006u)
+
+#define DCAN_NWDAT_X_NEWDATREG5 (0x00000300u)
+#define DCAN_NWDAT_X_NEWDATREG5_SHIFT (0x00000008u)
+
+#define DCAN_NWDAT_X_NEWDATREG6 (0x00000C00u)
+#define DCAN_NWDAT_X_NEWDATREG6_SHIFT (0x0000000Au)
+
+#define DCAN_NWDAT_X_NEWDATREG7 (0x00003000u)
+#define DCAN_NWDAT_X_NEWDATREG7_SHIFT (0x0000000Cu)
+
+#define DCAN_NWDAT_X_NEWDATREG8 (0x0000C000u)
+#define DCAN_NWDAT_X_NEWDATREG8_SHIFT (0x0000000Eu)
+
+
+/* NWDAT12 */
+#define DCAN_NWDAT12_NEWDAT_16_1 (0x0000FFFFu)
+#define DCAN_NWDAT12_NEWDAT_16_1_SHIFT (0x00000000u)
+
+#define DCAN_NWDAT12_NEWDAT_32_17 (0xFFFF0000u)
+#define DCAN_NWDAT12_NEWDAT_32_17_SHIFT (0x00000010u)
+
+#define DCAN_NWDAT12_NEWDAT_80_65 (0x0000FFFFu)
+#define DCAN_NWDAT12_NEWDAT_80_65_SHIFT (0x00000000u)
+
+
+/* NWDAT34 */
+#define DCAN_NWDAT34_NEWDAT_48_33 (0x0000FFFFu)
+#define DCAN_NWDAT34_NEWDAT_48_33_SHIFT (0x00000000u)
+
+#define DCAN_NWDAT34_NEWDAT_64_49 (0xFFFF0000u)
+#define DCAN_NWDAT34_NEWDAT_64_49_SHIFT (0x00000010u)
+
+
+/* NWDAT56 */
+
+#define DCAN_NWDAT56_NEWDAT_96_81 (0xFFFF0000u)
+#define DCAN_NWDAT56_NEWDAT_96_81_SHIFT (0x00000000u)
+
+
+/* NWDAT78 */
+#define DCAN_NWDAT78_NEWDAT_112_97 (0x0000FFFFu)
+#define DCAN_NWDAT78_NEWDAT_112_97_SHIFT (0x00000000u)
+
+#define DCAN_NWDAT78_NEWDAT_128_113 (0xFFFF0000u)
+#define DCAN_NWDAT78_NEWDAT_128_113_SHIFT (0x00000010u)
+
+
+/* INTPND_X */
+#define DCAN_INTPND_X_INTPNDREG1 (0x00000003u)
+#define DCAN_INTPND_X_INTPNDREG1_SHIFT (0x00000000u)
+
+#define DCAN_INTPND_X_INTPNDREG2 (0x0000000Cu)
+#define DCAN_INTPND_X_INTPNDREG2_SHIFT (0x00000002u)
+
+#define DCAN_INTPND_X_INTPNDREG3 (0x00000030u)
+#define DCAN_INTPND_X_INTPNDREG3_SHIFT (0x00000004u)
+
+#define DCAN_INTPND_X_INTPNDREG4 (0x000000C0u)
+#define DCAN_INTPND_X_INTPNDREG4_SHIFT (0x00000006u)
+
+#define DCAN_INTPND_X_INTPNDREG5 (0x00000300u)
+#define DCAN_INTPND_X_INTPNDREG5_SHIFT (0x00000008u)
+
+#define DCAN_INTPND_X_INTPNDREG6 (0x00000C00u)
+#define DCAN_INTPND_X_INTPNDREG6_SHIFT (0x0000000Au)
+
+#define DCAN_INTPND_X_INTPNDREG7 (0x00003000u)
+#define DCAN_INTPND_X_INTPNDREG7_SHIFT (0x0000000Cu)
+
+#define DCAN_INTPND_X_INTPNDREG8 (0x0000C000u)
+#define DCAN_INTPND_X_INTPNDREG8_SHIFT (0x0000000Eu)
+
+
+/* INTPND12 */
+#define DCAN_INTPND12_INTPND_16_1 (0x0000FFFFu)
+#define DCAN_INTPND12_INTPND_16_1_SHIFT (0x00000001u)
+
+#define DCAN_INTPND12_INTPND_32_17 (0xFFFF0000u)
+#define DCAN_INTPND12_INTPND_32_17_SHIFT (0x00000010u)
+
+
+/* INTPND34 */
+#define DCAN_INTPND34_INTPND_48_33 (0x0000FFFFu)
+#define DCAN_INTPND34_INTPND_48_33_SHIFT (0x00000001u)
+
+#define DCAN_INTPND34_INTPND_64_49 (0xFFFF0000u)
+#define DCAN_INTPND34_INTPND_64_49_SHIFT (0x00000010u)
+
+
+/* INTPND56 */
+#define DCAN_INTPND56_INTPND_80_65 (0x0000FFFFu)
+#define DCAN_INTPND56_INTPND_80_65_SHIFT (0x00000001u)
+
+#define DCAN_INTPND56_INTPND_96_81 (0xFFFF0000u)
+#define DCAN_INTPND56_INTPND_96_81_SHIFT (0x00000000u)
+
+
+
+/* INTPND78 */
+
+#define DCAN_INTPND78_INTPND_128_113 (0xFFFF0000u)
+#define DCAN_INTPND78_INTPND_128_113_SHIFT (0x00000010u)
+
+
+/* MSGVAL_X */
+#define DCAN_MSGVAL_X_MSGVALREG1 (0x00000003u)
+#define DCAN_MSGVAL_X_MSGVALREG1_SHIFT (0x00000000u)
+
+#define DCAN_MSGVAL_X_MSGVALREG2 (0x0000000Cu)
+#define DCAN_MSGVAL_X_MSGVALREG2_SHIFT (0x00000002u)
+
+#define DCAN_MSGVAL_X_MSGVALREG3 (0x00000030u)
+#define DCAN_MSGVAL_X_MSGVALREG3_SHIFT (0x00000004u)
+
+#define DCAN_MSGVAL_X_MSGVALREG4 (0x000000C0u)
+#define DCAN_MSGVAL_X_MSGVALREG4_SHIFT (0x00000006u)
+
+#define DCAN_MSGVAL_X_MSGVALREG5 (0x00000300u)
+#define DCAN_MSGVAL_X_MSGVALREG5_SHIFT (0x00000008u)
+
+#define DCAN_MSGVAL_X_MSGVALREG6 (0x00000C00u)
+#define DCAN_MSGVAL_X_MSGVALREG6_SHIFT (0x0000000Au)
+
+#define DCAN_MSGVAL_X_MSGVALREG7 (0x00003000u)
+#define DCAN_MSGVAL_X_MSGVALREG7_SHIFT (0x0000000Cu)
+
+#define DCAN_MSGVAL_X_MSGVALREG8 (0x0000C000u)
+#define DCAN_MSGVAL_X_MSGVALREG8_SHIFT (0x00000000u)
+
+
+/* MSGVAL12 */
+#define DCAN_MSGVAL12_MSGVAL_16_1 (0x0000FFFFu)
+#define DCAN_MSGVAL12_MSGVAL_16_1_SHIFT (0x00000001u)
+
+#define DCAN_MSGVAL12_MSGVAL_32_17 (0xFFFF0000u)
+#define DCAN_MSGVAL12_MSGVAL_32_17_SHIFT (0x00000010u)
+
+
+/* MSGVAL34 */
+#define DCAN_MSGVAL34_MSGVAL_48_33 (0x0000FFFFu)
+#define DCAN_MSGVAL34_MSGVAL_48_33_SHIFT (0x00000001u)
+
+#define DCAN_MSGVAL34_MSGVAL_64_49 (0xFFFF0000u)
+#define DCAN_MSGVAL34_MSGVAL_64_49_SHIFT (0x00000010u)
+
+
+/* MSGVAL56 */
+#define DCAN_MSGVAL56_MSGVAL_80_65 (0x0000FFFFu)
+#define DCAN_MSGVAL56_MSGVAL_80_65_SHIFT (0x00000001u)
+
+#define DCAN_MSGVAL56_MSGVAL_96_81 (0xFFFF0000u)
+#define DCAN_MSGVAL56_MSGVAL_96_81_SHIFT (0x00000010u)
+
+
+/* MSGVAL78 */
+#define DCAN_MSGVAL78_MSGVAL_112_97 (0x0000FFFFu)
+#define DCAN_MSGVAL78_MSGVAL_112_97_SHIFT (0x00000001u)
+
+#define DCAN_MSGVAL78_MSGVAL_128_113 (0xFFFF0000u)
+#define DCAN_MSGVAL78_MSGVAL_128_113_SHIFT (0x00000010u)
+
+
+/* INTMUX12 */
+#define DCAN_INTMUX12_INTMUX_16_1 (0x0000FFFFu)
+#define DCAN_INTMUX12_INTMUX_16_1_SHIFT (0x00000001u)
+
+#define DCAN_INTMUX12_INTMUX_32_17 (0xFFFF0000u)
+#define DCAN_INTMUX12_INTMUX_32_17_SHIFT (0x00000010u)
+
+
+/* INTMUX34 */
+#define DCAN_INTMUX34_INTMUX_48_33 (0x0000FFFFu)
+#define DCAN_INTMUX34_INTMUX_48_33_SHIFT (0x00000001u)
+
+#define DCAN_INTMUX34_INTMUX_64_49 (0xFFFF0000u)
+#define DCAN_INTMUX34_INTMUX_64_49_SHIFT (0x00000010u)
+
+
+/* INTMUX56 */
+#define DCAN_INTMUX56_INTMUX_80_65 (0x0000FFFFu)
+#define DCAN_INTMUX56_INTMUX_80_65_SHIFT (0x00000001u)
+
+#define DCAN_INTMUX56_INTMUX_96_81 (0xFFFF0000u)
+#define DCAN_INTMUX56_INTMUX_96_81_SHIFT (0x00000010u)
+
+
+/* INTMUX78 */
+#define DCAN_INTMUX78_INTMUX_112_95 (0x0000FFFFu)
+#define DCAN_INTMUX78_INTMUX_112_95_SHIFT (0x00000001u)
+
+#define DCAN_INTMUX78_INTMUX_128_113 (0xFFFF0000u)
+#define DCAN_INTMUX78_INTMUX_128_113_SHIFT (0x00000010u)
+
+/* IFxCMD mu */
+#define DCAN_IFCMD_ARB (0x00200000u)
+#define DCAN_IFCMD_ARB_SHIFT (0x00000015u)
+#define DCAN_IFCMD_ARB_NOCHANGE (0x0u)
+#define DCAN_IFCMD_ARB_OBJTOREG (0x1u)
+#define DCAN_IFCMD_ARB_REGTOOBJ (0x1u)
+
+#define DCAN_IFCMD_BUSY (0x00008000u)
+#define DCAN_IFCMD_BUSY_SHIFT (0x0000000Fu)
+#define DCAN_IFCMD_BUSY_NOTRANSFER (0x0u)
+#define DCAN_IFCMD_BUSY_TRANSFER (0x1u)
+
+#define DCAN_IFCMD_CLRINTPND (0x00080000u)
+#define DCAN_IFCMD_CLRINTPND_SHIFT (0x00000013u)
+#define DCAN_IFCMD_CLRINTPND_CHANGE (0x1u)
+#define DCAN_IFCMD_CLRINTPND_NOCHANGE (0x0u)
+
+#define DCAN_IFCMD_CONTROL (0x00100000u)
+#define DCAN_IFCMD_CONTROL_SHIFT (0x00000014u)
+
+#define DCAN_IFCMD_DATAA (0x00020000u)
+#define DCAN_IFCMD_DATAA_SHIFT (0x00000011u)
+
+#define DCAN_IFCMD_DATAB (0x00010000u)
+#define DCAN_IFCMD_DATAB_SHIFT (0x00000010u)
+
+#define DCAN_IFCMD_DMAACTIVE (0x00004000u)
+#define DCAN_IFCMD_DMAACTIVE_SHIFT (0x0000000Eu)
+#define DCAN_IFCMD_DMAACTIVE_ACTIVE (0x1u)
+#define DCAN_IFCMD_DMAACTIVE_INACTIVE (0x0u)
+
+#define DCAN_IFCMD_MASK (0x00400000u)
+#define DCAN_IFCMD_MASK_SHIFT (0x00000016u)
+
+#define DCAN_IFCMD_MESSAGENUMBER (0x000000FFu)
+#define DCAN_IFCMD_MESSAGENUMBER_SHIFT (0x00000000u)
+
+#define DCAN_IFCMD_TXRQST_NEWDAT (0x00040000u)
+#define DCAN_IFCMD_TXRQST_NEWDAT_SHIFT (0x00000012u)
+
+#define DCAN_IFCMD_WR_RD (0x00800000u)
+#define DCAN_IFCMD_WR_RD_SHIFT (0x00000017u)
+
+
+/* IFxMSK mu */
+#define DCAN_IFMSK_MDIR (0x40000000u)
+#define DCAN_IFMSK_MDIR_SHIFT (0x00000001Eu)
+#define DCAN_IFMSK_MDIR_NOTUSED (0x0u)
+#define DCAN_IFMSK_MDIR_USED (0x1u)
+
+#define DCAN_IFMSK_MSK (0x1FFFFFFFu)
+#define DCAN_IFMSK_MSK_SHIFT (0x00000000u)
+#define DCAN_IFMSK_MSK_NOTUSED (0x0u)
+#define DCAN_IFMSK_MSK_USED (0x1u)
+
+#define DCAN_IFMSK_MXTD (0x80000000u)
+#define DCAN_IFMSK_MXTD_SHIFT (0x00000001Fu)
+#define DCAN_IFMSK_MXTD_NOTUSED (0x0u)
+#define DCAN_IFMSK_MXTD_USED (0x1u)
+
+
+/* IFxARB mu */
+#define DCAN_IFARB_DIR (0x20000000u)
+#define DCAN_IFARB_DIR_SHIFT (0x0000001Du)
+#define DCAN_IFARB_DIR_RECEIVE (0x0u)
+#define DCAN_IFARB_DIR_TRANSMIT (0x1u)
+
+#define DCAN_IFARB_MSGVAL (0x80000000u)
+#define DCAN_IFARB_MSGVAL_SHIFT (0x0000001Fu)
+#define DCAN_IFARB_MSGVAL_IGNORED (0x0u)
+#define DCAN_IFARB_MSGVAL_USED (0x1u)
+
+#define DCAN_IFARB_MSK (0x1FFFFFFFu)
+#define DCAN_IFARB_MSK_SHIFT (0x000000000u)
+#define DCAN_IFARB_MSK_RECEIVE (0x0u)
+#define DCAN_IFARB_MSK_TRANSMIT (0x1u)
+
+#define DCAN_IFARB_XTD (0x40000000u)
+#define DCAN_IFARB_XTD_SHIFT (0x0000001Eu)
+#define DCAN_IFARB_XTD_11_BIT (0x0u)
+#define DCAN_IFARB_XTD_29_BIT (0x1u)
+
+/* IFxMCTL mu */
+#define DCAN_IFMCTL_DATALENGTHCODE (0x0000000Fu)
+#define DCAN_IFMCTL_DATALENGTHCODE_SHIFT (0x00000000u)
+
+#define DCAN_IFMCTL_EOB (0x00000080u)
+#define DCAN_IFMCTL_EOB_SHIFT (0x00000007u)
+
+#define DCAN_IFMCTL_INTPND (0x00002000u)
+#define DCAN_IFMCTL_INTPND_SHIFT (0x0000000Du)
+#define DCAN_IFMCTL_INTPND_INTERRUPT (0x1u)
+#define DCAN_IFMCTL_INTPND_NOINTERRUPT (0x0u)
+
+#define DCAN_IFMCTL_MSGLST (0x00004000u)
+#define DCAN_IFMCTL_MSGLST_SHIFT (0x0000000Eu)
+#define DCAN_IFMCTL_MSGLST_MSGLOST (0x1u)
+#define DCAN_IFMCTL_MSGLST_NOMSGLOST (0x0u)
+
+#define DCAN_IFMCTL_NEWDAT (0x00008000u)
+#define DCAN_IFMCTL_NEWDAT_SHIFT (0x0000000Fu)
+#define DCAN_IFMCTL_NEWDAT_NEWDATA (0x1u)
+#define DCAN_IFMCTL_NEWDAT_NONEWDATA (0x0u)
+
+#define DCAN_IFMCTL_RMTEN (0x00000200u)
+#define DCAN_IFMCTL_RMTEN_SHIFT (0x00000009u)
+#define DCAN_IFMCTL_RMTEN_DISABLE (0x0u)
+#define DCAN_IFMCTL_RMTEN_ENABLE (0x1u)
+
+#define DCAN_IFMCTL_RXIE (0x00000400u)
+#define DCAN_IFMCTL_RXIE_SHIFT (0x0000000Au)
+#define DCAN_IFMCTL_RXIE_NOTRIGGER (0x0u)
+#define DCAN_IFMCTL_RXIE_TRIGGER (0x1u)
+
+#define DCAN_IFMCTL_TXIE (0x00000800u)
+#define DCAN_IFMCTL_TXIE_SHIFT (0x0000000Bu)
+#define DCAN_IFMCTL_TXIE_NOTRIGGER (0x0u)
+#define DCAN_IFMCTL_TXIE_TRIGGER (0x1u)
+
+#define DCAN_IFMCTL_TXRQST (0x00000100u)
+#define DCAN_IFMCTL_TXRQST_SHIFT (0x00000008u)
+#define DCAN_IFMCTL_TXRQST_NOREQUESTED (0x0u)
+#define DCAN_IFMCTL_TXRQST_REQUESTED (0x1u)
+
+#define DCAN_IFMCTL_UMASK (0x00001000u)
+#define DCAN_IFMCTL_UMASK_SHIFT (0x0000000Cu)
+#define DCAN_IFMCTL_UMASK_IGNORED (0x0u)
+#define DCAN_IFMCTL_UMASK_MASKED (0x1u)
+
+/* IFxDATA mu */
+#define DCAN_IFDATA_DCAN_IFDATA (0xFFFFFFFFu)
+#define DCAN_IFDATA_DCAN_IFDATA_SHIFT (0x00000000u)
+
+
+/* IFxDATB mu */
+#define DCAN_IFDATB_DCAN_IFDATB (0xFFFFFFFFu)
+#define DCAN_IFDATB_DCAN_IFDATB_SHIFT (0x00000000u)
+
+/* IF1CMD */
+#define DCAN_IF1CMD_ARB (0x00200000u)
+#define DCAN_IF1CMD_ARB_SHIFT (0x00000015u)
+
+#define DCAN_IF1CMD_BUSY (0x00008000u)
+#define DCAN_IF1CMD_BUSY_SHIFT (0x0000000Fu)
+#define DCAN_IF1CMD_BUSY_NOTRANSFER (0x0u)
+#define DCAN_IF1CMD_BUSY_TRANSFER (0x1u)
+
+#define DCAN_IF1CMD_CLRINTPND (0x00080000u)
+#define DCAN_IF1CMD_CLRINTPND_SHIFT (0x00000013u)
+#define DCAN_IF1CMD_CLRINTPND_CHANGE (0x1u)
+#define DCAN_IF1CMD_CLRINTPND_NOCHANGE (0x0u)
+
+#define DCAN_IF1CMD_CONTROL (0x00100000u)
+#define DCAN_IF1CMD_CONTROL_SHIFT (0x00000014u)
+
+#define DCAN_IF1CMD_DATAA (0x00020000u)
+#define DCAN_IF1CMD_DATAA_SHIFT (0x00000011u)
+
+#define DCAN_IF1CMD_DATAB (0x00010000u)
+#define DCAN_IF1CMD_DATAB_SHIFT (0x00000010u)
+
+#define DCAN_IF1CMD_DMAACTIVE (0x00004000u)
+#define DCAN_IF1CMD_DMAACTIVE_SHIFT (0x0000000Eu)
+#define DCAN_IF1CMD_DMAACTIVE_ACTIVE (0x1u)
+#define DCAN_IF1CMD_DMAACTIVE_INACTIVE (0x0u)
+
+#define DCAN_IF1CMD_MASK (0x00400000u)
+#define DCAN_IF1CMD_MASK_SHIFT (0x00000016u)
+
+#define DCAN_IF1CMD_MESSAGENUMBER (0x0000000Fu)
+#define DCAN_IF1CMD_MESSAGENUMBER_SHIFT (0x00000000u)
+
+#define DCAN_IF1CMD_TXRQST_NEWDAT (0x00040000u)
+#define DCAN_IF1CMD_TXRQST_NEWDAT_SHIFT (0x00000012u)
+
+#define DCAN_IF1CMD_WR_RD (0x00800000u)
+#define DCAN_IF1CMD_WR_RD_SHIFT (0x00000017u)
+
+
+/* IF1MSK */
+#define DCAN_IF1MSK_MDIR (0x40000000u)
+#define DCAN_IF1MSK_MDIR_SHIFT (0x00000001Eu)
+#define DCAN_IF1MSK_MDIR_NOTUSED (0x0u)
+#define DCAN_IF1MSK_MDIR_USED (0x1u)
+
+#define DCAN_IF1MSK_MSK (0x1FFFFFFFu)
+#define DCAN_IF1MSK_MSK_SHIFT (0x00000000u)
+#define DCAN_IF1MSK_MSK_NOTUSED (0x0u)
+#define DCAN_IF1MSK_MSK_USED (0x1u)
+
+#define DCAN_IF1MSK_MXTD (0x80000000u)
+#define DCAN_IF1MSK_MXTD_SHIFT (0x00000001Fu)
+#define DCAN_IF1MSK_MXTD_NOTUSED (0x0u)
+#define DCAN_IF1MSK_MXTD_USED (0x1u)
+
+
+/* IF1ARB */
+#define DCAN_IF1ARB_DIR (0x20000000u)
+#define DCAN_IF1ARB_DIR_SHIFT (0x0000001Du)
+#define DCAN_IF1ARB_DIR_RECEIVE (0x0u)
+#define DCAN_IF1ARB_DIR_TRANSMIT (0x1u)
+
+#define DCAN_IF1ARB_MSGVAL (0x80000000u)
+#define DCAN_IF1ARB_MSGVAL_SHIFT (0x0000001Fu)
+#define DCAN_IF1ARB_MSGVAL_IGNORED (0x0u)
+#define DCAN_IF1ARB_MSGVAL_USED (0x1u)
+
+#define DCAN_IF1ARB_MSK (0x1FFFFFFFu)
+#define DCAN_IF1ARB_MSK_SHIFT (0x000000000u)
+#define DCAN_IF1ARB_MSK_RECEIVE (0x0u)
+#define DCAN_IF1ARB_MSK_TRANSMIT (0x1u)
+
+#define DCAN_IF1ARB_XTD (0x40000000u)
+#define DCAN_IF1ARB_XTD_SHIFT (0x0000001Eu)
+#define DCAN_IF1ARB_XTD_11_BIT (0x0u)
+#define DCAN_IF1ARB_XTD_29_BIT (0x1u)
+
+
+/* IF1MCTL */
+#define DCAN_IF1MCTL_DATALENGTHCODE (0x0000000Fu)
+#define DCAN_IF1MCTL_DATALENGTHCODE_SHIFT (0x00000000u)
+
+#define DCAN_IF1MCTL_EOB (0x00000080u)
+#define DCAN_IF1MCTL_EOB_SHIFT (0x00000007u)
+
+#define DCAN_IF1MCTL_INTPND (0x00002000u)
+#define DCAN_IF1MCTL_INTPND_SHIFT (0x0000000Du)
+#define DCAN_IF1MCTL_INTPND_INTERRUPT (0x1u)
+#define DCAN_IF1MCTL_INTPND_NOINTERRUPT (0x0u)
+
+#define DCAN_IF1MCTL_MSGLST (0x00004000u)
+#define DCAN_IF1MCTL_MSGLST_SHIFT (0x0000000Eu)
+#define DCAN_IF1MCTL_MSGLST_MSGLOST (0x1u)
+#define DCAN_IF1MCTL_MSGLST_NOMSGLOST (0x0u)
+
+#define DCAN_IF1MCTL_NEWDAT (0x00008000u)
+#define DCAN_IF1MCTL_NEWDAT_SHIFT (0x0000000Fu)
+#define DCAN_IF1MCTL_NEWDAT_NEWDATA (0x1u)
+#define DCAN_IF1MCTL_NEWDAT_NONEWDATA (0x0u)
+
+#define DCAN_IF1MCTL_RMTEN (0x00000200u)
+#define DCAN_IF1MCTL_RMTEN_SHIFT (0x00000009u)
+#define DCAN_IF1MCTL_RMTEN_DISABLE (0x0u)
+#define DCAN_IF1MCTL_RMTEN_ENABLE (0x1u)
+
+#define DCAN_IF1MCTL_RXIE (0x00000400u)
+#define DCAN_IF1MCTL_RXIE_SHIFT (0x0000000Au)
+#define DCAN_IF1MCTL_RXIE_NOTRIGGER (0x0u)
+#define DCAN_IF1MCTL_RXIE_TRIGGER (0x1u)
+
+#define DCAN_IF1MCTL_TXIE (0x00000800u)
+#define DCAN_IF1MCTL_TXIE_SHIFT (0x0000000Bu)
+#define DCAN_IF1MCTL_TXIE_NOTRIGGER (0x0u)
+#define DCAN_IF1MCTL_TXIE_TRIGGER (0x1u)
+
+#define DCAN_IF1MCTL_TXRQST (0x00000100u)
+#define DCAN_IF1MCTL_TXRQST_SHIFT (0x00000008u)
+#define DCAN_IF1MCTL_TXRQST_NOREQUESTED (0x0u)
+#define DCAN_IF1MCTL_TXRQST_REQUESTED (0x1u)
+
+#define DCAN_IF1MCTL_UMASK (0x00001000u)
+#define DCAN_IF1MCTL_UMASK_SHIFT (0x0000000Cu)
+#define DCAN_IF1MCTL_UMASK_IGNORED (0x0u)
+#define DCAN_IF1MCTL_UMASK_MASKED (0x1u)
+
+
+/* IF1DATA */
+#define DCAN_IF1DATA_DCAN_IF1DATA (0xFFFFFFFFu)
+#define DCAN_IF1DATA_DCAN_IF1DATA_SHIFT (0x00000000u)
+
+
+/* IF1DATB */
+#define DCAN_IF1DATB_DCAN_IF1DATB (0xFFFFFFFFu)
+#define DCAN_IF1DATB_DCAN_IF1DATB_SHIFT (0x00000000u)
+
+
+/* IF2CMD */
+#define DCAN_IF2CMD_ARB (0x00200000u)
+#define DCAN_IF2CMD_ARB_SHIFT (0x00000015u)
+
+#define DCAN_IF2CMD_BUSY (0x00008000u)
+#define DCAN_IF2CMD_BUSY_SHIFT (0x0000000Fu)
+#define DCAN_IF2CMD_BUSY_NOTRANSFER (0x0u)
+#define DCAN_IF2CMD_BUSY_TRANSFER (0x1u)
+
+#define DCAN_IF2CMD_CLRINTPND (0x00080000u)
+#define DCAN_IF2CMD_CLRINTPND_SHIFT (0x00000013u)
+#define DCAN_IF2CMD_CLRINTPND_CHANGE (0x1u)
+#define DCAN_IF2CMD_CLRINTPND_NOCHANGE (0x0u)
+
+#define DCAN_IF2CMD_CONTROL (0x00100000u)
+#define DCAN_IF2CMD_CONTROL_SHIFT (0x00000014u)
+
+#define DCAN_IF2CMD_DATAA (0x00020000u)
+#define DCAN_IF2CMD_DATAA_SHIFT (0x00000011u)
+
+#define DCAN_IF2CMD_DATAB (0x00010000u)
+#define DCAN_IF2CMD_DATAB_SHIFT (0x00000010u)
+
+#define DCAN_IF2CMD_DMAACTIVE (0x00004000u)
+#define DCAN_IF2CMD_DMAACTIVE_SHIFT (0x0000000Eu)
+#define DCAN_IF2CMD_DMAACTIVE_ACTIVE (0x1u)
+#define DCAN_IF2CMD_DMAACTIVE_INACTIVE (0x0u)
+
+#define DCAN_IF2CMD_MASK (0x00400000u)
+#define DCAN_IF2CMD_MASK_SHIFT (0x00000016u)
+
+#define DCAN_IF2CMD_MESSAGENUMBER (0x000000FFu)
+#define DCAN_IF2CMD_MESSAGENUMBER_SHIFT (0x00000000u)
+
+#define DCAN_IF2CMD_TXRQST_NEWDAT (0x00040000u)
+#define DCAN_IF2CMD_TXRQST_NEWDAT_SHIFT (0x00000012u)
+
+#define DCAN_IF2CMD_WR_RD (0x00800000u)
+#define DCAN_IF2CMD_WR_RD_SHIFT (0x00000017u)
+
+
+/* IF2MSK */
+#define DCAN_IF2MSK_MDIR (0x40000000u)
+#define DCAN_IF2MSK_MDIR_SHIFT (0x00000001Eu)
+#define DCAN_IF2MSK_MDIR_NOTUSED (0x0u)
+#define DCAN_IF2MSK_MDIR_USED (0x1u)
+
+#define DCAN_IF2MSK_MSK (0x1FFFFFFFu)
+#define DCAN_IF2MSK_MSK_SHIFT (0x00000000u)
+#define DCAN_IF2MSK_MSK_NOTUSED (0x0u)
+#define DCAN_IF2MSK_MSK_USED (0x1u)
+
+#define DCAN_IF2MSK_MXTD (0x80000000u)
+#define DCAN_IF2MSK_MXTD_SHIFT (0x00000001Fu)
+#define DCAN_IF2MSK_MXTD_NOTUSED (0x0u)
+#define DCAN_IF2MSK_MXTD_USED (0x1u)
+
+
+/* IF2ARB */
+#define DCAN_IF2ARB_DIR (0x20000000u)
+#define DCAN_IF2ARB_DIR_SHIFT (0x0000001Du)
+#define DCAN_IF2ARB_DIR_RECEIVE (0x0u)
+#define DCAN_IF2ARB_DIR_TRANSMIT (0x1u)
+
+#define DCAN_IF2ARB_MSGVAL (0x80000000u)
+#define DCAN_IF2ARB_MSGVAL_SHIFT (0x0000001Fu)
+#define DCAN_IF2ARB_MSGVAL_IGNORED (0x0u)
+#define DCAN_IF2ARB_MSGVAL_USED (0x1u)
+
+#define DCAN_IF2ARB_MSK (0x1FFFFFFFu)
+#define DCAN_IF2ARB_MSK_SHIFT (0x000000000u)
+#define DCAN_IF2ARB_MSK_RECEIVE (0x0u)
+#define DCAN_IF2ARB_MSK_TRANSMIT (0x1u)
+
+#define DCAN_IF2ARB_XTD (0x40000000u)
+#define DCAN_IF2ARB_XTD_SHIFT (0x0000001Eu)
+#define DCAN_IF2ARB_XTD_11_BIT (0x0u)
+#define DCAN_IF2ARB_XTD_29_BIT (0x1u)
+
+
+/* IF2MCTL */
+#define DCAN_IF2MCTL_DATALENGTHCODE (0x0000000Fu)
+#define DCAN_IF2MCTL_DATALENGTHCODE_SHIFT (0x00000000u)
+
+#define DCAN_IF2MCTL_EOB (0x00000080u)
+#define DCAN_IF2MCTL_EOB_SHIFT (0x00000007u)
+
+#define DCAN_IF2MCTL_INTPND (0x00002000u)
+#define DCAN_IF2MCTL_INTPND_SHIFT (0x0000000Du)
+#define DCAN_IF2MCTL_INTPND_INTERRUPT (0x1u)
+#define DCAN_IF2MCTL_INTPND_NOINTERRUPT (0x0u)
+
+#define DCAN_IF2MCTL_MSGLST (0x00004000u)
+#define DCAN_IF2MCTL_MSGLST_SHIFT (0x0000000Eu)
+#define DCAN_IF2MCTL_MSGLST_MSGLOST (0x1u)
+#define DCAN_IF2MCTL_MSGLST_NOMSGLOST (0x0u)
+
+#define DCAN_IF2MCTL_NEWDAT (0x00008000u)
+#define DCAN_IF2MCTL_NEWDAT_SHIFT (0x0000000Fu)
+#define DCAN_IF2MCTL_NEWDAT_NEWDATA (0x1u)
+#define DCAN_IF2MCTL_NEWDAT_NONEWDATA (0x0u)
+
+#define DCAN_IF2MCTL_RMTEN (0x00000200u)
+#define DCAN_IF2MCTL_RMTEN_SHIFT (0x00000009u)
+#define DCAN_IF2MCTL_RMTEN_DISABLE (0x0u)
+#define DCAN_IF2MCTL_RMTEN_ENABLE (0x1u)
+
+#define DCAN_IF2MCTL_RXIE (0x00000400u)
+#define DCAN_IF2MCTL_RXIE_SHIFT (0x0000000Au)
+#define DCAN_IF2MCTL_RXIE_NOTRIGGER (0x0u)
+#define DCAN_IF2MCTL_RXIE_TRIGGER (0x1u)
+
+#define DCAN_IF2MCTL_TXIE (0x00000800u)
+#define DCAN_IF2MCTL_TXIE_SHIFT (0x0000000Bu)
+#define DCAN_IF2MCTL_TXIE_NOTRIGGER (0x0u)
+#define DCAN_IF2MCTL_TXIE_TRIGGER (0x1u)
+
+#define DCAN_IF2MCTL_TXRQST (0x00000100u)
+#define DCAN_IF2MCTL_TXRQST_SHIFT (0x00000008u)
+#define DCAN_IF2MCTL_TXRQST_NOREQUESTED (0x0u)
+#define DCAN_IF2MCTL_TXRQST_REQUESTED (0x1u)
+
+#define DCAN_IF2MCTL_UMASK (0x00001000u)
+#define DCAN_IF2MCTL_UMASK_SHIFT (0x0000000Cu)
+#define DCAN_IF2MCTL_UMASK_IGNORED (0x0u)
+#define DCAN_IF2MCTL_UMASK_MASKED (0x1u)
+
+
+/* IF2DATA */
+#define DCAN_IF2DATA_DCAN_IF2DATA (0xFFFFFFFFu)
+#define DCAN_IF2DATA_DCAN_IF2DATA_SHIFT (0x00000000u)
+
+
+/* IF2DATB */
+#define DCAN_IF2DATB_DCAN_IF2DATB (0xFFFFFFFFu)
+#define DCAN_IF2DATB_DCAN_IF2DATB_SHIFT (0x00000000u)
+
+
+/* IF3OBS */
+#define DCAN_IF3OBS_ARB (0x00000002u)
+#define DCAN_IF3OBS_ARB_SHIFT (0x00000001u)
+#define DCAN_IF3OBS_ARB_DATATOBEREAD (0x1u)
+#define DCAN_IF3OBS_ARB_NOTTOBEREAD (0x0u)
+
+#define DCAN_IF3OBS_CTRL (0x00000004u)
+#define DCAN_IF3OBS_CTRL_SHIFT (0x00000002u)
+#define DCAN_IF3OBS_CTRL_DATATOBEREAD (0x1u)
+#define DCAN_IF3OBS_CTRL_NOTTOBEREAD (0x0u)
+
+#define DCAN_IF3OBS_DATAA (0x00000008u)
+#define DCAN_IF3OBS_DATAA_SHIFT (0x00000003u)
+#define DCAN_IF3OBS_DATAA_DATATOBEREAD (0x1u)
+#define DCAN_IF3OBS_DATAA_NOTTOBEREAD (0x0u)
+
+#define DCAN_IF3OBS_DATAB (0x00000010u)
+#define DCAN_IF3OBS_DATAB_SHIFT (0x00000004u)
+#define DCAN_IF3OBS_DATAB_DATATOBEREAD (0x1u)
+#define DCAN_IF3OBS_DATAB_NOTTOBEREAD (0x0u)
+
+#define DCAN_IF3OBS_IF3SA (0x00000200u)
+#define DCAN_IF3OBS_IF3SA_SHIFT (0x00000009u)
+#define DCAN_IF3OBS_IF3SA_ALREADYREADOUT (0x0u)
+#define DCAN_IF3OBS_IF3SA_STILLTOBEREAD (0x1u)
+
+#define DCAN_IF3OBS_IF3SC (0x00000400u)
+#define DCAN_IF3OBS_IF3SC_SHIFT (0x0000000Au)
+#define DCAN_IF3OBS_IF3SC_ALREADYREADOUT (0x0u)
+#define DCAN_IF3OBS_IF3SC_STILLTOBEREAD (0x1u)
+
+#define DCAN_IF3OBS_IF3SDA (0x00000800u)
+#define DCAN_IF3OBS_IF3SDA_SHIFT (0x0000000Bu)
+#define DCAN_IF3OBS_IF3SDA_ALREADYREADOUT (0x0u)
+#define DCAN_IF3OBS_IF3SDA_STILLTOBEREAD (0x1u)
+
+#define DCAN_IF3OBS_IF3SDB (0x00001000u)
+#define DCAN_IF3OBS_IF3SDB_SHIFT (0x0000000Cu)
+#define DCAN_IF3OBS_IF3SDB_ALREADYREADOUT (0x0u)
+#define DCAN_IF3OBS_IF3SDB_STILLTOBEREAD (0x1u)
+
+#define DCAN_IF3OBS_IF3SM (0x00000100u)
+#define DCAN_IF3OBS_IF3SM_SHIFT (0x00000008u)
+#define DCAN_IF3OBS_IF3SM_ALREADYREADOUT (0x0u)
+#define DCAN_IF3OBS_IF3SM_STILLTOBEREAD (0x1u)
+
+#define DCAN_IF3OBS_IF3UPD (0x00008000u)
+#define DCAN_IF3OBS_IF3UPD_SHIFT (0x0000000Fu)
+#define DCAN_IF3OBS_IF3UPD_NEWDATALOAD (0x1u)
+#define DCAN_IF3OBS_IF3UPD_NONEWDATALOAD (0x0u)
+
+#define DCAN_IF3OBS_MASK (0x00000001u)
+#define DCAN_IF3OBS_MASK_SHIFT (0x00000000u)
+#define DCAN_IF3OBS_MASK_DATATOBEREAD (0x1u)
+#define DCAN_IF3OBS_MASK_NOTTOBEREAD (0x0u)
+
+
+/* IF3MSK */
+#define DCAN_IF3MSK_MDIR (0x40000000u)
+#define DCAN_IF3MSK_MDIR_SHIFT (0x00000001Eu)
+#define DCAN_IF3MSK_MDIR_NOTUSED (0x0u)
+#define DCAN_IF3MSK_MDIR_USED (0x1u)
+
+#define DCAN_IF3MSK_MSK (0x1FFFFFFFu)
+#define DCAN_IF3MSK_MSK_SHIFT (0x00000000u)
+#define DCAN_IF3MSK_MSK_NOTUSED (0x0u)
+#define DCAN_IF3MSK_MSK_USED (0x1u)
+
+#define DCAN_IF3MSK_MXTD (0x80000000u)
+#define DCAN_IF3MSK_MXTD_SHIFT (0x00000001Fu)
+#define DCAN_IF3MSK_MXTD_NOTUSED (0x0u)
+#define DCAN_IF3MSK_MXTD_USED (0x1u)
+
+
+/* IF3ARB */
+#define DCAN_IF3ARB_DIR (0x20000000u)
+#define DCAN_IF3ARB_DIR_SHIFT (0x0000001Du)
+#define DCAN_IF3ARB_DIR_RECEIVE (0x0u)
+#define DCAN_IF3ARB_DIR_TRANSMIT (0x1u)
+
+#define DCAN_IF3ARB_MSGVAL (0x80000000u)
+#define DCAN_IF3ARB_MSGVAL_SHIFT (0x0000001Fu)
+#define DCAN_IF3ARB_MSGVAL_IGNORED (0x0u)
+#define DCAN_IF3ARB_MSGVAL_USED (0x1u)
+
+#define DCAN_IF3ARB_MSK (0x1FFFFFFFu)
+#define DCAN_IF3ARB_MSK_SHIFT (0x000000000u)
+#define DCAN_IF3ARB_MSK_RECEIVE (0x0u)
+#define DCAN_IF3ARB_MSK_TRANSMIT (0x1u)
+
+#define DCAN_IF3ARB_XTD (0x40000000u)
+#define DCAN_IF3ARB_XTD_SHIFT (0x0000001Eu)
+#define DCAN_IF3ARB_XTD_11_BIT (0x0u)
+#define DCAN_IF3ARB_XTD_29_BIT (0x1u)
+
+
+/* IF3MCTL */
+#define DCAN_IF3MCTL_DATALENGTHCODE (0x0000000Fu)
+#define DCAN_IF3MCTL_DATALENGTHCODE_SHIFT (0x00000000u)
+
+#define DCAN_IF3MCTL_EOB (0x00000080u)
+#define DCAN_IF3MCTL_EOB_SHIFT (0x00000007u)
+
+#define DCAN_IF3MCTL_INTPND (0x00002000u)
+#define DCAN_IF3MCTL_INTPND_SHIFT (0x0000000Du)
+#define DCAN_IF3MCTL_INTPND_INTERRUPT (0x1u)
+#define DCAN_IF3MCTL_INTPND_NOINTERRUPT (0x0u)
+
+#define DCAN_IF3MCTL_MSGLST (0x00004000u)
+#define DCAN_IF3MCTL_MSGLST_SHIFT (0x0000000Eu)
+#define DCAN_IF3MCTL_MSGLST_MSGLOST (0x1u)
+#define DCAN_IF3MCTL_MSGLST_NOMSGLOST (0x0u)
+
+#define DCAN_IF3MCTL_NEWDAT (0x00008000u)
+#define DCAN_IF3MCTL_NEWDAT_SHIFT (0x0000000Fu)
+#define DCAN_IF3MCTL_NEWDAT_NEWDATA (0x1u)
+#define DCAN_IF3MCTL_NEWDAT_NONEWDATA (0x0u)
+
+#define DCAN_IF3MCTL_RMTEN (0x00000200u)
+#define DCAN_IF3MCTL_RMTEN_SHIFT (0x00000009u)
+#define DCAN_IF3MCTL_RMTEN_DISABLE (0x0u)
+#define DCAN_IF3MCTL_RMTEN_ENABLE (0x1u)
+
+#define DCAN_IF3MCTL_RXIE (0x00000400u)
+#define DCAN_IF3MCTL_RXIE_SHIFT (0x0000000Au)
+#define DCAN_IF3MCTL_RXIE_NOTRIGGER (0x0u)
+#define DCAN_IF3MCTL_RXIE_TRIGGER (0x1u)
+
+#define DCAN_IF3MCTL_TXIE (0x00000800u)
+#define DCAN_IF3MCTL_TXIE_SHIFT (0x0000000Bu)
+#define DCAN_IF3MCTL_TXIE_NOTRIGGER (0x0u)
+#define DCAN_IF3MCTL_TXIE_TRIGGER (0x1u)
+
+#define DCAN_IF3MCTL_TXRQST (0x00000100u)
+#define DCAN_IF3MCTL_TXRQST_SHIFT (0x00000008u)
+#define DCAN_IF3MCTL_TXRQST_NOREQUESTED (0x0u)
+#define DCAN_IF3MCTL_TXRQST_REQUESTED (0x1u)
+
+#define DCAN_IF3MCTL_UMASK (0x00001000u)
+#define DCAN_IF3MCTL_UMASK_SHIFT (0x0000000Cu)
+#define DCAN_IF3MCTL_UMASK_IGNORED (0x0u)
+#define DCAN_IF3MCTL_UMASK_MASKED (0x1u)
+
+
+/* IF3DATA */
+#define DCAN_IF3DATA_DCAN_IF3DATA (0xFFFFFFFFu)
+#define DCAN_IF3DATA_DCAN_IF3DATA_SHIFT (0x00000000u)
+
+
+/* IF3DATB */
+#define DCAN_IF3DATB_DCAN_IF3DATB (0xFFFFFFFFu)
+#define DCAN_IF3DATB_DCAN_IF3DATB_SHIFT (0x00000000u)
+
+
+/* IF3UPD12 */
+#define DCAN_IF3UPD12_IF3UPDEN_16_1 (0x0000FFFFu)
+#define DCAN_IF3UPD12_IF3UPDEN_16_1_SHIFT (0x00000001u)
+
+#define DCAN_IF3UPD12_IF3UPDEN_32_17 (0xFFFF0000u)
+#define DCAN_IF3UPD12_IF3UPDEN_32_17_SHIFT (0x00000010u)
+
+
+/* IF3UPD34 */
+#define DCAN_IF3UPD34_IF3UPDEN_48_33 (0x0000FFFFu)
+#define DCAN_IF3UPD34_IF3UPDEN_48_33_SHIFT (0x00000001u)
+
+#define DCAN_IF3UPD34_IF3UPDEN_64_49 (0xFFFF0000u)
+#define DCAN_IF3UPD34_IF3UPDEN_64_49_SHIFT (0x00000010u)
+
+
+/* IF3UPD56 */
+#define DCAN_IF3UPD56_IF3UPDEN_80_65 (0x0000FFFFu)
+#define DCAN_IF3UPD56_IF3UPDEN_80_65_SHIFT (0x00000001u)
+
+#define DCAN_IF3UPD56_IF3UPDEN_96_81 (0xFFFF0000u)
+#define DCAN_IF3UPD56_IF3UPDEN_96_81_SHIFT (0x00000010u)
+
+
+/* IF3UPD78 */
+#define DCAN_IF3UPD78_IF3UPDEN_112_97 (0x0000FFFFu)
+#define DCAN_IF3UPD78_IF3UPDEN_112_97_SHIFT (0x00000001u)
+
+#define DCAN_IF3UPD78_IF3UPDEN_128_113 (0xFFFF0000u)
+#define DCAN_IF3UPD78_IF3UPDEN_128_113_SHIFT (0x00000010u)
+
+
+/* TIOC */
+#define DCAN_TIOC_DIR (0x00000004u)
+#define DCAN_TIOC_DIR_SHIFT (0x00000002u)
+#define DCAN_TIOC_DIR_INPUT (0x0u)
+#define DCAN_TIOC_DIR_OUTPUT (0x1u)
+
+#define DCAN_TIOC_FUNC (0x00000008u)
+#define DCAN_TIOC_FUNC_SHIFT (0x00000003u)
+#define DCAN_TIOC_FUNC_FUNCTIONAL (0x1u)
+#define DCAN_TIOC_FUNC_GIO (0x0u)
+
+#define DCAN_TIOC_IN (0x00000001u)
+#define DCAN_TIOC_IN_SHIFT (0x00000000u)
+#define DCAN_TIOC_IN_HIGH (0x1u)
+#define DCAN_TIOC_IN_LOW (0x0u)
+
+#define DCAN_TIOC_OD (0x00010000u)
+#define DCAN_TIOC_OD_SHIFT (0x00000010u)
+#define DCAN_TIOC_OD_OPEN_DRAIN (0x1u)
+#define DCAN_TIOC_OD_PUSH_PULL (0x0u)
+
+#define DCAN_TIOC_OUT (0x00000002u)
+#define DCAN_TIOC_OUT_SHIFT (0x00000001u)
+#define DCAN_TIOC_OUT_HIGH (0x1u)
+#define DCAN_TIOC_OUT_LOW (0x0u)
+
+#define DCAN_TIOC_PD (0x00020000u)
+#define DCAN_TIOC_PD_SHIFT (0x00000011u)
+#define DCAN_TIOC_PD_ACTIVE (0x0u)
+#define DCAN_TIOC_PD_DISABLED (0x1u)
+
+#define DCAN_TIOC_PU (0x00040000u)
+#define DCAN_TIOC_PU_SHIFT (0x00000011u)
+#define DCAN_TIOC_PU_PULL_DOWN (0x0u)
+#define DCAN_TIOC_PU_PULL_UP (0x1u)
+
+
+/* RIOC */
+#define DCAN_RIOC_DIR (0x00000004u)
+#define DCAN_RIOC_DIR_SHIFT (0x00000002u)
+#define DCAN_RIOC_DIR_INPUT (0x0u)
+#define DCAN_RIOC_DIR_OUTPUT (0x1u)
+
+#define DCAN_RIOC_FUNC (0x00000008u)
+#define DCAN_RIOC_FUNC_SHIFT (0x00000003u)
+#define DCAN_RIOC_FUNC_FUNCTIONAL (0x1u)
+#define DCAN_RIOC_FUNC_GIO (0x0u)
+
+#define DCAN_RIOC_IN (0x00000001u)
+#define DCAN_RIOC_IN_SHIFT (0x00000000u)
+#define DCAN_RIOC_IN_HIGH (0x1u)
+#define DCAN_RIOC_IN_LOW (0x0u)
+
+#define DCAN_RIOC_OD (0x00010000u)
+#define DCAN_RIOC_OD_SHIFT (0x00000010u)
+#define DCAN_RIOC_OD_OPEN_DRAIN (0x1u)
+#define DCAN_RIOC_OD_PUSH_PULL (0x0u)
+
+#define DCAN_RIOC_OUT (0x00000002u)
+#define DCAN_RIOC_OUT_SHIFT (0x00000001u)
+#define DCAN_RIOC_OUT_HIGH (0x1u)
+#define DCAN_RIOC_OUT_LOW (0x0u)
+
+#define DCAN_RIOC_PD (0x00020000u)
+#define DCAN_RIOC_PD_SHIFT (0x00000011u)
+#define DCAN_RIOC_PD_ACTIVE (0x0u)
+#define DCAN_RIOC_PD_DISABLED (0x1u)
+
+#define DCAN_RIOC_PU (0x00020000u)
+#define DCAN_RIOC_PU_SHIFT (0x00000011u)
+#define DCAN_RIOC_PU_PULL_DOWN (0x0u)
+#define DCAN_RIOC_PU_PULL_UP (0x1u)
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/bsps/arm/beagle/include/bsp/am335x_dcan.h b/bsps/arm/beagle/include/bsp/am335x_dcan.h
new file mode 100644
index 0000000000..c83f3a91ab
--- /dev/null
+++ b/bsps/arm/beagle/include/bsp/am335x_dcan.h
@@ -0,0 +1,106 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+
+/**
+ * @file
+ *
+ * @ingroup CANBus
+ *
+ * @brief Controller Area Network (DCAN) Controller Implementation
+ *
+ */
+
+/*
+ * Copyright (C) 2022 Prashanth S (fishesprashanth@gmail.com)
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _BSP_AM335X_CAN_H
+#define _BSP_AM335X_CAN_H
+
+#include <stdio.h>
+
+#include <dev/can/can.h>
+#include <bsp.h>
+
+#define CAN_NODES 2
+
+#define CAN_NUM_OF_MSG_OBJS (0x40)
+#define CAN_RX_MSG_OBJ_NUM (0x20)
+#define CAN_TX_MSG_OBJ_NUM (0x20)
+
+#define CAN_EXT_MSG (0x00000001)
+
+#define CAN_TX_MSG_OBJ_START_NUM ((CAN_NUM_OF_MSG_OBJS / 2) + 1)
+#define CAN_TX_MSG_OBJ_END_NUM (CAN_NUM_OF_MSG_OBJS)
+
+#define CAN_RX_MSG_OBJ_START_NUM (1)
+#define CAN_RX_MSG_OBJ_END_NUM (CAN_NUM_OF_MSG_OBJS / 2)
+
+#define DCAN_IFCMD_MSG_NUM_SHIFT (0) /* Bits 0-7: Number of message object in message RAM which is used for data transfer */
+#define DCAN_IFCMD_MSG_NUM_MASK (0xff << DCAN_IFCMD_MSG_NUM_SHIFT)
+#define DCAN_IFCMD_MSG_NUM(n) (((unsigned int)(n) & DCAN_IFCMD_MSG_NUM_MASK) << DCAN_IFCMD_MSG_NUM_SHIFT)
+
+#define CONTROL_STATUS_SYSBOOT1_MASK (3 << CONTROL_STATUS_SYSBOOT1_SHIFT)
+#define CONTROL_STATUS_SYSBOOT1_19p2MHZ (0 << CONTROL_STATUS_SYSBOOT1_SHIFT)
+#define CONTROL_STATUS_SYSBOOT1_24MHZ (1 << CONTROL_STATUS_SYSBOOT1_SHIFT)
+#define CONTROL_STATUS_SYSBOOT1_25MHZ (2 << CONTROL_STATUS_SYSBOOT1_SHIFT)
+#define CONTROL_STATUS_SYSBOOT1_26MHZ (3 << CONTROL_STATUS_SYSBOOT1_SHIFT)
+
+#define CONFIG_AM335X_CAN_TSEG1 6
+#define CONFIG_AM335X_CAN_TSEG2 1
+#define CAN_BIT_QUANTA (CONFIG_AM335X_CAN_TSEG1 + CONFIG_AM335X_CAN_TSEG2 + 1)
+#define CAN_CLOCK_FREQUENCY (am335x_get_sysclk())
+
+struct am335x_dcan_irq {
+ uint32_t dcan_intr0;
+ uint32_t dcan_intr1;
+ uint32_t dcan_parity;
+};
+
+struct am335x_dcan_priv {
+ uint32_t node;
+ uint32_t base_reg;
+ uint32_t baudrate;
+ struct can_bus *bus;
+ struct am335x_dcan_irq irq;
+};
+
+int dcan_init(struct am335x_dcan_priv *dcan_priv);
+void beagle_can_init(void *node);
+
+void dcan_init_ops(struct am335x_dcan_priv *priv);
+
+#define can_putreg(priv, off, val) \
+ do { \
+ REG(priv->base_reg + off) = val; \
+ CAN_DEBUG_REG("%s:%d %08x<-%08x\n", __FILE__, __LINE__, priv->base_reg + off, val); \
+ } while (0)
+
+static inline uint32_t can_getreg(struct am335x_dcan_priv *priv, uint32_t off)
+{
+ CAN_DEBUG_REG("can_getreg 0x%08x = 0x%08x\n", priv->base_reg + off,
+ REG(priv->base_reg + off));
+ return REG(priv->base_reg + off);
+}
+
+#endif /* _BSP_AM335X_CAN_H */
diff --git a/bsps/arm/beagle/include/bsp/hw_control_AM335x.h b/bsps/arm/beagle/include/bsp/hw_control_AM335x.h
new file mode 100755
index 0000000000..c3312f92fe
--- /dev/null
+++ b/bsps/arm/beagle/include/bsp/hw_control_AM335x.h
@@ -0,0 +1,7794 @@
+
+
+/**
+ * @Component: CONTROL
+ *
+ * @Filename: ../../CredDataBase/CONTROL_cred.h
+ *
+ ============================================================================ */
+/*
+* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+*/
+/*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+
+#ifndef _HW_CONTROL_H_
+#define _HW_CONTROL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***********************************************************************\
+ * Register arrays Definition
+\***********************************************************************/
+
+
+/***********************************************************************\
+ * Bundle arrays Definition
+\***********************************************************************/
+
+
+/***********************************************************************\
+ * Bundles Definition
+\***********************************************************************/
+
+
+
+/*************************************************************************\
+ * Registers Definition
+\*************************************************************************/
+
+#define CONTROL_REVISION (0x0)
+#define CONTROL_HWINFO (0x4)
+#define CONTROL_SYSCONFIG (0x10)
+#define CONTROL_STATUS (0x40)
+#define CONTROL_BOOTSTAT (0x44)
+#define CONTROL_SEC_CTRL (0x100)
+#define CONTROL_SEC_SW (0x104)
+#define CONTROL_SEC_EMU (0x108)
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG (0x110)
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2 (0x114)
+#define CONTROL_SW_CFG (0x118)
+#define CONTROL_SW_CCFG (0x11c)
+#define CONTROL_MPK(n) (0x120 + (n * 4))
+#define CONTROL_SWRV(n) (0x140 + (n * 4))
+#define CONTROL_SEC_TAP (0x180)
+#define CONTROL_SEC_TAP_CMDIN (0x184)
+#define CONTROL_SEC_TAP_CMDOUT (0x188)
+#define CONTROL_SEC_TAP_DATIN (0x18c)
+#define CONTROL_SEC_TAP_DATOUT (0x190)
+#define CONTROL_MREQDOMAIN_EXP1 (0x198)
+#define CONTROL_MREQDOMAIN_EXP2 (0x19c)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0 (0x1a0)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1 (0x1a4)
+#define CONTROL_L4_HW_FW_EXP_VAL_CONF (0x1a8)
+#define CONTROL_SEC_LOAD_FW_EXP_VAL (0x1ac)
+#define CONTROL_SEC_CTRL_RO (0x1b4)
+#define CONTROL_EMIF_OBFUSCATION_KEY (0x1b8)
+#define CONTROL_SEC_CLK_CTRL (0x1bc)
+#define CONTROL_MREQDOMAIN_EXP3 (0x1d4)
+#define CONTROL_CEK(n) (0x200 + (n * 4))
+#define CONTROL_CEK_BCH(n) (0x210 + (n * 4))
+#define CONTROL_MSV_0 (0x224)
+#define CONTROL_MSV_BCH(n) (0x228 + (n * 4))
+#define CONTROL_SEC_STATUS (0x240)
+#define CONTROL_SECMEM_STATUS (0x244)
+#define CONTROL_SEC_ERR_STAT_FUNC(n) (0x248 + (n * 4))
+#define CONTROL_SEC_ERR_STAT_DBUG(n) (0x250 + (n * 4))
+#define CONTROL_KEK_SW(n) (0x260 + (n * 4))
+#define CONTROL_CMPK_BCH(n) (0x280 + (n * 4))
+#define CONTROL_CMPK(n) (0x2b0 + (n * 4))
+#define CONTROL_SSM_END_FAST_SECRAM (0x300)
+#define CONTROL_SSM_FIREWALL_CONTROLLER (0x304)
+#define CONTROL_SSM_START_SECURE_STACKED_RAM (0x308)
+#define CONTROL_SSM_END_SECURE_STACKED_RAM (0x30c)
+#define CONTROL_SSM_START_SPM_STACK (0x310)
+#define CONTROL_SSM_END_SPM_STACK (0x314)
+#define CONTROL_SSM_START_MONITOR_RAMCODE (0x318)
+#define CONTROL_SSM_END_MONITOR_RAMCODE (0x31c)
+#define CONTROL_SSM_END_MONITOR_RAMDATA (0x320)
+#define CONTROL_SSM_START_MONITOR_CODE (0x324)
+#define CONTROL_SSM_END_MONITOR_CODE (0x328)
+#define CONTROL_SSM_START_MONITOR_PERIPH (0x32c)
+#define CONTROL_SSM_END_MONITOR_PERIPH (0x330)
+#define CONTROL_SSM_START_MONITOR_STACK (0x334)
+#define CONTROL_SSM_END_MONITOR_STACK (0x338)
+#define CONTROL_SSM_START_MONITOR_RAMCODE_ETM (0x33c)
+#define CONTROL_SSM_END_MONITOR_RAMCODE_ETM (0x340)
+#define CONTROL_SSM_END_MONITOR_RAMDATA_ETM (0x344)
+#define CONTROL_SSM_START_MONITOR_CODE_ETM (0x348)
+#define CONTROL_SSM_END_MONITOR_CODE_ETM (0x34c)
+#define CONTROL_SSM_START_MONITOR_STACK_ETM (0x350)
+#define CONTROL_SSM_END_MONITOR_STACK_ETM (0x354)
+#define CONTROL_SSM_START_MONITOR_SHARED_ETM (0x358)
+#define CONTROL_SSM_END_MONITOR_SHARED_ETM (0x35c)
+#define CONTROL_SSM_START_MONITOR_PERIPH_ETM (0x360)
+#define CONTROL_SSM_END_MONITOR_PERIPH_ETM (0x364)
+#define CONTROL_SSM_CPSR_MODE_ENFC (0x368)
+#define CONTROL_SSM_END_L3_SECRAM (0x36c)
+#define CONTROL_CORTEX_VBBLDO_CTRL (0x41c)
+#define CONTROL_CORE_SLDO_CTRL (0x428)
+#define CONTROL_MPU_SLDO_CTRL (0x42c)
+#define CONTROL_REFCLK_LJCBLDO_CTRL (0x440)
+#define CONTROL_CLK32KDIVRATIO_CTRL (0x444)
+#define CONTROL_BANDGAP_CTRL (0x448)
+#define CONTROL_BANDGAP_TRIM (0x44c)
+#define CONTROL_PLL_CLKINPULOW_CTRL (0x458)
+#define CONTROL_MOSC_CTRL (0x468)
+#define CONTROL_RCOSC_CTRL (0x46c)
+#define CONTROL_DEEPSLEEP_CTRL (0x470)
+#define CONTROL_PE_SCRATCHPAD(n) (0x500 + (n * 4))
+#define CONTROL_DEVICE_ID (0x600)
+#define CONTROL_DEV_FEATURE (0x604)
+#define CONTROL_INIT_PRIORITY(n) (0x608 + (n * 4))
+#define CONTROL_MMU_CFG (0x610)
+#define CONTROL_TPTC_CFG (0x614)
+#define CONTROL_OCMC_CFG (0x618)
+#define CONTROL_USB_CTRL(n) (0x620 + (n * 8))
+#define CONTROL_USB_STS(n) (0x624 + (n * 8))
+#define CONTROL_MAC_ID_LO(n) (0x630 + (n * 8))
+#define CONTROL_MAC_ID_HI(n) (0x634 + (n * 8))
+#define CONTROL_DCAN_RAMINIT (0x644)
+#define CONTROL_USB_WKUP_CTRL (0x648)
+#define CONTROL_GMII_SEL (0x650)
+#define CONTROL_PWMSS_CTRL (0x664)
+#define CONTROL_MREQPRIO(n) (0x670 + (n * 4))
+#define CONTROL_HW_EVENT_SEL_GRP(n) (0x690 + (n * 4))
+#define CONTROL_SMRT_CTRL (0x6a0)
+#define CONTROL_SABTOOTH_HW_DEBUG_SEL (0x6a4)
+#define CONTROL_SABTOOTH_HW_DBG_INFO (0x6a8)
+#define CONTROL_MRGN_MODE(n) (0x6c0 + (n * 4))
+#define CONTROL_VDD_MPU_OPP(n) (0x770 + (n * 4))
+#define CONTROL_VDD_MPU_OPP_TURBO (0x77c)
+#define CONTROL_VDD_CORE_OPP(n) (0x7b8 + (n * 4))
+#define CONTROL_BB_SCALE (0x7d0)
+#define CONTROL_USB_VID_PID (0x7f4)
+#define CONTROL_EFUSE_SMA (0x7fc)
+#define CONTROL_CONF_GPMC_AD(n) (0x800 + (n * 4))
+#define CONTROL_CONF_GPMC_A(n) (0x840 + (n * 4))
+#define CONTROL_CONF_GPMC_WAIT0 (0x870)
+#define CONTROL_CONF_GPMC_WPN (0x874)
+#define CONTROL_CONF_GPMC_BE1N (0x878)
+#define CONTROL_CONF_GPMC_CSN(n) (0x87c + (n * 4))
+#define CONTROL_CONF_GPMC_CLK (0x88c)
+#define CONTROL_CONF_GPMC_ADVN_ALE (0x890)
+#define CONTROL_CONF_GPMC_OEN_REN (0x894)
+#define CONTROL_CONF_GPMC_WEN (0x898)
+#define CONTROL_CONF_GPMC_BE0N_CLE (0x89c)
+#define CONTROL_CONF_LCD_DATA(n) (0x8a0 + (n * 4))
+#define CONTROL_CONF_LCD_VSYNC (0x8e0)
+#define CONTROL_CONF_LCD_HSYNC (0x8e4)
+#define CONTROL_CONF_LCD_PCLK (0x8e8)
+#define CONTROL_CONF_LCD_AC_BIAS_EN (0x8ec)
+#define CONTROL_CONF_MMC0_DAT3 (0x8f0)
+#define CONTROL_CONF_MMC0_DAT2 (0x8f4)
+#define CONTROL_CONF_MMC0_DAT1 (0x8f8)
+#define CONTROL_CONF_MMC0_DAT0 (0x8fc)
+#define CONTROL_CONF_MMC0_CLK (0x900)
+#define CONTROL_CONF_MMC0_CMD (0x904)
+#define CONTROL_CONF_MII1_COL (0x908)
+#define CONTROL_CONF_MII1_CRS (0x90c)
+#define CONTROL_CONF_MII1_RXERR (0x910)
+#define CONTROL_CONF_MII1_TXEN (0x914)
+#define CONTROL_CONF_MII1_RXDV (0x918)
+#define CONTROL_CONF_MII1_TXD3 (0x91c)
+#define CONTROL_CONF_MII1_TXD2 (0x920)
+#define CONTROL_CONF_MII1_TXD1 (0x924)
+#define CONTROL_CONF_MII1_TXD0 (0x928)
+#define CONTROL_CONF_MII1_TXCLK (0x92c)
+#define CONTROL_CONF_MII1_RXCLK (0x930)
+#define CONTROL_CONF_MII1_RXD3 (0x934)
+#define CONTROL_CONF_MII1_RXD2 (0x938)
+#define CONTROL_CONF_MII1_RXD1 (0x93c)
+#define CONTROL_CONF_MII1_RXD0 (0x940)
+#define CONTROL_CONF_RMII1_REFCLK (0x944)
+#define CONTROL_CONF_MDIO_DATA (0x948)
+#define CONTROL_CONF_MDIO_CLK (0x94c)
+#define CONTROL_CONF_SPI0_SCLK (0x950)
+#define CONTROL_CONF_SPI0_D0 (0x954)
+#define CONTROL_CONF_SPI0_D1 (0x958)
+#define CONTROL_CONF_SPI0_CS0 (0x95c)
+#define CONTROL_CONF_SPI0_CS1 (0x960)
+#define CONTROL_CONF_ECAP0_IN_PWM0_OUT (0x964)
+#define CONTROL_CONF_UART_CTSN(n) (0x968 + ((n) * 0x10))
+#define CONTROL_CONF_UART_RTSN(n) (0x96c + ((n) * 0x10))
+#define CONTROL_CONF_UART_RXD(n) (0x970 + ((n) * 0x10))
+#define CONTROL_CONF_UART_TXD(n) (0x974 + ((n) * 0x10))
+#define CONTROL_CONF_I2C0_SDA (0x988)
+#define CONTROL_CONF_I2C0_SCL (0x98c)
+#define CONTROL_CONF_MCASP0_ACLKX (0x990)
+#define CONTROL_CONF_MCASP0_FSX (0x994)
+#define CONTROL_CONF_MCASP0_AXR0 (0x998)
+#define CONTROL_CONF_MCASP0_AHCLKR (0x99c)
+#define CONTROL_CONF_MCASP0_ACLKR (0x9a0)
+#define CONTROL_CONF_MCASP0_FSR (0x9a4)
+#define CONTROL_CONF_MCASP0_AXR1 (0x9a8)
+#define CONTROL_CONF_MCASP0_AHCLKX (0x9ac)
+#define CONTROL_CONF_XDMA_EVENT_INTR(n) (0x9b0 + (n * 4))
+#define CONTROL_CONF_NRESETIN_OUT (0x9b8)
+#define CONTROL_CONF_PORZ (0x9bc)
+#define CONTROL_CONF_NNMI (0x9c0)
+#define CONTROL_CONF_OSC_IN(n) (0x9c4 + (n * 0x24))
+#define CONTROL_CONF_OSC_OUT(n) (0x9c8 + (n * 0x24))
+#define CONTROL_CONF_OSC_VSS(n) (0x9cc + (n * 0x24))
+#define CONTROL_CONF_TMS (0x9d0)
+#define CONTROL_CONF_TDI (0x9d4)
+#define CONTROL_CONF_TDO (0x9d8)
+#define CONTROL_CONF_TCK (0x9dc)
+#define CONTROL_CONF_NTRST (0x9e0)
+#define CONTROL_CONF_EMU(n) (0x9e4 + (n * 4))
+#define CONTROL_CONF_RTC_PORZ (0x9f8)
+#define CONTROL_CONF_PMIC_POWER_EN (0x9fc)
+#define CONTROL_CONF_EXT_WAKEUP (0xa00)
+#define CONTROL_CONF_ENZ_KALDO_1P8V (0xa04)
+#define CONTROL_CONF_USB_DM(n) (0xa08 + ((n) * 0x18))
+#define CONTROL_CONF_USB_DP(n) (0xa0c + ((n) * 0x18))
+#define CONTROL_CONF_USB_CE(n) (0xa10 + ((n) * 0x18))
+#define CONTROL_CONF_USB_ID(n) (0xa14 + ((n) * 0x18))
+#define CONTROL_CONF_USB_VBUS(n) (0xa18 + ((n) * 0x18))
+#define CONTROL_CONF_USB_DRVVBUS(n) (0xa1c + ((n) * 0x18))
+#define CONTROL_CONF_DDR_RESETN (0xa38)
+#define CONTROL_CONF_DDR_CSN0 (0xa3c)
+#define CONTROL_CONF_DDR_CKE (0xa40)
+#define CONTROL_CONF_DDR_CK (0xa44)
+#define CONTROL_CONF_DDR_NCK (0xa48)
+#define CONTROL_CONF_DDR_CASN (0xa4c)
+#define CONTROL_CONF_DDR_RASN (0xa50)
+#define CONTROL_CONF_DDR_WEN (0xa54)
+#define CONTROL_CONF_DDR_BA(n) (0xa58 + (n * 4))
+#define CONTROL_CONF_DDR_A(n) (0xa64 + (n * 4))
+#define CONTROL_CONF_DDR_ODT (0xaa4)
+#define CONTROL_CONF_DDR_D(n) (0xaa8 + (n * 4))
+#define CONTROL_CONF_DDR_DQM(n) (0xae8 + (n * 4))
+#define CONTROL_CONF_DDR_DQS(n) (0xaf0 + (n * 8))
+#define CONTROL_CONF_DDR_DQSN(n) (0xaf4 + (n * 8))
+#define CONTROL_CONF_DDR_VREF (0xb00)
+#define CONTROL_CONF_DDR_VTP (0xb04)
+#define CONTROL_CONF_DDR_STRBEN(n) (0xb08 + (n * 4))
+#define CONTROL_CONF_AIN0 (0xb2c)
+#define CONTROL_CONF_AIN1 (0xb28)
+#define CONTROL_CONF_AIN2 (0xb24)
+#define CONTROL_CONF_AIN3 (0xb20)
+#define CONTROL_CONF_AIN4 (0xb1c)
+#define CONTROL_CONF_AIN5 (0xb18)
+#define CONTROL_CONF_AIN6 (0xb14)
+#define CONTROL_CONF_AIN7 (0xb10)
+#define CONTROL_CONF_VREFP (0xb30)
+#define CONTROL_CONF_VREFN (0xb34)
+#define CONTROL_CONF_AVDD (0xb38)
+#define CONTROL_CONF_AVSS (0xb3c)
+#define CONTROL_CONF_IFORCE (0xb40)
+#define CONTROL_CONF_VSENSE (0xb44)
+#define CONTROL_CONF_TESTOUT (0xb48)
+#define CONTROL_CQDETECT_STATUS (0xe00)
+#define CONTROL_DDR_IO_CTRL (0xe04)
+#define CONTROL_VTP_CTRL (0xe0c)
+#define CONTROL_VREF_CTRL (0xe14)
+#define CONTROL_SERDES_REFCLK_CTL (0xe24)
+#define CONTROL_TPCC_EVT_MUX_0_3 (0xf90)
+#define CONTROL_TPCC_EVT_MUX_4_7 (0xf94)
+#define CONTROL_TPCC_EVT_MUX_8_11 (0xf98)
+#define CONTROL_TPCC_EVT_MUX_12_15 (0xf9c)
+#define CONTROL_TPCC_EVT_MUX_16_19 (0xfa0)
+#define CONTROL_TPCC_EVT_MUX_20_23 (0xfa4)
+#define CONTROL_TPCC_EVT_MUX_24_27 (0xfa8)
+#define CONTROL_TPCC_EVT_MUX_28_31 (0xfac)
+#define CONTROL_TPCC_EVT_MUX_32_35 (0xfb0)
+#define CONTROL_TPCC_EVT_MUX_36_39 (0xfb4)
+#define CONTROL_TPCC_EVT_MUX_40_43 (0xfb8)
+#define CONTROL_TPCC_EVT_MUX_44_47 (0xfbc)
+#define CONTROL_TPCC_EVT_MUX_48_51 (0xfc0)
+#define CONTROL_TPCC_EVT_MUX_52_55 (0xfc4)
+#define CONTROL_TPCC_EVT_MUX_56_59 (0xfc8)
+#define CONTROL_TPCC_EVT_MUX_60_63 (0xfcc)
+#define CONTROL_TIMER_EVT_CAPT (0xfd0)
+#define CONTROL_ECAP_EVT_CAPT (0xfd4)
+#define CONTROL_ADC_EVT_CAPT (0xfd8)
+#define CONTROL_RESET_ISO (0x1000)
+#define CONTROL_SMA(n) (0x1318 + (n * 8))
+#define CONTROL_DDR_CKE_CTRL (0x131c)
+#define CONTROL_M3_TXEV_EOI (0x1324)
+#define CONTROL_IPC_MSG_REG(n) (0x1328 + (n * 4))
+#define CONTROL_DDR_CMD_IOCTRL(n) (0x1404 + (n * 4))
+#define CONTROL_DDR_DATA_IOCTRL(n) (0x1440 + (n * 4))
+
+
+#define CONTROL_CONF_PULLUDDISABLE 0x00000008
+#define CONTROL_CONF_PULLUPSEL 0x00000010
+#define CONTROL_CONF_RXACTIVE 0x00000020
+#define CONTROL_CONF_SLOWSLEW 0x00000040
+#define CONTROL_CONF_MUXMODE(n) (n)
+
+
+/**************************************************************************\
+ * Field Definition Macros
+\**************************************************************************/
+
+/* CONTROL_REVISION */
+#define CONTROL_REVISION_IP_REV_CUSTOM (0x000000C0u)
+#define CONTROL_REVISION_IP_REV_CUSTOM_SHIFT (0x00000006u)
+
+#define CONTROL_REVISION_IP_REV_FUNC (0x0FFF0000u)
+#define CONTROL_REVISION_IP_REV_FUNC_SHIFT (0x00000010u)
+
+#define CONTROL_REVISION_IP_REV_MAJOR (0x00000700u)
+#define CONTROL_REVISION_IP_REV_MAJOR_SHIFT (0x00000008u)
+
+#define CONTROL_REVISION_IP_REV_MINOR (0x0000003Fu)
+#define CONTROL_REVISION_IP_REV_MINOR_SHIFT (0x00000000u)
+
+#define CONTROL_REVISION_IP_REV_RTL (0x0000F800u)
+#define CONTROL_REVISION_IP_REV_RTL_SHIFT (0x0000000Bu)
+
+#define CONTROL_REVISION_IP_REV_SCHEME (0xC0000000u)
+#define CONTROL_REVISION_IP_REV_SCHEME_SHIFT (0x0000001Eu)
+
+
+/* CONTROL_HWINFO */
+#define CONTROL_HWINFO_IP_HWINFO (0xFFFFFFFFu)
+#define CONTROL_HWINFO_IP_HWINFO_SHIFT (0x00000000u)
+
+
+/* CONTROL_SYSCONFIG */
+#define CONTROL_SYSCONFIG_FREEEMU (0x00000002u)
+#define CONTROL_SYSCONFIG_FREEEMU_SHIFT (0x00000001u)
+
+#define CONTROL_SYSCONFIG_IDLEMODE (0x0000000Cu)
+#define CONTROL_SYSCONFIG_IDLEMODE_SHIFT (0x00000002u)
+
+#define CONTROL_SYSCONFIG_RSVD2 (0xFFFFFFC0u)
+#define CONTROL_SYSCONFIG_RSVD2_SHIFT (0x00000006u)
+
+#define CONTROL_SYSCONFIG_STANDBY (0x00000030u)
+#define CONTROL_SYSCONFIG_STANDBY_SHIFT (0x00000004u)
+
+
+/* CONTROL_STATUS */
+#define CONTROL_STATUS_ADMUX (0x000C0000u)
+#define CONTROL_STATUS_ADMUX_SHIFT (0x00000012u)
+
+#define CONTROL_STATUS_BW (0x00010000u)
+#define CONTROL_STATUS_BW_SHIFT (0x00000010u)
+
+#define CONTROL_STATUS_DEVTYPE (0x00000700u)
+#define CONTROL_STATUS_DEVTYPE_SHIFT (0x00000008u)
+
+#define CONTROL_STATUS_RSVD2 (0xFF000000u)
+#define CONTROL_STATUS_RSVD2_SHIFT (0x00000018u)
+
+#define CONTROL_STATUS_SYSBOOT0 (0x000000FFu)
+#define CONTROL_STATUS_SYSBOOT0_SHIFT (0x00000000u)
+
+#define CONTROL_STATUS_SYSBOOT1 (0x00C00000u)
+#define CONTROL_STATUS_SYSBOOT1_SHIFT (0x00000016u)
+
+#define CONTROL_STATUS_TESTMD (0x00300000u)
+#define CONTROL_STATUS_TESTMD_SHIFT (0x00000014u)
+
+#define CONTROL_STATUS_WAITEN (0x00020000u)
+#define CONTROL_STATUS_WAITEN_SHIFT (0x00000011u)
+
+
+/* BOOTSTAT */
+#define CONTROL_BOOTSTAT_BC (0x00000001u)
+#define CONTROL_BOOTSTAT_BC_SHIFT (0x00000000u)
+
+#define CONTROL_BOOTSTAT_BOOTERR (0x000F0000u)
+#define CONTROL_BOOTSTAT_BOOTERR_SHIFT (0x00000010u)
+
+#define CONTROL_BOOTSTAT_RSVD2 (0xFFF00000u)
+#define CONTROL_BOOTSTAT_RSVD2_SHIFT (0x00000014u)
+
+
+/* CONTROL_SEC_CTRL */
+#define CONTROL_SEC_CTRL_BSCENABLE (0x00000200u)
+#define CONTROL_SEC_CTRL_BSCENABLE_SHIFT (0x00000009u)
+
+#define CONTROL_SEC_CTRL_CATSCANEN (0x00000100u)
+#define CONTROL_SEC_CTRL_CATSCANEN_SHIFT (0x00000008u)
+
+#define CONTROL_SEC_CTRL_CMPKEFUSENOTDEC (0x00002000u)
+#define CONTROL_SEC_CTRL_CMPKEFUSENOTDEC_SHIFT (0x0000000Du)
+
+#define CONTROL_SEC_CTRL_CPEFUSELDDONE (0x00000400u)
+#define CONTROL_SEC_CTRL_CPEFUSELDDONE_SHIFT (0x0000000Au)
+
+#define CONTROL_SEC_CTRL_CPEFUSENOTDEC (0x00001000u)
+#define CONTROL_SEC_CTRL_CPEFUSENOTDEC_SHIFT (0x0000000Cu)
+
+#define CONTROL_SEC_CTRL_CPEFUSEWRDIS (0x00000800u)
+#define CONTROL_SEC_CTRL_CPEFUSEWRDIS_SHIFT (0x0000000Bu)
+
+#define CONTROL_SEC_CTRL_DMLEDCOREEN (0x00000080u)
+#define CONTROL_SEC_CTRL_DMLEDCOREEN_SHIFT (0x00000007u)
+
+#define CONTROL_SEC_CTRL_FASTOCMSECSAVE (0x30000000u)
+#define CONTROL_SEC_CTRL_FASTOCMSECSAVE_SHIFT (0x0000001Cu)
+
+#define CONTROL_SEC_CTRL_KEKSWENABLE0 (0x00000004u)
+#define CONTROL_SEC_CTRL_KEKSWENABLE0_SHIFT (0x00000002u)
+
+#define CONTROL_SEC_CTRL_KEKSWENABLE1 (0x00000010u)
+#define CONTROL_SEC_CTRL_KEKSWENABLE1_SHIFT (0x00000004u)
+
+#define CONTROL_SEC_CTRL_L3OCMSECSAVE (0x0C000000u)
+#define CONTROL_SEC_CTRL_L3OCMSECSAVE_SHIFT (0x0000001Au)
+
+#define CONTROL_SEC_CTRL_RSVD2 (0x00000060u)
+#define CONTROL_SEC_CTRL_RSVD2_SHIFT (0x00000005u)
+
+#define CONTROL_SEC_CTRL_SECCTRLWRDISABLE (0x80000000u)
+#define CONTROL_SEC_CTRL_SECCTRLWRDISABLE_SHIFT (0x0000001Fu)
+
+#define CONTROL_SEC_CTRL_SECUREMODEINITDONE (0x40000000u)
+#define CONTROL_SEC_CTRL_SECUREMODEINITDONE_SHIFT (0x0000001Eu)
+
+#define CONTROL_SEC_CTRL_WDOPDISABLE (0x00000001u)
+#define CONTROL_SEC_CTRL_WDOPDISABLE_SHIFT (0x00000000u)
+
+#define CONTROL_SEC_CTRL_WDREGENABLE (0x00000002u)
+#define CONTROL_SEC_CTRL_WDREGENABLE_SHIFT (0x00000001u)
+
+
+/* CONTROL_SEC_SW */
+#define CONTROL_SEC_SW_SW_HW_PARAMETERS (0xFFFFFFFFu)
+#define CONTROL_SEC_SW_SW_HW_PARAMETERS_SHIFT (0x00000000u)
+
+
+/* CONTROL_SEC_EMU */
+#define CONTROL_SEC_EMU_ETMSECPRIVDBGEN (0x00001000u)
+#define CONTROL_SEC_EMU_ETMSECPRIVDBGEN_SHIFT (0x0000000Cu)
+
+#define CONTROL_SEC_EMU_GENDBGEN (0x00000FFFu)
+#define CONTROL_SEC_EMU_GENDBGEN_SHIFT (0x00000000u)
+
+#define CONTROL_SEC_EMU_GENDBGEN_M3 (0x0000C000u)
+#define CONTROL_SEC_EMU_GENDBGEN_M3_SHIFT (0x0000000Eu)
+
+#define CONTROL_SEC_EMU_ICESECPRIVDBGEN (0x00002000u)
+#define CONTROL_SEC_EMU_ICESECPRIVDBGEN_SHIFT (0x0000000Du)
+
+#define CONTROL_SEC_EMU_SECEMUWRDIS (0x80000000u)
+#define CONTROL_SEC_EMU_SECEMUWRDIS_SHIFT (0x0000001Fu)
+
+
+/* SECURE_EMIF_SDRAM_CONFIG */
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_CL (0x00003C00u)
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_CL_SHIFT (0x0000000Au)
+
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_CWL (0x00030000u)
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_CWL_SHIFT (0x00000010u)
+
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_DDR_TERM (0x07000000u)
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_DDR_TERM_SHIFT (0x00000018u)
+
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_DYN_ODT (0x00600000u)
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_DYN_ODT_SHIFT (0x00000015u)
+
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_EBANK (0x00000008u)
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_EBANK_SHIFT (0x00000003u)
+
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_IBANK (0x00000070u)
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_IBANK_SHIFT (0x00000004u)
+
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_IBANK_POS (0x18000000u)
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_IBANK_POS_SHIFT (0x0000001Bu)
+
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_NARROW_MODE (0x0000C000u)
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_NARROW_MODE_SHIFT (0x0000000Eu)
+
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_PAGESIZE (0x00000007u)
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_PAGESIZE_SHIFT (0x00000000u)
+
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_ROWSIZE (0x00000380u)
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_ROWSIZE_SHIFT (0x00000007u)
+
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_RSVD2 (0x00800000u)
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_RSVD2_SHIFT (0x00000017u)
+
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_SDRAM_DRIVE (0x000C0000u)
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_SDRAM_DRIVE_SHIFT (0x00000012u)
+
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_SDRAM_TYPE (0xE0000000u)
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_SDRAM_TYPE_SHIFT (0x0000001Du)
+
+
+/* SECURE_EMIF_SDRAM_CONFIG_2 */
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_CS1_NVMEN (0x40000000u)
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_CS1_NVMEN_SHIFT (0x0000001Eu)
+
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_EBANK_POS (0x08000000u)
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_EBANK_POS_SHIFT (0x0000001Bu)
+
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_RDBNUM (0x00000030u)
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_RDBNUM_SHIFT (0x00000004u)
+
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_RDBSIZE (0x00000007u)
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_RDBSIZE_SHIFT (0x00000000u)
+
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_RSVD2 (0x07FFFFC0u)
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_RSVD2_SHIFT (0x00000006u)
+
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_RSVD3 (0x30000000u)
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_RSVD3_SHIFT (0x0000001Cu)
+
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_RSVD4 (0x80000000u)
+#define CONTROL_SECURE_EMIF_SDRAM_CONFIG_2_RSVD4_SHIFT (0x0000001Fu)
+
+
+/* CONTROL_SW_CFG */
+#define CONTROL_SW_CFG_SW_CFG (0xFFFFFFFFu)
+#define CONTROL_SW_CFG_SW_CFG_SHIFT (0x00000000u)
+
+
+/* CONTROL_SW_CCFG */
+#define CONTROL_SW_CCFG_SW_CCFG (0x0000FFFFu)
+#define CONTROL_SW_CCFG_SW_CCFG_SHIFT (0x00000000u)
+
+#define CONTROL_SW_CCFG_SW_CCFG_RED (0xFFFF0000u)
+#define CONTROL_SW_CCFG_SW_CCFG_RED_SHIFT (0x00000010u)
+
+
+/* CONTROL_MPK_0 */
+#define CONTROL_MPK_0_MPK (0xFFFFFFFFu)
+#define CONTROL_MPK_0_MPK_SHIFT (0x00000000u)
+
+
+/* CONTROL_MPK_1 */
+#define CONTROL_MPK_1_MPK (0xFFFFFFFFu)
+#define CONTROL_MPK_1_MPK_SHIFT (0x00000000u)
+
+
+/* CONTROL_MPK_2 */
+#define CONTROL_MPK_2_MPK (0xFFFFFFFFu)
+#define CONTROL_MPK_2_MPK_SHIFT (0x00000000u)
+
+
+/* CONTROL_MPK_3 */
+#define CONTROL_MPK_3_MPK (0xFFFFFFFFu)
+#define CONTROL_MPK_3_MPK_SHIFT (0x00000000u)
+
+
+/* CONTROL_MPK_4 */
+#define CONTROL_MPK_4_MPK (0xFFFFFFFFu)
+#define CONTROL_MPK_4_MPK_SHIFT (0x00000000u)
+
+
+/* CONTROL_MPK_5 */
+#define CONTROL_MPK_5_MPK (0xFFFFFFFFu)
+#define CONTROL_MPK_5_MPK_SHIFT (0x00000000u)
+
+
+/* CONTROL_MPK_6 */
+#define CONTROL_MPK_6_MPK (0xFFFFFFFFu)
+#define CONTROL_MPK_6_MPK_SHIFT (0x00000000u)
+
+
+/* CONTROL_MPK_7 */
+#define CONTROL_MPK_7_MPK (0xFFFFFFFFu)
+#define CONTROL_MPK_7_MPK_SHIFT (0x00000000u)
+
+
+/* CONTROL_SWRV_0 */
+#define CONTROL_SWRV_0_SWRV (0x0000FFFFu)
+#define CONTROL_SWRV_0_SWRV_SHIFT (0x00000000u)
+
+#define CONTROL_SWRV_0_SWRV_RED (0xFFFF0000u)
+#define CONTROL_SWRV_0_SWRV_RED_SHIFT (0x00000010u)
+
+
+/* CONTROL_SWRV_1 */
+#define CONTROL_SWRV_1_SWRV (0x0000FFFFu)
+#define CONTROL_SWRV_1_SWRV_SHIFT (0x00000000u)
+
+#define CONTROL_SWRV_1_SWRV_RED (0xFFFF0000u)
+#define CONTROL_SWRV_1_SWRV_RED_SHIFT (0x00000010u)
+
+
+/* CONTROL_SWRV_2 */
+#define CONTROL_SWRV_2_SWRV (0x0000FFFFu)
+#define CONTROL_SWRV_2_SWRV_SHIFT (0x00000000u)
+
+#define CONTROL_SWRV_2_SWRV_RED (0xFFFF0000u)
+#define CONTROL_SWRV_2_SWRV_RED_SHIFT (0x00000010u)
+
+
+/* CONTROL_SWRV_3 */
+#define CONTROL_SWRV_3_SWRV (0x0000FFFFu)
+#define CONTROL_SWRV_3_SWRV_SHIFT (0x00000000u)
+
+#define CONTROL_SWRV_3_SWRV_RED (0xFFFF0000u)
+#define CONTROL_SWRV_3_SWRV_RED_SHIFT (0x00000010u)
+
+
+/* CONTROL_SWRV_4 */
+#define CONTROL_SWRV_4_SWRV (0x0000FFFFu)
+#define CONTROL_SWRV_4_SWRV_SHIFT (0x00000000u)
+
+#define CONTROL_SWRV_4_SWRV_RED (0xFFFF0000u)
+#define CONTROL_SWRV_4_SWRV_RED_SHIFT (0x00000010u)
+
+
+/* CONTROL_SWRV_5 */
+#define CONTROL_SWRV_5_SWRV (0x0000FFFFu)
+#define CONTROL_SWRV_5_SWRV_SHIFT (0x00000000u)
+
+#define CONTROL_SWRV_5_SWRV_RED (0xFFFF0000u)
+#define CONTROL_SWRV_5_SWRV_RED_SHIFT (0x00000010u)
+
+
+/* CONTROL_SWRV_6 */
+#define CONTROL_SWRV_6_SWRV (0x0000FFFFu)
+#define CONTROL_SWRV_6_SWRV_SHIFT (0x00000000u)
+
+#define CONTROL_SWRV_6_SWRV_RED (0xFFFF0000u)
+#define CONTROL_SWRV_6_SWRV_RED_SHIFT (0x00000010u)
+
+
+/* CONTROL_SEC_TAP */
+#define CONTROL_SEC_TAP_1500EN (0x00000008u)
+#define CONTROL_SEC_TAP_1500EN_SHIFT (0x00000003u)
+
+#define CONTROL_SEC_TAP_DAPTAPEN (0x00000001u)
+#define CONTROL_SEC_TAP_DAPTAPEN_SHIFT (0x00000000u)
+
+#define CONTROL_SEC_TAP_PART1500DIS (0x00000010u)
+#define CONTROL_SEC_TAP_PART1500DIS_SHIFT (0x00000004u)
+
+#define CONTROL_SEC_TAP_RSVD2 (0x000001E0u)
+#define CONTROL_SEC_TAP_RSVD2_SHIFT (0x00000005u)
+
+#define CONTROL_SEC_TAP_RSVD3 (0x7FFFFC00u)
+#define CONTROL_SEC_TAP_RSVD3_SHIFT (0x0000000Au)
+
+#define CONTROL_SEC_TAP_SABERMPUTAPEN (0x00000200u)
+#define CONTROL_SEC_TAP_SABERMPUTAPEN_SHIFT (0x00000009u)
+
+#define CONTROL_SEC_TAP_SECTAPWRDISABLE (0x80000000u)
+#define CONTROL_SEC_TAP_SECTAPWRDISABLE_SHIFT (0x0000001Fu)
+
+#define CONTROL_SEC_TAP_WAKEUPTAPEN (0x00000004u)
+#define CONTROL_SEC_TAP_WAKEUPTAPEN_SHIFT (0x00000002u)
+
+
+/* CONTROL_SEC_TAP_CMDIN */
+#define CONTROL_SEC_TAP_CMDIN_CMDIN (0x000000FFu)
+#define CONTROL_SEC_TAP_CMDIN_CMDIN_SHIFT (0x00000000u)
+
+
+/* CONTROL_SEC_TAP_CMDOUT */
+#define CONTROL_SEC_TAP_CMDOUT_CMDOUT (0x000000FFu)
+#define CONTROL_SEC_TAP_CMDOUT_CMDOUT_SHIFT (0x00000000u)
+
+
+/* CONTROL_SEC_TAP_DATIN */
+#define CONTROL_SEC_TAP_DATIN_DATAIN (0x000000FFu)
+#define CONTROL_SEC_TAP_DATIN_DATAIN_SHIFT (0x00000000u)
+
+
+/* CONTROL_SEC_TAP_DATOUT */
+#define CONTROL_SEC_TAP_DATOUT_DATAOUT (0x000000FFu)
+#define CONTROL_SEC_TAP_DATOUT_DATAOUT_SHIFT (0x00000000u)
+
+
+/* CONTROL_MREQDOMAIN_EXP1 */
+#define CONTROL_MREQDOMAIN_EXP1_2DBITBLT_DOM (0x001C0000u)
+#define CONTROL_MREQDOMAIN_EXP1_2DBITBLT_DOM_SHIFT (0x00000012u)
+
+#define CONTROL_MREQDOMAIN_EXP1_L3_EXP_DOM (0x00000007u)
+#define CONTROL_MREQDOMAIN_EXP1_L3_EXP_DOM_SHIFT (0x00000000u)
+
+#define CONTROL_MREQDOMAIN_EXP1_LCD_CTRL_DOM (0x00038000u)
+#define CONTROL_MREQDOMAIN_EXP1_LCD_CTRL_DOM_SHIFT (0x0000000Fu)
+
+#define CONTROL_MREQDOMAIN_EXP1_LCK (0x80000000u)
+#define CONTROL_MREQDOMAIN_EXP1_LCK_SHIFT (0x0000001Fu)
+
+#define CONTROL_MREQDOMAIN_EXP1_MLB_DOM (0x00007000u)
+#define CONTROL_MREQDOMAIN_EXP1_MLB_DOM_SHIFT (0x0000000Cu)
+
+#define CONTROL_MREQDOMAIN_EXP1_RSVD2 (0x78000000u)
+#define CONTROL_MREQDOMAIN_EXP1_RSVD2_SHIFT (0x0000001Bu)
+
+#define CONTROL_MREQDOMAIN_EXP1_SGX_DOM (0x07000000u)
+#define CONTROL_MREQDOMAIN_EXP1_SGX_DOM_SHIFT (0x00000018u)
+
+#define CONTROL_MREQDOMAIN_EXP1_WAKE_DOM (0x00E00000u)
+#define CONTROL_MREQDOMAIN_EXP1_WAKE_DOM_SHIFT (0x00000015u)
+
+
+/* CONTROL_MREQDOMAIN_EXP2 */
+#define CONTROL_MREQDOMAIN_EXP2_GEMAC_DOM (0x001C0000u)
+#define CONTROL_MREQDOMAIN_EXP2_GEMAC_DOM_SHIFT (0x00000012u)
+
+#define CONTROL_MREQDOMAIN_EXP2_LCK (0x80000000u)
+#define CONTROL_MREQDOMAIN_EXP2_LCK_SHIFT (0x0000001Fu)
+
+#define CONTROL_MREQDOMAIN_EXP2_P1500_DOM (0x00038000u)
+#define CONTROL_MREQDOMAIN_EXP2_P1500_DOM_SHIFT (0x0000000Fu)
+
+#define CONTROL_MREQDOMAIN_EXP2_RSVD2 (0x7FE00000u)
+#define CONTROL_MREQDOMAIN_EXP2_RSVD2_SHIFT (0x00000015u)
+
+#define CONTROL_MREQDOMAIN_EXP2_USB0_DOM (0x00000E00u)
+#define CONTROL_MREQDOMAIN_EXP2_USB0_DOM_SHIFT (0x00000009u)
+
+#define CONTROL_MREQDOMAIN_EXP2_USB1_DOM (0x00007000u)
+#define CONTROL_MREQDOMAIN_EXP2_USB1_DOM_SHIFT (0x0000000Cu)
+
+
+/* L3_HW_FW_EXP_VAL_CONF0 */
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_L3EXP_SECDBG_EN (0x00040000u)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_L3EXP_SECDBG_EN_SHIFT (0x00000012u)
+
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_L3EXP_SECLOCK_EN (0x00000004u)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_L3EXP_SECLOCK_EN_SHIFT (0x00000002u)
+
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_L3RAM_SECDBG_EN (0x01000000u)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_L3RAM_SECDBG_EN_SHIFT (0x00000018u)
+
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_L3RAM_SECLOCK_EN (0x00000100u)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_L3RAM_SECLOCK_EN_SHIFT (0x00000008u)
+
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_RSVD2 (0x00000020u)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_RSVD2_SHIFT (0x00000005u)
+
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_RSVD3 (0x00000200u)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_RSVD3_SHIFT (0x00000009u)
+
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_RSVD4 (0x0003F800u)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_RSVD4_SHIFT (0x0000000Bu)
+
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_RSVD5 (0x00200000u)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_RSVD5_SHIFT (0x00000015u)
+
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_RSVD6 (0x02000000u)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_RSVD6_SHIFT (0x00000019u)
+
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_RSVD7 (0xF8000000u)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_RSVD7_SHIFT (0x0000001Bu)
+
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_SGX_SECDBG_EN (0x00800000u)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_SGX_SECDBG_EN_SHIFT (0x00000017u)
+
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_SGX_SECLOCK_EN (0x00000080u)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_SGX_SECLOCK_EN_SHIFT (0x00000007u)
+
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_TPCC_SECDBG_EN (0x00100000u)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_TPCC_SECDBG_EN_SHIFT (0x00000014u)
+
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_TPCC_SECLOCK_EN (0x00000010u)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_TPCC_SECLOCK_EN_SHIFT (0x00000004u)
+
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_TPTC_SECDBG_EN (0x00080000u)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_TPTC_SECDBG_EN_SHIFT (0x00000013u)
+
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_TPTC_SECLOCK_EN (0x00000008u)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_TPTC_SECLOCK_EN_SHIFT (0x00000003u)
+
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_USB_SECDBG_EN (0x04000000u)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_USB_SECDBG_EN_SHIFT (0x0000001Au)
+
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_USB_SECLOCK_EN (0x00000400u)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF0_USB_SECLOCK_EN_SHIFT (0x0000000Au)
+
+
+/* L3_HW_FW_EXP_VAL_CONF1 */
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_ADCTSC_SECDBG_EN (0x08000000u)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_ADCTSC_SECDBG_EN_SHIFT (0x0000001Bu)
+
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_ADCTSC_SECLOCK_EN (0x00000800u)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_ADCTSC_SECLOCK_EN_SHIFT (0x0000000Bu)
+
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_AES0_SECDBG_EN (0x10000000u)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_AES0_SECDBG_EN_SHIFT (0x0000001Cu)
+
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_AES0_SECLOCK_EN (0x00001000u)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_AES0_SECLOCK_EN_SHIFT (0x0000000Cu)
+
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_DEBUG_SECDBG_EN (0x02000000u)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_DEBUG_SECDBG_EN_SHIFT (0x00000019u)
+
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_DEBUG_SECLOCK_EN (0x00000200u)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_DEBUG_SECLOCK_EN_SHIFT (0x00000009u)
+
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_EMIF_SECDBG_EN (0x01000000u)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_EMIF_SECDBG_EN_SHIFT (0x00000018u)
+
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_EMIF_SECLOCK_EN (0x00000100u)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_EMIF_SECLOCK_EN_SHIFT (0x00000008u)
+
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_GPMC_SECDBG_EN (0x00080000u)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_GPMC_SECDBG_EN_SHIFT (0x00000013u)
+
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_GPMC_SECLOCK_EN (0x00000008u)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_GPMC_SECLOCK_EN_SHIFT (0x00000003u)
+
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MCASP0_SECDBG_EN (0x00100000u)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MCASP0_SECDBG_EN_SHIFT (0x00000014u)
+
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MCASP0_SECLOCK_EN (0x00000010u)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MCASP0_SECLOCK_EN_SHIFT (0x00000004u)
+
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MCASP1_SECDBG_EN (0x00200000u)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MCASP1_SECDBG_EN_SHIFT (0x00000015u)
+
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MCASP1_SECLOCK_EN (0x00000020u)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MCASP1_SECLOCK_EN_SHIFT (0x00000005u)
+
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MMCHS2_SECDBG_EN (0x04000000u)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MMCHS2_SECDBG_EN_SHIFT (0x0000001Au)
+
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MMCHS2_SECLOCK_EN (0x00000400u)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_MMCHS2_SECLOCK_EN_SHIFT (0x0000000Au)
+
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_RSVD2 (0x00000080u)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_RSVD2_SHIFT (0x00000007u)
+
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_RSVD3 (0x00078000u)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_RSVD3_SHIFT (0x0000000Fu)
+
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_RSVD4 (0x00800000u)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_RSVD4_SHIFT (0x00000017u)
+
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_RSVD5 (0x80000000u)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_RSVD5_SHIFT (0x0000001Fu)
+
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_SHA_SECDBG_EN (0x40000000u)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_SHA_SECDBG_EN_SHIFT (0x0000001Eu)
+
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_SHA_SECLOCK_EN (0x00004000u)
+#define CONTROL_L3_HW_FW_EXP_VAL_CONF1_SHA_SECLOCK_EN_SHIFT (0x0000000Eu)
+
+
+/* L4_HW_FW_EXP_VAL_CONF */
+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FAST_AP_SECDBG_EN (0x01000000u)
+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FAST_AP_SECDBG_EN_SHIFT (0x00000018u)
+
+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FAST_AP_SECLOCK_EN (0x00000100u)
+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FAST_AP_SECLOCK_EN_SHIFT (0x00000008u)
+
+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FW_AP_SECDBG_EN (0x00100000u)
+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FW_AP_SECDBG_EN_SHIFT (0x00000014u)
+
+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FW_AP_SECLOCK_EN (0x00000010u)
+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FW_AP_SECLOCK_EN_SHIFT (0x00000004u)
+
+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FW_SEC_SECDBG_EN (0x00200000u)
+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FW_SEC_SECDBG_EN_SHIFT (0x00000015u)
+
+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FW_SEC_SECLOCK_EN (0x00000020u)
+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4FW_SEC_SECLOCK_EN_SHIFT (0x00000005u)
+
+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4PER_AP_SECDBG_EN (0x00010000u)
+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4PER_AP_SECDBG_EN_SHIFT (0x00000010u)
+
+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4PER_AP_SECLOCK_EN (0x00000001u)
+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4PER_AP_SECLOCK_EN_SHIFT (0x00000000u)
+
+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4PER_CRYPTO_SECDBG_EN (0x00020000u)
+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4PER_CRYPTO_SECDBG_EN_SHIFT (0x00000011u)
+
+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4PER_CRYPTO_SECLOCK_EN (0x00000002u)
+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4PER_CRYPTO_SECLOCK_EN_SHIFT (0x00000001u)
+
+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4WKUP_AP_SECDBG_EN (0x10000000u)
+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4WKUP_AP_SECDBG_EN_SHIFT (0x0000001Cu)
+
+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4WKUP_AP_SECLOCK_EN (0x00001000u)
+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4WKUP_AP_SECLOCK_EN_SHIFT (0x0000000Cu)
+
+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4WKUP_SEC_SECDBG_EN (0x20000000u)
+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4WKUP_SEC_SECDBG_EN_SHIFT (0x0000001Du)
+
+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4WKUP_SEC_SECLOCK_EN (0x00002000u)
+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_L4WKUP_SEC_SECLOCK_EN_SHIFT (0x0000000Du)
+
+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_RSVD2 (0x000000C0u)
+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_RSVD2_SHIFT (0x00000006u)
+
+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_RSVD3 (0x00000E00u)
+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_RSVD3_SHIFT (0x00000009u)
+
+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_RSVD4 (0x0000C000u)
+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_RSVD4_SHIFT (0x0000000Eu)
+
+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_RSVD5 (0x000C0000u)
+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_RSVD5_SHIFT (0x00000012u)
+
+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_RSVD6 (0x00C00000u)
+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_RSVD6_SHIFT (0x00000016u)
+
+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_RSVD7 (0x0E000000u)
+#define CONTROL_L4_HW_FW_EXP_VAL_CONF_RSVD7_SHIFT (0x00000019u)
+
+
+/* CONTROL_SEC_LOAD_FW_EXP_VAL */
+#define CONTROL_SEC_LOAD_FW_EXP_VAL_L4FAST_LD_EXPVAL_REQN (0x00000010u)
+#define CONTROL_SEC_LOAD_FW_EXP_VAL_L4FAST_LD_EXPVAL_REQN_SHIFT (0x00000004u)
+
+#define CONTROL_SEC_LOAD_FW_EXP_VAL_L4FW_LD_EXPVAL_REQN (0x00000004u)
+#define CONTROL_SEC_LOAD_FW_EXP_VAL_L4FW_LD_EXPVAL_REQN_SHIFT (0x00000002u)
+
+#define CONTROL_SEC_LOAD_FW_EXP_VAL_L4PER_LD_EXPVAL_REQN (0x00000008u)
+#define CONTROL_SEC_LOAD_FW_EXP_VAL_L4PER_LD_EXPVAL_REQN_SHIFT (0x00000003u)
+
+#define CONTROL_SEC_LOAD_FW_EXP_VAL_L4WKUP_LD_EXPVAL_REQN (0x00000020u)
+#define CONTROL_SEC_LOAD_FW_EXP_VAL_L4WKUP_LD_EXPVAL_REQN_SHIFT (0x00000005u)
+
+#define CONTROL_SEC_LOAD_FW_EXP_VAL_RSVD2 (0xFFFFFFC0u)
+#define CONTROL_SEC_LOAD_FW_EXP_VAL_RSVD2_SHIFT (0x00000006u)
+
+
+/* CONTROL_SEC_CTRL_RO */
+#define CONTROL_SEC_CTRL_RO_CUSTMPK (0x00000010u)
+#define CONTROL_SEC_CTRL_RO_CUSTMPK_SHIFT (0x00000004u)
+
+#define CONTROL_SEC_CTRL_RO_EMIF_CFG_RO_EN (0x00000002u)
+#define CONTROL_SEC_CTRL_RO_EMIF_CFG_RO_EN_SHIFT (0x00000001u)
+
+#define CONTROL_SEC_CTRL_RO_EMIF_OBFS_EN (0x00000004u)
+#define CONTROL_SEC_CTRL_RO_EMIF_OBFS_EN_SHIFT (0x00000002u)
+
+#define CONTROL_SEC_CTRL_RO_RSVD2 (0xFFFFFFE0u)
+#define CONTROL_SEC_CTRL_RO_RSVD2_SHIFT (0x00000005u)
+
+#define CONTROL_SEC_CTRL_RO_SECKEYACCEN (0x00000008u)
+#define CONTROL_SEC_CTRL_RO_SECKEYACCEN_SHIFT (0x00000003u)
+
+
+/* EMIF_OBFUSCATION_KEY */
+#define CONTROL_EMIF_OBFUSCATION_KEY_OBFUSCATIONKEY (0x0000FFFFu)
+#define CONTROL_EMIF_OBFUSCATION_KEY_OBFUSCATIONKEY_SHIFT (0x00000000u)
+
+
+/* SEC_CLK_CTRL */
+#define CONTROL_SEC_CLK_CTRL_RSVD2 (0x7FFFFFC0u)
+#define CONTROL_SEC_CLK_CTRL_RSVD2_SHIFT (0x00000006u)
+
+#define CONTROL_SEC_CLK_CTRL_SECCLKLCK (0x80000000u)
+#define CONTROL_SEC_CLK_CTRL_SECCLKLCK_SHIFT (0x0000001Fu)
+
+#define CONTROL_SEC_CLK_CTRL_SECTIMERCLKSEL (0x00000030u)
+#define CONTROL_SEC_CLK_CTRL_SECTIMERCLKSEL_SHIFT (0x00000004u)
+
+#define CONTROL_SEC_CLK_CTRL_SECWDCLKSEL (0x00000001u)
+#define CONTROL_SEC_CLK_CTRL_SECWDCLKSEL_SHIFT (0x00000000u)
+
+
+/* CONTROL_MREQDOMAIN_EXP3 */
+#define CONTROL_MREQDOMAIN_EXP3_LCK (0x80000000u)
+#define CONTROL_MREQDOMAIN_EXP3_LCK_SHIFT (0x0000001Fu)
+
+#define CONTROL_MREQDOMAIN_EXP3_PRU0_DOM (0x00000007u)
+#define CONTROL_MREQDOMAIN_EXP3_PRU0_DOM_SHIFT (0x00000000u)
+
+#define CONTROL_MREQDOMAIN_EXP3_PRU1_DOM (0x00000038u)
+#define CONTROL_MREQDOMAIN_EXP3_PRU1_DOM_SHIFT (0x00000003u)
+
+#define CONTROL_MREQDOMAIN_EXP3_PRU2_DOM (0x000001C0u)
+#define CONTROL_MREQDOMAIN_EXP3_PRU2_DOM_SHIFT (0x00000006u)
+
+#define CONTROL_MREQDOMAIN_EXP3_PRU3_DOM (0x00000E00u)
+#define CONTROL_MREQDOMAIN_EXP3_PRU3_DOM_SHIFT (0x00000009u)
+
+
+/* CONTROL_CEK_0 */
+#define CONTROL_CEK_0_CEK (0xFFFFFFFFu)
+#define CONTROL_CEK_0_CEK_SHIFT (0x00000000u)
+
+
+/* CONTROL_CEK_1 */
+#define CONTROL_CEK_1_CEK (0xFFFFFFFFu)
+#define CONTROL_CEK_1_CEK_SHIFT (0x00000000u)
+
+
+/* CONTROL_CEK_2 */
+#define CONTROL_CEK_2_CEK (0xFFFFFFFFu)
+#define CONTROL_CEK_2_CEK_SHIFT (0x00000000u)
+
+
+/* CONTROL_CEK_3 */
+#define CONTROL_CEK_3_CEK (0xFFFFFFFFu)
+#define CONTROL_CEK_3_CEK_SHIFT (0x00000000u)
+
+
+/* CONTROL_CEK_BCH_0 */
+#define CONTROL_CEK_BCH_0_CEK_BCH (0xFFFFFFFFu)
+#define CONTROL_CEK_BCH_0_CEK_BCH_SHIFT (0x00000000u)
+
+
+/* CONTROL_CEK_BCH_1 */
+#define CONTROL_CEK_BCH_1_CEK_BCH (0xFFFFFFFFu)
+#define CONTROL_CEK_BCH_1_CEK_BCH_SHIFT (0x00000000u)
+
+
+/* CONTROL_CEK_BCH_2 */
+#define CONTROL_CEK_BCH_2_CEK_BCH (0xFFFFFFFFu)
+#define CONTROL_CEK_BCH_2_CEK_BCH_SHIFT (0x00000000u)
+
+
+/* CONTROL_CEK_BCH_3 */
+#define CONTROL_CEK_BCH_3_CEK_BCH (0xFFFFFFFFu)
+#define CONTROL_CEK_BCH_3_CEK_BCH_SHIFT (0x00000000u)
+
+
+/* CONTROL_CEK_BCH_4 */
+#define CONTROL_CEK_BCH_4_CEK_BCH (0x0000FFFFu)
+#define CONTROL_CEK_BCH_4_CEK_BCH_SHIFT (0x00000000u)
+
+
+/* CONTROL_MSV_0 */
+#define CONTROL_MSV_0_MSV (0xFFFFFFFFu)
+#define CONTROL_MSV_0_MSV_SHIFT (0x00000000u)
+
+
+/* CONTROL_MSV_BCH_0 */
+#define CONTROL_MSV_BCH_0_MSV_BCH (0xFFFFFFFFu)
+#define CONTROL_MSV_BCH_0_MSV_BCH_SHIFT (0x00000000u)
+
+
+/* CONTROL_MSV_BCH_1 */
+#define CONTROL_MSV_BCH_1_MSV_BCH (0xFFFFFFFFu)
+#define CONTROL_MSV_BCH_1_MSV_BCH_SHIFT (0x00000000u)
+
+
+/* CONTROL_SEC_STATUS */
+#define CONTROL_SEC_STATUS_EMURST (0x00000020u)
+#define CONTROL_SEC_STATUS_EMURST_SHIFT (0x00000005u)
+
+#define CONTROL_SEC_STATUS_GFXDOMAINRST (0x00000200u)
+#define CONTROL_SEC_STATUS_GFXDOMAINRST_SHIFT (0x00000009u)
+
+#define CONTROL_SEC_STATUS_GLOBALCOLDRST (0x00000001u)
+#define CONTROL_SEC_STATUS_GLOBALCOLDRST_SHIFT (0x00000000u)
+
+#define CONTROL_SEC_STATUS_GLOBALWARMRST (0x00000002u)
+#define CONTROL_SEC_STATUS_GLOBALWARMRST_SHIFT (0x00000001u)
+
+#define CONTROL_SEC_STATUS_ICSS0RST (0x00040000u)
+#define CONTROL_SEC_STATUS_ICSS0RST_SHIFT (0x00000012u)
+
+#define CONTROL_SEC_STATUS_ICSS1RST (0x00080000u)
+#define CONTROL_SEC_STATUS_ICSS1RST_SHIFT (0x00000013u)
+
+#define CONTROL_SEC_STATUS_MPUDOMAINRST (0x00000040u)
+#define CONTROL_SEC_STATUS_MPUDOMAINRST_SHIFT (0x00000006u)
+
+#define CONTROL_SEC_STATUS_MPURST (0x00020000u)
+#define CONTROL_SEC_STATUS_MPURST_SHIFT (0x00000011u)
+
+#define CONTROL_SEC_STATUS_PERDOMAINRST (0x00000080u)
+#define CONTROL_SEC_STATUS_PERDOMAINRST_SHIFT (0x00000007u)
+
+#define CONTROL_SEC_STATUS_PUBWDRST (0x00000004u)
+#define CONTROL_SEC_STATUS_PUBWDRST_SHIFT (0x00000002u)
+
+#define CONTROL_SEC_STATUS_RSVD2 (0xFFF00000u)
+#define CONTROL_SEC_STATUS_RSVD2_SHIFT (0x00000014u)
+
+#define CONTROL_SEC_STATUS_SECWDRST (0x00000008u)
+#define CONTROL_SEC_STATUS_SECWDRST_SHIFT (0x00000003u)
+
+#define CONTROL_SEC_STATUS_SSMVIOLATIONRST (0x00000010u)
+#define CONTROL_SEC_STATUS_SSMVIOLATIONRST_SHIFT (0x00000004u)
+
+#define CONTROL_SEC_STATUS_WKUPDOMAINRST (0x00000100u)
+#define CONTROL_SEC_STATUS_WKUPDOMAINRST_SHIFT (0x00000008u)
+
+
+/* CONTROL_SECMEM_STATUS */
+#define CONTROL_SECMEM_STATUS_A8L1DEST (0x00000001u)
+#define CONTROL_SECMEM_STATUS_A8L1DEST_SHIFT (0x00000000u)
+
+#define CONTROL_SECMEM_STATUS_A8L1NOTACC (0x00010000u)
+#define CONTROL_SECMEM_STATUS_A8L1NOTACC_SHIFT (0x00000010u)
+
+#define CONTROL_SECMEM_STATUS_A8L2DEST (0x00000002u)
+#define CONTROL_SECMEM_STATUS_A8L2DEST_SHIFT (0x00000001u)
+
+#define CONTROL_SECMEM_STATUS_A8L2NOTACC (0x00020000u)
+#define CONTROL_SECMEM_STATUS_A8L2NOTACC_SHIFT (0x00000011u)
+
+#define CONTROL_SECMEM_STATUS_FASTSECRAMDEST (0x00000004u)
+#define CONTROL_SECMEM_STATUS_FASTSECRAMDEST_SHIFT (0x00000002u)
+
+#define CONTROL_SECMEM_STATUS_FASTSECRAMNOTACC (0x00040000u)
+#define CONTROL_SECMEM_STATUS_FASTSECRAMNOTACC_SHIFT (0x00000012u)
+
+#define CONTROL_SECMEM_STATUS_L3SECRAMDEST (0x00000008u)
+#define CONTROL_SECMEM_STATUS_L3SECRAMDEST_SHIFT (0x00000003u)
+
+#define CONTROL_SECMEM_STATUS_L3SECRAMNOTACC (0x00080000u)
+#define CONTROL_SECMEM_STATUS_L3SECRAMNOTACC_SHIFT (0x00000013u)
+
+#define CONTROL_SECMEM_STATUS_RSVD2 (0xFFF00000u)
+#define CONTROL_SECMEM_STATUS_RSVD2_SHIFT (0x00000014u)
+
+
+/* CONTROL_SEC_ERR_STAT_FUNC0 */
+#define CONTROL_SEC_ERR_STAT_FUNC0_EMIFFWERR (0x00000010u)
+#define CONTROL_SEC_ERR_STAT_FUNC0_EMIFFWERR_SHIFT (0x00000004u)
+
+#define CONTROL_SEC_ERR_STAT_FUNC0_GPMCFWERR (0x00000004u)
+#define CONTROL_SEC_ERR_STAT_FUNC0_GPMCFWERR_SHIFT (0x00000002u)
+
+#define CONTROL_SEC_ERR_STAT_FUNC0_L3RAMFWERR (0x00000001u)
+#define CONTROL_SEC_ERR_STAT_FUNC0_L3RAMFWERR_SHIFT (0x00000000u)
+
+#define CONTROL_SEC_ERR_STAT_FUNC0_RSVD2 (0x00000008u)
+#define CONTROL_SEC_ERR_STAT_FUNC0_RSVD2_SHIFT (0x00000003u)
+
+#define CONTROL_SEC_ERR_STAT_FUNC0_RSVD3 (0x0001FFE0u)
+#define CONTROL_SEC_ERR_STAT_FUNC0_RSVD3_SHIFT (0x00000005u)
+
+#define CONTROL_SEC_ERR_STAT_FUNC0_RSVD4 (0x007C0000u)
+#define CONTROL_SEC_ERR_STAT_FUNC0_RSVD4_SHIFT (0x00000012u)
+
+#define CONTROL_SEC_ERR_STAT_FUNC0_RSVD5 (0xF8000000u)
+#define CONTROL_SEC_ERR_STAT_FUNC0_RSVD5_SHIFT (0x0000001Bu)
+
+#define CONTROL_SEC_ERR_STAT_FUNC0_SGXFWERR (0x00020000u)
+#define CONTROL_SEC_ERR_STAT_FUNC0_SGXFWERR_SHIFT (0x00000011u)
+
+#define CONTROL_SEC_ERR_STAT_FUNC0_TPTC0FWERR (0x01000000u)
+#define CONTROL_SEC_ERR_STAT_FUNC0_TPTC0FWERR_SHIFT (0x00000018u)
+
+#define CONTROL_SEC_ERR_STAT_FUNC0_TPTC1FWERR (0x02000000u)
+#define CONTROL_SEC_ERR_STAT_FUNC0_TPTC1FWERR_SHIFT (0x00000019u)
+
+#define CONTROL_SEC_ERR_STAT_FUNC0_TPTC2FWERR (0x04000000u)
+#define CONTROL_SEC_ERR_STAT_FUNC0_TPTC2FWERR_SHIFT (0x0000001Au)
+
+#define CONTROL_SEC_ERR_STAT_FUNC0_TPTCCFWERR (0x00800000u)
+#define CONTROL_SEC_ERR_STAT_FUNC0_TPTCCFWERR_SHIFT (0x00000017u)
+
+
+/* CONTROL_SEC_ERR_STAT_FUNC1 */
+#define CONTROL_SEC_ERR_STAT_FUNC1_ADCFWERR (0x00000200u)
+#define CONTROL_SEC_ERR_STAT_FUNC1_ADCFWERR_SHIFT (0x00000009u)
+
+#define CONTROL_SEC_ERR_STAT_FUNC1_AES0FWERR (0x00100000u)
+#define CONTROL_SEC_ERR_STAT_FUNC1_AES0FWERR_SHIFT (0x00000014u)
+
+#define CONTROL_SEC_ERR_STAT_FUNC1_CRYPTODMAFWERR (0x00080000u)
+#define CONTROL_SEC_ERR_STAT_FUNC1_CRYPTODMAFWERR_SHIFT (0x00000013u)
+
+#define CONTROL_SEC_ERR_STAT_FUNC1_DBGPORTFWERR (0x00020000u)
+#define CONTROL_SEC_ERR_STAT_FUNC1_DBGPORTFWERR_SHIFT (0x00000011u)
+
+#define CONTROL_SEC_ERR_STAT_FUNC1_L3EXPFWERR (0x00010000u)
+#define CONTROL_SEC_ERR_STAT_FUNC1_L3EXPFWERR_SHIFT (0x00000010u)
+
+#define CONTROL_SEC_ERR_STAT_FUNC1_L4FASTFWERR (0x02000000u)
+#define CONTROL_SEC_ERR_STAT_FUNC1_L4FASTFWERR_SHIFT (0x00000019u)
+
+#define CONTROL_SEC_ERR_STAT_FUNC1_L4FWFWERR (0x08000000u)
+#define CONTROL_SEC_ERR_STAT_FUNC1_L4FWFWERR_SHIFT (0x0000001Bu)
+
+#define CONTROL_SEC_ERR_STAT_FUNC1_L4PERFWERR (0x01000000u)
+#define CONTROL_SEC_ERR_STAT_FUNC1_L4PERFWERR_SHIFT (0x00000018u)
+
+#define CONTROL_SEC_ERR_STAT_FUNC1_L4WKUPFWERR (0x04000000u)
+#define CONTROL_SEC_ERR_STAT_FUNC1_L4WKUPFWERR_SHIFT (0x0000001Au)
+
+#define CONTROL_SEC_ERR_STAT_FUNC1_MCASP0FWERR (0x00000001u)
+#define CONTROL_SEC_ERR_STAT_FUNC1_MCASP0FWERR_SHIFT (0x00000000u)
+
+#define CONTROL_SEC_ERR_STAT_FUNC1_MCASP1FWERR (0x00000002u)
+#define CONTROL_SEC_ERR_STAT_FUNC1_MCASP1FWERR_SHIFT (0x00000001u)
+
+#define CONTROL_SEC_ERR_STAT_FUNC1_MMCHS2FWERR (0x00008000u)
+#define CONTROL_SEC_ERR_STAT_FUNC1_MMCHS2FWERR_SHIFT (0x0000000Fu)
+
+#define CONTROL_SEC_ERR_STAT_FUNC1_RSVD2 (0x00000400u)
+#define CONTROL_SEC_ERR_STAT_FUNC1_RSVD2_SHIFT (0x0000000Au)
+
+#define CONTROL_SEC_ERR_STAT_FUNC1_RSVD3 (0x00006000u)
+#define CONTROL_SEC_ERR_STAT_FUNC1_RSVD3_SHIFT (0x0000000Du)
+
+#define CONTROL_SEC_ERR_STAT_FUNC1_RSVD4 (0x00800000u)
+#define CONTROL_SEC_ERR_STAT_FUNC1_RSVD4_SHIFT (0x00000017u)
+
+#define CONTROL_SEC_ERR_STAT_FUNC1_RSVD5 (0xF0000000u)
+#define CONTROL_SEC_ERR_STAT_FUNC1_RSVD5_SHIFT (0x0000001Cu)
+
+#define CONTROL_SEC_ERR_STAT_FUNC1_SECMODFWERR (0x00040000u)
+#define CONTROL_SEC_ERR_STAT_FUNC1_SECMODFWERR_SHIFT (0x00000012u)
+
+#define CONTROL_SEC_ERR_STAT_FUNC1_SHAFWERR (0x00400000u)
+#define CONTROL_SEC_ERR_STAT_FUNC1_SHAFWERR_SHIFT (0x00000016u)
+
+#define CONTROL_SEC_ERR_STAT_FUNC1_USBFWERR (0x00000800u)
+#define CONTROL_SEC_ERR_STAT_FUNC1_USBFWERR_SHIFT (0x0000000Bu)
+
+
+/* CONTROL_SEC_ERR_STAT_DBUG0 */
+#define CONTROL_SEC_ERR_STAT_DBUG0_EMIFDBGFWERR (0x00000010u)
+#define CONTROL_SEC_ERR_STAT_DBUG0_EMIFDBGFWERR_SHIFT (0x00000004u)
+
+#define CONTROL_SEC_ERR_STAT_DBUG0_GPMCDBGFWERR (0x00000004u)
+#define CONTROL_SEC_ERR_STAT_DBUG0_GPMCDBGFWERR_SHIFT (0x00000002u)
+
+#define CONTROL_SEC_ERR_STAT_DBUG0_L3RAMDBGFWERR (0x00000001u)
+#define CONTROL_SEC_ERR_STAT_DBUG0_L3RAMDBGFWERR_SHIFT (0x00000000u)
+
+#define CONTROL_SEC_ERR_STAT_DBUG0_RSVD2 (0x00000008u)
+#define CONTROL_SEC_ERR_STAT_DBUG0_RSVD2_SHIFT (0x00000003u)
+
+#define CONTROL_SEC_ERR_STAT_DBUG0_RSVD3 (0x0001FFE0u)
+#define CONTROL_SEC_ERR_STAT_DBUG0_RSVD3_SHIFT (0x00000005u)
+
+#define CONTROL_SEC_ERR_STAT_DBUG0_RSVD4 (0x007C0000u)
+#define CONTROL_SEC_ERR_STAT_DBUG0_RSVD4_SHIFT (0x00000012u)
+
+#define CONTROL_SEC_ERR_STAT_DBUG0_RSVD5 (0xF8000000u)
+#define CONTROL_SEC_ERR_STAT_DBUG0_RSVD5_SHIFT (0x0000001Bu)
+
+#define CONTROL_SEC_ERR_STAT_DBUG0_SGXDBGFWERR (0x00020000u)
+#define CONTROL_SEC_ERR_STAT_DBUG0_SGXDBGFWERR_SHIFT (0x00000011u)
+
+#define CONTROL_SEC_ERR_STAT_DBUG0_TPTC0DBGFWERR (0x01000000u)
+#define CONTROL_SEC_ERR_STAT_DBUG0_TPTC0DBGFWERR_SHIFT (0x00000018u)
+
+#define CONTROL_SEC_ERR_STAT_DBUG0_TPTC1DBGFWERR (0x02000000u)
+#define CONTROL_SEC_ERR_STAT_DBUG0_TPTC1DBGFWERR_SHIFT (0x00000019u)
+
+#define CONTROL_SEC_ERR_STAT_DBUG0_TPTC2DBGFWERR (0x04000000u)
+#define CONTROL_SEC_ERR_STAT_DBUG0_TPTC2DBGFWERR_SHIFT (0x0000001Au)
+
+#define CONTROL_SEC_ERR_STAT_DBUG0_TPTCCDBGFWERR (0x00800000u)
+#define CONTROL_SEC_ERR_STAT_DBUG0_TPTCCDBGFWERR_SHIFT (0x00000017u)
+
+
+/* CONTROL_SEC_ERR_STAT_DBUG1 */
+#define CONTROL_SEC_ERR_STAT_DBUG1_ADCDBGFWERR (0x00000200u)
+#define CONTROL_SEC_ERR_STAT_DBUG1_ADCDBGFWERR_SHIFT (0x00000009u)
+
+#define CONTROL_SEC_ERR_STAT_DBUG1_AES0DBGFWERR (0x00100000u)
+#define CONTROL_SEC_ERR_STAT_DBUG1_AES0DBGFWERR_SHIFT (0x00000014u)
+
+#define CONTROL_SEC_ERR_STAT_DBUG1_CRYPTODMADBGFWERR (0x00080000u)
+#define CONTROL_SEC_ERR_STAT_DBUG1_CRYPTODMADBGFWERR_SHIFT (0x00000013u)
+
+#define CONTROL_SEC_ERR_STAT_DBUG1_DBGPORTDBGFWERR (0x00020000u)
+#define CONTROL_SEC_ERR_STAT_DBUG1_DBGPORTDBGFWERR_SHIFT (0x00000011u)
+
+#define CONTROL_SEC_ERR_STAT_DBUG1_L3EXPDBGFWERR (0x00010000u)
+#define CONTROL_SEC_ERR_STAT_DBUG1_L3EXPDBGFWERR_SHIFT (0x00000010u)
+
+#define CONTROL_SEC_ERR_STAT_DBUG1_L4FASTDBGFWERR (0x02000000u)
+#define CONTROL_SEC_ERR_STAT_DBUG1_L4FASTDBGFWERR_SHIFT (0x00000019u)
+
+#define CONTROL_SEC_ERR_STAT_DBUG1_L4FWDBGFWERR (0x08000000u)
+#define CONTROL_SEC_ERR_STAT_DBUG1_L4FWDBGFWERR_SHIFT (0x0000001Bu)
+
+#define CONTROL_SEC_ERR_STAT_DBUG1_L4PERDBGFWERR (0x01000000u)
+#define CONTROL_SEC_ERR_STAT_DBUG1_L4PERDBGFWERR_SHIFT (0x00000018u)
+
+#define CONTROL_SEC_ERR_STAT_DBUG1_L4WKUPDBGFWERR (0x04000000u)
+#define CONTROL_SEC_ERR_STAT_DBUG1_L4WKUPDBGFWERR_SHIFT (0x0000001Au)
+
+#define CONTROL_SEC_ERR_STAT_DBUG1_MCASP0DBGFWERR (0x00000001u)
+#define CONTROL_SEC_ERR_STAT_DBUG1_MCASP0DBGFWERR_SHIFT (0x00000000u)
+
+#define CONTROL_SEC_ERR_STAT_DBUG1_MCASP1DBGFWERR (0x00000002u)
+#define CONTROL_SEC_ERR_STAT_DBUG1_MCASP1DBGFWERR_SHIFT (0x00000001u)
+
+#define CONTROL_SEC_ERR_STAT_DBUG1_MMCHS2DBGFWERR (0x00008000u)
+#define CONTROL_SEC_ERR_STAT_DBUG1_MMCHS2DBGFWERR_SHIFT (0x0000000Fu)
+
+#define CONTROL_SEC_ERR_STAT_DBUG1_RSVD2 (0x00000400u)
+#define CONTROL_SEC_ERR_STAT_DBUG1_RSVD2_SHIFT (0x0000000Au)
+
+#define CONTROL_SEC_ERR_STAT_DBUG1_RSVD3 (0x00006000u)
+#define CONTROL_SEC_ERR_STAT_DBUG1_RSVD3_SHIFT (0x0000000Du)
+
+#define CONTROL_SEC_ERR_STAT_DBUG1_RSVD4 (0x00040000u)
+#define CONTROL_SEC_ERR_STAT_DBUG1_RSVD4_SHIFT (0x00000012u)
+
+#define CONTROL_SEC_ERR_STAT_DBUG1_RSVD5 (0x00800000u)
+#define CONTROL_SEC_ERR_STAT_DBUG1_RSVD5_SHIFT (0x00000017u)
+
+#define CONTROL_SEC_ERR_STAT_DBUG1_RSVD6 (0xF0000000u)
+#define CONTROL_SEC_ERR_STAT_DBUG1_RSVD6_SHIFT (0x0000001Cu)
+
+#define CONTROL_SEC_ERR_STAT_DBUG1_SHADBGFWERR (0x00400000u)
+#define CONTROL_SEC_ERR_STAT_DBUG1_SHADBGFWERR_SHIFT (0x00000016u)
+
+#define CONTROL_SEC_ERR_STAT_DBUG1_USBDBGFWERR (0x00000800u)
+#define CONTROL_SEC_ERR_STAT_DBUG1_USBDBGFWERR_SHIFT (0x0000000Bu)
+
+
+/* CONTROL_KEK_SW_0 */
+#define CONTROL_KEK_SW_0_KEK_SW (0xFFFFFFFFu)
+#define CONTROL_KEK_SW_0_KEK_SW_SHIFT (0x00000000u)
+
+
+/* CONTROL_KEK_SW_1 */
+#define CONTROL_KEK_SW_1_KEK_SW (0xFFFFFFFFu)
+#define CONTROL_KEK_SW_1_KEK_SW_SHIFT (0x00000000u)
+
+
+/* CONTROL_KEK_SW_2 */
+#define CONTROL_KEK_SW_2_KEK_SW (0xFFFFFFFFu)
+#define CONTROL_KEK_SW_2_KEK_SW_SHIFT (0x00000000u)
+
+
+/* CONTROL_KEK_SW_3 */
+#define CONTROL_KEK_SW_3_KEK_SW (0xFFFFFFFFu)
+#define CONTROL_KEK_SW_3_KEK_SW_SHIFT (0x00000000u)
+
+
+/* CONTROL_CMPK_BCH_0 */
+#define CONTROL_CMPK_BCH_0_CMPK_BCH (0xFFFFFFFFu)
+#define CONTROL_CMPK_BCH_0_CMPK_BCH_SHIFT (0x00000000u)
+
+
+/* CONTROL_CMPK_BCH_1 */
+#define CONTROL_CMPK_BCH_1_CMPK_BCH (0xFFFFFFFFu)
+#define CONTROL_CMPK_BCH_1_CMPK_BCH_SHIFT (0x00000000u)
+
+
+/* CONTROL_CMPK_BCH_2 */
+#define CONTROL_CMPK_BCH_2_CMPK_BCH (0xFFFFFFFFu)
+#define CONTROL_CMPK_BCH_2_CMPK_BCH_SHIFT (0x00000000u)
+
+
+/* CONTROL_CMPK_BCH_3 */
+#define CONTROL_CMPK_BCH_3_CMPK_BCH (0xFFFFFFFFu)
+#define CONTROL_CMPK_BCH_3_CMPK_BCH_SHIFT (0x00000000u)
+
+
+/* CONTROL_CMPK_BCH_4 */
+#define CONTROL_CMPK_BCH_4_CMPK_BCH (0xFFFFFFFFu)
+#define CONTROL_CMPK_BCH_4_CMPK_BCH_SHIFT (0x00000000u)
+
+
+/* CONTROL_CMPK_BCH_5 */
+#define CONTROL_CMPK_BCH_5_CMPK_BCH (0xFFFFFFFFu)
+#define CONTROL_CMPK_BCH_5_CMPK_BCH_SHIFT (0x00000000u)
+
+
+/* CONTROL_CMPK_BCH_6 */
+#define CONTROL_CMPK_BCH_6_CMPK_BCH (0xFFFFFFFFu)
+#define CONTROL_CMPK_BCH_6_CMPK_BCH_SHIFT (0x00000000u)
+
+
+/* CONTROL_CMPK_BCH_7 */
+#define CONTROL_CMPK_BCH_7_CMPK_BCH (0xFFFFFFFFu)
+#define CONTROL_CMPK_BCH_7_CMPK_BCH_SHIFT (0x00000000u)
+
+
+/* CONTROL_CMPK_BCH_8 */
+#define CONTROL_CMPK_BCH_8_CMPK_BCH (0xFFFFFFFFu)
+#define CONTROL_CMPK_BCH_8_CMPK_BCH_SHIFT (0x00000000u)
+
+
+/* CONTROL_CMPK_0 */
+#define CONTROL_CMPK_0_CMPK (0xFFFFFFFFu)
+#define CONTROL_CMPK_0_CMPK_SHIFT (0x00000000u)
+
+
+/* CONTROL_CMPK_1 */
+#define CONTROL_CMPK_1_CMPK (0xFFFFFFFFu)
+#define CONTROL_CMPK_1_CMPK_SHIFT (0x00000000u)
+
+
+/* CONTROL_CMPK_2 */
+#define CONTROL_CMPK_2_CMPK (0xFFFFFFFFu)
+#define CONTROL_CMPK_2_CMPK_SHIFT (0x00000000u)
+
+
+/* CONTROL_CMPK_3 */
+#define CONTROL_CMPK_3_CMPK (0xFFFFFFFFu)
+#define CONTROL_CMPK_3_CMPK_SHIFT (0x00000000u)
+
+
+/* CONTROL_CMPK_4 */
+#define CONTROL_CMPK_4_CMPK (0xFFFFFFFFu)
+#define CONTROL_CMPK_4_CMPK_SHIFT (0x00000000u)
+
+
+/* CONTROL_CMPK_5 */
+#define CONTROL_CMPK_5_CMPK (0xFFFFFFFFu)
+#define CONTROL_CMPK_5_CMPK_SHIFT (0x00000000u)
+
+
+/* CONTROL_CMPK_6 */
+#define CONTROL_CMPK_6_CMPK (0xFFFFFFFFu)
+#define CONTROL_CMPK_6_CMPK_SHIFT (0x00000000u)
+
+
+/* CONTROL_CMPK_7 */
+#define CONTROL_CMPK_7_CMPK (0xFFFFFFFFu)
+#define CONTROL_CMPK_7_CMPK_SHIFT (0x00000000u)
+
+
+/* SSM_END_FAST_SECRAM */
+#define CONTROL_SSM_END_FAST_SECRAM_END_FAST_SECRAM (0x0000FC00u)
+#define CONTROL_SSM_END_FAST_SECRAM_END_FAST_SECRAM_SHIFT (0x0000000Au)
+
+#define CONTROL_SSM_END_FAST_SECRAM_RSVD2 (0xFFFF0000u)
+#define CONTROL_SSM_END_FAST_SECRAM_RSVD2_SHIFT (0x00000010u)
+
+
+/* SSM_FIREWALL_CONTROLLER */
+#define CONTROL_SSM_FIREWALL_CONTROLLER_CPSR_ENFC_EN (0x00001000u)
+#define CONTROL_SSM_FIREWALL_CONTROLLER_CPSR_ENFC_EN_SHIFT (0x0000000Cu)
+
+#define CONTROL_SSM_FIREWALL_CONTROLLER_DC_ENFC_EN (0x00000800u)
+#define CONTROL_SSM_FIREWALL_CONTROLLER_DC_ENFC_EN_SHIFT (0x0000000Bu)
+
+#define CONTROL_SSM_FIREWALL_CONTROLLER_IC_ENFC_EN (0x00000400u)
+#define CONTROL_SSM_FIREWALL_CONTROLLER_IC_ENFC_EN_SHIFT (0x0000000Au)
+
+#define CONTROL_SSM_FIREWALL_CONTROLLER_MMU_ENFC_EN (0x00000200u)
+#define CONTROL_SSM_FIREWALL_CONTROLLER_MMU_ENFC_EN_SHIFT (0x00000009u)
+
+#define CONTROL_SSM_FIREWALL_CONTROLLER_MONITOR_EN (0x00000001u)
+#define CONTROL_SSM_FIREWALL_CONTROLLER_MONITOR_EN_SHIFT (0x00000000u)
+
+#define CONTROL_SSM_FIREWALL_CONTROLLER_MON_DATA_TRASH_EN (0x00000080u)
+#define CONTROL_SSM_FIREWALL_CONTROLLER_MON_DATA_TRASH_EN_SHIFT (0x00000007u)
+
+#define CONTROL_SSM_FIREWALL_CONTROLLER_MON_DETM_EN (0x00000020u)
+#define CONTROL_SSM_FIREWALL_CONTROLLER_MON_DETM_EN_SHIFT (0x00000005u)
+
+#define CONTROL_SSM_FIREWALL_CONTROLLER_MON_IETM_EN (0x00000010u)
+#define CONTROL_SSM_FIREWALL_CONTROLLER_MON_IETM_EN_SHIFT (0x00000004u)
+
+#define CONTROL_SSM_FIREWALL_CONTROLLER_MON_RAMCODE_EN (0x00000100u)
+#define CONTROL_SSM_FIREWALL_CONTROLLER_MON_RAMCODE_EN_SHIFT (0x00000008u)
+
+#define CONTROL_SSM_FIREWALL_CONTROLLER_MON_STACK_EN (0x00000040u)
+#define CONTROL_SSM_FIREWALL_CONTROLLER_MON_STACK_EN_SHIFT (0x00000006u)
+
+#define CONTROL_SSM_FIREWALL_CONTROLLER_SECRAM_EN (0x00000002u)
+#define CONTROL_SSM_FIREWALL_CONTROLLER_SECRAM_EN_SHIFT (0x00000001u)
+
+#define CONTROL_SSM_FIREWALL_CONTROLLER_SPM_STACK_EN (0x00000008u)
+#define CONTROL_SSM_FIREWALL_CONTROLLER_SPM_STACK_EN_SHIFT (0x00000003u)
+
+#define CONTROL_SSM_FIREWALL_CONTROLLER_SSM_FC_REG_LOCK (0x00002000u)
+#define CONTROL_SSM_FIREWALL_CONTROLLER_SSM_FC_REG_LOCK_SHIFT (0x0000000Du)
+
+#define CONTROL_SSM_FIREWALL_CONTROLLER_STACKEDRAM_EN (0x00000004u)
+#define CONTROL_SSM_FIREWALL_CONTROLLER_STACKEDRAM_EN_SHIFT (0x00000002u)
+
+
+/* SSM_START_SECURE_STACKED_RAM */
+#define CONTROL_SSM_START_SECURE_STACKED_RAM_START_STACKEDRAM (0xFFFF0000u)
+#define CONTROL_SSM_START_SECURE_STACKED_RAM_START_STACKEDRAM_SHIFT (0x00000010u)
+
+
+/* SSM_END_SECURE_STACKED_RAM */
+#define CONTROL_SSM_END_SECURE_STACKED_RAM_END_STACKEDRAM (0xFFFF0000u)
+#define CONTROL_SSM_END_SECURE_STACKED_RAM_END_STACKEDRAM_SHIFT (0x00000010u)
+
+
+/* SSM_START_SPM_STACK */
+#define CONTROL_SSM_START_SPM_STACK_START_SPM_STACK (0xFFFFFC00u)
+#define CONTROL_SSM_START_SPM_STACK_START_SPM_STACK_SHIFT (0x0000000Au)
+
+
+/* SSM_END_SPM_STACK */
+#define CONTROL_SSM_END_SPM_STACK_END_SPM_STACK (0x0000FC00u)
+#define CONTROL_SSM_END_SPM_STACK_END_SPM_STACK_SHIFT (0x0000000Au)
+
+#define CONTROL_SSM_END_SPM_STACK_START_SPM_STACK (0xFFFF0000u)
+#define CONTROL_SSM_END_SPM_STACK_START_SPM_STACK_SHIFT (0x00000010u)
+
+
+/* SSM_START_MONITOR_RAMCODE */
+#define CONTROL_SSM_START_MONITOR_RAMCODE_START_MON_RAMCODE (0xFFFFFC00u)
+#define CONTROL_SSM_START_MONITOR_RAMCODE_START_MON_RAMCODE_SHIFT (0x0000000Au)
+
+
+/* SSM_END_MONITOR_RAMCODE */
+#define CONTROL_SSM_END_MONITOR_RAMCODE_END_MON_RAMCODE (0x0000FC00u)
+#define CONTROL_SSM_END_MONITOR_RAMCODE_END_MON_RAMCODE_SHIFT (0x0000000Au)
+
+#define CONTROL_SSM_END_MONITOR_RAMCODE_START_MON_RAMCODE (0xFFFF0000u)
+#define CONTROL_SSM_END_MONITOR_RAMCODE_START_MON_RAMCODE_SHIFT (0x00000010u)
+
+
+/* SSM_END_MONITOR_RAMDATA */
+#define CONTROL_SSM_END_MONITOR_RAMDATA_END_MON_RAMDATA (0x0000FC00u)
+#define CONTROL_SSM_END_MONITOR_RAMDATA_END_MON_RAMDATA_SHIFT (0x0000000Au)
+
+#define CONTROL_SSM_END_MONITOR_RAMDATA_START_MON_RAMCODE (0xFFFF0000u)
+#define CONTROL_SSM_END_MONITOR_RAMDATA_START_MON_RAMCODE_SHIFT (0x00000010u)
+
+
+/* SSM_START_MONITOR_CODE */
+#define CONTROL_SSM_START_MONITOR_CODE_START_MON_CODE (0xFFFFFC00u)
+#define CONTROL_SSM_START_MONITOR_CODE_START_MON_CODE_SHIFT (0x0000000Au)
+
+
+/* SSM_END_MONITOR_CODE */
+#define CONTROL_SSM_END_MONITOR_CODE_END_MON_CODE (0x0001FC00u)
+#define CONTROL_SSM_END_MONITOR_CODE_END_MON_CODE_SHIFT (0x0000000Au)
+
+#define CONTROL_SSM_END_MONITOR_CODE_START_MON_CODE (0xFFFE0000u)
+#define CONTROL_SSM_END_MONITOR_CODE_START_MON_CODE_SHIFT (0x00000011u)
+
+
+/* SSM_START_MONITOR_PERIPH */
+#define CONTROL_SSM_START_MONITOR_PERIPH_START_MON_PERIPH (0xFFFFF000u)
+#define CONTROL_SSM_START_MONITOR_PERIPH_START_MON_PERIPH_SHIFT (0x0000000Cu)
+
+
+/* SSM_END_MONITOR_PERIPH */
+#define CONTROL_SSM_END_MONITOR_PERIPH_END_MON_PERIPH (0x0FFFF000u)
+#define CONTROL_SSM_END_MONITOR_PERIPH_END_MON_PERIPH_SHIFT (0x0000000Cu)
+
+#define CONTROL_SSM_END_MONITOR_PERIPH_START_MON_PERIPH (0xF0000000u)
+#define CONTROL_SSM_END_MONITOR_PERIPH_START_MON_PERIPH_SHIFT (0x0000001Cu)
+
+
+/* SSM_START_MONITOR_STACK */
+#define CONTROL_SSM_START_MONITOR_STACK_START_MON_STACK (0xFFFFFC00u)
+#define CONTROL_SSM_START_MONITOR_STACK_START_MON_STACK_SHIFT (0x0000000Au)
+
+
+/* SSM_END_MONITOR_STACK */
+#define CONTROL_SSM_END_MONITOR_STACK_END_MON_STACK (0x00007C00u)
+#define CONTROL_SSM_END_MONITOR_STACK_END_MON_STACK_SHIFT (0x0000000Au)
+
+#define CONTROL_SSM_END_MONITOR_STACK_START_MON_STACK (0xFFFF8000u)
+#define CONTROL_SSM_END_MONITOR_STACK_START_MON_STACK_SHIFT (0x0000000Fu)
+
+
+/* SSM_START_MONITOR_RAMCODE_ETM */
+#define CONTROL_SSM_START_MONITOR_RAMCODE_ETM_START_MON_RAMCODE_ETM (0xFFFFF000u)
+#define CONTROL_SSM_START_MONITOR_RAMCODE_ETM_START_MON_RAMCODE_ETM_SHIFT (0x0000000Cu)
+
+
+/* SSM_END_MONITOR_RAMCODE_ETM */
+#define CONTROL_SSM_END_MONITOR_RAMCODE_ETM_END_MON_RAMCODE_ETM (0x0000F000u)
+#define CONTROL_SSM_END_MONITOR_RAMCODE_ETM_END_MON_RAMCODE_ETM_SHIFT (0x0000000Cu)
+
+#define CONTROL_SSM_END_MONITOR_RAMCODE_ETM_START_MON_RAMCODE_ETM (0xFFFF0000u)
+#define CONTROL_SSM_END_MONITOR_RAMCODE_ETM_START_MON_RAMCODE_ETM_SHIFT (0x00000010u)
+
+
+/* SSM_END_MONITOR_RAMDATA_ETM */
+#define CONTROL_SSM_END_MONITOR_RAMDATA_ETM_END_MON_RAMDATA_ETM (0x0000F000u)
+#define CONTROL_SSM_END_MONITOR_RAMDATA_ETM_END_MON_RAMDATA_ETM_SHIFT (0x0000000Cu)
+
+#define CONTROL_SSM_END_MONITOR_RAMDATA_ETM_START_MON_RAMCODE_ETM (0xFFFF0000u)
+#define CONTROL_SSM_END_MONITOR_RAMDATA_ETM_START_MON_RAMCODE_ETM_SHIFT (0x00000010u)
+
+
+/* SSM_START_MONITOR_CODE_ETM */
+#define CONTROL_SSM_START_MONITOR_CODE_ETM_START_MON_CODE_ETM (0xFFFFF000u)
+#define CONTROL_SSM_START_MONITOR_CODE_ETM_START_MON_CODE_ETM_SHIFT (0x0000000Cu)
+
+
+/* SSM_END_MONITOR_CODE_ETM */
+#define CONTROL_SSM_END_MONITOR_CODE_ETM_END_MON_CODE_ETM (0x0001F000u)
+#define CONTROL_SSM_END_MONITOR_CODE_ETM_END_MON_CODE_ETM_SHIFT (0x0000000Cu)
+
+#define CONTROL_SSM_END_MONITOR_CODE_ETM_START_MON_CODE_ETM (0xFFFE0000u)
+#define CONTROL_SSM_END_MONITOR_CODE_ETM_START_MON_CODE_ETM_SHIFT (0x00000011u)
+
+
+/* SSM_START_MONITOR_STACK_ETM */
+#define CONTROL_SSM_START_MONITOR_STACK_ETM_START_MON_STACK_ETM (0xFFFFF000u)
+#define CONTROL_SSM_START_MONITOR_STACK_ETM_START_MON_STACK_ETM_SHIFT (0x0000000Cu)
+
+
+/* SSM_END_MONITOR_STACK_ETM */
+#define CONTROL_SSM_END_MONITOR_STACK_ETM_END_MON_STACK_ETM (0x0000F000u)
+#define CONTROL_SSM_END_MONITOR_STACK_ETM_END_MON_STACK_ETM_SHIFT (0x0000000Cu)
+
+#define CONTROL_SSM_END_MONITOR_STACK_ETM_START_MON_STACK_ETM (0xFFFF0000u)
+#define CONTROL_SSM_END_MONITOR_STACK_ETM_START_MON_STACK_ETM_SHIFT (0x00000010u)
+
+
+/* SSM_START_MONITOR_SHARED_ETM */
+#define CONTROL_SSM_START_MONITOR_SHARED_ETM_START_MON_SHARED_ETM (0xFFFFF000u)
+#define CONTROL_SSM_START_MONITOR_SHARED_ETM_START_MON_SHARED_ETM_SHIFT (0x0000000Cu)
+
+
+/* SSM_END_MONITOR_SHARED_ETM */
+#define CONTROL_SSM_END_MONITOR_SHARED_ETM_END_MON_SHARED_ETM (0x0000F000u)
+#define CONTROL_SSM_END_MONITOR_SHARED_ETM_END_MON_SHARED_ETM_SHIFT (0x0000000Cu)
+
+#define CONTROL_SSM_END_MONITOR_SHARED_ETM_START_MON_SHARED_ETM (0xFFFF0000u)
+#define CONTROL_SSM_END_MONITOR_SHARED_ETM_START_MON_SHARED_ETM_SHIFT (0x00000010u)
+
+
+/* SSM_START_MONITOR_PERIPH_ETM */
+#define CONTROL_SSM_START_MONITOR_PERIPH_ETM_START_MON_PERIPH_ETM (0xFFFFF000u)
+#define CONTROL_SSM_START_MONITOR_PERIPH_ETM_START_MON_PERIPH_ETM_SHIFT (0x0000000Cu)
+
+
+/* SSM_END_MONITOR_PERIPH_ETM */
+#define CONTROL_SSM_END_MONITOR_PERIPH_ETM_END_MON_PERIPH_ETM (0xFFFFF000u)
+#define CONTROL_SSM_END_MONITOR_PERIPH_ETM_END_MON_PERIPH_ETM_SHIFT (0x0000000Cu)
+
+
+/* SSM_CPSR_MODE_ENFC */
+#define CONTROL_SSM_CPSR_MODE_ENFC_EA_TRAPPED_IN_MON (0x00000100u)
+#define CONTROL_SSM_CPSR_MODE_ENFC_EA_TRAPPED_IN_MON_SHIFT (0x00000008u)
+
+#define CONTROL_SSM_CPSR_MODE_ENFC_FIQ_TRAPPED_IN_MON (0x00000080u)
+#define CONTROL_SSM_CPSR_MODE_ENFC_FIQ_TRAPPED_IN_MON_SHIFT (0x00000007u)
+
+#define CONTROL_SSM_CPSR_MODE_ENFC_IRQ_TRAPPED_IN_MON (0x00000040u)
+#define CONTROL_SSM_CPSR_MODE_ENFC_IRQ_TRAPPED_IN_MON_SHIFT (0x00000006u)
+
+#define CONTROL_SSM_CPSR_MODE_ENFC_MON_VS_ABORT_ENFC (0x00000004u)
+#define CONTROL_SSM_CPSR_MODE_ENFC_MON_VS_ABORT_ENFC_SHIFT (0x00000002u)
+
+#define CONTROL_SSM_CPSR_MODE_ENFC_MON_VS_SYS_ENFC (0x00000010u)
+#define CONTROL_SSM_CPSR_MODE_ENFC_MON_VS_SYS_ENFC_SHIFT (0x00000004u)
+
+#define CONTROL_SSM_CPSR_MODE_ENFC_MON_VS_UNDEF_ENFC (0x00000008u)
+#define CONTROL_SSM_CPSR_MODE_ENFC_MON_VS_UNDEF_ENFC_SHIFT (0x00000003u)
+
+#define CONTROL_SSM_CPSR_MODE_ENFC_MON_VS_USER_ENFC (0x00000002u)
+#define CONTROL_SSM_CPSR_MODE_ENFC_MON_VS_USER_ENFC_SHIFT (0x00000001u)
+
+#define CONTROL_SSM_CPSR_MODE_ENFC_SYS_VS_USER_ENFC (0x00000020u)
+#define CONTROL_SSM_CPSR_MODE_ENFC_SYS_VS_USER_ENFC_SHIFT (0x00000005u)
+
+#define CONTROL_SSM_CPSR_MODE_ENFC_TZ_NS_BIT_ENFC (0x00000001u)
+#define CONTROL_SSM_CPSR_MODE_ENFC_TZ_NS_BIT_ENFC_SHIFT (0x00000000u)
+
+
+/* SSM_END_L3_SECRAM */
+#define CONTROL_SSM_END_L3_SECRAM_END_L3_SECRAM (0x0000FC00u)
+#define CONTROL_SSM_END_L3_SECRAM_END_L3_SECRAM_SHIFT (0x0000000Au)
+
+#define CONTROL_SSM_END_L3_SECRAM_RSVD2 (0xFFFF0000u)
+#define CONTROL_SSM_END_L3_SECRAM_RSVD2_SHIFT (0x00000010u)
+
+
+/* CORTEX_VBBLDO_CTRL */
+#define CONTROL_CORTEX_VBBLDO_CTRL_BBSEL (0x00000004u)
+#define CONTROL_CORTEX_VBBLDO_CTRL_BBSEL_SHIFT (0x00000002u)
+
+#define CONTROL_CORTEX_VBBLDO_CTRL_HZ (0x00000008u)
+#define CONTROL_CORTEX_VBBLDO_CTRL_HZ_SHIFT (0x00000003u)
+
+#define CONTROL_CORTEX_VBBLDO_CTRL_LDOBYPASSZ (0x00000020u)
+#define CONTROL_CORTEX_VBBLDO_CTRL_LDOBYPASSZ_SHIFT (0x00000005u)
+
+#define CONTROL_CORTEX_VBBLDO_CTRL_LOWPWR (0x00000010u)
+#define CONTROL_CORTEX_VBBLDO_CTRL_LOWPWR_SHIFT (0x00000004u)
+
+#define CONTROL_CORTEX_VBBLDO_CTRL_NOCAP (0x00000002u)
+#define CONTROL_CORTEX_VBBLDO_CTRL_NOCAP_SHIFT (0x00000001u)
+
+#define CONTROL_CORTEX_VBBLDO_CTRL_NOVBGBYR (0x00000001u)
+#define CONTROL_CORTEX_VBBLDO_CTRL_NOVBGBYR_SHIFT (0x00000000u)
+
+#define CONTROL_CORTEX_VBBLDO_CTRL_RSVD2 (0xFC000000u)
+#define CONTROL_CORTEX_VBBLDO_CTRL_RSVD2_SHIFT (0x0000001Au)
+
+#define CONTROL_CORTEX_VBBLDO_CTRL_VSETFBB (0x03E00000u)
+#define CONTROL_CORTEX_VBBLDO_CTRL_VSETFBB_SHIFT (0x00000015u)
+
+#define CONTROL_CORTEX_VBBLDO_CTRL_VSETRBB (0x001F0000u)
+#define CONTROL_CORTEX_VBBLDO_CTRL_VSETRBB_SHIFT (0x00000010u)
+
+
+/* CORE_SLDO_CTRL */
+#define CONTROL_CORE_SLDO_CTRL_RSVD2 (0xFC000000u)
+#define CONTROL_CORE_SLDO_CTRL_RSVD2_SHIFT (0x0000001Au)
+
+#define CONTROL_CORE_SLDO_CTRL_VSET (0x03FF0000u)
+#define CONTROL_CORE_SLDO_CTRL_VSET_SHIFT (0x00000010u)
+
+
+/* MPU_SLDO_CTRL */
+#define CONTROL_MPU_SLDO_CTRL_RSVD2 (0xFC000000u)
+#define CONTROL_MPU_SLDO_CTRL_RSVD2_SHIFT (0x0000001Au)
+
+#define CONTROL_MPU_SLDO_CTRL_VSET (0x03FF0000u)
+#define CONTROL_MPU_SLDO_CTRL_VSET_SHIFT (0x00000010u)
+
+
+/* REFCLK_LJCBLDO_CTRL */
+#define CONTROL_REFCLK_LJCBLDO_CTRL_ABBOFF (0x00000040u)
+#define CONTROL_REFCLK_LJCBLDO_CTRL_ABBOFF_SHIFT (0x00000006u)
+
+#define CONTROL_REFCLK_LJCBLDO_CTRL_AIPOFF (0x00000080u)
+#define CONTROL_REFCLK_LJCBLDO_CTRL_AIPOFF_SHIFT (0x00000007u)
+
+#define CONTROL_REFCLK_LJCBLDO_CTRL_ENFUNC1 (0x00000001u)
+#define CONTROL_REFCLK_LJCBLDO_CTRL_ENFUNC1_SHIFT (0x00000000u)
+
+#define CONTROL_REFCLK_LJCBLDO_CTRL_ENFUNC2 (0x00000002u)
+#define CONTROL_REFCLK_LJCBLDO_CTRL_ENFUNC2_SHIFT (0x00000001u)
+
+#define CONTROL_REFCLK_LJCBLDO_CTRL_ENFUNC3 (0x00000004u)
+#define CONTROL_REFCLK_LJCBLDO_CTRL_ENFUNC3_SHIFT (0x00000002u)
+
+#define CONTROL_REFCLK_LJCBLDO_CTRL_ENFUNC4 (0x00000008u)
+#define CONTROL_REFCLK_LJCBLDO_CTRL_ENFUNC4_SHIFT (0x00000003u)
+
+#define CONTROL_REFCLK_LJCBLDO_CTRL_ENFUNC5 (0x00000010u)
+#define CONTROL_REFCLK_LJCBLDO_CTRL_ENFUNC5_SHIFT (0x00000004u)
+
+#define CONTROL_REFCLK_LJCBLDO_CTRL_RSVD2 (0xFC000000u)
+#define CONTROL_REFCLK_LJCBLDO_CTRL_RSVD2_SHIFT (0x0000001Au)
+
+#define CONTROL_REFCLK_LJCBLDO_CTRL_VSET (0x03FF0000u)
+#define CONTROL_REFCLK_LJCBLDO_CTRL_VSET_SHIFT (0x00000010u)
+
+
+/* CLK32KDIVRATIO_CTRL */
+#define CONTROL_CLK32KDIVRATIO_CTRL_CLKDIVOPP50_EN (0x00000001u)
+#define CONTROL_CLK32KDIVRATIO_CTRL_CLKDIVOPP50_EN_SHIFT (0x00000000u)
+
+
+/* BANDGAP_CTRL */
+#define CONTROL_BANDGAP_CTRL_BGROFF (0x00000040u)
+#define CONTROL_BANDGAP_CTRL_BGROFF_SHIFT (0x00000006u)
+
+#define CONTROL_BANDGAP_CTRL_CBIASSEL (0x00000080u)
+#define CONTROL_BANDGAP_CTRL_CBIASSEL_SHIFT (0x00000007u)
+
+#define CONTROL_BANDGAP_CTRL_CLRZ (0x00000008u)
+#define CONTROL_BANDGAP_CTRL_CLRZ_SHIFT (0x00000003u)
+
+#define CONTROL_BANDGAP_CTRL_CONTCONV (0x00000004u)
+#define CONTROL_BANDGAP_CTRL_CONTCONV_SHIFT (0x00000002u)
+
+#define CONTROL_BANDGAP_CTRL_DTEMP (0x0000FF00u)
+#define CONTROL_BANDGAP_CTRL_DTEMP_SHIFT (0x00000008u)
+
+#define CONTROL_BANDGAP_CTRL_ECOZ (0x00000002u)
+#define CONTROL_BANDGAP_CTRL_ECOZ_SHIFT (0x00000001u)
+
+#define CONTROL_BANDGAP_CTRL_SOC (0x00000010u)
+#define CONTROL_BANDGAP_CTRL_SOC_SHIFT (0x00000004u)
+
+#define CONTROL_BANDGAP_CTRL_TMPSOFF (0x00000020u)
+#define CONTROL_BANDGAP_CTRL_TMPSOFF_SHIFT (0x00000005u)
+
+#define CONTROL_BANDGAP_CTRL_TSHUT (0x00000001u)
+#define CONTROL_BANDGAP_CTRL_TSHUT_SHIFT (0x00000000u)
+
+
+/* BANDGAP_TRIM */
+#define CONTROL_BANDGAP_TRIM_DTRBGAPC (0xFF000000u)
+#define CONTROL_BANDGAP_TRIM_DTRBGAPC_SHIFT (0x00000018u)
+
+#define CONTROL_BANDGAP_TRIM_DTRBGAPV (0x00FF0000u)
+#define CONTROL_BANDGAP_TRIM_DTRBGAPV_SHIFT (0x00000010u)
+
+#define CONTROL_BANDGAP_TRIM_DTRTEMPS (0x0000FF00u)
+#define CONTROL_BANDGAP_TRIM_DTRTEMPS_SHIFT (0x00000008u)
+
+#define CONTROL_BANDGAP_TRIM_DTRTEMPSC (0x000000FFu)
+#define CONTROL_BANDGAP_TRIM_DTRTEMPSC_SHIFT (0x00000000u)
+
+
+/* PLL_CLKINPULOW_CTRL */
+#define CONTROL_PLL_CLKINPULOW_CTRL_DDR_PLL_CLKINPULOW_SEL (0x00000004u)
+#define CONTROL_PLL_CLKINPULOW_CTRL_DDR_PLL_CLKINPULOW_SEL_SHIFT (0x00000002u)
+
+#define CONTROL_PLL_CLKINPULOW_CTRL_DISP_PLL_CLKINPULOW_SEL (0x00000002u)
+#define CONTROL_PLL_CLKINPULOW_CTRL_DISP_PLL_CLKINPULOW_SEL_SHIFT (0x00000001u)
+
+#define CONTROL_PLL_CLKINPULOW_CTRL_MPU_DPLL_CLKINPULOW_SEL (0x00000001u)
+#define CONTROL_PLL_CLKINPULOW_CTRL_MPU_DPLL_CLKINPULOW_SEL_SHIFT (0x00000000u)
+
+
+/* MOSC_CTRL */
+#define CONTROL_MOSC_CTRL_RESSELECT (0x00000001u)
+#define CONTROL_MOSC_CTRL_RESSELECT_SHIFT (0x00000000u)
+
+
+/* RCOSC_CTRL */
+#define CONTROL_RCOSC_CTRL_STOPOSC (0x00000001u)
+#define CONTROL_RCOSC_CTRL_STOPOSC_SHIFT (0x00000000u)
+
+
+/* DEEPSLEEP_CTRL */
+#define CONTROL_DEEPSLEEP_CTRL_DSCOUNT (0x0000FFFFu)
+#define CONTROL_DEEPSLEEP_CTRL_DSCOUNT_SHIFT (0x00000000u)
+
+#define CONTROL_DEEPSLEEP_CTRL_DSENABLE (0x00020000u)
+#define CONTROL_DEEPSLEEP_CTRL_DSENABLE_SHIFT (0x00000011u)
+
+#define CONTROL_DEEPSLEEP_CTRL_RSVD2 (0xFFFC0000u)
+#define CONTROL_DEEPSLEEP_CTRL_RSVD2_SHIFT (0x00000012u)
+
+
+/* PE_SCRATCHPAD_0 */
+#define CONTROL_PE_SCRATCHPAD_0_PE_SCRATCHPAD_0 (0xFFFFFFFFu)
+#define CONTROL_PE_SCRATCHPAD_0_PE_SCRATCHPAD_0_SHIFT (0x00000000u)
+
+
+/* PE_SCRATCHPAD_1 */
+#define CONTROL_PE_SCRATCHPAD_1_PE_SCRATCHPAD_1 (0xFFFFFFFFu)
+#define CONTROL_PE_SCRATCHPAD_1_PE_SCRATCHPAD_1_SHIFT (0x00000000u)
+
+
+/* PE_SCRATCHPAD_2 */
+#define CONTROL_PE_SCRATCHPAD_2_PE_SCRATCHPAD_2 (0xFFFFFFFFu)
+#define CONTROL_PE_SCRATCHPAD_2_PE_SCRATCHPAD_2_SHIFT (0x00000000u)
+
+
+/* PE_SCRATCHPAD_3 */
+#define CONTROL_PE_SCRATCHPAD_3_PE_SCRATCHPAD_3 (0xFFFFFFFFu)
+#define CONTROL_PE_SCRATCHPAD_3_PE_SCRATCHPAD_3_SHIFT (0x00000000u)
+
+
+/* DEVICE_ID */
+#define CONTROL_DEVICE_ID_DEVREV (0xF0000000u)
+#define CONTROL_DEVICE_ID_DEVREV_SHIFT (0x0000001Cu)
+
+#define CONTROL_DEVICE_ID_MFGR (0x00000FFEu)
+#define CONTROL_DEVICE_ID_MFGR_SHIFT (0x00000001u)
+
+#define CONTROL_DEVICE_ID_PARTNUM (0x0FFFF000u)
+#define CONTROL_DEVICE_ID_PARTNUM_SHIFT (0x0000000Cu)
+
+
+/* DEV_FEATURE */
+#define CONTROL_DEV_FEATURE_CPSW (0x00000002u)
+#define CONTROL_DEV_FEATURE_CPSW_SHIFT (0x00000001u)
+
+#define CONTROL_DEV_FEATURE_DCAN (0x00000080u)
+#define CONTROL_DEV_FEATURE_DCAN_SHIFT (0x00000007u)
+
+#define CONTROL_DEV_FEATURE_ICSS (0x00000001u)
+#define CONTROL_DEV_FEATURE_ICSS_SHIFT (0x00000000u)
+
+#define CONTROL_DEV_FEATURE_ICSS_FEA (0x00FF0000u)
+#define CONTROL_DEV_FEATURE_ICSS_FEA_SHIFT (0x00000010u)
+
+#define CONTROL_DEV_FEATURE_RSVD2 (0x0000FC00u)
+#define CONTROL_DEV_FEATURE_RSVD2_SHIFT (0x0000000Au)
+
+#define CONTROL_DEV_FEATURE_RSVD3 (0x1F000000u)
+#define CONTROL_DEV_FEATURE_RSVD3_SHIFT (0x00000018u)
+
+#define CONTROL_DEV_FEATURE_RSVD4 (0xC0000000u)
+#define CONTROL_DEV_FEATURE_RSVD4_SHIFT (0x0000001Eu)
+
+#define CONTROL_DEV_FEATURE_SEC_PKA_RNG_SHA (0x00000200u)
+#define CONTROL_DEV_FEATURE_SEC_PKA_RNG_SHA_SHIFT (0x00000009u)
+
+#define CONTROL_DEV_FEATURE_SGX (0x20000000u)
+#define CONTROL_DEV_FEATURE_SGX_SHIFT (0x0000001Du)
+
+
+/* INIT_PRIORITY_0 */
+#define CONTROL_INIT_PRIORITY_0_HOST_ARM (0x00000003u)
+#define CONTROL_INIT_PRIORITY_0_HOST_ARM_SHIFT (0x00000000u)
+
+#define CONTROL_INIT_PRIORITY_0_MMU (0x000000C0u)
+#define CONTROL_INIT_PRIORITY_0_MMU_SHIFT (0x00000006u)
+
+#define CONTROL_INIT_PRIORITY_0_P1500 (0x0000C000u)
+#define CONTROL_INIT_PRIORITY_0_P1500_SHIFT (0x0000000Eu)
+
+#define CONTROL_INIT_PRIORITY_0_PRUSS0 (0x0000000Cu)
+#define CONTROL_INIT_PRIORITY_0_PRUSS0_SHIFT (0x00000002u)
+
+#define CONTROL_INIT_PRIORITY_0_PRUSS1 (0x00000030u)
+#define CONTROL_INIT_PRIORITY_0_PRUSS1_SHIFT (0x00000004u)
+
+#define CONTROL_INIT_PRIORITY_0_RSVD2 (0xF0000000u)
+#define CONTROL_INIT_PRIORITY_0_RSVD2_SHIFT (0x0000001Cu)
+
+#define CONTROL_INIT_PRIORITY_0_TCRD0 (0x00030000u)
+#define CONTROL_INIT_PRIORITY_0_TCRD0_SHIFT (0x00000010u)
+
+#define CONTROL_INIT_PRIORITY_0_TCRD1 (0x00300000u)
+#define CONTROL_INIT_PRIORITY_0_TCRD1_SHIFT (0x00000014u)
+
+#define CONTROL_INIT_PRIORITY_0_TCRD2 (0x03000000u)
+#define CONTROL_INIT_PRIORITY_0_TCRD2_SHIFT (0x00000018u)
+
+#define CONTROL_INIT_PRIORITY_0_TCWR0 (0x000C0000u)
+#define CONTROL_INIT_PRIORITY_0_TCWR0_SHIFT (0x00000012u)
+
+#define CONTROL_INIT_PRIORITY_0_TCWR1 (0x00C00000u)
+#define CONTROL_INIT_PRIORITY_0_TCWR1_SHIFT (0x00000016u)
+
+#define CONTROL_INIT_PRIORITY_0_TCWR2 (0x0C000000u)
+#define CONTROL_INIT_PRIORITY_0_TCWR2_SHIFT (0x0000001Au)
+
+
+/* INIT_PRIORITY_1 */
+#define CONTROL_INIT_PRIORITY_1_CPSW (0x00000003u)
+#define CONTROL_INIT_PRIORITY_1_CPSW_SHIFT (0x00000000u)
+
+#define CONTROL_INIT_PRIORITY_1_DEBUG (0x03000000u)
+#define CONTROL_INIT_PRIORITY_1_DEBUG_SHIFT (0x00000018u)
+
+#define CONTROL_INIT_PRIORITY_1_LCD (0x00C00000u)
+#define CONTROL_INIT_PRIORITY_1_LCD_SHIFT (0x00000016u)
+
+#define CONTROL_INIT_PRIORITY_1_RSVD2 (0x0000FF00u)
+#define CONTROL_INIT_PRIORITY_1_RSVD2_SHIFT (0x00000008u)
+
+#define CONTROL_INIT_PRIORITY_1_RSVD3 (0x000C0000u)
+#define CONTROL_INIT_PRIORITY_1_RSVD3_SHIFT (0x00000012u)
+
+#define CONTROL_INIT_PRIORITY_1_RSVD4 (0xFC000000u)
+#define CONTROL_INIT_PRIORITY_1_RSVD4_SHIFT (0x0000001Au)
+
+#define CONTROL_INIT_PRIORITY_1_SGX (0x00300000u)
+#define CONTROL_INIT_PRIORITY_1_SGX_SHIFT (0x00000014u)
+
+#define CONTROL_INIT_PRIORITY_1_USB_DMA (0x00000030u)
+#define CONTROL_INIT_PRIORITY_1_USB_DMA_SHIFT (0x00000004u)
+
+#define CONTROL_INIT_PRIORITY_1_USB_QMGR (0x000000C0u)
+#define CONTROL_INIT_PRIORITY_1_USB_QMGR_SHIFT (0x00000006u)
+
+
+/* MMU_CFG */
+#define CONTROL_MMU_CFG_MMU_ABORT (0x00008000u)
+#define CONTROL_MMU_CFG_MMU_ABORT_SHIFT (0x0000000Fu)
+
+#define CONTROL_MMU_CFG_MMU_DISABLE (0x00000080u)
+#define CONTROL_MMU_CFG_MMU_DISABLE_SHIFT (0x00000007u)
+
+#define CONTROL_MMU_CFG_RSVD2 (0x00007F00u)
+#define CONTROL_MMU_CFG_RSVD2_SHIFT (0x00000008u)
+
+#define CONTROL_MMU_CFG_RSVD3 (0xFFFF0000u)
+#define CONTROL_MMU_CFG_RSVD3_SHIFT (0x00000010u)
+
+
+/* TPTC_CFG */
+#define CONTROL_TPTC_CFG_TC0DBS (0x00000003u)
+#define CONTROL_TPTC_CFG_TC0DBS_SHIFT (0x00000000u)
+
+#define CONTROL_TPTC_CFG_TC1DBS (0x0000000Cu)
+#define CONTROL_TPTC_CFG_TC1DBS_SHIFT (0x00000002u)
+
+#define CONTROL_TPTC_CFG_TC2DBS (0x00000030u)
+#define CONTROL_TPTC_CFG_TC2DBS_SHIFT (0x00000004u)
+
+
+/* OCMC_CFG */
+#define CONTROL_OCMC_CFG_PAR_EN (0x00000001u)
+#define CONTROL_OCMC_CFG_PAR_EN_SHIFT (0x00000000u)
+
+#define CONTROL_OCMC_CFG_PAR_INT_CLR (0x00000010u)
+#define CONTROL_OCMC_CFG_PAR_INT_CLR_SHIFT (0x00000004u)
+
+#define CONTROL_OCMC_CFG_PAR_RESP_EN (0x00000002u)
+#define CONTROL_OCMC_CFG_PAR_RESP_EN_SHIFT (0x00000001u)
+
+#define CONTROL_OCMC_CFG_RSVD2 (0xFFFFFFE0u)
+#define CONTROL_OCMC_CFG_RSVD2_SHIFT (0x00000005u)
+
+
+/* USB_CTRL0 */
+#define CONTROL_USB_CTRL0_CDET_EXTCTL (0x00000400u)
+#define CONTROL_USB_CTRL0_CDET_EXTCTL_SHIFT (0x0000000Au)
+
+#define CONTROL_USB_CTRL0_CHGDET_DIS (0x00000004u)
+#define CONTROL_USB_CTRL0_CHGDET_DIS_SHIFT (0x00000002u)
+
+#define CONTROL_USB_CTRL0_CHGDET_RSTRT (0x00000008u)
+#define CONTROL_USB_CTRL0_CHGDET_RSTRT_SHIFT (0x00000003u)
+
+#define CONTROL_USB_CTRL0_CHGISINK_EN (0x00000040u)
+#define CONTROL_USB_CTRL0_CHGISINK_EN_SHIFT (0x00000006u)
+
+#define CONTROL_USB_CTRL0_CHGVSRC_EN (0x00000080u)
+#define CONTROL_USB_CTRL0_CHGVSRC_EN_SHIFT (0x00000007u)
+
+#define CONTROL_USB_CTRL0_CM_PWRDN (0x00000001u)
+#define CONTROL_USB_CTRL0_CM_PWRDN_SHIFT (0x00000000u)
+
+#define CONTROL_USB_CTRL0_DATAPOLARITY_INV (0x00800000u)
+#define CONTROL_USB_CTRL0_DATAPOLARITY_INV_SHIFT (0x00000017u)
+
+#define CONTROL_USB_CTRL0_DMGPIO_PD (0x00040000u)
+#define CONTROL_USB_CTRL0_DMGPIO_PD_SHIFT (0x00000012u)
+
+#define CONTROL_USB_CTRL0_DMPULLUP (0x00000100u)
+#define CONTROL_USB_CTRL0_DMPULLUP_SHIFT (0x00000008u)
+
+#define CONTROL_USB_CTRL0_DPGPIO_PD (0x00020000u)
+#define CONTROL_USB_CTRL0_DPGPIO_PD_SHIFT (0x00000011u)
+
+#define CONTROL_USB_CTRL0_DPPULLUP (0x00000200u)
+#define CONTROL_USB_CTRL0_DPPULLUP_SHIFT (0x00000009u)
+
+#define CONTROL_USB_CTRL0_GPIOMODE (0x00001000u)
+#define CONTROL_USB_CTRL0_GPIOMODE_SHIFT (0x0000000Cu)
+
+#define CONTROL_USB_CTRL0_GPIO_SIG_CROSS (0x00004000u)
+#define CONTROL_USB_CTRL0_GPIO_SIG_CROSS_SHIFT (0x0000000Eu)
+
+#define CONTROL_USB_CTRL0_GPIO_SIG_INV (0x00002000u)
+#define CONTROL_USB_CTRL0_GPIO_SIG_INV_SHIFT (0x0000000Du)
+
+#define CONTROL_USB_CTRL0_OTGSESSENDEN (0x00100000u)
+#define CONTROL_USB_CTRL0_OTGSESSENDEN_SHIFT (0x00000014u)
+
+#define CONTROL_USB_CTRL0_OTGVDET_EN (0x00080000u)
+#define CONTROL_USB_CTRL0_OTGVDET_EN_SHIFT (0x00000013u)
+
+#define CONTROL_USB_CTRL0_OTG_PWRDN (0x00000002u)
+#define CONTROL_USB_CTRL0_OTG_PWRDN_SHIFT (0x00000001u)
+
+#define CONTROL_USB_CTRL0_RSVD2 (0x00008000u)
+#define CONTROL_USB_CTRL0_RSVD2_SHIFT (0x0000000Fu)
+
+#define CONTROL_USB_CTRL0_RSVD3 (0x00010000u)
+#define CONTROL_USB_CTRL0_RSVD3_SHIFT (0x00000010u)
+
+#define CONTROL_USB_CTRL0_SINKONDP (0x00000020u)
+#define CONTROL_USB_CTRL0_SINKONDP_SHIFT (0x00000005u)
+
+#define CONTROL_USB_CTRL0_SPAREIN (0xFF000000u)
+#define CONTROL_USB_CTRL0_SPAREIN_SHIFT (0x00000018u)
+
+#define CONTROL_USB_CTRL0_SRCONDM (0x00000010u)
+#define CONTROL_USB_CTRL0_SRCONDM_SHIFT (0x00000004u)
+
+#define CONTROL_USB_CTRL0_USB_PHY_SMA1 (0x00200000u)
+#define CONTROL_USB_CTRL0_USB_PHY_SMA1_SHIFT (0x00000015u)
+
+#define CONTROL_USB_CTRL0_USB_PHY_SMA2 (0x00400000u)
+#define CONTROL_USB_CTRL0_USB_PHY_SMA2_SHIFT (0x00000016u)
+
+
+/* USB_STS0 */
+#define CONTROL_USB_STS0_CDET_DATADET (0x00000004u)
+#define CONTROL_USB_STS0_CDET_DATADET_SHIFT (0x00000002u)
+
+#define CONTROL_USB_STS0_CDET_DMDET (0x00000010u)
+#define CONTROL_USB_STS0_CDET_DMDET_SHIFT (0x00000004u)
+
+#define CONTROL_USB_STS0_CDET_DPDET (0x00000008u)
+#define CONTROL_USB_STS0_CDET_DPDET_SHIFT (0x00000003u)
+
+#define CONTROL_USB_STS0_CHGDETDONE (0x00000001u)
+#define CONTROL_USB_STS0_CHGDETDONE_SHIFT (0x00000000u)
+
+#define CONTROL_USB_STS0_CHGDETECT (0x00000002u)
+#define CONTROL_USB_STS0_CHGDETECT_SHIFT (0x00000001u)
+
+#define CONTROL_USB_STS0_CHGDETSTS (0x000000E0u)
+#define CONTROL_USB_STS0_CHGDETSTS_SHIFT (0x00000005u)
+
+
+/* USB_CTRL1 */
+#define CONTROL_USB_CTRL1_CDET_EXTCTL (0x00000400u)
+#define CONTROL_USB_CTRL1_CDET_EXTCTL_SHIFT (0x0000000Au)
+
+#define CONTROL_USB_CTRL1_CHGDET_DIS (0x00000004u)
+#define CONTROL_USB_CTRL1_CHGDET_DIS_SHIFT (0x00000002u)
+
+#define CONTROL_USB_CTRL1_CHGDET_RSTRT (0x00000008u)
+#define CONTROL_USB_CTRL1_CHGDET_RSTRT_SHIFT (0x00000003u)
+
+#define CONTROL_USB_CTRL1_CHGISINK_EN (0x00000040u)
+#define CONTROL_USB_CTRL1_CHGISINK_EN_SHIFT (0x00000006u)
+
+#define CONTROL_USB_CTRL1_CHGVSRC_EN (0x00000080u)
+#define CONTROL_USB_CTRL1_CHGVSRC_EN_SHIFT (0x00000007u)
+
+#define CONTROL_USB_CTRL1_CM_PWRDN (0x00000001u)
+#define CONTROL_USB_CTRL1_CM_PWRDN_SHIFT (0x00000000u)
+
+#define CONTROL_USB_CTRL1_DATAPOLARITY_INV (0x00800000u)
+#define CONTROL_USB_CTRL1_DATAPOLARITY_INV_SHIFT (0x00000017u)
+
+#define CONTROL_USB_CTRL1_DMGPIO_PD (0x00040000u)
+#define CONTROL_USB_CTRL1_DMGPIO_PD_SHIFT (0x00000012u)
+
+#define CONTROL_USB_CTRL1_DMPULLUP (0x00000100u)
+#define CONTROL_USB_CTRL1_DMPULLUP_SHIFT (0x00000008u)
+
+#define CONTROL_USB_CTRL1_DPGPIO_PD (0x00020000u)
+#define CONTROL_USB_CTRL1_DPGPIO_PD_SHIFT (0x00000011u)
+
+#define CONTROL_USB_CTRL1_DPPULLUP (0x00000200u)
+#define CONTROL_USB_CTRL1_DPPULLUP_SHIFT (0x00000009u)
+
+#define CONTROL_USB_CTRL1_GPIOMODE (0x00001000u)
+#define CONTROL_USB_CTRL1_GPIOMODE_SHIFT (0x0000000Cu)
+
+#define CONTROL_USB_CTRL1_GPIO_SIG_CROSS (0x00004000u)
+#define CONTROL_USB_CTRL1_GPIO_SIG_CROSS_SHIFT (0x0000000Eu)
+
+#define CONTROL_USB_CTRL1_GPIO_SIG_INV (0x00002000u)
+#define CONTROL_USB_CTRL1_GPIO_SIG_INV_SHIFT (0x0000000Du)
+
+#define CONTROL_USB_CTRL1_OTGSESSENDEN (0x00100000u)
+#define CONTROL_USB_CTRL1_OTGSESSENDEN_SHIFT (0x00000014u)
+
+#define CONTROL_USB_CTRL1_OTGVDET_EN (0x00080000u)
+#define CONTROL_USB_CTRL1_OTGVDET_EN_SHIFT (0x00000013u)
+
+#define CONTROL_USB_CTRL1_OTG_PWRDN (0x00000002u)
+#define CONTROL_USB_CTRL1_OTG_PWRDN_SHIFT (0x00000001u)
+
+#define CONTROL_USB_CTRL1_RSVD2 (0x00008000u)
+#define CONTROL_USB_CTRL1_RSVD2_SHIFT (0x0000000Fu)
+
+#define CONTROL_USB_CTRL1_RSVD3 (0x00010000u)
+#define CONTROL_USB_CTRL1_RSVD3_SHIFT (0x00000010u)
+
+#define CONTROL_USB_CTRL1_SINKONDP (0x00000020u)
+#define CONTROL_USB_CTRL1_SINKONDP_SHIFT (0x00000005u)
+
+#define CONTROL_USB_CTRL1_SPAREIN (0xFF000000u)
+#define CONTROL_USB_CTRL1_SPAREIN_SHIFT (0x00000018u)
+
+#define CONTROL_USB_CTRL1_SRCONDM (0x00000010u)
+#define CONTROL_USB_CTRL1_SRCONDM_SHIFT (0x00000004u)
+
+#define CONTROL_USB_CTRL1_USB_PHY_SMA1 (0x00200000u)
+#define CONTROL_USB_CTRL1_USB_PHY_SMA1_SHIFT (0x00000015u)
+
+#define CONTROL_USB_CTRL1_USB_PHY_SMA2 (0x00400000u)
+#define CONTROL_USB_CTRL1_USB_PHY_SMA2_SHIFT (0x00000016u)
+
+
+/* USB_STS1 */
+#define CONTROL_USB_STS1_CDET_DATADET (0x00000004u)
+#define CONTROL_USB_STS1_CDET_DATADET_SHIFT (0x00000002u)
+
+#define CONTROL_USB_STS1_CDET_DMDET (0x00000010u)
+#define CONTROL_USB_STS1_CDET_DMDET_SHIFT (0x00000004u)
+
+#define CONTROL_USB_STS1_CDET_DPDET (0x00000008u)
+#define CONTROL_USB_STS1_CDET_DPDET_SHIFT (0x00000003u)
+
+#define CONTROL_USB_STS1_CHGDETDONE (0x00000001u)
+#define CONTROL_USB_STS1_CHGDETDONE_SHIFT (0x00000000u)
+
+#define CONTROL_USB_STS1_CHGDETECT (0x00000002u)
+#define CONTROL_USB_STS1_CHGDETECT_SHIFT (0x00000001u)
+
+#define CONTROL_USB_STS1_CHGDETSTS (0x000000E0u)
+#define CONTROL_USB_STS1_CHGDETSTS_SHIFT (0x00000005u)
+
+
+/* MAC_ID0_LO */
+#define CONTROL_MAC_ID0_LO_MACADDR_15_8 (0x000000FFu)
+#define CONTROL_MAC_ID0_LO_MACADDR_15_8_SHIFT (0x00000000u)
+
+#define CONTROL_MAC_ID0_LO_MACADDR_7_0 (0x0000FF00u)
+#define CONTROL_MAC_ID0_LO_MACADDR_7_0_SHIFT (0x00000008u)
+
+
+/* MAC_ID0_HI */
+#define CONTROL_MAC_ID0_HI_MACADDR_23_16 (0xFF000000u)
+#define CONTROL_MAC_ID0_HI_MACADDR_23_16_SHIFT (0x00000018u)
+
+#define CONTROL_MAC_ID0_HI_MACADDR_31_24 (0x00FF0000u)
+#define CONTROL_MAC_ID0_HI_MACADDR_31_24_SHIFT (0x00000010u)
+
+#define CONTROL_MAC_ID0_HI_MACADDR_39_32 (0x0000FF00u)
+#define CONTROL_MAC_ID0_HI_MACADDR_39_32_SHIFT (0x00000008u)
+
+#define CONTROL_MAC_ID0_HI_MACADDR_47_40 (0x000000FFu)
+#define CONTROL_MAC_ID0_HI_MACADDR_47_40_SHIFT (0x00000000u)
+
+
+/* MAC_ID1_LO */
+#define CONTROL_MAC_ID1_LO_MACADDR_15_8 (0x000000FFu)
+#define CONTROL_MAC_ID1_LO_MACADDR_15_8_SHIFT (0x00000000u)
+
+#define CONTROL_MAC_ID1_LO_MACADDR_7_0 (0x0000FF00u)
+#define CONTROL_MAC_ID1_LO_MACADDR_7_0_SHIFT (0x00000008u)
+
+
+/* MAC_ID1_HI */
+#define CONTROL_MAC_ID1_HI_MACADDR_23_16 (0xFF000000u)
+#define CONTROL_MAC_ID1_HI_MACADDR_23_16_SHIFT (0x00000018u)
+
+#define CONTROL_MAC_ID1_HI_MACADDR_31_24 (0x00FF0000u)
+#define CONTROL_MAC_ID1_HI_MACADDR_31_24_SHIFT (0x00000010u)
+
+#define CONTROL_MAC_ID1_HI_MACADDR_39_32 (0x0000FF00u)
+#define CONTROL_MAC_ID1_HI_MACADDR_39_32_SHIFT (0x00000008u)
+
+#define CONTROL_MAC_ID1_HI_MACADDR_47_40 (0x000000FFu)
+#define CONTROL_MAC_ID1_HI_MACADDR_47_40_SHIFT (0x00000000u)
+
+
+/* DCAN_RAMINIT */
+#define CONTROL_DCAN_RAMINIT_DCAN0_RAMINIT_DONE (0x00000100u)
+#define CONTROL_DCAN_RAMINIT_DCAN0_RAMINIT_DONE_SHIFT (0x00000008u)
+
+#define CONTROL_DCAN_RAMINIT_DCAN0_RAMINIT_START (0x00000001u)
+#define CONTROL_DCAN_RAMINIT_DCAN0_RAMINIT_START_SHIFT (0x00000000u)
+
+#define CONTROL_DCAN_RAMINIT_DCAN1_RAMINIT_DONE (0x00000200u)
+#define CONTROL_DCAN_RAMINIT_DCAN1_RAMINIT_DONE_SHIFT (0x00000009u)
+
+#define CONTROL_DCAN_RAMINIT_DCAN1_RAMINIT_START (0x00000002u)
+#define CONTROL_DCAN_RAMINIT_DCAN1_RAMINIT_START_SHIFT (0x00000001u)
+
+#define CONTROL_DCAN_RAMINIT_RSVD2 (0xFFFFFC00u)
+#define CONTROL_DCAN_RAMINIT_RSVD2_SHIFT (0x0000000Au)
+
+
+/* USB_WKUP_CTRL */
+#define CONTROL_USB_WKUP_CTRL_PHY0_WUEN (0x00000001u)
+#define CONTROL_USB_WKUP_CTRL_PHY0_WUEN_SHIFT (0x00000000u)
+
+#define CONTROL_USB_WKUP_CTRL_PHY1_WUEN (0x00000100u)
+#define CONTROL_USB_WKUP_CTRL_PHY1_WUEN_SHIFT (0x00000008u)
+
+#define CONTROL_USB_WKUP_CTRL_RSVD2 (0xFFFFFE00u)
+#define CONTROL_USB_WKUP_CTRL_RSVD2_SHIFT (0x00000009u)
+
+
+/* GMII_SEL */
+#define CONTROL_GMII_SEL_GMII1_SEL (0x00000003u)
+#define CONTROL_GMII_SEL_GMII1_SEL_SHIFT (0x00000000u)
+
+#define CONTROL_GMII_SEL_GMII2_SEL (0x0000000Cu)
+#define CONTROL_GMII_SEL_GMII2_SEL_SHIFT (0x00000002u)
+
+#define CONTROL_GMII_SEL_RGMII1_IDMODE (0x00000010u)
+#define CONTROL_GMII_SEL_RGMII1_IDMODE_SHIFT (0x00000004u)
+
+#define CONTROL_GMII_SEL_RGMII2_IDMOE (0x00000020u)
+#define CONTROL_GMII_SEL_RGMII2_IDMOE_SHIFT (0x00000005u)
+
+#define CONTROL_GMII_SEL_RMII1_IO_CLK_EN (0x00000040u)
+#define CONTROL_GMII_SEL_RMII1_IO_CLK_EN_SHIFT (0x00000006u)
+
+#define CONTROL_GMII_SEL_RMII2_IO_CLK_EN (0x00000080u)
+#define CONTROL_GMII_SEL_RMII2_IO_CLK_EN_SHIFT (0x00000007u)
+
+
+/* PWMSS_CTRL */
+#define CONTROL_PWMSS_CTRL_PWMMS1_TBCLKEN (0x00000002u)
+#define CONTROL_PWMSS_CTRL_PWMMS1_TBCLKEN_SHIFT (0x00000001u)
+
+#define CONTROL_PWMSS_CTRL_PWMSS0_TBCLKEN (0x00000001u)
+#define CONTROL_PWMSS_CTRL_PWMSS0_TBCLKEN_SHIFT (0x00000000u)
+
+#define CONTROL_PWMSS_CTRL_PWMSS2_TBCLKEN (0x00000004u)
+#define CONTROL_PWMSS_CTRL_PWMSS2_TBCLKEN_SHIFT (0x00000002u)
+
+
+/* MREQPRIO_0 */
+#define CONTROL_MREQPRIO_0_CPSW (0x00070000u)
+#define CONTROL_MREQPRIO_0_CPSW_SHIFT (0x00000010u)
+
+#define CONTROL_MREQPRIO_0_PRUSS1_PRU0 (0x00000700u)
+#define CONTROL_MREQPRIO_0_PRUSS1_PRU0_SHIFT (0x00000008u)
+
+#define CONTROL_MREQPRIO_0_PRUSS1_PRU1 (0x00007000u)
+#define CONTROL_MREQPRIO_0_PRUSS1_PRU1_SHIFT (0x0000000Cu)
+
+#define CONTROL_MREQPRIO_0_RSVD2 (0x00000080u)
+#define CONTROL_MREQPRIO_0_RSVD2_SHIFT (0x00000007u)
+
+#define CONTROL_MREQPRIO_0_RSVD3 (0x00000800u)
+#define CONTROL_MREQPRIO_0_RSVD3_SHIFT (0x0000000Bu)
+
+#define CONTROL_MREQPRIO_0_RSVD4 (0x00008000u)
+#define CONTROL_MREQPRIO_0_RSVD4_SHIFT (0x0000000Fu)
+
+#define CONTROL_MREQPRIO_0_RSVD5 (0x00080000u)
+#define CONTROL_MREQPRIO_0_RSVD5_SHIFT (0x00000013u)
+
+#define CONTROL_MREQPRIO_0_RSVD6 (0x00800000u)
+#define CONTROL_MREQPRIO_0_RSVD6_SHIFT (0x00000017u)
+
+#define CONTROL_MREQPRIO_0_RSVD7 (0x08000000u)
+#define CONTROL_MREQPRIO_0_RSVD7_SHIFT (0x0000001Bu)
+
+#define CONTROL_MREQPRIO_0_RSVD8 (0x80000000u)
+#define CONTROL_MREQPRIO_0_RSVD8_SHIFT (0x0000001Fu)
+
+#define CONTROL_MREQPRIO_0_SAB_INIT0 (0x00000007u)
+#define CONTROL_MREQPRIO_0_SAB_INIT0_SHIFT (0x00000000u)
+
+#define CONTROL_MREQPRIO_0_SAB_INIT1 (0x00000070u)
+#define CONTROL_MREQPRIO_0_SAB_INIT1_SHIFT (0x00000004u)
+
+#define CONTROL_MREQPRIO_0_SGX (0x70000000u)
+#define CONTROL_MREQPRIO_0_SGX_SHIFT (0x0000001Cu)
+
+#define CONTROL_MREQPRIO_0_USB0 (0x00700000u)
+#define CONTROL_MREQPRIO_0_USB0_SHIFT (0x00000014u)
+
+#define CONTROL_MREQPRIO_0_USB1 (0x07000000u)
+#define CONTROL_MREQPRIO_0_USB1_SHIFT (0x00000018u)
+
+
+/* MREQPRIO_1 */
+#define CONTROL_MREQPRIO_1_EXP (0x00000007u)
+#define CONTROL_MREQPRIO_1_EXP_SHIFT (0x00000000u)
+
+
+/* HW_EVENT_SEL_GRP1 */
+#define CONTROL_HW_EVENT_SEL_GRP1_EVENT1 (0x000000FFu)
+#define CONTROL_HW_EVENT_SEL_GRP1_EVENT1_SHIFT (0x00000000u)
+
+#define CONTROL_HW_EVENT_SEL_GRP1_EVENT2 (0x0000FF00u)
+#define CONTROL_HW_EVENT_SEL_GRP1_EVENT2_SHIFT (0x00000008u)
+
+#define CONTROL_HW_EVENT_SEL_GRP1_EVENT3 (0x00FF0000u)
+#define CONTROL_HW_EVENT_SEL_GRP1_EVENT3_SHIFT (0x00000010u)
+
+#define CONTROL_HW_EVENT_SEL_GRP1_EVENT4 (0xFF000000u)
+#define CONTROL_HW_EVENT_SEL_GRP1_EVENT4_SHIFT (0x00000018u)
+
+
+/* HW_EVENT_SEL_GRP2 */
+#define CONTROL_HW_EVENT_SEL_GRP2_EVENT5 (0x000000FFu)
+#define CONTROL_HW_EVENT_SEL_GRP2_EVENT5_SHIFT (0x00000000u)
+
+#define CONTROL_HW_EVENT_SEL_GRP2_EVENT6 (0x0000FF00u)
+#define CONTROL_HW_EVENT_SEL_GRP2_EVENT6_SHIFT (0x00000008u)
+
+#define CONTROL_HW_EVENT_SEL_GRP2_EVENT7 (0x00FF0000u)
+#define CONTROL_HW_EVENT_SEL_GRP2_EVENT7_SHIFT (0x00000010u)
+
+#define CONTROL_HW_EVENT_SEL_GRP2_EVENT8 (0xFF000000u)
+#define CONTROL_HW_EVENT_SEL_GRP2_EVENT8_SHIFT (0x00000018u)
+
+
+/* HW_EVENT_SEL_GRP3 */
+#define CONTROL_HW_EVENT_SEL_GRP3_EVENT10 (0x0000FF00u)
+#define CONTROL_HW_EVENT_SEL_GRP3_EVENT10_SHIFT (0x00000008u)
+
+#define CONTROL_HW_EVENT_SEL_GRP3_EVENT11 (0x00FF0000u)
+#define CONTROL_HW_EVENT_SEL_GRP3_EVENT11_SHIFT (0x00000010u)
+
+#define CONTROL_HW_EVENT_SEL_GRP3_EVENT12 (0xFF000000u)
+#define CONTROL_HW_EVENT_SEL_GRP3_EVENT12_SHIFT (0x00000018u)
+
+#define CONTROL_HW_EVENT_SEL_GRP3_EVENT9 (0x000000FFu)
+#define CONTROL_HW_EVENT_SEL_GRP3_EVENT9_SHIFT (0x00000000u)
+
+
+/* HW_EVENT_SEL_GRP4 */
+#define CONTROL_HW_EVENT_SEL_GRP4_EVENT13 (0x000000FFu)
+#define CONTROL_HW_EVENT_SEL_GRP4_EVENT13_SHIFT (0x00000000u)
+
+#define CONTROL_HW_EVENT_SEL_GRP4_EVENT14 (0x0000FF00u)
+#define CONTROL_HW_EVENT_SEL_GRP4_EVENT14_SHIFT (0x00000008u)
+
+#define CONTROL_HW_EVENT_SEL_GRP4_EVENT15 (0x00FF0000u)
+#define CONTROL_HW_EVENT_SEL_GRP4_EVENT15_SHIFT (0x00000010u)
+
+#define CONTROL_HW_EVENT_SEL_GRP4_EVENT16 (0xFF000000u)
+#define CONTROL_HW_EVENT_SEL_GRP4_EVENT16_SHIFT (0x00000018u)
+
+
+/* SMRT_CTRL */
+#define CONTROL_SMRT_CTRL_SR0_SLEEP (0x00000001u)
+#define CONTROL_SMRT_CTRL_SR0_SLEEP_SHIFT (0x00000000u)
+
+#define CONTROL_SMRT_CTRL_SR1_SLEEP (0x00000002u)
+#define CONTROL_SMRT_CTRL_SR1_SLEEP_SHIFT (0x00000001u)
+
+
+/* SABTOOTH_HW_DEBUG_SEL */
+#define CONTROL_SABTOOTH_HW_DEBUG_SEL_HW_DBG_GATE_EN (0x00000200u)
+#define CONTROL_SABTOOTH_HW_DEBUG_SEL_HW_DBG_GATE_EN_SHIFT (0x00000009u)
+
+#define CONTROL_SABTOOTH_HW_DEBUG_SEL_HW_DBG_SEL (0x0000000Fu)
+#define CONTROL_SABTOOTH_HW_DEBUG_SEL_HW_DBG_SEL_SHIFT (0x00000000u)
+
+#define CONTROL_SABTOOTH_HW_DEBUG_SEL_RSVD3 (0xFFFFFC00u)
+#define CONTROL_SABTOOTH_HW_DEBUG_SEL_RSVD3_SHIFT (0x0000000Au)
+
+
+/* SABTOOTH_HW_DBG_INFO */
+#define CONTROL_SABTOOTH_HW_DBG_INFO_HW_DBG_INFO (0xFFFFFFFFu)
+#define CONTROL_SABTOOTH_HW_DBG_INFO_HW_DBG_INFO_SHIFT (0x00000000u)
+
+
+/* MRGN_MODE0 */
+#define CONTROL_MRGN_MODE0_MMODE0 (0x00000003u)
+#define CONTROL_MRGN_MODE0_MMODE0_SHIFT (0x00000000u)
+
+#define CONTROL_MRGN_MODE0_MMODE1 (0x0000000Cu)
+#define CONTROL_MRGN_MODE0_MMODE1_SHIFT (0x00000002u)
+
+#define CONTROL_MRGN_MODE0_MMODE10 (0x00300000u)
+#define CONTROL_MRGN_MODE0_MMODE10_SHIFT (0x00000014u)
+
+#define CONTROL_MRGN_MODE0_MMODE11 (0x00C00000u)
+#define CONTROL_MRGN_MODE0_MMODE11_SHIFT (0x00000016u)
+
+#define CONTROL_MRGN_MODE0_MMODE12 (0x03000000u)
+#define CONTROL_MRGN_MODE0_MMODE12_SHIFT (0x00000018u)
+
+#define CONTROL_MRGN_MODE0_MMODE13 (0x0C000000u)
+#define CONTROL_MRGN_MODE0_MMODE13_SHIFT (0x0000001Au)
+
+#define CONTROL_MRGN_MODE0_MMODE14 (0x30000000u)
+#define CONTROL_MRGN_MODE0_MMODE14_SHIFT (0x0000001Cu)
+
+#define CONTROL_MRGN_MODE0_MMODE15 (0xC0000000u)
+#define CONTROL_MRGN_MODE0_MMODE15_SHIFT (0x0000001Eu)
+
+#define CONTROL_MRGN_MODE0_MMODE2 (0x00000030u)
+#define CONTROL_MRGN_MODE0_MMODE2_SHIFT (0x00000004u)
+
+#define CONTROL_MRGN_MODE0_MMODE3 (0x000000C0u)
+#define CONTROL_MRGN_MODE0_MMODE3_SHIFT (0x00000006u)
+
+#define CONTROL_MRGN_MODE0_MMODE4 (0x00000300u)
+#define CONTROL_MRGN_MODE0_MMODE4_SHIFT (0x00000008u)
+
+#define CONTROL_MRGN_MODE0_MMODE5 (0x00000C00u)
+#define CONTROL_MRGN_MODE0_MMODE5_SHIFT (0x0000000Au)
+
+#define CONTROL_MRGN_MODE0_MMODE6 (0x00003000u)
+#define CONTROL_MRGN_MODE0_MMODE6_SHIFT (0x0000000Cu)
+
+#define CONTROL_MRGN_MODE0_MMODE7 (0x0000C000u)
+#define CONTROL_MRGN_MODE0_MMODE7_SHIFT (0x0000000Eu)
+
+#define CONTROL_MRGN_MODE0_MMODE8 (0x00030000u)
+#define CONTROL_MRGN_MODE0_MMODE8_SHIFT (0x00000010u)
+
+#define CONTROL_MRGN_MODE0_MMODE9 (0x000C0000u)
+#define CONTROL_MRGN_MODE0_MMODE9_SHIFT (0x00000012u)
+
+
+/* MRGN_MODE1 */
+#define CONTROL_MRGN_MODE1_MMODE16 (0x00000003u)
+#define CONTROL_MRGN_MODE1_MMODE16_SHIFT (0x00000000u)
+
+#define CONTROL_MRGN_MODE1_MMODE17 (0x0000000Cu)
+#define CONTROL_MRGN_MODE1_MMODE17_SHIFT (0x00000002u)
+
+#define CONTROL_MRGN_MODE1_MMODE18 (0x00000030u)
+#define CONTROL_MRGN_MODE1_MMODE18_SHIFT (0x00000004u)
+
+#define CONTROL_MRGN_MODE1_MMODE19 (0x000000C0u)
+#define CONTROL_MRGN_MODE1_MMODE19_SHIFT (0x00000006u)
+
+
+/* VDD_MPU_OPP_050 */
+#define CONTROL_VDD_MPU_OPP_050_NTARGET (0x00FFFFFFu)
+#define CONTROL_VDD_MPU_OPP_050_NTARGET_SHIFT (0x00000000u)
+
+
+/* VDD_MPU_OPP_100 */
+#define CONTROL_VDD_MPU_OPP_100_NTARGET (0x00FFFFFFu)
+#define CONTROL_VDD_MPU_OPP_100_NTARGET_SHIFT (0x00000000u)
+
+
+/* VDD_MPU_OPP_119 */
+#define CONTROL_VDD_MPU_OPP_119_NTARGET (0x00FFFFFFu)
+#define CONTROL_VDD_MPU_OPP_119_NTARGET_SHIFT (0x00000000u)
+
+
+/* VDD_MPU_OPP_TURBO */
+#define CONTROL_VDD_MPU_OPP_TURBO_NTARGET (0x00FFFFFFu)
+#define CONTROL_VDD_MPU_OPP_TURBO_NTARGET_SHIFT (0x00000000u)
+
+
+/* VDD_CORE_OPP_050 */
+#define CONTROL_VDD_CORE_OPP_050_NTARGET (0x00FFFFFFu)
+#define CONTROL_VDD_CORE_OPP_050_NTARGET_SHIFT (0x00000000u)
+
+
+/* VDD_CORE_OPP_100 */
+#define CONTROL_VDD_CORE_OPP_100_NTARGET (0x00FFFFFFu)
+#define CONTROL_VDD_CORE_OPP_100_NTARGET_SHIFT (0x00000000u)
+
+
+/* BB_SCALE */
+#define CONTROL_BB_SCALE_BBIAS (0x00000003u)
+#define CONTROL_BB_SCALE_BBIAS_SHIFT (0x00000000u)
+
+#define CONTROL_BB_SCALE_RSVD2 (0xFFFFF000u)
+#define CONTROL_BB_SCALE_RSVD2_SHIFT (0x0000000Cu)
+
+#define CONTROL_BB_SCALE_SCALE (0x00000F00u)
+#define CONTROL_BB_SCALE_SCALE_SHIFT (0x00000008u)
+
+
+/* USB_VID_PID */
+#define CONTROL_USB_VID_PID_USB_PID (0x0000FFFFu)
+#define CONTROL_USB_VID_PID_USB_PID_SHIFT (0x00000000u)
+
+#define CONTROL_USB_VID_PID_USB_VID (0xFFFF0000u)
+#define CONTROL_USB_VID_PID_USB_VID_SHIFT (0x00000010u)
+
+
+/* EFUSE_SMA */
+#define CONTROL_EFUSE_SMA_EFUSE_SMA (0xFFFFFFFFu)
+#define CONTROL_EFUSE_SMA_EFUSE_SMA_SHIFT (0x00000000u)
+
+
+/* CONF_GPMC_ADx */
+#define CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_MMODE (0x00000007u)
+#define CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUDEN (0x00000008u)
+#define CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_RSVD (0x000FFF80u)
+#define CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_GPMC_AD0 */
+#define CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_MMODE (0x00000007u)
+#define CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_PUDEN (0x00000008u)
+#define CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RSVD (0x000FFF80u)
+#define CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_GPMC_AD0_CONF_GPMC_AD0_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_GPMC_AD1 */
+#define CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_MMODE (0x00000007u)
+#define CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_PUDEN (0x00000008u)
+#define CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_RSVD (0x000FFF80u)
+#define CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_GPMC_AD2 */
+#define CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_MMODE (0x00000007u)
+#define CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_PUDEN (0x00000008u)
+#define CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_RSVD (0x000FFF80u)
+#define CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_GPMC_AD3 */
+#define CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_MMODE (0x00000007u)
+#define CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_PUDEN (0x00000008u)
+#define CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_RSVD (0x000FFF80u)
+#define CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_GPMC_AD4 */
+#define CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_MMODE (0x00000007u)
+#define CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_PUDEN (0x00000008u)
+#define CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_RSVD (0x000FFF80u)
+#define CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_GPMC_AD5 */
+#define CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_MMODE (0x00000007u)
+#define CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_PUDEN (0x00000008u)
+#define CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_RSVD (0x000FFF80u)
+#define CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_GPMC_AD6 */
+#define CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_MMODE (0x00000007u)
+#define CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_PUDEN (0x00000008u)
+#define CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_RSVD (0x000FFF80u)
+#define CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_GPMC_AD7 */
+#define CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_MMODE (0x00000007u)
+#define CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_PUDEN (0x00000008u)
+#define CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_RSVD (0x000FFF80u)
+#define CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_GPMC_AD8 */
+#define CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_MMODE (0x00000007u)
+#define CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_PUDEN (0x00000008u)
+#define CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_RSVD (0x000FFF80u)
+#define CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_GPMC_AD9 */
+#define CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_MMODE (0x00000007u)
+#define CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_PUDEN (0x00000008u)
+#define CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_RSVD (0x000FFF80u)
+#define CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_GPMC_AD10 */
+#define CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_MMODE (0x00000007u)
+#define CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_PUDEN (0x00000008u)
+#define CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_RSVD (0x000FFF80u)
+#define CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_GPMC_AD11 */
+#define CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_MMODE (0x00000007u)
+#define CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_PUDEN (0x00000008u)
+#define CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_RSVD (0x000FFF80u)
+#define CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_GPMC_AD12 */
+#define CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_MMODE (0x00000007u)
+#define CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_PUDEN (0x00000008u)
+#define CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_RSVD (0x000FFF80u)
+#define CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_GPMC_AD13 */
+#define CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_MMODE (0x00000007u)
+#define CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_PUDEN (0x00000008u)
+#define CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_RSVD (0x000FFF80u)
+#define CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_GPMC_AD14 */
+#define CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_MMODE (0x00000007u)
+#define CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_PUDEN (0x00000008u)
+#define CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_RSVD (0x000FFF80u)
+#define CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_GPMC_AD15 */
+#define CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_MMODE (0x00000007u)
+#define CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_PUDEN (0x00000008u)
+#define CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_RSVD (0x000FFF80u)
+#define CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_GPMC_A0 */
+#define CONTROL_CONF_GPMC_A0_CONF_GPMC_A0_MMODE (0x00000007u)
+#define CONTROL_CONF_GPMC_A0_CONF_GPMC_A0_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_GPMC_A0_CONF_GPMC_A0_PUDEN (0x00000008u)
+#define CONTROL_CONF_GPMC_A0_CONF_GPMC_A0_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_GPMC_A0_CONF_GPMC_A0_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_GPMC_A0_CONF_GPMC_A0_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_GPMC_A0_CONF_GPMC_A0_RSVD (0x000FFF80u)
+#define CONTROL_CONF_GPMC_A0_CONF_GPMC_A0_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_GPMC_A0_CONF_GPMC_A0_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_GPMC_A0_CONF_GPMC_A0_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_GPMC_A0_CONF_GPMC_A0_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_GPMC_A0_CONF_GPMC_A0_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_GPMC_A1 */
+#define CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_MMODE (0x00000007u)
+#define CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_PUDEN (0x00000008u)
+#define CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_RSVD (0x000FFF80u)
+#define CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_GPMC_A2 */
+#define CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_MMODE (0x00000007u)
+#define CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_PUDEN (0x00000008u)
+#define CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_RSVD (0x000FFF80u)
+#define CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_GPMC_A3 */
+#define CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_MMODE (0x00000007u)
+#define CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_PUDEN (0x00000008u)
+#define CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_RSVD (0x000FFF80u)
+#define CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_GPMC_A4 */
+#define CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_MMODE (0x00000007u)
+#define CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_PUDEN (0x00000008u)
+#define CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_RSVD (0x000FFF80u)
+#define CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_GPMC_A5 */
+#define CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_MMODE (0x00000007u)
+#define CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_PUDEN (0x00000008u)
+#define CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_RSVD (0x000FFF80u)
+#define CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_GPMC_A6 */
+#define CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_MMODE (0x00000007u)
+#define CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_PUDEN (0x00000008u)
+#define CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_RSVD (0x000FFF80u)
+#define CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_GPMC_A7 */
+#define CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_MMODE (0x00000007u)
+#define CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_PUDEN (0x00000008u)
+#define CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_RSVD (0x000FFF80u)
+#define CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_GPMC_A8 */
+#define CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_MMODE (0x00000007u)
+#define CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_PUDEN (0x00000008u)
+#define CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_RSVD (0x000FFF80u)
+#define CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_GPMC_A9 */
+#define CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_MMODE (0x00000007u)
+#define CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_PUDEN (0x00000008u)
+#define CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_RSVD (0x000FFF80u)
+#define CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_GPMC_A10 */
+#define CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_MMODE (0x00000007u)
+#define CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_PUDEN (0x00000008u)
+#define CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_RSVD (0x000FFF80u)
+#define CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_GPMC_A11 */
+#define CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_MMODE (0x00000007u)
+#define CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_PUDEN (0x00000008u)
+#define CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_RSVD (0x000FFF80u)
+#define CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_GPMC_WAIT0 */
+#define CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_MMODE (0x00000007u)
+#define CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_PUDEN (0x00000008u)
+#define CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_RSVD (0x000FFF80u)
+#define CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_GPMC_WAIT0_CONF_GPMC_WAIT0_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_GPMC_WPN */
+#define CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_MMODE (0x00000007u)
+#define CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_PUDEN (0x00000008u)
+#define CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_RSVD (0x000FFF80u)
+#define CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_GPMC_WPN_CONF_GPMC_WPN_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_GPMC_BE1N */
+#define CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_MMODE (0x00000007u)
+#define CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_PUDEN (0x00000008u)
+#define CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_RSVD (0x000FFF80u)
+#define CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_GPMC_BE1N_CONF_GPMC_BE1N_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_GPMC_CSN0 */
+#define CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_MMODE (0x00000007u)
+#define CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_PUDEN (0x00000008u)
+#define CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_RSVD (0x000FFF80u)
+#define CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_GPMC_CSN1 */
+#define CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_MMODE (0x00000007u)
+#define CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_PUDEN (0x00000008u)
+#define CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_RSVD (0x000FFF80u)
+#define CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_GPMC_CSN1_CONF_GPMC_CSN1_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_GPMC_CSN2 */
+#define CONTROL_CONF_GPMC_CSN2_CONF_GPMC_CSN2_MMODE (0x00000007u)
+#define CONTROL_CONF_GPMC_CSN2_CONF_GPMC_CSN2_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_GPMC_CSN2_CONF_GPMC_CSN2_PUDEN (0x00000008u)
+#define CONTROL_CONF_GPMC_CSN2_CONF_GPMC_CSN2_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_GPMC_CSN2_CONF_GPMC_CSN2_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_GPMC_CSN2_CONF_GPMC_CSN2_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_GPMC_CSN2_CONF_GPMC_CSN2_RSVD (0x000FFF80u)
+#define CONTROL_CONF_GPMC_CSN2_CONF_GPMC_CSN2_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_GPMC_CSN2_CONF_GPMC_CSN2_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_GPMC_CSN2_CONF_GPMC_CSN2_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_GPMC_CSN2_CONF_GPMC_CSN2_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_GPMC_CSN2_CONF_GPMC_CSN2_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_GPMC_CSN3 */
+#define CONTROL_CONF_GPMC_CSN3_CONF_GPMC_CSN3_MMODE (0x00000007u)
+#define CONTROL_CONF_GPMC_CSN3_CONF_GPMC_CSN3_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_GPMC_CSN3_CONF_GPMC_CSN3_PUDEN (0x00000008u)
+#define CONTROL_CONF_GPMC_CSN3_CONF_GPMC_CSN3_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_GPMC_CSN3_CONF_GPMC_CSN3_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_GPMC_CSN3_CONF_GPMC_CSN3_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_GPMC_CSN3_CONF_GPMC_CSN3_RSVD (0x000FFF80u)
+#define CONTROL_CONF_GPMC_CSN3_CONF_GPMC_CSN3_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_GPMC_CSN3_CONF_GPMC_CSN3_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_GPMC_CSN3_CONF_GPMC_CSN3_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_GPMC_CSN3_CONF_GPMC_CSN3_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_GPMC_CSN3_CONF_GPMC_CSN3_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_GPMC_CLK */
+#define CONTROL_CONF_GPMC_CLK_CONF_GPMC_CLK_MMODE (0x00000007u)
+#define CONTROL_CONF_GPMC_CLK_CONF_GPMC_CLK_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_GPMC_CLK_CONF_GPMC_CLK_PUDEN (0x00000008u)
+#define CONTROL_CONF_GPMC_CLK_CONF_GPMC_CLK_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_GPMC_CLK_CONF_GPMC_CLK_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_GPMC_CLK_CONF_GPMC_CLK_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_GPMC_CLK_CONF_GPMC_CLK_RSVD (0x000FFF80u)
+#define CONTROL_CONF_GPMC_CLK_CONF_GPMC_CLK_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_GPMC_CLK_CONF_GPMC_CLK_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_GPMC_CLK_CONF_GPMC_CLK_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_GPMC_CLK_CONF_GPMC_CLK_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_GPMC_CLK_CONF_GPMC_CLK_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_GPMC_ADVN_ALE */
+#define CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_MMODE (0x00000007u)
+#define CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_PUDEN (0x00000008u)
+#define CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_RSVD (0x000FFF80u)
+#define CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_GPMC_OEN_REN */
+#define CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_MMODE (0x00000007u)
+#define CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_PUDEN (0x00000008u)
+#define CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_RSVD (0x000FFF80u)
+#define CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_GPMC_WEN */
+#define CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_MMODE (0x00000007u)
+#define CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_PUDEN (0x00000008u)
+#define CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_RSVD (0x000FFF80u)
+#define CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_GPMC_BE0N_CLE */
+#define CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_MMODE (0x00000007u)
+#define CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_PUDEN (0x00000008u)
+#define CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_RSVD (0x000FFF80u)
+#define CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_GPMC_BE0N_CLE_CONF_GPMC_BE0N_CLE_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_LCD_DATA0 */
+#define CONTROL_CONF_LCD_DATA0_CONF_LCD_DATA0_MMODE (0x00000007u)
+#define CONTROL_CONF_LCD_DATA0_CONF_LCD_DATA0_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_LCD_DATA0_CONF_LCD_DATA0_PUDEN (0x00000008u)
+#define CONTROL_CONF_LCD_DATA0_CONF_LCD_DATA0_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_LCD_DATA0_CONF_LCD_DATA0_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_LCD_DATA0_CONF_LCD_DATA0_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_LCD_DATA0_CONF_LCD_DATA0_RSVD (0x000FFF80u)
+#define CONTROL_CONF_LCD_DATA0_CONF_LCD_DATA0_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_LCD_DATA0_CONF_LCD_DATA0_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_LCD_DATA0_CONF_LCD_DATA0_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_LCD_DATA0_CONF_LCD_DATA0_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_LCD_DATA0_CONF_LCD_DATA0_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_LCD_DATA1 */
+#define CONTROL_CONF_LCD_DATA1_CONF_LCD_DATA1_MMODE (0x00000007u)
+#define CONTROL_CONF_LCD_DATA1_CONF_LCD_DATA1_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_LCD_DATA1_CONF_LCD_DATA1_PUDEN (0x00000008u)
+#define CONTROL_CONF_LCD_DATA1_CONF_LCD_DATA1_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_LCD_DATA1_CONF_LCD_DATA1_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_LCD_DATA1_CONF_LCD_DATA1_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_LCD_DATA1_CONF_LCD_DATA1_RSVD (0x000FFF80u)
+#define CONTROL_CONF_LCD_DATA1_CONF_LCD_DATA1_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_LCD_DATA1_CONF_LCD_DATA1_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_LCD_DATA1_CONF_LCD_DATA1_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_LCD_DATA1_CONF_LCD_DATA1_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_LCD_DATA1_CONF_LCD_DATA1_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_LCD_DATA2 */
+#define CONTROL_CONF_LCD_DATA2_CONF_LCD_DATA2_MMODE (0x00000007u)
+#define CONTROL_CONF_LCD_DATA2_CONF_LCD_DATA2_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_LCD_DATA2_CONF_LCD_DATA2_PUDEN (0x00000008u)
+#define CONTROL_CONF_LCD_DATA2_CONF_LCD_DATA2_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_LCD_DATA2_CONF_LCD_DATA2_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_LCD_DATA2_CONF_LCD_DATA2_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_LCD_DATA2_CONF_LCD_DATA2_RSVD (0x000FFF80u)
+#define CONTROL_CONF_LCD_DATA2_CONF_LCD_DATA2_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_LCD_DATA2_CONF_LCD_DATA2_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_LCD_DATA2_CONF_LCD_DATA2_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_LCD_DATA2_CONF_LCD_DATA2_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_LCD_DATA2_CONF_LCD_DATA2_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_LCD_DATA3 */
+#define CONTROL_CONF_LCD_DATA3_CONF_LCD_DATA3_MMODE (0x00000007u)
+#define CONTROL_CONF_LCD_DATA3_CONF_LCD_DATA3_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_LCD_DATA3_CONF_LCD_DATA3_PUDEN (0x00000008u)
+#define CONTROL_CONF_LCD_DATA3_CONF_LCD_DATA3_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_LCD_DATA3_CONF_LCD_DATA3_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_LCD_DATA3_CONF_LCD_DATA3_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_LCD_DATA3_CONF_LCD_DATA3_RSVD (0x000FFF80u)
+#define CONTROL_CONF_LCD_DATA3_CONF_LCD_DATA3_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_LCD_DATA3_CONF_LCD_DATA3_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_LCD_DATA3_CONF_LCD_DATA3_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_LCD_DATA3_CONF_LCD_DATA3_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_LCD_DATA3_CONF_LCD_DATA3_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_LCD_DATA4 */
+#define CONTROL_CONF_LCD_DATA4_CONF_LCD_DATA4_MMODE (0x00000007u)
+#define CONTROL_CONF_LCD_DATA4_CONF_LCD_DATA4_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_LCD_DATA4_CONF_LCD_DATA4_PUDEN (0x00000008u)
+#define CONTROL_CONF_LCD_DATA4_CONF_LCD_DATA4_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_LCD_DATA4_CONF_LCD_DATA4_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_LCD_DATA4_CONF_LCD_DATA4_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_LCD_DATA4_CONF_LCD_DATA4_RSVD (0x000FFF80u)
+#define CONTROL_CONF_LCD_DATA4_CONF_LCD_DATA4_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_LCD_DATA4_CONF_LCD_DATA4_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_LCD_DATA4_CONF_LCD_DATA4_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_LCD_DATA4_CONF_LCD_DATA4_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_LCD_DATA4_CONF_LCD_DATA4_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_LCD_DATA5 */
+#define CONTROL_CONF_LCD_DATA5_CONF_LCD_DATA5_MMODE (0x00000007u)
+#define CONTROL_CONF_LCD_DATA5_CONF_LCD_DATA5_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_LCD_DATA5_CONF_LCD_DATA5_PUDEN (0x00000008u)
+#define CONTROL_CONF_LCD_DATA5_CONF_LCD_DATA5_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_LCD_DATA5_CONF_LCD_DATA5_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_LCD_DATA5_CONF_LCD_DATA5_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_LCD_DATA5_CONF_LCD_DATA5_RSVD (0x000FFF80u)
+#define CONTROL_CONF_LCD_DATA5_CONF_LCD_DATA5_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_LCD_DATA5_CONF_LCD_DATA5_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_LCD_DATA5_CONF_LCD_DATA5_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_LCD_DATA5_CONF_LCD_DATA5_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_LCD_DATA5_CONF_LCD_DATA5_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_LCD_DATA6 */
+#define CONTROL_CONF_LCD_DATA6_CONF_LCD_DATA6_MMODE (0x00000007u)
+#define CONTROL_CONF_LCD_DATA6_CONF_LCD_DATA6_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_LCD_DATA6_CONF_LCD_DATA6_PUDEN (0x00000008u)
+#define CONTROL_CONF_LCD_DATA6_CONF_LCD_DATA6_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_LCD_DATA6_CONF_LCD_DATA6_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_LCD_DATA6_CONF_LCD_DATA6_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_LCD_DATA6_CONF_LCD_DATA6_RSVD (0x000FFF80u)
+#define CONTROL_CONF_LCD_DATA6_CONF_LCD_DATA6_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_LCD_DATA6_CONF_LCD_DATA6_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_LCD_DATA6_CONF_LCD_DATA6_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_LCD_DATA6_CONF_LCD_DATA6_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_LCD_DATA6_CONF_LCD_DATA6_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_LCD_DATA7 */
+#define CONTROL_CONF_LCD_DATA7_CONF_LCD_DATA7_MMODE (0x00000007u)
+#define CONTROL_CONF_LCD_DATA7_CONF_LCD_DATA7_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_LCD_DATA7_CONF_LCD_DATA7_PUDEN (0x00000008u)
+#define CONTROL_CONF_LCD_DATA7_CONF_LCD_DATA7_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_LCD_DATA7_CONF_LCD_DATA7_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_LCD_DATA7_CONF_LCD_DATA7_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_LCD_DATA7_CONF_LCD_DATA7_RSVD (0x000FFF80u)
+#define CONTROL_CONF_LCD_DATA7_CONF_LCD_DATA7_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_LCD_DATA7_CONF_LCD_DATA7_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_LCD_DATA7_CONF_LCD_DATA7_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_LCD_DATA7_CONF_LCD_DATA7_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_LCD_DATA7_CONF_LCD_DATA7_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_LCD_DATA8 */
+#define CONTROL_CONF_LCD_DATA8_CONF_LCD_DATA8_MMODE (0x00000007u)
+#define CONTROL_CONF_LCD_DATA8_CONF_LCD_DATA8_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_LCD_DATA8_CONF_LCD_DATA8_PUDEN (0x00000008u)
+#define CONTROL_CONF_LCD_DATA8_CONF_LCD_DATA8_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_LCD_DATA8_CONF_LCD_DATA8_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_LCD_DATA8_CONF_LCD_DATA8_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_LCD_DATA8_CONF_LCD_DATA8_RSVD (0x000FFF80u)
+#define CONTROL_CONF_LCD_DATA8_CONF_LCD_DATA8_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_LCD_DATA8_CONF_LCD_DATA8_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_LCD_DATA8_CONF_LCD_DATA8_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_LCD_DATA8_CONF_LCD_DATA8_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_LCD_DATA8_CONF_LCD_DATA8_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_LCD_DATA9 */
+#define CONTROL_CONF_LCD_DATA9_CONF_LCD_DATA9_MMODE (0x00000007u)
+#define CONTROL_CONF_LCD_DATA9_CONF_LCD_DATA9_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_LCD_DATA9_CONF_LCD_DATA9_PUDEN (0x00000008u)
+#define CONTROL_CONF_LCD_DATA9_CONF_LCD_DATA9_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_LCD_DATA9_CONF_LCD_DATA9_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_LCD_DATA9_CONF_LCD_DATA9_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_LCD_DATA9_CONF_LCD_DATA9_RSVD (0x000FFF80u)
+#define CONTROL_CONF_LCD_DATA9_CONF_LCD_DATA9_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_LCD_DATA9_CONF_LCD_DATA9_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_LCD_DATA9_CONF_LCD_DATA9_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_LCD_DATA9_CONF_LCD_DATA9_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_LCD_DATA9_CONF_LCD_DATA9_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_LCD_DATA10 */
+#define CONTROL_CONF_LCD_DATA10_CONF_LCD_DATA10_MMODE (0x00000007u)
+#define CONTROL_CONF_LCD_DATA10_CONF_LCD_DATA10_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_LCD_DATA10_CONF_LCD_DATA10_PUDEN (0x00000008u)
+#define CONTROL_CONF_LCD_DATA10_CONF_LCD_DATA10_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_LCD_DATA10_CONF_LCD_DATA10_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_LCD_DATA10_CONF_LCD_DATA10_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_LCD_DATA10_CONF_LCD_DATA10_RSVD (0x000FFF80u)
+#define CONTROL_CONF_LCD_DATA10_CONF_LCD_DATA10_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_LCD_DATA10_CONF_LCD_DATA10_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_LCD_DATA10_CONF_LCD_DATA10_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_LCD_DATA10_CONF_LCD_DATA10_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_LCD_DATA10_CONF_LCD_DATA10_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_LCD_DATA11 */
+#define CONTROL_CONF_LCD_DATA11_CONF_LCD_DATA11_MMODE (0x00000007u)
+#define CONTROL_CONF_LCD_DATA11_CONF_LCD_DATA11_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_LCD_DATA11_CONF_LCD_DATA11_PUDEN (0x00000008u)
+#define CONTROL_CONF_LCD_DATA11_CONF_LCD_DATA11_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_LCD_DATA11_CONF_LCD_DATA11_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_LCD_DATA11_CONF_LCD_DATA11_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_LCD_DATA11_CONF_LCD_DATA11_RSVD (0x000FFF80u)
+#define CONTROL_CONF_LCD_DATA11_CONF_LCD_DATA11_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_LCD_DATA11_CONF_LCD_DATA11_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_LCD_DATA11_CONF_LCD_DATA11_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_LCD_DATA11_CONF_LCD_DATA11_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_LCD_DATA11_CONF_LCD_DATA11_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_LCD_DATA12 */
+#define CONTROL_CONF_LCD_DATA12_CONF_LCD_DATA12_MMODE (0x00000007u)
+#define CONTROL_CONF_LCD_DATA12_CONF_LCD_DATA12_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_LCD_DATA12_CONF_LCD_DATA12_PUDEN (0x00000008u)
+#define CONTROL_CONF_LCD_DATA12_CONF_LCD_DATA12_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_LCD_DATA12_CONF_LCD_DATA12_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_LCD_DATA12_CONF_LCD_DATA12_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_LCD_DATA12_CONF_LCD_DATA12_RSVD (0x000FFF80u)
+#define CONTROL_CONF_LCD_DATA12_CONF_LCD_DATA12_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_LCD_DATA12_CONF_LCD_DATA12_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_LCD_DATA12_CONF_LCD_DATA12_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_LCD_DATA12_CONF_LCD_DATA12_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_LCD_DATA12_CONF_LCD_DATA12_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_LCD_DATA13 */
+#define CONTROL_CONF_LCD_DATA13_CONF_LCD_DATA13_MMODE (0x00000007u)
+#define CONTROL_CONF_LCD_DATA13_CONF_LCD_DATA13_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_LCD_DATA13_CONF_LCD_DATA13_PUDEN (0x00000008u)
+#define CONTROL_CONF_LCD_DATA13_CONF_LCD_DATA13_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_LCD_DATA13_CONF_LCD_DATA13_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_LCD_DATA13_CONF_LCD_DATA13_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_LCD_DATA13_CONF_LCD_DATA13_RSVD (0x000FFF80u)
+#define CONTROL_CONF_LCD_DATA13_CONF_LCD_DATA13_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_LCD_DATA13_CONF_LCD_DATA13_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_LCD_DATA13_CONF_LCD_DATA13_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_LCD_DATA13_CONF_LCD_DATA13_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_LCD_DATA13_CONF_LCD_DATA13_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_LCD_DATA14 */
+#define CONTROL_CONF_LCD_DATA14_CONF_LCD_DATA14_MMODE (0x00000007u)
+#define CONTROL_CONF_LCD_DATA14_CONF_LCD_DATA14_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_LCD_DATA14_CONF_LCD_DATA14_PUDEN (0x00000008u)
+#define CONTROL_CONF_LCD_DATA14_CONF_LCD_DATA14_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_LCD_DATA14_CONF_LCD_DATA14_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_LCD_DATA14_CONF_LCD_DATA14_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_LCD_DATA14_CONF_LCD_DATA14_RSVD (0x000FFF80u)
+#define CONTROL_CONF_LCD_DATA14_CONF_LCD_DATA14_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_LCD_DATA14_CONF_LCD_DATA14_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_LCD_DATA14_CONF_LCD_DATA14_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_LCD_DATA14_CONF_LCD_DATA14_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_LCD_DATA14_CONF_LCD_DATA14_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_LCD_DATA15 */
+#define CONTROL_CONF_LCD_DATA15_CONF_LCD_DATA15_MMODE (0x00000007u)
+#define CONTROL_CONF_LCD_DATA15_CONF_LCD_DATA15_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_LCD_DATA15_CONF_LCD_DATA15_PUDEN (0x00000008u)
+#define CONTROL_CONF_LCD_DATA15_CONF_LCD_DATA15_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_LCD_DATA15_CONF_LCD_DATA15_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_LCD_DATA15_CONF_LCD_DATA15_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_LCD_DATA15_CONF_LCD_DATA15_RSVD (0x000FFF80u)
+#define CONTROL_CONF_LCD_DATA15_CONF_LCD_DATA15_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_LCD_DATA15_CONF_LCD_DATA15_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_LCD_DATA15_CONF_LCD_DATA15_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_LCD_DATA15_CONF_LCD_DATA15_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_LCD_DATA15_CONF_LCD_DATA15_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_LCD_DATA16 */
+#define CONTROL_CONF_LCD_DATA16_CONF_LCD_DATA16_MMODE (0x00000007u)
+#define CONTROL_CONF_LCD_DATA16_CONF_LCD_DATA16_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_LCD_DATA16_CONF_LCD_DATA16_PUDEN (0x00000008u)
+#define CONTROL_CONF_LCD_DATA16_CONF_LCD_DATA16_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_LCD_DATA16_CONF_LCD_DATA16_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_LCD_DATA16_CONF_LCD_DATA16_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_LCD_DATA16_CONF_LCD_DATA16_RSVD (0x000FFF80u)
+#define CONTROL_CONF_LCD_DATA16_CONF_LCD_DATA16_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_LCD_DATA16_CONF_LCD_DATA16_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_LCD_DATA16_CONF_LCD_DATA16_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_LCD_DATA16_CONF_LCD_DATA16_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_LCD_DATA16_CONF_LCD_DATA16_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_LCD_DATA17 */
+#define CONTROL_CONF_LCD_DATA17_CONF_LCD_DATA17_MMODE (0x00000007u)
+#define CONTROL_CONF_LCD_DATA17_CONF_LCD_DATA17_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_LCD_DATA17_CONF_LCD_DATA17_PUDEN (0x00000008u)
+#define CONTROL_CONF_LCD_DATA17_CONF_LCD_DATA17_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_LCD_DATA17_CONF_LCD_DATA17_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_LCD_DATA17_CONF_LCD_DATA17_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_LCD_DATA17_CONF_LCD_DATA17_RSVD (0x000FFF80u)
+#define CONTROL_CONF_LCD_DATA17_CONF_LCD_DATA17_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_LCD_DATA17_CONF_LCD_DATA17_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_LCD_DATA17_CONF_LCD_DATA17_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_LCD_DATA17_CONF_LCD_DATA17_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_LCD_DATA17_CONF_LCD_DATA17_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_LCD_DATA18 */
+#define CONTROL_CONF_LCD_DATA18_CONF_LCD_DATA18_MMODE (0x00000007u)
+#define CONTROL_CONF_LCD_DATA18_CONF_LCD_DATA18_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_LCD_DATA18_CONF_LCD_DATA18_PUDEN (0x00000008u)
+#define CONTROL_CONF_LCD_DATA18_CONF_LCD_DATA18_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_LCD_DATA18_CONF_LCD_DATA18_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_LCD_DATA18_CONF_LCD_DATA18_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_LCD_DATA18_CONF_LCD_DATA18_RSVD (0x000FFF80u)
+#define CONTROL_CONF_LCD_DATA18_CONF_LCD_DATA18_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_LCD_DATA18_CONF_LCD_DATA18_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_LCD_DATA18_CONF_LCD_DATA18_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_LCD_DATA18_CONF_LCD_DATA18_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_LCD_DATA18_CONF_LCD_DATA18_SLEWCTRL_SHIFT (0x00000006u)
+
+/* CONF_LCD_DATA19 */
+#define CONTROL_CONF_LCD_DATA19_CONF_LCD_DATA19_MMODE (0x00000007u)
+#define CONTROL_CONF_LCD_DATA19_CONF_LCD_DATA19_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_LCD_DATA19_CONF_LCD_DATA19_PUDEN (0x00000008u)
+#define CONTROL_CONF_LCD_DATA19_CONF_LCD_DATA19_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_LCD_DATA19_CONF_LCD_DATA19_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_LCD_DATA19_CONF_LCD_DATA19_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_LCD_DATA19_CONF_LCD_DATA19_RSVD (0x000FFF80u)
+#define CONTROL_CONF_LCD_DATA19_CONF_LCD_DATA19_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_LCD_DATA19_CONF_LCD_DATA19_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_LCD_DATA19_CONF_LCD_DATA19_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_LCD_DATA19_CONF_LCD_DATA19_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_LCD_DATA19_CONF_LCD_DATA19_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_LCD_DATA20 */
+#define CONTROL_CONF_LCD_DATA20_CONF_LCD_DATA20_MMODE (0x00000007u)
+#define CONTROL_CONF_LCD_DATA20_CONF_LCD_DATA20_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_LCD_DATA20_CONF_LCD_DATA20_PUDEN (0x00000008u)
+#define CONTROL_CONF_LCD_DATA20_CONF_LCD_DATA20_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_LCD_DATA20_CONF_LCD_DATA20_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_LCD_DATA20_CONF_LCD_DATA20_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_LCD_DATA20_CONF_LCD_DATA20_RSVD (0x000FFF80u)
+#define CONTROL_CONF_LCD_DATA20_CONF_LCD_DATA20_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_LCD_DATA20_CONF_LCD_DATA20_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_LCD_DATA20_CONF_LCD_DATA20_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_LCD_DATA20_CONF_LCD_DATA20_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_LCD_DATA20_CONF_LCD_DATA20_SLEWCTRL_SHIFT (0x00000006u)
+
+/* CONF_LCD_DATA21 */
+#define CONTROL_CONF_LCD_DATA21_CONF_LCD_DATA21_MMODE (0x00000007u)
+#define CONTROL_CONF_LCD_DATA21_CONF_LCD_DATA21_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_LCD_DATA21_CONF_LCD_DATA21_PUDEN (0x00000008u)
+#define CONTROL_CONF_LCD_DATA21_CONF_LCD_DATA21_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_LCD_DATA21_CONF_LCD_DATA21_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_LCD_DATA21_CONF_LCD_DATA21_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_LCD_DATA21_CONF_LCD_DATA21_RSVD (0x000FFF80u)
+#define CONTROL_CONF_LCD_DATA21_CONF_LCD_DATA21_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_LCD_DATA21_CONF_LCD_DATA21_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_LCD_DATA21_CONF_LCD_DATA21_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_LCD_DATA21_CONF_LCD_DATA21_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_LCD_DATA21_CONF_LCD_DATA21_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_LCD_DATA22 */
+#define CONTROL_CONF_LCD_DATA22_CONF_LCD_DATA22_MMODE (0x00000007u)
+#define CONTROL_CONF_LCD_DATA22_CONF_LCD_DATA22_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_LCD_DATA22_CONF_LCD_DATA22_PUDEN (0x00000008u)
+#define CONTROL_CONF_LCD_DATA22_CONF_LCD_DATA22_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_LCD_DATA22_CONF_LCD_DATA22_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_LCD_DATA22_CONF_LCD_DATA22_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_LCD_DATA22_CONF_LCD_DATA22_RSVD (0x000FFF80u)
+#define CONTROL_CONF_LCD_DATA22_CONF_LCD_DATA22_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_LCD_DATA22_CONF_LCD_DATA22_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_LCD_DATA22_CONF_LCD_DATA22_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_LCD_DATA22_CONF_LCD_DATA22_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_LCD_DATA22_CONF_LCD_DATA22_SLEWCTRL_SHIFT (0x00000006u)
+
+/* CONF_LCD_DATA20 */
+#define CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_MMODE (0x00000007u)
+#define CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_PUDEN (0x00000008u)
+#define CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_RSVD (0x000FFF80u)
+#define CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_LCD_DATA23_CONF_LCD_DATA23_SLEWCTRL_SHIFT (0x00000006u)
+
+
+
+
+
+
+
+
+
+/* CONF_LCD_VSYNC */
+#define CONTROL_CONF_LCD_VSYNC_CONF_LCD_VSYNC_MMODE (0x00000007u)
+#define CONTROL_CONF_LCD_VSYNC_CONF_LCD_VSYNC_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_LCD_VSYNC_CONF_LCD_VSYNC_PUDEN (0x00000008u)
+#define CONTROL_CONF_LCD_VSYNC_CONF_LCD_VSYNC_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_LCD_VSYNC_CONF_LCD_VSYNC_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_LCD_VSYNC_CONF_LCD_VSYNC_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_LCD_VSYNC_CONF_LCD_VSYNC_RSVD (0x000FFF80u)
+#define CONTROL_CONF_LCD_VSYNC_CONF_LCD_VSYNC_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_LCD_VSYNC_CONF_LCD_VSYNC_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_LCD_VSYNC_CONF_LCD_VSYNC_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_LCD_VSYNC_CONF_LCD_VSYNC_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_LCD_VSYNC_CONF_LCD_VSYNC_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_LCD_HSYNC */
+#define CONTROL_CONF_LCD_HSYNC_CONF_LCD_HSYNC_MMODE (0x00000007u)
+#define CONTROL_CONF_LCD_HSYNC_CONF_LCD_HSYNC_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_LCD_HSYNC_CONF_LCD_HSYNC_PUDEN (0x00000008u)
+#define CONTROL_CONF_LCD_HSYNC_CONF_LCD_HSYNC_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_LCD_HSYNC_CONF_LCD_HSYNC_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_LCD_HSYNC_CONF_LCD_HSYNC_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_LCD_HSYNC_CONF_LCD_HSYNC_RSVD (0x000FFF80u)
+#define CONTROL_CONF_LCD_HSYNC_CONF_LCD_HSYNC_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_LCD_HSYNC_CONF_LCD_HSYNC_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_LCD_HSYNC_CONF_LCD_HSYNC_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_LCD_HSYNC_CONF_LCD_HSYNC_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_LCD_HSYNC_CONF_LCD_HSYNC_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_LCD_PCLK */
+#define CONTROL_CONF_LCD_PCLK_CONF_LCD_PCLK_MMODE (0x00000007u)
+#define CONTROL_CONF_LCD_PCLK_CONF_LCD_PCLK_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_LCD_PCLK_CONF_LCD_PCLK_PUDEN (0x00000008u)
+#define CONTROL_CONF_LCD_PCLK_CONF_LCD_PCLK_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_LCD_PCLK_CONF_LCD_PCLK_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_LCD_PCLK_CONF_LCD_PCLK_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_LCD_PCLK_CONF_LCD_PCLK_RSVD (0x000FFF80u)
+#define CONTROL_CONF_LCD_PCLK_CONF_LCD_PCLK_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_LCD_PCLK_CONF_LCD_PCLK_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_LCD_PCLK_CONF_LCD_PCLK_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_LCD_PCLK_CONF_LCD_PCLK_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_LCD_PCLK_CONF_LCD_PCLK_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_LCD_AC_BIAS_EN */
+#define CONTROL_CONF_LCD_AC_BIAS_EN_CONF_LCD_AC_BIAS_EN_MMODE (0x00000007u)
+#define CONTROL_CONF_LCD_AC_BIAS_EN_CONF_LCD_AC_BIAS_EN_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_LCD_AC_BIAS_EN_CONF_LCD_AC_BIAS_EN_PUDEN (0x00000008u)
+#define CONTROL_CONF_LCD_AC_BIAS_EN_CONF_LCD_AC_BIAS_EN_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_LCD_AC_BIAS_EN_CONF_LCD_AC_BIAS_EN_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_LCD_AC_BIAS_EN_CONF_LCD_AC_BIAS_EN_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_LCD_AC_BIAS_EN_CONF_LCD_AC_BIAS_EN_RSVD (0x000FFF80u)
+#define CONTROL_CONF_LCD_AC_BIAS_EN_CONF_LCD_AC_BIAS_EN_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_LCD_AC_BIAS_EN_CONF_LCD_AC_BIAS_EN_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_LCD_AC_BIAS_EN_CONF_LCD_AC_BIAS_EN_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_LCD_AC_BIAS_EN_CONF_LCD_AC_BIAS_EN_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_LCD_AC_BIAS_EN_CONF_LCD_AC_BIAS_EN_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_MMC0_DAT3 */
+#define CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_MMODE (0x00000007u)
+#define CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_PUDEN (0x00000008u)
+#define CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_RSVD (0x000FFF80u)
+#define CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_MMC0_DAT3_CONF_MMC0_DAT3_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_MMC0_DAT2 */
+#define CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_MMODE (0x00000007u)
+#define CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_PUDEN (0x00000008u)
+#define CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_RSVD (0x000FFF80u)
+#define CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_MMC0_DAT2_CONF_MMC0_DAT2_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_MMC0_DAT1 */
+#define CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_MMODE (0x00000007u)
+#define CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_PUDEN (0x00000008u)
+#define CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_RSVD (0x000FFF80u)
+#define CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_MMC0_DAT1_CONF_MMC0_DAT1_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_MMC0_DAT0 */
+#define CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_MMODE (0x00000007u)
+#define CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_PUDEN (0x00000008u)
+#define CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_RSVD (0x000FFF80u)
+#define CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_MMC0_DAT0_CONF_MMC0_DAT0_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_MMC0_CLK */
+#define CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_MMODE (0x00000007u)
+#define CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_PUDEN (0x00000008u)
+#define CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_RSVD (0x000FFF80u)
+#define CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_MMC0_CLK_CONF_MMC0_CLK_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_MMC0_CMD */
+#define CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_MMODE (0x00000007u)
+#define CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_PUDEN (0x00000008u)
+#define CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_RSVD (0x000FFF80u)
+#define CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_MMC0_CMD_CONF_MMC0_CMD_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_MII1_COL */
+#define CONTROL_CONF_MII1_COL_CONF_MII1_COL_MMODE (0x00000007u)
+#define CONTROL_CONF_MII1_COL_CONF_MII1_COL_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_MII1_COL_CONF_MII1_COL_PUDEN (0x00000008u)
+#define CONTROL_CONF_MII1_COL_CONF_MII1_COL_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_MII1_COL_CONF_MII1_COL_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_MII1_COL_CONF_MII1_COL_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_MII1_COL_CONF_MII1_COL_RSVD (0x000FFF80u)
+#define CONTROL_CONF_MII1_COL_CONF_MII1_COL_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_MII1_COL_CONF_MII1_COL_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_MII1_COL_CONF_MII1_COL_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_MII1_COL_CONF_MII1_COL_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_MII1_COL_CONF_MII1_COL_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_MII1_CRS */
+#define CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_MMODE (0x00000007u)
+#define CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_PUDEN (0x00000008u)
+#define CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_RSVD (0x000FFF80u)
+#define CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_MII1_CRS_CONF_MII1_CRS_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_MII1_RXERR */
+#define CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_MMODE (0x00000007u)
+#define CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_PUDEN (0x00000008u)
+#define CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_RSVD (0x000FFF80u)
+#define CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_MII1_RXERR_CONF_MII1_RXERR_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_MII1_TXEN */
+#define CONTROL_CONF_MII1_TXEN_CONF_MII1_TXEN_MMODE (0x00000007u)
+#define CONTROL_CONF_MII1_TXEN_CONF_MII1_TXEN_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_MII1_TXEN_CONF_MII1_TXEN_PUDEN (0x00000008u)
+#define CONTROL_CONF_MII1_TXEN_CONF_MII1_TXEN_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_MII1_TXEN_CONF_MII1_TXEN_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_MII1_TXEN_CONF_MII1_TXEN_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_MII1_TXEN_CONF_MII1_TXEN_RSVD (0x000FFF80u)
+#define CONTROL_CONF_MII1_TXEN_CONF_MII1_TXEN_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_MII1_TXEN_CONF_MII1_TXEN_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_MII1_TXEN_CONF_MII1_TXEN_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_MII1_TXEN_CONF_MII1_TXEN_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_MII1_TXEN_CONF_MII1_TXEN_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_MII1_RXDV */
+#define CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_MMODE (0x00000007u)
+#define CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_PUDEN (0x00000008u)
+#define CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_RSVD (0x000FFF80u)
+#define CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_MII1_RXDV_CONF_MII1_RXDV_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_MII1_TXD3 */
+#define CONTROL_CONF_MII1_TXD3_CONF_MII1_TXD3_MMODE (0x00000007u)
+#define CONTROL_CONF_MII1_TXD3_CONF_MII1_TXD3_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_MII1_TXD3_CONF_MII1_TXD3_PUDEN (0x00000008u)
+#define CONTROL_CONF_MII1_TXD3_CONF_MII1_TXD3_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_MII1_TXD3_CONF_MII1_TXD3_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_MII1_TXD3_CONF_MII1_TXD3_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_MII1_TXD3_CONF_MII1_TXD3_RSVD (0x000FFF80u)
+#define CONTROL_CONF_MII1_TXD3_CONF_MII1_TXD3_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_MII1_TXD3_CONF_MII1_TXD3_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_MII1_TXD3_CONF_MII1_TXD3_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_MII1_TXD3_CONF_MII1_TXD3_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_MII1_TXD3_CONF_MII1_TXD3_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_MII1_TXD2 */
+#define CONTROL_CONF_MII1_TXD2_CONF_MII1_TXD2_MMODE (0x00000007u)
+#define CONTROL_CONF_MII1_TXD2_CONF_MII1_TXD2_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_MII1_TXD2_CONF_MII1_TXD2_PUDEN (0x00000008u)
+#define CONTROL_CONF_MII1_TXD2_CONF_MII1_TXD2_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_MII1_TXD2_CONF_MII1_TXD2_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_MII1_TXD2_CONF_MII1_TXD2_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_MII1_TXD2_CONF_MII1_TXD2_RSVD (0x000FFF80u)
+#define CONTROL_CONF_MII1_TXD2_CONF_MII1_TXD2_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_MII1_TXD2_CONF_MII1_TXD2_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_MII1_TXD2_CONF_MII1_TXD2_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_MII1_TXD2_CONF_MII1_TXD2_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_MII1_TXD2_CONF_MII1_TXD2_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_MII1_TXD1 */
+#define CONTROL_CONF_MII1_TXD1_CONF_MII1_TXD1_MMODE (0x00000007u)
+#define CONTROL_CONF_MII1_TXD1_CONF_MII1_TXD1_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_MII1_TXD1_CONF_MII1_TXD1_PUDEN (0x00000008u)
+#define CONTROL_CONF_MII1_TXD1_CONF_MII1_TXD1_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_MII1_TXD1_CONF_MII1_TXD1_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_MII1_TXD1_CONF_MII1_TXD1_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_MII1_TXD1_CONF_MII1_TXD1_RSVD (0x000FFF80u)
+#define CONTROL_CONF_MII1_TXD1_CONF_MII1_TXD1_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_MII1_TXD1_CONF_MII1_TXD1_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_MII1_TXD1_CONF_MII1_TXD1_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_MII1_TXD1_CONF_MII1_TXD1_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_MII1_TXD1_CONF_MII1_TXD1_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_MII1_TXD0 */
+#define CONTROL_CONF_MII1_TXD0_CONF_MII1_TXD0_MMODE (0x00000007u)
+#define CONTROL_CONF_MII1_TXD0_CONF_MII1_TXD0_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_MII1_TXD0_CONF_MII1_TXD0_PUDEN (0x00000008u)
+#define CONTROL_CONF_MII1_TXD0_CONF_MII1_TXD0_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_MII1_TXD0_CONF_MII1_TXD0_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_MII1_TXD0_CONF_MII1_TXD0_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_MII1_TXD0_CONF_MII1_TXD0_RSVD (0x000FFF80u)
+#define CONTROL_CONF_MII1_TXD0_CONF_MII1_TXD0_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_MII1_TXD0_CONF_MII1_TXD0_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_MII1_TXD0_CONF_MII1_TXD0_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_MII1_TXD0_CONF_MII1_TXD0_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_MII1_TXD0_CONF_MII1_TXD0_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_MII1_TXCLK */
+#define CONTROL_CONF_MII1_TXCLK_CONF_MII1_TXCLK_MMODE (0x00000007u)
+#define CONTROL_CONF_MII1_TXCLK_CONF_MII1_TXCLK_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_MII1_TXCLK_CONF_MII1_TXCLK_PUDEN (0x00000008u)
+#define CONTROL_CONF_MII1_TXCLK_CONF_MII1_TXCLK_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_MII1_TXCLK_CONF_MII1_TXCLK_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_MII1_TXCLK_CONF_MII1_TXCLK_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_MII1_TXCLK_CONF_MII1_TXCLK_RSVD (0x000FFF80u)
+#define CONTROL_CONF_MII1_TXCLK_CONF_MII1_TXCLK_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_MII1_TXCLK_CONF_MII1_TXCLK_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_MII1_TXCLK_CONF_MII1_TXCLK_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_MII1_TXCLK_CONF_MII1_TXCLK_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_MII1_TXCLK_CONF_MII1_TXCLK_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_MII1_RXCLK */
+#define CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_MMODE (0x00000007u)
+#define CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_PUDEN (0x00000008u)
+#define CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_RSVD (0x000FFF80u)
+#define CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_MII1_RXCLK_CONF_MII1_RXCLK_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_MII1_RXD3 */
+#define CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_MMODE (0x00000007u)
+#define CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_PUDEN (0x00000008u)
+#define CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_RSVD (0x000FFF80u)
+#define CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_MII1_RXD3_CONF_MII1_RXD3_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_MII1_RXD2 */
+#define CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_MMODE (0x00000007u)
+#define CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_PUDEN (0x00000008u)
+#define CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_RSVD (0x000FFF80u)
+#define CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_MII1_RXD2_CONF_MII1_RXD2_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_MII1_RXD1 */
+#define CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_MMODE (0x00000007u)
+#define CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_PUDEN (0x00000008u)
+#define CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_RSVD (0x000FFF80u)
+#define CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_MII1_RXD1_CONF_MII1_RXD1_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_MII1_RXD0 */
+#define CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_MMODE (0x00000007u)
+#define CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_PUDEN (0x00000008u)
+#define CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_RSVD (0x000FFF80u)
+#define CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_MII1_RXD0_CONF_MII1_RXD0_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_RMII1_REFCLK */
+#define CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_MMODE (0x00000007u)
+#define CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_PUDEN (0x00000008u)
+#define CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_RSVD (0x000FFF80u)
+#define CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_RMII1_REFCLK_CONF_RMII1_REFCLK_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_MDIO_DATA */
+#define CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_MMODE (0x00000007u)
+#define CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_PUDEN (0x00000008u)
+#define CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_RSVD (0x000FFF80u)
+#define CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_MDIO_DATA_CONF_MDIO_DATA_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_MDIO_CLK */
+#define CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_MMODE (0x00000007u)
+#define CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_PUDEN (0x00000008u)
+#define CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_RSVD (0x000FFF80u)
+#define CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_MDIO_CLK_CONF_MDIO_CLK_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_SPI0_SCLK */
+#define CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_MMODE (0x00000007u)
+#define CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_PUDEN (0x00000008u)
+#define CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_RSVD (0x000FFF80u)
+#define CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_SPI0_SCLK_CONF_SPI0_SCLK_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_SPI0_D0 */
+#define CONTROL_CONF_SPI0_D0_CONF_SPI0_D0_MMODE (0x00000007u)
+#define CONTROL_CONF_SPI0_D0_CONF_SPI0_D0_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_SPI0_D0_CONF_SPI0_D0_PUDEN (0x00000008u)
+#define CONTROL_CONF_SPI0_D0_CONF_SPI0_D0_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_SPI0_D0_CONF_SPI0_D0_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_SPI0_D0_CONF_SPI0_D0_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_SPI0_D0_CONF_SPI0_D0_RSVD (0x000FFF80u)
+#define CONTROL_CONF_SPI0_D0_CONF_SPI0_D0_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_SPI0_D0_CONF_SPI0_D0_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_SPI0_D0_CONF_SPI0_D0_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_SPI0_D0_CONF_SPI0_D0_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_SPI0_D0_CONF_SPI0_D0_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_SPI0_D1 */
+#define CONTROL_CONF_SPI0_D1_CONF_SPI0_D1_MMODE (0x00000007u)
+#define CONTROL_CONF_SPI0_D1_CONF_SPI0_D1_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_SPI0_D1_CONF_SPI0_D1_PUDEN (0x00000008u)
+#define CONTROL_CONF_SPI0_D1_CONF_SPI0_D1_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_SPI0_D1_CONF_SPI0_D1_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_SPI0_D1_CONF_SPI0_D1_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_SPI0_D1_CONF_SPI0_D1_RSVD (0x000FFF80u)
+#define CONTROL_CONF_SPI0_D1_CONF_SPI0_D1_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_SPI0_D1_CONF_SPI0_D1_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_SPI0_D1_CONF_SPI0_D1_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_SPI0_D1_CONF_SPI0_D1_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_SPI0_D1_CONF_SPI0_D1_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_SPI0_CS0 */
+#define CONTROL_CONF_SPI0_CS0_CONF_SPI0_CS0_MMODE (0x00000007u)
+#define CONTROL_CONF_SPI0_CS0_CONF_SPI0_CS0_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_SPI0_CS0_CONF_SPI0_CS0_PUDEN (0x00000008u)
+#define CONTROL_CONF_SPI0_CS0_CONF_SPI0_CS0_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_SPI0_CS0_CONF_SPI0_CS0_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_SPI0_CS0_CONF_SPI0_CS0_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_SPI0_CS0_CONF_SPI0_CS0_RSVD (0x000FFF80u)
+#define CONTROL_CONF_SPI0_CS0_CONF_SPI0_CS0_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_SPI0_CS0_CONF_SPI0_CS0_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_SPI0_CS0_CONF_SPI0_CS0_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_SPI0_CS0_CONF_SPI0_CS0_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_SPI0_CS0_CONF_SPI0_CS0_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_SPI0_CS1 */
+#define CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_MMODE (0x00000007u)
+#define CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_PUDEN (0x00000008u)
+#define CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_RSVD (0x000FFF80u)
+#define CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_SPI0_CS1_CONF_SPI0_CS1_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_ECAP0_IN_PWM0_OUT */
+#define CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_MMODE (0x00000007u)
+#define CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_PUDEN (0x00000008u)
+#define CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_RSVD (0x000FFF80u)
+#define CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_ECAP0_IN_PWM0_OUT_CONF_ECAP0_IN_PWM0_OUT_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_UART0_CTSN */
+#define CONTROL_CONF_UART0_CTSN_CONF_UART0_CTSN_MMODE (0x00000007u)
+#define CONTROL_CONF_UART0_CTSN_CONF_UART0_CTSN_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_UART0_CTSN_CONF_UART0_CTSN_PUDEN (0x00000008u)
+#define CONTROL_CONF_UART0_CTSN_CONF_UART0_CTSN_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_UART0_CTSN_CONF_UART0_CTSN_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_UART0_CTSN_CONF_UART0_CTSN_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_UART0_CTSN_CONF_UART0_CTSN_RSVD (0x000FFF80u)
+#define CONTROL_CONF_UART0_CTSN_CONF_UART0_CTSN_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_UART0_CTSN_CONF_UART0_CTSN_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_UART0_CTSN_CONF_UART0_CTSN_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_UART0_CTSN_CONF_UART0_CTSN_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_UART0_CTSN_CONF_UART0_CTSN_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_UART0_RTSN */
+#define CONTROL_CONF_UART0_RTSN_CONF_UART0_RTSN_MMODE (0x00000007u)
+#define CONTROL_CONF_UART0_RTSN_CONF_UART0_RTSN_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_UART0_RTSN_CONF_UART0_RTSN_PUDEN (0x00000008u)
+#define CONTROL_CONF_UART0_RTSN_CONF_UART0_RTSN_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_UART0_RTSN_CONF_UART0_RTSN_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_UART0_RTSN_CONF_UART0_RTSN_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_UART0_RTSN_CONF_UART0_RTSN_RSVD (0x000FFF80u)
+#define CONTROL_CONF_UART0_RTSN_CONF_UART0_RTSN_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_UART0_RTSN_CONF_UART0_RTSN_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_UART0_RTSN_CONF_UART0_RTSN_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_UART0_RTSN_CONF_UART0_RTSN_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_UART0_RTSN_CONF_UART0_RTSN_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_UART0_RXD */
+#define CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_MMODE (0x00000007u)
+#define CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_PUDEN (0x00000008u)
+#define CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_RSVD (0x000FFF80u)
+#define CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_UART0_RXD_CONF_UART0_RXD_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_UART0_TXD */
+#define CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_MMODE (0x00000007u)
+#define CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_PUDEN (0x00000008u)
+#define CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_RSVD (0x000FFF80u)
+#define CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_UART0_TXD_CONF_UART0_TXD_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_UART1_CTSN */
+#define CONTROL_CONF_UART1_CTSN_CONF_UART1_CTSN_MMODE (0x00000007u)
+#define CONTROL_CONF_UART1_CTSN_CONF_UART1_CTSN_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_UART1_CTSN_CONF_UART1_CTSN_PUDEN (0x00000008u)
+#define CONTROL_CONF_UART1_CTSN_CONF_UART1_CTSN_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_UART1_CTSN_CONF_UART1_CTSN_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_UART1_CTSN_CONF_UART1_CTSN_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_UART1_CTSN_CONF_UART1_CTSN_RSVD (0x000FFF80u)
+#define CONTROL_CONF_UART1_CTSN_CONF_UART1_CTSN_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_UART1_CTSN_CONF_UART1_CTSN_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_UART1_CTSN_CONF_UART1_CTSN_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_UART1_CTSN_CONF_UART1_CTSN_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_UART1_CTSN_CONF_UART1_CTSN_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_UART1_RTSN */
+#define CONTROL_CONF_UART1_RTSN_CONF_UART1_RTSN_MMODE (0x00000007u)
+#define CONTROL_CONF_UART1_RTSN_CONF_UART1_RTSN_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_UART1_RTSN_CONF_UART1_RTSN_PUDEN (0x00000008u)
+#define CONTROL_CONF_UART1_RTSN_CONF_UART1_RTSN_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_UART1_RTSN_CONF_UART1_RTSN_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_UART1_RTSN_CONF_UART1_RTSN_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_UART1_RTSN_CONF_UART1_RTSN_RSVD (0x000FFF80u)
+#define CONTROL_CONF_UART1_RTSN_CONF_UART1_RTSN_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_UART1_RTSN_CONF_UART1_RTSN_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_UART1_RTSN_CONF_UART1_RTSN_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_UART1_RTSN_CONF_UART1_RTSN_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_UART1_RTSN_CONF_UART1_RTSN_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_UART1_RXD */
+#define CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_MMODE (0x00000007u)
+#define CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_PUDEN (0x00000008u)
+#define CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_RSVD (0x000FFF80u)
+#define CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_UART1_RXD_CONF_UART1_RXD_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_UART1_TXD */
+#define CONTROL_CONF_UART1_TXD_CONF_UART1_TXD_MMODE (0x00000007u)
+#define CONTROL_CONF_UART1_TXD_CONF_UART1_TXD_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_UART1_TXD_CONF_UART1_TXD_PUDEN (0x00000008u)
+#define CONTROL_CONF_UART1_TXD_CONF_UART1_TXD_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_UART1_TXD_CONF_UART1_TXD_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_UART1_TXD_CONF_UART1_TXD_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_UART1_TXD_CONF_UART1_TXD_RSVD (0x000FFF80u)
+#define CONTROL_CONF_UART1_TXD_CONF_UART1_TXD_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_UART1_TXD_CONF_UART1_TXD_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_UART1_TXD_CONF_UART1_TXD_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_UART1_TXD_CONF_UART1_TXD_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_UART1_TXD_CONF_UART1_TXD_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_I2C0_SDA */
+#define CONTROL_CONF_I2C0_SDA_CONF_I2C0_SDA_MMODE (0x00000007u)
+#define CONTROL_CONF_I2C0_SDA_CONF_I2C0_SDA_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_I2C0_SDA_CONF_I2C0_SDA_PUDEN (0x00000008u)
+#define CONTROL_CONF_I2C0_SDA_CONF_I2C0_SDA_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_I2C0_SDA_CONF_I2C0_SDA_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_I2C0_SDA_CONF_I2C0_SDA_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_I2C0_SDA_CONF_I2C0_SDA_RSVD (0x000FFF80u)
+#define CONTROL_CONF_I2C0_SDA_CONF_I2C0_SDA_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_I2C0_SDA_CONF_I2C0_SDA_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_I2C0_SDA_CONF_I2C0_SDA_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_I2C0_SDA_CONF_I2C0_SDA_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_I2C0_SDA_CONF_I2C0_SDA_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_I2C0_SCL */
+#define CONTROL_CONF_I2C0_SCL_CONF_I2C0_SCL_MMODE (0x00000007u)
+#define CONTROL_CONF_I2C0_SCL_CONF_I2C0_SCL_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_I2C0_SCL_CONF_I2C0_SCL_PUDEN (0x00000008u)
+#define CONTROL_CONF_I2C0_SCL_CONF_I2C0_SCL_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_I2C0_SCL_CONF_I2C0_SCL_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_I2C0_SCL_CONF_I2C0_SCL_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_I2C0_SCL_CONF_I2C0_SCL_RSVD (0x000FFF80u)
+#define CONTROL_CONF_I2C0_SCL_CONF_I2C0_SCL_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_I2C0_SCL_CONF_I2C0_SCL_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_I2C0_SCL_CONF_I2C0_SCL_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_I2C0_SCL_CONF_I2C0_SCL_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_I2C0_SCL_CONF_I2C0_SCL_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_I2C0_SDA */
+#define CONTROL_CONF_I2C1_SDA_CONF_I2C1_SDA_MMODE (0x00000007u)
+#define CONTROL_CONF_I2C1_SDA_CONF_I2C1_SDA_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_I2C1_SDA_CONF_I2C1_SDA_PUDEN (0x00000008u)
+#define CONTROL_CONF_I2C1_SDA_CONF_I2C1_SDA_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_I2C1_SDA_CONF_I2C1_SDA_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_I2C1_SDA_CONF_I2C1_SDA_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_I2C1_SDA_CONF_I2C1_SDA_RSVD (0x000FFF80u)
+#define CONTROL_CONF_I2C1_SDA_CONF_I2C1_SDA_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_I2C1_SDA_CONF_I2C1_SDA_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_I2C1_SDA_CONF_I2C1_SDA_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_I2C1_SDA_CONF_I2C1_SDA_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_I2C1_SDA_CONF_I2C1_SDA_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_I2C0_SCL */
+#define CONTROL_CONF_I2C1_SCL_CONF_I2C1_SCL_MMODE (0x00000007u)
+#define CONTROL_CONF_I2C1_SCL_CONF_I2C1_SCL_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_I2C1_SCL_CONF_I2C1_SCL_PUDEN (0x00000008u)
+#define CONTROL_CONF_I2C1_SCL_CONF_I2C1_SCL_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_I2C1_SCL_CONF_I2C1_SCL_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_I2C1_SCL_CONF_I2C1_SCL_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_I2C1_SCL_CONF_I2C1_SCL_RSVD (0x000FFF80u)
+#define CONTROL_CONF_I2C1_SCL_CONF_I2C1_SCL_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_I2C1_SCL_CONF_I2C1_SCL_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_I2C1_SCL_CONF_I2C1_SCL_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_I2C1_SCL_CONF_I2C1_SCL_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_I2C1_SCL_CONF_I2C1_SCL_SLEWCTRL_SHIFT (0x00000006u)
+
+
+
+/* CONF_MCASP0_ACLKX */
+#define CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_MMODE (0x00000007u)
+#define CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_PUDEN (0x00000008u)
+#define CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_RSVD (0x000FFF80u)
+#define CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_MCASP0_FSX */
+#define CONTROL_CONF_MCASP0_FSX_CONF_MCASP0_FSX_MMODE (0x00000007u)
+#define CONTROL_CONF_MCASP0_FSX_CONF_MCASP0_FSX_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_MCASP0_FSX_CONF_MCASP0_FSX_PUDEN (0x00000008u)
+#define CONTROL_CONF_MCASP0_FSX_CONF_MCASP0_FSX_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_MCASP0_FSX_CONF_MCASP0_FSX_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_MCASP0_FSX_CONF_MCASP0_FSX_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_MCASP0_FSX_CONF_MCASP0_FSX_RSVD (0x000FFF80u)
+#define CONTROL_CONF_MCASP0_FSX_CONF_MCASP0_FSX_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_MCASP0_FSX_CONF_MCASP0_FSX_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_MCASP0_FSX_CONF_MCASP0_FSX_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_MCASP0_FSX_CONF_MCASP0_FSX_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_MCASP0_FSX_CONF_MCASP0_FSX_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_MCASP0_AXR0 */
+#define CONTROL_CONF_MCASP0_AXR0_CONF_MCASP0_AXR0_MMODE (0x00000007u)
+#define CONTROL_CONF_MCASP0_AXR0_CONF_MCASP0_AXR0_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_MCASP0_AXR0_CONF_MCASP0_AXR0_PUDEN (0x00000008u)
+#define CONTROL_CONF_MCASP0_AXR0_CONF_MCASP0_AXR0_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_MCASP0_AXR0_CONF_MCASP0_AXR0_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_MCASP0_AXR0_CONF_MCASP0_AXR0_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_MCASP0_AXR0_CONF_MCASP0_AXR0_RSVD (0x000FFF80u)
+#define CONTROL_CONF_MCASP0_AXR0_CONF_MCASP0_AXR0_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_MCASP0_AXR0_CONF_MCASP0_AXR0_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_MCASP0_AXR0_CONF_MCASP0_AXR0_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_MCASP0_AXR0_CONF_MCASP0_AXR0_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_MCASP0_AXR0_CONF_MCASP0_AXR0_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_MCASP0_AHCLKR */
+#define CONTROL_CONF_MCASP0_AHCLKR_CONF_MCASP0_AHCLKR_MMODE (0x00000007u)
+#define CONTROL_CONF_MCASP0_AHCLKR_CONF_MCASP0_AHCLKR_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_MCASP0_AHCLKR_CONF_MCASP0_AHCLKR_PUDEN (0x00000008u)
+#define CONTROL_CONF_MCASP0_AHCLKR_CONF_MCASP0_AHCLKR_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_MCASP0_AHCLKR_CONF_MCASP0_AHCLKR_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_MCASP0_AHCLKR_CONF_MCASP0_AHCLKR_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_MCASP0_AHCLKR_CONF_MCASP0_AHCLKR_RSVD (0x000FFF80u)
+#define CONTROL_CONF_MCASP0_AHCLKR_CONF_MCASP0_AHCLKR_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_MCASP0_AHCLKR_CONF_MCASP0_AHCLKR_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_MCASP0_AHCLKR_CONF_MCASP0_AHCLKR_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_MCASP0_AHCLKR_CONF_MCASP0_AHCLKR_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_MCASP0_AHCLKR_CONF_MCASP0_AHCLKR_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_MCASP0_ACLKR */
+#define CONTROL_CONF_MCASP0_ACLKR_CONF_MCASP0_ACLKR_MMODE (0x00000007u)
+#define CONTROL_CONF_MCASP0_ACLKR_CONF_MCASP0_ACLKR_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_MCASP0_ACLKR_CONF_MCASP0_ACLKR_PUDEN (0x00000008u)
+#define CONTROL_CONF_MCASP0_ACLKR_CONF_MCASP0_ACLKR_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_MCASP0_ACLKR_CONF_MCASP0_ACLKR_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_MCASP0_ACLKR_CONF_MCASP0_ACLKR_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_MCASP0_ACLKR_CONF_MCASP0_ACLKR_RSVD (0x000FFF80u)
+#define CONTROL_CONF_MCASP0_ACLKR_CONF_MCASP0_ACLKR_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_MCASP0_ACLKR_CONF_MCASP0_ACLKR_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_MCASP0_ACLKR_CONF_MCASP0_ACLKR_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_MCASP0_ACLKR_CONF_MCASP0_ACLKR_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_MCASP0_ACLKR_CONF_MCASP0_ACLKR_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_MCASP0_FSR */
+#define CONTROL_CONF_MCASP0_FSR_CONF_MCASP0_FSR_MMODE (0x00000007u)
+#define CONTROL_CONF_MCASP0_FSR_CONF_MCASP0_FSR_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_MCASP0_FSR_CONF_MCASP0_FSR_PUDEN (0x00000008u)
+#define CONTROL_CONF_MCASP0_FSR_CONF_MCASP0_FSR_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_MCASP0_FSR_CONF_MCASP0_FSR_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_MCASP0_FSR_CONF_MCASP0_FSR_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_MCASP0_FSR_CONF_MCASP0_FSR_RSVD (0x000FFF80u)
+#define CONTROL_CONF_MCASP0_FSR_CONF_MCASP0_FSR_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_MCASP0_FSR_CONF_MCASP0_FSR_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_MCASP0_FSR_CONF_MCASP0_FSR_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_MCASP0_FSR_CONF_MCASP0_FSR_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_MCASP0_FSR_CONF_MCASP0_FSR_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_MCASP0_AXR1 */
+#define CONTROL_CONF_MCASP0_AXR1_CONF_MCASP0_AXR1_MMODE (0x00000007u)
+#define CONTROL_CONF_MCASP0_AXR1_CONF_MCASP0_AXR1_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_MCASP0_AXR1_CONF_MCASP0_AXR1_PUDEN (0x00000008u)
+#define CONTROL_CONF_MCASP0_AXR1_CONF_MCASP0_AXR1_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_MCASP0_AXR1_CONF_MCASP0_AXR1_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_MCASP0_AXR1_CONF_MCASP0_AXR1_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_MCASP0_AXR1_CONF_MCASP0_AXR1_RSVD (0x000FFF80u)
+#define CONTROL_CONF_MCASP0_AXR1_CONF_MCASP0_AXR1_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_MCASP0_AXR1_CONF_MCASP0_AXR1_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_MCASP0_AXR1_CONF_MCASP0_AXR1_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_MCASP0_AXR1_CONF_MCASP0_AXR1_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_MCASP0_AXR1_CONF_MCASP0_AXR1_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_MCASP0_AHCLKX */
+#define CONTROL_CONF_MCASP0_AHCLKX_CONF_MCASP0_AHCLKX_MMODE (0x00000007u)
+#define CONTROL_CONF_MCASP0_AHCLKX_CONF_MCASP0_AHCLKX_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_MCASP0_AHCLKX_CONF_MCASP0_AHCLKX_PUDEN (0x00000008u)
+#define CONTROL_CONF_MCASP0_AHCLKX_CONF_MCASP0_AHCLKX_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_MCASP0_AHCLKX_CONF_MCASP0_AHCLKX_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_MCASP0_AHCLKX_CONF_MCASP0_AHCLKX_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_MCASP0_AHCLKX_CONF_MCASP0_AHCLKX_RSVD (0x000FFF80u)
+#define CONTROL_CONF_MCASP0_AHCLKX_CONF_MCASP0_AHCLKX_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_MCASP0_AHCLKX_CONF_MCASP0_AHCLKX_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_MCASP0_AHCLKX_CONF_MCASP0_AHCLKX_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_MCASP0_AHCLKX_CONF_MCASP0_AHCLKX_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_MCASP0_AHCLKX_CONF_MCASP0_AHCLKX_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_XDMA_EVENT_INTR0 */
+#define CONTROL_CONF_XDMA_EVENT_INTR0_CONF_XDMA_EVENT_INTR0_MMODE (0x00000007u)
+#define CONTROL_CONF_XDMA_EVENT_INTR0_CONF_XDMA_EVENT_INTR0_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_XDMA_EVENT_INTR0_CONF_XDMA_EVENT_INTR0_PUDEN (0x00000008u)
+#define CONTROL_CONF_XDMA_EVENT_INTR0_CONF_XDMA_EVENT_INTR0_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_XDMA_EVENT_INTR0_CONF_XDMA_EVENT_INTR0_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_XDMA_EVENT_INTR0_CONF_XDMA_EVENT_INTR0_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_XDMA_EVENT_INTR0_CONF_XDMA_EVENT_INTR0_RSVD (0x000FFF80u)
+#define CONTROL_CONF_XDMA_EVENT_INTR0_CONF_XDMA_EVENT_INTR0_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_XDMA_EVENT_INTR0_CONF_XDMA_EVENT_INTR0_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_XDMA_EVENT_INTR0_CONF_XDMA_EVENT_INTR0_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_XDMA_EVENT_INTR0_CONF_XDMA_EVENT_INTR0_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_XDMA_EVENT_INTR0_CONF_XDMA_EVENT_INTR0_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_XDMA_EVENT_INTR1 */
+#define CONTROL_CONF_XDMA_EVENT_INTR1_CONF_XDMA_EVENT_INTR1_MMODE (0x00000007u)
+#define CONTROL_CONF_XDMA_EVENT_INTR1_CONF_XDMA_EVENT_INTR1_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_XDMA_EVENT_INTR1_CONF_XDMA_EVENT_INTR1_PUDEN (0x00000008u)
+#define CONTROL_CONF_XDMA_EVENT_INTR1_CONF_XDMA_EVENT_INTR1_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_XDMA_EVENT_INTR1_CONF_XDMA_EVENT_INTR1_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_XDMA_EVENT_INTR1_CONF_XDMA_EVENT_INTR1_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_XDMA_EVENT_INTR1_CONF_XDMA_EVENT_INTR1_RSVD (0x000FFF80u)
+#define CONTROL_CONF_XDMA_EVENT_INTR1_CONF_XDMA_EVENT_INTR1_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_XDMA_EVENT_INTR1_CONF_XDMA_EVENT_INTR1_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_XDMA_EVENT_INTR1_CONF_XDMA_EVENT_INTR1_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_XDMA_EVENT_INTR1_CONF_XDMA_EVENT_INTR1_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_XDMA_EVENT_INTR1_CONF_XDMA_EVENT_INTR1_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_NRESETIN_OUT */
+#define CONTROL_CONF_NRESETIN_OUT_CONF_NRESETIN_OUT_MMODE (0x00000007u)
+#define CONTROL_CONF_NRESETIN_OUT_CONF_NRESETIN_OUT_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_NRESETIN_OUT_CONF_NRESETIN_OUT_PUDEN (0x00000008u)
+#define CONTROL_CONF_NRESETIN_OUT_CONF_NRESETIN_OUT_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_NRESETIN_OUT_CONF_NRESETIN_OUT_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_NRESETIN_OUT_CONF_NRESETIN_OUT_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_NRESETIN_OUT_CONF_NRESETIN_OUT_RSVD (0x000FFF80u)
+#define CONTROL_CONF_NRESETIN_OUT_CONF_NRESETIN_OUT_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_NRESETIN_OUT_CONF_NRESETIN_OUT_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_NRESETIN_OUT_CONF_NRESETIN_OUT_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_NRESETIN_OUT_CONF_NRESETIN_OUT_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_NRESETIN_OUT_CONF_NRESETIN_OUT_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_PORZ */
+#define CONTROL_CONF_PORZ_CONF_PORZ_MMODE (0x00000007u)
+#define CONTROL_CONF_PORZ_CONF_PORZ_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_PORZ_CONF_PORZ_PUDEN (0x00000008u)
+#define CONTROL_CONF_PORZ_CONF_PORZ_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_PORZ_CONF_PORZ_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_PORZ_CONF_PORZ_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_PORZ_CONF_PORZ_RSVD (0x000FFF80u)
+#define CONTROL_CONF_PORZ_CONF_PORZ_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_PORZ_CONF_PORZ_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_PORZ_CONF_PORZ_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_PORZ_CONF_PORZ_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_PORZ_CONF_PORZ_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_NNMI */
+#define CONTROL_CONF_NNMI_CONF_NNMI_MMODE (0x00000007u)
+#define CONTROL_CONF_NNMI_CONF_NNMI_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_NNMI_CONF_NNMI_PUDEN (0x00000008u)
+#define CONTROL_CONF_NNMI_CONF_NNMI_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_NNMI_CONF_NNMI_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_NNMI_CONF_NNMI_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_NNMI_CONF_NNMI_RSVD (0x000FFF80u)
+#define CONTROL_CONF_NNMI_CONF_NNMI_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_NNMI_CONF_NNMI_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_NNMI_CONF_NNMI_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_NNMI_CONF_NNMI_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_NNMI_CONF_NNMI_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_OSC0_IN */
+#define CONTROL_CONF_OSC0_IN_CONF_OSC0_IN_MMODE (0x00000007u)
+#define CONTROL_CONF_OSC0_IN_CONF_OSC0_IN_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_OSC0_IN_CONF_OSC0_IN_PUDEN (0x00000008u)
+#define CONTROL_CONF_OSC0_IN_CONF_OSC0_IN_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_OSC0_IN_CONF_OSC0_IN_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_OSC0_IN_CONF_OSC0_IN_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_OSC0_IN_CONF_OSC0_IN_RSVD (0x000FFF80u)
+#define CONTROL_CONF_OSC0_IN_CONF_OSC0_IN_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_OSC0_IN_CONF_OSC0_IN_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_OSC0_IN_CONF_OSC0_IN_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_OSC0_IN_CONF_OSC0_IN_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_OSC0_IN_CONF_OSC0_IN_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_OSC0_OUT */
+#define CONTROL_CONF_OSC0_OUT_CONF_OSC0_OUT_MMODE (0x00000007u)
+#define CONTROL_CONF_OSC0_OUT_CONF_OSC0_OUT_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_OSC0_OUT_CONF_OSC0_OUT_PUDEN (0x00000008u)
+#define CONTROL_CONF_OSC0_OUT_CONF_OSC0_OUT_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_OSC0_OUT_CONF_OSC0_OUT_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_OSC0_OUT_CONF_OSC0_OUT_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_OSC0_OUT_CONF_OSC0_OUT_RSVD (0x000FFF80u)
+#define CONTROL_CONF_OSC0_OUT_CONF_OSC0_OUT_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_OSC0_OUT_CONF_OSC0_OUT_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_OSC0_OUT_CONF_OSC0_OUT_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_OSC0_OUT_CONF_OSC0_OUT_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_OSC0_OUT_CONF_OSC0_OUT_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_OSC0_VSS */
+#define CONTROL_CONF_OSC0_VSS_CONF_OSC0_VSS_MMODE (0x00000007u)
+#define CONTROL_CONF_OSC0_VSS_CONF_OSC0_VSS_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_OSC0_VSS_CONF_OSC0_VSS_PUDEN (0x00000008u)
+#define CONTROL_CONF_OSC0_VSS_CONF_OSC0_VSS_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_OSC0_VSS_CONF_OSC0_VSS_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_OSC0_VSS_CONF_OSC0_VSS_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_OSC0_VSS_CONF_OSC0_VSS_RSVD (0x000FFF80u)
+#define CONTROL_CONF_OSC0_VSS_CONF_OSC0_VSS_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_OSC0_VSS_CONF_OSC0_VSS_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_OSC0_VSS_CONF_OSC0_VSS_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_OSC0_VSS_CONF_OSC0_VSS_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_OSC0_VSS_CONF_OSC0_VSS_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_TMS */
+#define CONTROL_CONF_TMS_CONF_TMS_MMODE (0x00000007u)
+#define CONTROL_CONF_TMS_CONF_TMS_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_TMS_CONF_TMS_PUDEN (0x00000008u)
+#define CONTROL_CONF_TMS_CONF_TMS_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_TMS_CONF_TMS_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_TMS_CONF_TMS_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_TMS_CONF_TMS_RSVD (0x000FFF80u)
+#define CONTROL_CONF_TMS_CONF_TMS_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_TMS_CONF_TMS_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_TMS_CONF_TMS_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_TMS_CONF_TMS_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_TMS_CONF_TMS_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_TDI */
+#define CONTROL_CONF_TDI_CONF_TDI_MMODE (0x00000007u)
+#define CONTROL_CONF_TDI_CONF_TDI_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_TDI_CONF_TDI_PUDEN (0x00000008u)
+#define CONTROL_CONF_TDI_CONF_TDI_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_TDI_CONF_TDI_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_TDI_CONF_TDI_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_TDI_CONF_TDI_RSVD (0x000FFF80u)
+#define CONTROL_CONF_TDI_CONF_TDI_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_TDI_CONF_TDI_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_TDI_CONF_TDI_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_TDI_CONF_TDI_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_TDI_CONF_TDI_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_TDO */
+#define CONTROL_CONF_TDO_CONF_TDO_MMODE (0x00000007u)
+#define CONTROL_CONF_TDO_CONF_TDO_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_TDO_CONF_TDO_PUDEN (0x00000008u)
+#define CONTROL_CONF_TDO_CONF_TDO_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_TDO_CONF_TDO_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_TDO_CONF_TDO_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_TDO_CONF_TDO_RSVD (0x000FFF80u)
+#define CONTROL_CONF_TDO_CONF_TDO_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_TDO_CONF_TDO_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_TDO_CONF_TDO_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_TDO_CONF_TDO_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_TDO_CONF_TDO_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_TCK */
+#define CONTROL_CONF_TCK_CONF_TCK_MMODE (0x00000007u)
+#define CONTROL_CONF_TCK_CONF_TCK_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_TCK_CONF_TCK_PUDEN (0x00000008u)
+#define CONTROL_CONF_TCK_CONF_TCK_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_TCK_CONF_TCK_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_TCK_CONF_TCK_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_TCK_CONF_TCK_RSVD (0x000FFF80u)
+#define CONTROL_CONF_TCK_CONF_TCK_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_TCK_CONF_TCK_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_TCK_CONF_TCK_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_TCK_CONF_TCK_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_TCK_CONF_TCK_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_NTRST */
+#define CONTROL_CONF_NTRST_CONF_NTRST_MMODE (0x00000007u)
+#define CONTROL_CONF_NTRST_CONF_NTRST_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_NTRST_CONF_NTRST_PUDEN (0x00000008u)
+#define CONTROL_CONF_NTRST_CONF_NTRST_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_NTRST_CONF_NTRST_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_NTRST_CONF_NTRST_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_NTRST_CONF_NTRST_RSVD (0x000FFF80u)
+#define CONTROL_CONF_NTRST_CONF_NTRST_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_NTRST_CONF_NTRST_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_NTRST_CONF_NTRST_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_NTRST_CONF_NTRST_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_NTRST_CONF_NTRST_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_EMU0 */
+#define CONTROL_CONF_EMU0_CONF_EMU0_MMODE (0x00000007u)
+#define CONTROL_CONF_EMU0_CONF_EMU0_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_EMU0_CONF_EMU0_PUDEN (0x00000008u)
+#define CONTROL_CONF_EMU0_CONF_EMU0_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_EMU0_CONF_EMU0_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_EMU0_CONF_EMU0_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_EMU0_CONF_EMU0_RSVD (0x000FFF80u)
+#define CONTROL_CONF_EMU0_CONF_EMU0_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_EMU0_CONF_EMU0_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_EMU0_CONF_EMU0_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_EMU0_CONF_EMU0_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_EMU0_CONF_EMU0_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_EMU1 */
+#define CONTROL_CONF_EMU1_CONF_EMU1_MMODE (0x00000007u)
+#define CONTROL_CONF_EMU1_CONF_EMU1_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_EMU1_CONF_EMU1_PUDEN (0x00000008u)
+#define CONTROL_CONF_EMU1_CONF_EMU1_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_EMU1_CONF_EMU1_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_EMU1_CONF_EMU1_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_EMU1_CONF_EMU1_RSVD (0x000FFF80u)
+#define CONTROL_CONF_EMU1_CONF_EMU1_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_EMU1_CONF_EMU1_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_EMU1_CONF_EMU1_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_EMU1_CONF_EMU1_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_EMU1_CONF_EMU1_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_OSC1_IN */
+#define CONTROL_CONF_OSC1_IN_CONF_OSC1_IN_MMODE (0x00000007u)
+#define CONTROL_CONF_OSC1_IN_CONF_OSC1_IN_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_OSC1_IN_CONF_OSC1_IN_PUDEN (0x00000008u)
+#define CONTROL_CONF_OSC1_IN_CONF_OSC1_IN_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_OSC1_IN_CONF_OSC1_IN_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_OSC1_IN_CONF_OSC1_IN_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_OSC1_IN_CONF_OSC1_IN_RSVD (0x000FFF80u)
+#define CONTROL_CONF_OSC1_IN_CONF_OSC1_IN_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_OSC1_IN_CONF_OSC1_IN_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_OSC1_IN_CONF_OSC1_IN_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_OSC1_IN_CONF_OSC1_IN_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_OSC1_IN_CONF_OSC1_IN_SLEWCTRL_SHIFT (0x00000006u)
+
+
+/* CONF_OSC1_OUT */
+#define CONTROL_CONF_OSC1_OUT_CONF_OSC1_OUT_MMODE (0x00000007u)
+#define CONTROL_CONF_OSC1_OUT_CONF_OSC1_OUT_MMODE_SHIFT (0x00000000u)
+
+#define CONTROL_CONF_OSC1_OUT_CONF_OSC1_OUT_PUDEN (0x00000008u)
+#define CONTROL_CONF_OSC1_OUT_CONF_OSC1_OUT_PUDEN_SHIFT (0x00000003u)
+
+#define CONTROL_CONF_OSC1_OUT_CONF_OSC1_OUT_PUTYPESEL (0x00000010u)
+#define CONTROL_CONF_OSC1_OUT_CONF_OSC1_OUT_PUTYPESEL_SHIFT (0x00000004u)
+
+#define CONTROL_CONF_OSC1_OUT_CONF_OSC1_OUT_RSVD (0x000FFF80u)
+#define CONTROL_CONF_OSC1_OUT_CONF_OSC1_OUT_RSVD_SHIFT (0x00000007u)
+
+#define CONTROL_CONF_OSC1_OUT_CONF_OSC1_OUT_RXACTIVE (0x00000020u)
+#define CONTROL_CONF_OSC1_OUT_CONF_OSC1_OUT_RXACTIVE_SHIFT (0x00000005u)
+
+#define CONTROL_CONF_OSC1_OUT_CONF_OSC1_OUT_SLEWCTRL (0x00000040u)
+#define CONTROL_CONF_OSC1_OUT_CONF_OSC1_OUT_SLEWCTRL_SHIFT (0x00000006u)
+
+