2010-12-17 Joel Sherrill <joel.sherrill@oarcorp.com>

		Jennifer Averett <jennifer.averett@oarcorp.com>

	Add RTEMS Scheduler Simulator.  This is the RTEMS "port" to and
	adapter code to run on GNU/Linux with a fake context switch.
	* ChangeLog, Makefile.am, interr.c, rtems_init.c, rtems_sched.h,
	wkspace.c, sched_cpu/cpu.c, sched_cpu/cpu_asm.c,
	sched_cpu/rtems/asm.h, sched_cpu/rtems/stringto.h,
	sched_cpu/rtems/score/cpu.h, sched_cpu/rtems/score/cpu_asm.h,
	sched_cpu/rtems/score/cpuopts.h, sched_cpu/rtems/score/no_cpu.h,
	sched_cpu/rtems/score/types.h: New files.

15 files changed, 2708 insertions, 0 deletions

diff --git a/tools/schedsim/rtems/ChangeLog b/tools/schedsim/rtems/ChangeLog
new file mode 100644
index 0000000000..cfd266cb5c
--- /dev/null
+++ b/tools/schedsim/rtems/ChangeLog
@@ -0,0 +1,12 @@
+2010-12-17	Joel Sherrill <joel.sherrill@oarcorp.com>
+		Jennifer Averett <jennifer.averett@oarcorp.com>
+
+	Add RTEMS Scheduler Simulator.  This is the RTEMS "port" to and
+	adapter code to run on GNU/Linux with a fake context switch.
+	* ChangeLog, Makefile.am, interr.c, rtems_init.c, rtems_sched.h,
+	wkspace.c, sched_cpu/cpu.c, sched_cpu/cpu_asm.c,
+	sched_cpu/rtems/asm.h, sched_cpu/rtems/stringto.h,
+	sched_cpu/rtems/score/cpu.h, sched_cpu/rtems/score/cpu_asm.h,
+	sched_cpu/rtems/score/cpuopts.h, sched_cpu/rtems/score/no_cpu.h,
+	sched_cpu/rtems/score/types.h: New files.
+
diff --git a/tools/schedsim/rtems/Makefile.am b/tools/schedsim/rtems/Makefile.am
new file mode 100644
index 0000000000..681563876d
--- /dev/null
+++ b/tools/schedsim/rtems/Makefile.am
@@ -0,0 +1,382 @@
+##
+##  $Id$
+##
+
+ACLOCAL_AMFLAGS = -I ../../../aclocal
+
+lib_LIBRARIES = librtems.a
+
+cpukitdir=$(srcdir)/../../../cpukit
+librtems_a_CPPFLAGS  = -D__RTEMS_VIOLATE_KERNEL_VISIBILITY__
+librtems_a_CPPFLAGS += -I$(srcdir)/sched_cpu
+librtems_a_CPPFLAGS += -I$(cpukitdir)/include
+librtems_a_CPPFLAGS += -I$(cpukitdir)/score/include
+librtems_a_CPPFLAGS += -I$(cpukitdir)/score/inline
+librtems_a_CPPFLAGS += -I$(cpukitdir)/rtems/include
+librtems_a_CPPFLAGS += -I$(cpukitdir)/rtems/inline
+librtems_a_CPPFLAGS += -I$(cpukitdir)/sapi/include
+librtems_a_CPPFLAGS += -I$(cpukitdir)/sapi/inline
+librtems_a_CPPFLAGS += -I$(cpukitdir)/libcsupport/include
+librtems_a_CPPFLAGS += -I$(cpukitdir)/libmisc/stringto
+
+## Have own version of these
+librtems_a_SOURCES = rtems_init.c wkspace.c
+librtems_a_SOURCES += sched_cpu/cpu_asm.c
+librtems_a_SOURCES += sched_cpu/cpu.c
+
+## CPUKIT/SCORE/SRC
+librtems_a_SOURCES += $(cpukitdir)/score/src/interr.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/percpu.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/apiext.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/apimutexallocate.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/apimutex.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/apimutexlock.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/apimutexunlock.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/chainappend.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/chain.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/chainextract.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/chainget.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/chaininsert.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/coremutex.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/coremutexflush.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/coremutexseize.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/coremutexseizeintr.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/coremutexsurrender.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/coresem.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/coresemflush.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/coresemseize.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/coresemsurrender.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/coretod.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/coretodget.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/coretodgetuptime.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/coretodgetuptimetimespec.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/coretodmsecstoticks.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/coretodset.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/coretodtickle.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/coretodtickspersec.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/coretodusectoticks.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/objectallocate.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/objectapimaximumclass.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/objectclose.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/objectextendinformation.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/objectfree.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/objectget.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/objectgetinfo.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/objectgetinfoid.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/objectgetisr.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/objectgetnameasstring.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/objectgetnext.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/objectgetnoprotection.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/objectidtoname.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/objectinitializeinformation.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/objectnamespaceremove.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/objectnametoid.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/objectnametoidstring.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/objectsetname.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/objectshrinkinformation.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/scheduler.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/schedulerpriority.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/schedulerpriorityblock.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/schedulerprioritythreadschedulerallocate.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/schedulerprioritythreadschedulerfree.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/schedulerprioritythreadschedulerupdate.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/schedulerpriorityschedule.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/schedulerpriorityunblock.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/schedulerpriorityyield.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/thread.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threadchangepriority.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threadclearstate.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threadclose.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threadcreateidle.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threaddelayended.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threaddispatch.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threadget.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threadhandler.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threadinitialize.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threadloadenv.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threadready.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threadreset.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threadrestart.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threadresume.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threadsetpriority.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threadsetstate.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threadsettransient.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threadstackallocate.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threadstackfree.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threadstart.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threadstartmultitasking.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threadsuspend.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threadtickletimeslice.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/iterateoverthreads.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threadq.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threadblockingoperationcancel.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threadqdequeue.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threadqdequeuefifo.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threadqdequeuepriority.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threadqenqueue.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threadqenqueuefifo.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threadqenqueuepriority.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threadqextract.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threadqextractfifo.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threadqextractpriority.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threadqextractwithproxy.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threadqfirst.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threadqfirstfifo.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threadqfirstpriority.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threadqflush.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threadqprocesstimeout.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threadqrequeue.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/threadqtimeout.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/timespecaddto.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/timespecdividebyinteger.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/timespecdivide.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/timespecfromticks.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/timespecgreaterthan.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/timespecisvalid.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/timespeclessthan.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/timespecsubtract.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/timespectoticks.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/userextaddset.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/userext.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/userextremoveset.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/userextthreadbegin.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/userextthreadcreate.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/userextthreaddelete.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/userextthreadrestart.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/userextthreadstart.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/userextthreadswitch.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/watchdogadjust.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/watchdogadjusttochain.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/watchdog.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/watchdoginsert.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/watchdognanoseconds.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/watchdogremove.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/watchdogreport.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/watchdogreportchain.c
+librtems_a_SOURCES += $(cpukitdir)/score/src/watchdogtickle.c
+librtems_a_SOURCES += $(cpukitdir)/sapi/src/debug.c
+librtems_a_SOURCES += $(cpukitdir)/rtems/src/clockgetsecondssinceepoch.c
+librtems_a_SOURCES += $(cpukitdir)/rtems/src/clockgettickspersecond.c
+librtems_a_SOURCES += $(cpukitdir)/rtems/src/clockgettickssinceboot.c
+librtems_a_SOURCES += $(cpukitdir)/rtems/src/clockgettod.c
+librtems_a_SOURCES += $(cpukitdir)/rtems/src/clockgettodtimeval.c
+librtems_a_SOURCES += $(cpukitdir)/rtems/src/clockgetuptime.c
+librtems_a_SOURCES += $(cpukitdir)/rtems/src/clockset.c
+librtems_a_SOURCES += $(cpukitdir)/rtems/src/clocksetnsecshandler.c
+librtems_a_SOURCES += $(cpukitdir)/rtems/src/clocktick.c
+librtems_a_SOURCES += $(cpukitdir)/rtems/src/clocktodtoseconds.c
+librtems_a_SOURCES += $(cpukitdir)/rtems/src/clocktodvalidate.c
+librtems_a_SOURCES += $(cpukitdir)/rtems/src/sem.c
+librtems_a_SOURCES += $(cpukitdir)/rtems/src/semcreate.c
+librtems_a_SOURCES += $(cpukitdir)/rtems/src/semdata.c
+librtems_a_SOURCES += $(cpukitdir)/rtems/src/semdelete.c
+librtems_a_SOURCES += $(cpukitdir)/rtems/src/semflush.c
+librtems_a_SOURCES += $(cpukitdir)/rtems/src/semident.c
+librtems_a_SOURCES += $(cpukitdir)/rtems/src/semobtain.c
+librtems_a_SOURCES += $(cpukitdir)/rtems/src/semrelease.c
+librtems_a_SOURCES += $(cpukitdir)/rtems/src/semtranslatereturncode.c
+librtems_a_SOURCES += $(cpukitdir)/rtems/src/tasks.c
+librtems_a_SOURCES += $(cpukitdir)/rtems/src/taskdata.c
+librtems_a_SOURCES += $(cpukitdir)/rtems/src/taskmode.c
+librtems_a_SOURCES += $(cpukitdir)/rtems/src/taskvariable_invoke_dtor.c
+librtems_a_SOURCES += $(cpukitdir)/rtems/src/taskcreate.c
+librtems_a_SOURCES += $(cpukitdir)/rtems/src/taskstart.c
+librtems_a_SOURCES += $(cpukitdir)/rtems/src/taskident.c
+librtems_a_SOURCES += $(cpukitdir)/rtems/src/taskdelete.c
+librtems_a_SOURCES += $(cpukitdir)/rtems/src/taskresume.c
+librtems_a_SOURCES += $(cpukitdir)/rtems/src/tasksuspend.c
+librtems_a_SOURCES += $(cpukitdir)/rtems/src/tasksetpriority.c
+librtems_a_SOURCES += $(cpukitdir)/rtems/src/taskmode.c
+librtems_a_SOURCES += $(cpukitdir)/rtems/src/taskwakeafter.c
+librtems_a_SOURCES += $(cpukitdir)/libcsupport/src/assoclocalbyname.c
+librtems_a_SOURCES += $(cpukitdir)/libcsupport/src/assoclocalbyremotebitfield.c
+librtems_a_SOURCES += $(cpukitdir)/libcsupport/src/assoclocalbyremote.c
+librtems_a_SOURCES += $(cpukitdir)/libcsupport/src/assocnamebad.c
+librtems_a_SOURCES += $(cpukitdir)/libcsupport/src/assocnamebylocalbitfield.c
+librtems_a_SOURCES += $(cpukitdir)/libcsupport/src/assocnamebylocal.c
+librtems_a_SOURCES += $(cpukitdir)/libcsupport/src/assocnamebyremotebitfield.c
+librtems_a_SOURCES += $(cpukitdir)/libcsupport/src/assocnamebyremote.c
+librtems_a_SOURCES += $(cpukitdir)/libcsupport/src/assocptrbylocal.c
+librtems_a_SOURCES += $(cpukitdir)/libcsupport/src/assocptrbyname.c
+librtems_a_SOURCES += $(cpukitdir)/libcsupport/src/assocptrbyremote.c
+librtems_a_SOURCES += $(cpukitdir)/libcsupport/src/assocremotebylocalbitfield.c
+librtems_a_SOURCES += $(cpukitdir)/libcsupport/src/assocremotebylocal.c
+librtems_a_SOURCES += $(cpukitdir)/libcsupport/src/assocremotebyname.c
+librtems_a_SOURCES += $(cpukitdir)/libcsupport/src/error.c
+librtems_a_SOURCES += $(cpukitdir)/libmisc/stringto/stringtodouble.c
+librtems_a_SOURCES += $(cpukitdir)/libmisc/stringto/stringtofloat.c
+librtems_a_SOURCES += $(cpukitdir)/libmisc/stringto/stringtoint.c
+librtems_a_SOURCES += $(cpukitdir)/libmisc/stringto/stringtolong.c
+librtems_a_SOURCES += $(cpukitdir)/libmisc/stringto/stringtopointer.c
+librtems_a_SOURCES += $(cpukitdir)/libmisc/stringto/stringtounsignedchar.c
+librtems_a_SOURCES += $(cpukitdir)/libmisc/stringto/stringtounsignedint.c
+librtems_a_SOURCES += $(cpukitdir)/libmisc/stringto/stringtounsignedlong.c
+
+schedsim_includedir = $(includedir)/schedsim
+schedsim_rtems_includedir = $(includedir)/schedsim/rtems
+schedsim_rtems_score_includedir = $(includedir)/schedsim/rtems/score
+schedsim_rtems_rtems_includedir = $(includedir)/schedsim/rtems/rtems
+
+schedsim_include_HEADERS  = \
+ ${cpukitdir}/rtems/include/rtems.h
+
+schedsim_rtems_include_HEADERS  = \
+  ${cpukitdir}/score/include//rtems/seterr.h \
+  ${cpukitdir}/score/include/rtems/system.h \
+  ${cpukitdir}/score/include/rtems/debug.h \
+  ${cpukitdir}/include/rtems/bspIo.h \
+  $(cpukitdir)/sapi/include/rtems/fatal.h \
+  $(cpukitdir)/sapi/include/rtems/init.h \
+  $(cpukitdir)/sapi/include/rtems/config.h \
+  $(cpukitdir)/sapi/include/rtems/sptables.h \
+  $(cpukitdir)/sapi/include/rtems/io.h \
+  $(cpukitdir)/sapi/include/rtems/mptables.h \
+  $(cpukitdir)/sapi/include/rtems/extension.h \
+  $(cpukitdir)/sapi/include/rtems/chain.h \
+  $(cpukitdir)/sapi/include/confdefs.h \
+  $(cpukitdir)/libcsupport/include/rtems/libio_.h \
+  $(cpukitdir)/libcsupport/include/rtems/watchdogdrv.h \
+  $(cpukitdir)/libcsupport/include/rtems/error.h \
+  $(cpukitdir)/libcsupport/include/rtems/framebuffer.h \
+  $(cpukitdir)/libcsupport/include/rtems/assoc.h \
+  $(cpukitdir)/libcsupport/include/rtems/libio.h \
+  $(cpukitdir)/libcsupport/include/rtems/gxx_wrappers.h \
+  $(cpukitdir)/libcsupport/include/rtems/libcsupport.h \
+  $(cpukitdir)/libcsupport/include/rtems/termiostypes.h \
+  $(cpukitdir)/libcsupport/include/rtems/malloc.h \
+  sched_cpu/rtems/stringto.h \
+  sched_cpu/rtems/asm.h 
+
+schedsim_rtems_score_include_HEADERS = \
+  ${cpukitdir}/score/include/rtems/score/address.h \
+  ${cpukitdir}/score/include/rtems/score/coremutex.h \
+  ${cpukitdir}/score/include/rtems/score/corerwlock.h \
+  ${cpukitdir}/score/include/rtems/score/threadsync.h \
+  ${cpukitdir}/score/include/rtems/score/priority.h \
+  ${cpukitdir}/score/include/rtems/score/sysstate.h \
+  ${cpukitdir}/score/include/rtems/score/threadmp.h \
+  ${cpukitdir}/score/include/rtems/score/mppkt.h \
+  ${cpukitdir}/score/include/rtems/score/stack.h \
+  ${cpukitdir}/score/include/rtems/score/context.h \
+  ${cpukitdir}/score/include/rtems/score/heap.h \
+  ${cpukitdir}/score/include/rtems/score/coresem.h \
+  ${cpukitdir}/score/include/rtems/score/corebarrier.h \
+  ${cpukitdir}/score/include/rtems/score/corespinlock.h \
+  ${cpukitdir}/score/include/rtems/score/prioritybitmap.h \
+  ${cpukitdir}/score/include/rtems/score/timestamp.h \
+  ${cpukitdir}/score/include/rtems/score/basedefs.h \
+  ${cpukitdir}/score/include/rtems/score/wkspace.h \
+  ${cpukitdir}/score/include/rtems/score/percpu.h \
+  ${cpukitdir}/score/include/rtems/score/watchdog.h \
+  ${cpukitdir}/score/include/rtems/score/tod.h \
+  ${cpukitdir}/score/include/rtems/score/protectedheap.h \
+  ${cpukitdir}/score/include/rtems/score/timestamp64.h \
+  ${cpukitdir}/score/include/rtems/score/chain.h \
+  ${cpukitdir}/score/include/rtems/score/apiext.h \
+  ${cpukitdir}/score/include/rtems/score/userext.h \
+  ${cpukitdir}/score/include/rtems/score/threadq.h \
+  ${cpukitdir}/score/include/rtems/score/apimutex.h \
+  ${cpukitdir}/score/include/rtems/score/scheduler.h \
+  ${cpukitdir}/score/include/rtems/score/isr.h \
+  ${cpukitdir}/score/include/rtems/score/mpci.h \
+  ${cpukitdir}/score/include/rtems/score/object.h \
+  ${cpukitdir}/score/include/rtems/score/copyrt.h \
+  ${cpukitdir}/score/include/rtems/score/states.h \
+  ${cpukitdir}/score/include/rtems/score/objectmp.h \
+  ${cpukitdir}/score/include/rtems/score/thread.h \
+  ${cpukitdir}/score/include/rtems/score/coremsg.h \
+  ${cpukitdir}/score/include/rtems/score/schedulerpriority.h \
+  ${cpukitdir}/score/include/rtems/score/timespec.h \
+  ${cpukitdir}/score/include/rtems/score/tqdata.h \
+  ${cpukitdir}/score/include/rtems/score/bitfield.h \
+  ${cpukitdir}/score/include/rtems/score/interr.h \
+  $(cpukitdir)/score/inline/rtems/score/address.inl \
+  $(cpukitdir)/score/inline/rtems/score/corespinlock.inl \
+  $(cpukitdir)/score/inline/rtems/score/priority.inl \
+  $(cpukitdir)/score/inline/rtems/score/threadmp.inl \
+  $(cpukitdir)/score/inline/rtems/score/chain.inl \
+  $(cpukitdir)/score/inline/rtems/score/heap.inl \
+  $(cpukitdir)/score/inline/rtems/score/scheduler.inl \
+  $(cpukitdir)/score/inline/rtems/score/threadq.inl \
+  $(cpukitdir)/score/inline/rtems/score/corebarrier.inl \
+  $(cpukitdir)/score/inline/rtems/score/isr.inl \
+  $(cpukitdir)/score/inline/rtems/score/schedulerpriority.inl \
+  $(cpukitdir)/score/inline/rtems/score/tod.inl \
+  $(cpukitdir)/score/inline/rtems/score/coremsg.inl \
+  $(cpukitdir)/score/inline/rtems/score/mppkt.inl \
+  $(cpukitdir)/score/inline/rtems/score/stack.inl \
+  $(cpukitdir)/score/inline/rtems/score/tqdata.inl \
+  $(cpukitdir)/score/inline/rtems/score/coremutex.inl \
+  $(cpukitdir)/score/inline/rtems/score/object.inl \
+  $(cpukitdir)/score/inline/rtems/score/states.inl \
+  $(cpukitdir)/score/inline/rtems/score/watchdog.inl \
+  $(cpukitdir)/score/inline/rtems/score/corerwlock.inl \
+  $(cpukitdir)/score/inline/rtems/score/objectmp.inl \
+  $(cpukitdir)/score/inline/rtems/score/sysstate.inl \
+  $(cpukitdir)/score/inline/rtems/score/wkspace.inl \
+  $(cpukitdir)/score/inline/rtems/score/coresem.inl \
+  $(cpukitdir)/score/inline/rtems/score/prioritybitmap.inl \
+  $(cpukitdir)/score/inline/rtems/score/thread.inl \
+  sched_cpu/rtems/score/cpu_asm.h \
+  sched_cpu/rtems/score/cpuopts.h \
+  sched_cpu/rtems/score/cpu.h \
+  sched_cpu/rtems/score/types.h \
+  sched_cpu/rtems/score/no_cpu.h 
+
+
+schedsim_rtems_rtems_include_HEADERS = \
+  ${cpukitdir}/rtems/include/rtems/rtems/event.h \
+  ${cpukitdir}/rtems/include/rtems/rtems/cache.h \
+  ${cpukitdir}/rtems/include/rtems/rtems/timer.h \
+  ${cpukitdir}/rtems/include/rtems/rtems/regionmp.h \
+  ${cpukitdir}/rtems/include/rtems/rtems/config.h \
+  ${cpukitdir}/rtems/include/rtems/rtems/ratemon.h \
+  ${cpukitdir}/rtems/include/rtems/rtems/rtemsapi.h \
+  ${cpukitdir}/rtems/include/rtems/rtems/eventset.h \
+  ${cpukitdir}/rtems/include/rtems/rtems/mp.h \
+  ${cpukitdir}/rtems/include/rtems/rtems/dpmem.h \
+  ${cpukitdir}/rtems/include/rtems/rtems/status.h \
+  ${cpukitdir}/rtems/include/rtems/rtems/sem.h \
+  ${cpukitdir}/rtems/include/rtems/rtems/barriermp.h \
+  ${cpukitdir}/rtems/include/rtems/rtems/types.h \
+  ${cpukitdir}/rtems/include/rtems/rtems/intr.h \
+  ${cpukitdir}/rtems/include/rtems/rtems/signalmp.h \
+  ${cpukitdir}/rtems/include/rtems/rtems/eventmp.h \
+  ${cpukitdir}/rtems/include/rtems/rtems/part.h \
+  ${cpukitdir}/rtems/include/rtems/rtems/message.h \
+  ${cpukitdir}/rtems/include/rtems/rtems/region.h \
+  ${cpukitdir}/rtems/include/rtems/rtems/object.h \
+  ${cpukitdir}/rtems/include/rtems/rtems/partmp.h \
+  ${cpukitdir}/rtems/include/rtems/rtems/msgmp.h \
+  ${cpukitdir}/rtems/include/rtems/rtems/clock.h \
+  ${cpukitdir}/rtems/include/rtems/rtems/modes.h \
+  ${cpukitdir}/rtems/include/rtems/rtems/taskmp.h \
+  ${cpukitdir}/rtems/include/rtems/rtems/asr.h \
+  ${cpukitdir}/rtems/include/rtems/rtems/semmp.h \
+  ${cpukitdir}/rtems/include/rtems/rtems/options.h \
+  ${cpukitdir}/rtems/include/rtems/rtems/attr.h \
+  ${cpukitdir}/rtems/include/rtems/rtems/support.h \
+  ${cpukitdir}/rtems/include/rtems/rtems/signal.h \
+  ${cpukitdir}/rtems/include/rtems/rtems/barrier.h \
+  ${cpukitdir}/rtems/include/rtems/rtems/tasks.h \
+  $(cpukitdir)/rtems/inline/rtems/rtems/asr.inl  \
+  $(cpukitdir)/rtems/inline/rtems/rtems/eventset.inl \
+  $(cpukitdir)/rtems/inline/rtems/rtems/ratemon.inl \
+  $(cpukitdir)/rtems/inline/rtems/rtems/tasks.inl \
+  $(cpukitdir)/rtems/inline/rtems/rtems/attr.inl \
+  $(cpukitdir)/rtems/inline/rtems/rtems/message.inl \
+  $(cpukitdir)/rtems/inline/rtems/rtems/region.inl \
+  $(cpukitdir)/rtems/inline/rtems/rtems/timer.inl \
+  $(cpukitdir)/rtems/inline/rtems/rtems/barrier.inl \
+  $(cpukitdir)/rtems/inline/rtems/rtems/modes.inl \
+  $(cpukitdir)/rtems/inline/rtems/rtems/sem.inl \
+  $(cpukitdir)/rtems/inline/rtems/rtems/dpmem.inl \
+  $(cpukitdir)/rtems/inline/rtems/rtems/options.inl \
+  $(cpukitdir)/rtems/inline/rtems/rtems/status.inl \
+  $(cpukitdir)/rtems/inline/rtems/rtems/event.inl \
+  $(cpukitdir)/rtems/inline/rtems/rtems/part.inl \
+  $(cpukitdir)/rtems/inline/rtems/rtems/support.inl
+
+schedsim_include_HEADERS += rtems_sched.h
+
+include $(top_srcdir)/../../automake/host.am
diff --git a/tools/schedsim/rtems/interr.c b/tools/schedsim/rtems/interr.c
new file mode 100644
index 0000000000..b708f41df6
--- /dev/null
+++ b/tools/schedsim/rtems/interr.c
@@ -0,0 +1,71 @@
+/*
+ *  BASED UPON SOURCE IN RTEMS, MODIFIED FOR SIMULATOR
+ *
+ *  Internal Error Handler
+ *
+ *  COPYRIGHT (c) 1989-2010.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  $Id$
+ */
+
+#if HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <rtems/system.h>
+#include <rtems/score/interr.h>
+#include <rtems/score/sysstate.h>
+#include <rtems/score/userext.h>
+
+#include <stdlib.h>
+#include <stdio.h>
+
+/*PAGE
+ *
+ *  _Internal_error_Occurred
+ *
+ *  This routine will invoke the fatal error handler supplied by the user
+ *  followed by the the default one provided by the executive.  The default
+ *  error handler assumes no hardware is present to help inform the user
+ *  of the problem.  Halt stores the error code in a known register,
+ *  disables interrupts, and halts the CPU.  If the CPU does not have a
+ *  halt instruction, it will loop to itself.
+ *
+ *  Input parameters:
+ *    the_source  - what subsystem the error originated in
+ *    is_internal - if the error was internally generated
+ *    the_error   - fatal error status code
+ *
+ *  Output parameters:
+ *    As much information as possible is stored in a CPU dependent fashion.
+ *    See the CPU dependent code for more information.
+ *
+ *  NOTE: The the_error is not necessarily a directive status code.
+ */
+
+void _Internal_error_Occurred(
+  Internal_errors_Source  the_source,
+  bool                    is_internal,
+  Internal_errors_t       the_error
+)
+{
+
+  _Internal_errors_What_happened.the_source  = the_source;
+  _Internal_errors_What_happened.is_internal = is_internal;
+  _Internal_errors_What_happened.the_error   = the_error;
+
+  // _User_extensions_Fatal( the_source, is_internal, the_error );
+
+  _System_state_Set( SYSTEM_STATE_FAILED );
+
+  fprintf( stderr, "FATAL ERROR!!\n" );
+  exit( -1 );
+
+  /* will not return from this routine */
+  while (true);
+}
diff --git a/tools/schedsim/rtems/rtems_init.c b/tools/schedsim/rtems/rtems_init.c
new file mode 100644
index 0000000000..1e6a5b6893
--- /dev/null
+++ b/tools/schedsim/rtems/rtems_init.c
@@ -0,0 +1,110 @@
+/*
+ *  BASED UPON SOURCE IN RTEMS, MODIFIED FOR SIMULATOR
+ *
+ *  COPYRIGHT (c) 1989-2010.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  $Id$
+ */
+
+
+#define SAPI_INIT
+#define SCORE_INIT
+#define RTEMS_API_INIT
+
+#include <rtems.h> 
+#include <rtems/score/apiext.h>
+#include <rtems/score/bitfield.h>
+#include <rtems/score/apimutex.h>
+#include <rtems/score/wkspace.h>
+
+Objects_Information *_Internal_Objects[ OBJECTS_INTERNAL_CLASSES_LAST + 1 ];
+
+Objects_Information *_RTEMS_Objects[ OBJECTS_RTEMS_CLASSES_LAST + 1 ];
+
+extern void check_heir_and_executing(void);
+
+void rtems_initialize_data_structures(void)
+{
+  _System_state_Handler_initialization( FALSE );
+
+  /*
+   *  Do this as early as possible to ensure no debugging output
+   *  is even attempted to be printed.
+   */
+  _Debug_Manager_initialization();
+
+  _API_extensions_Initialization();
+
+  _Thread_Dispatch_initialization();
+
+  /*
+   *  Before this is called, we are not allowed to allocate memory
+   *  from the Workspace because it is not initialized.
+   */
+  _Workspace_Handler_initialization();
+
+  _User_extensions_Handler_initialization();
+
+  // _ISR_Handler_initialization();
+
+  /*
+   * Initialize the internal support API and allocator Mutex
+   */
+  _Objects_Information_table[OBJECTS_INTERNAL_API] = _Internal_Objects;
+
+  _API_Mutex_Initialization( 1 );
+  _API_Mutex_Allocate( &_RTEMS_Allocator_Mutex );
+
+  _Priority_bit_map_Handler_initialization();
+  _Watchdog_Handler_initialization();
+  _TOD_Handler_initialization();
+
+  _Thread_Handler_initialization();
+
+  _Scheduler_Handler_initialization();
+
+
+/* MANAGERS */
+  /*
+   * Install our API Object Management Table and initialize the
+   * various managers.
+   */
+  _Objects_Information_table[OBJECTS_CLASSIC_API] = _RTEMS_Objects;
+
+  _RTEMS_tasks_Manager_initialization();
+  _Semaphore_Manager_initialization();
+
+  _System_state_Set( SYSTEM_STATE_BEFORE_MULTITASKING );
+
+  /*
+   *  No threads should be created before this point!!!
+   *  _Thread_Executing and _Thread_Heir are not set.
+   *
+   *  At this point all API extensions are in place.  After the call to
+   *  _Thread_Create_idle() _Thread_Executing and _Thread_Heir will be set.
+   */
+  _Thread_Create_idle();
+
+  /*
+   *  Scheduling can properly occur now as long as we avoid dispatching.
+   */
+
+  _System_state_Set( SYSTEM_STATE_BEGIN_MULTITASKING );
+
+  _Thread_Start_multitasking();
+
+  /*
+   *  Now we are back in a non-dispatching critical section
+   */
+  _Thread_Dispatch_disable_level = 0;
+
+  /*
+   * Print an initial message
+   */
+  check_heir_and_executing();
+}
diff --git a/tools/schedsim/rtems/rtems_sched.h b/tools/schedsim/rtems/rtems_sched.h
new file mode 100644
index 0000000000..f399f0c1fb
--- /dev/null
+++ b/tools/schedsim/rtems/rtems_sched.h
@@ -0,0 +1,27 @@
+/*
+ *  RTEMS Scheduler Simulator Interface
+ *
+ *  COPYRIGHT (c) 1989-2010.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  $Id$
+ */
+
+#ifndef __RTEMS_SCHEDULER_SIMULATOR_h
+#define __RTEMS_SCHEDULER_SIMULATOR_h
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void rtems_initialize_data_structures(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tools/schedsim/rtems/sched_cpu/cpu.c b/tools/schedsim/rtems/sched_cpu/cpu.c
new file mode 100644
index 0000000000..0d2e6f6206
--- /dev/null
+++ b/tools/schedsim/rtems/sched_cpu/cpu.c
@@ -0,0 +1,169 @@
+/*
+ *  XXX CPU Dependent Source
+ *
+ *  BASED UPON SOURCE IN RTEMS, MODIFIED FOR SIMULATOR
+ *
+ *  COPYRIGHT (c) 1989-2010.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  $Id$
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <rtems/system.h>
+#include <rtems/score/isr.h>
+#include <rtems/score/wkspace.h>
+
+/*  _CPU_Initialize
+ *
+ *  This routine performs processor dependent initialization.
+ *
+ *  INPUT PARAMETERS: NONE
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+
+void _CPU_Initialize(void)
+{
+  /*
+   *  If there is not an easy way to initialize the FP context
+   *  during Context_Initialize, then it is usually easier to
+   *  save an "uninitialized" FP context here and copy it to
+   *  the task's during Context_Initialize.
+   */
+
+  /* FP context initialization support goes here */
+}
+
+/*PAGE
+ *
+ *  _CPU_ISR_Get_level
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+
+uint32_t   _CPU_ISR_Get_level( void )
+{
+  /*
+   *  This routine returns the current interrupt level.
+   */
+
+  return 0;
+}
+
+/*PAGE
+ *
+ *  _CPU_ISR_install_raw_handler
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+
+void _CPU_ISR_install_raw_handler(
+  uint32_t    vector,
+  proc_ptr    new_handler,
+  proc_ptr   *old_handler
+)
+{
+  /*
+   *  This is where we install the interrupt handler into the "raw" interrupt
+   *  table used by the CPU to dispatch interrupt handlers.
+   */
+}
+
+/*PAGE
+ *
+ *  _CPU_ISR_install_vector
+ *
+ *  This kernel routine installs the RTEMS handler for the
+ *  specified vector.
+ *
+ *  Input parameters:
+ *    vector      - interrupt vector number
+ *    old_handler - former ISR for this vector number
+ *    new_handler - replacement ISR for this vector number
+ *
+ *  Output parameters:  NONE
+ *
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+
+void _CPU_ISR_install_vector(
+  uint32_t    vector,
+  proc_ptr    new_handler,
+  proc_ptr   *old_handler
+)
+{
+   *old_handler = _ISR_Vector_table[ vector ];
+
+   /*
+    *  If the interrupt vector table is a table of pointer to isr entry
+    *  points, then we need to install the appropriate RTEMS interrupt
+    *  handler for this vector number.
+    */
+
+   _CPU_ISR_install_raw_handler( vector, new_handler, old_handler );
+
+   /*
+    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
+    *  be used by the _ISR_Handler so the user gets control.
+    */
+
+    _ISR_Vector_table[ vector ] = new_handler;
+}
+
+/*PAGE
+ *
+ *  _CPU_Install_interrupt_stack
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+
+void _CPU_Install_interrupt_stack( void )
+{
+}
+
+/*PAGE
+ *
+ *  _CPU_Thread_Idle_body
+ *
+ *  NOTES:
+ *
+ *  1. This is the same as the regular CPU independent algorithm.
+ *
+ *  2. If you implement this using a "halt", "idle", or "shutdown"
+ *     instruction, then don't forget to put it in an infinite loop.
+ *
+ *  3. Be warned. Some processors with onboard DMA have been known
+ *     to stop the DMA if the CPU were put in IDLE mode.  This might
+ *     also be a problem with other on-chip peripherals.  So use this
+ *     hook with caution.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+
+void *_CPU_Thread_Idle_body( uintptr_t ignored )
+{
+
+  for( ; ; )
+    /* insert your "halt" instruction here */ ;
+}
diff --git a/tools/schedsim/rtems/sched_cpu/cpu_asm.c b/tools/schedsim/rtems/sched_cpu/cpu_asm.c
new file mode 100644
index 0000000000..e31c980a25
--- /dev/null
+++ b/tools/schedsim/rtems/sched_cpu/cpu_asm.c
@@ -0,0 +1,188 @@
+/*  cpu_asm.c  ===> cpu_asm.S or cpu_asm.s
+ *  BASED UPON SOURCE IN RTEMS, MODIFIED FOR SIMULATOR
+ *
+ *
+ *  This file contains the basic algorithms for all assembly code used
+ *  in an specific CPU port of RTEMS.  These algorithms must be implemented
+ *  in assembly language
+ *
+ *  NOTE:  This is supposed to be a .S or .s file NOT a C file.
+ *
+ *  COPYRIGHT (c) 1989-2010.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  $Id$
+ */
+
+/*
+ *  This is supposed to be an assembly file.  This means that system.h
+ *  and cpu.h should not be included in a "real" cpu_asm file.  An
+ *  implementation in assembly should include "cpu_asm.h>
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <rtems/system.h>
+#include <rtems/score/cpu.h>
+/* #include "cpu_asm.h> */
+
+/*
+ *  _CPU_Context_save_fp_context
+ *
+ *  This routine is responsible for saving the FP context
+ *  at *fp_context_ptr.  If the point to load the FP context
+ *  from is changed then the pointer is modified by this routine.
+ *
+ *  Sometimes a macro implementation of this is in cpu.h which dereferences
+ *  the ** and a similarly named routine in this file is passed something
+ *  like a (Context_Control_fp *).  The general rule on making this decision
+ *  is to avoid writing assembly language.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+
+void _CPU_Context_save_fp(
+  Context_Control_fp **fp_context_ptr
+)
+{
+}
+
+/*
+ *  _CPU_Context_restore_fp_context
+ *
+ *  This routine is responsible for restoring the FP context
+ *  at *fp_context_ptr.  If the point to load the FP context
+ *  from is changed then the pointer is modified by this routine.
+ *
+ *  Sometimes a macro implementation of this is in cpu.h which dereferences
+ *  the ** and a similarly named routine in this file is passed something
+ *  like a (Context_Control_fp *).  The general rule on making this decision
+ *  is to avoid writing assembly language.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+
+void _CPU_Context_restore_fp(
+  Context_Control_fp **fp_context_ptr
+)
+{
+}
+
+/*  _CPU_Context_switch
+ *
+ *  This routine performs a normal non-FP context switch.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+
+void _CPU_Context_switch(
+  Context_Control  *run,
+  Context_Control  *heir
+)
+{
+}
+
+/*
+ *  _CPU_Context_restore
+ *
+ *  This routine is generally used only to restart self in an
+ *  efficient manner.  It may simply be a label in _CPU_Context_switch.
+ *
+ *  NOTE: May be unnecessary to reload some registers.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+
+void _CPU_Context_restore(
+  Context_Control *new_context
+)
+{
+}
+
+/*  void __ISR_Handler()
+ *
+ *  This routine provides the RTEMS interrupt management.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+
+void _ISR_Handler(void)
+{
+   /*
+    *  This discussion ignores a lot of the ugly details in a real
+    *  implementation such as saving enough registers/state to be
+    *  able to do something real.  Keep in mind that the goal is
+    *  to invoke a user's ISR handler which is written in C and
+    *  uses a certain set of registers.
+    *
+    *  Also note that the exact order is to a large extent flexible.
+    *  Hardware will dictate a sequence for a certain subset of
+    *  _ISR_Handler while requirements for setting
+    */
+
+  /*
+   *  At entry to "common" _ISR_Handler, the vector number must be
+   *  available.  On some CPUs the hardware puts either the vector
+   *  number or the offset into the vector table for this ISR in a
+   *  known place.  If the hardware does not give us this information,
+   *  then the assembly portion of RTEMS for this port will contain
+   *  a set of distinct interrupt entry points which somehow place
+   *  the vector number in a known place (which is safe if another
+   *  interrupt nests this one) and branches to _ISR_Handler.
+   *
+   *  save some or all context on stack
+   *  may need to save some special interrupt information for exit
+   *
+   *  #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
+   *    if ( _ISR_Nest_level == 0 )
+   *      switch to software interrupt stack
+   *  #endif
+   *
+   *  _ISR_Nest_level++;
+   *
+   *  _Thread_Dispatch_disable_level++;
+   *
+   *  (*_ISR_Vector_table[ vector ])( vector );
+   *
+   *  _Thread_Dispatch_disable_level--;
+   *
+   *  --_ISR_Nest_level;
+   *
+   *  if ( _ISR_Nest_level )
+   *    goto the label "exit interrupt (simple case)"
+   *
+   *  if ( _Thread_Dispatch_disable_level )
+   *    _ISR_Signals_to_thread_executing = FALSE;
+   *    goto the label "exit interrupt (simple case)"
+   *
+   *  if ( _Context_Switch_necessary || _ISR_Signals_to_thread_executing ) {
+   *    _ISR_Signals_to_thread_executing = FALSE;
+   *    call _Thread_Dispatch() or prepare to return to _ISR_Dispatch
+   *    prepare to get out of interrupt
+   *    return from interrupt  (maybe to _ISR_Dispatch)
+   *
+   *  LABEL "exit interrupt (simple case):
+   *  #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
+   *    if outermost interrupt
+   *      restore stack
+   *  #endif
+   *  prepare to get out of interrupt
+   *  return from interrupt
+   */
+}
diff --git a/tools/schedsim/rtems/sched_cpu/rtems/asm.h b/tools/schedsim/rtems/sched_cpu/rtems/asm.h
new file mode 100644
index 0000000000..8ad1d57032
--- /dev/null
+++ b/tools/schedsim/rtems/sched_cpu/rtems/asm.h
@@ -0,0 +1,127 @@
+/**
+ * @file rtems/asm.h
+ *
+ *  BASED UPON SOURCE IN RTEMS, MODIFIED FOR SIMULATOR
+ *
+ *  This include file attempts to address the problems
+ *  caused by incompatible flavors of assemblers and
+ *  toolsets.  It primarily addresses variations in the
+ *  use of leading underscores on symbols and the requirement
+ *  that register names be preceded by a %.
+ */
+
+/*
+ *  NOTE: The spacing in the use of these macros
+ *        is critical to them working as advertised.
+ *
+ *  COPYRIGHT:
+ *
+ *  This file is based on similar code found in newlib available
+ *  from ftp.cygnus.com.  The file which was used had no copyright
+ *  notice.  This file is freely distributable as long as the source
+ *  of the file is noted.  This file is:
+ *
+ *  COPYRIGHT (c) 1994-2010.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  $Id$
+ */
+
+#ifndef _RTEMS_ASM_H
+#define _RTEMS_ASM_H
+
+/*
+ *  Indicate we are in an assembly file and get the basic CPU definitions.
+ */
+
+#ifndef ASM
+#define ASM
+#endif
+#include <rtems/score/cpuopts.h>
+#include <rtems/score/no_cpu.h>
+
+#ifndef __USER_LABEL_PREFIX__
+/**
+ *  Recent versions of GNU cpp define variables which indicate the
+ *  need for underscores and percents.  If not using GNU cpp or
+ *  the version does not support this, then you will obviously
+ *  have to define these as appropriate.
+ *
+ *  This symbol is prefixed to all C program symbols.
+ */
+#define __USER_LABEL_PREFIX__ _
+#endif
+
+#ifndef __REGISTER_PREFIX__
+/**
+ *  Recent versions of GNU cpp define variables which indicate the
+ *  need for underscores and percents.  If not using GNU cpp or
+ *  the version does not support this, then you will obviously
+ *  have to define these as appropriate.
+ *
+ *  This symbol is prefixed to all register names.
+ */
+#define __REGISTER_PREFIX__
+#endif
+
+#include <rtems/concat.h>
+
+/** Use the right prefix for global labels.  */
+#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
+
+/** Use the right prefix for registers.  */
+#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
+
+/*
+ *  define macros for all of the registers on this CPU
+ *
+ *  EXAMPLE:     #define d0 REG (d0)
+ */
+
+/*
+ *  Define macros to handle section beginning and ends.
+ */
+
+
+/** This macro is used to denote the beginning of a code declaration. */
+#define BEGIN_CODE_DCL .text
+/** This macro is used to denote the end of a code declaration. */
+#define END_CODE_DCL
+/** This macro is used to denote the beginning of a data declaration section. */
+#define BEGIN_DATA_DCL .data
+/** This macro is used to denote the end of a data declaration section. */
+#define END_DATA_DCL
+/** This macro is used to denote the beginning of a code section. */
+#define BEGIN_CODE .text
+/** This macro is used to denote the end of a code section. */
+#define END_CODE
+/** This macro is used to denote the beginning of a data section. */
+#define BEGIN_DATA
+/** This macro is used to denote the end of a data section. */
+#define END_DATA
+/** This macro is used to denote the beginning of the
+ *  unitialized data section.
+ */
+#define BEGIN_BSS
+/** This macro is used to denote the end of the unitialized data section.  */
+#define END_BSS
+/** This macro is used to denote the end of the assembly file.  */
+#define END
+
+/**
+ *  This macro is used to declare a public global symbol.
+ *
+ *  @note This must be tailored for a particular flavor of the C compiler.
+ *  They may need to put underscores in front of the symbols.
+ */
+#define PUBLIC(sym) .globl SYM (sym)
+
+/**
+ *  This macro is used to prototype a public global symbol.
+ *
+ *  @note This must be tailored for a particular flavor of the C compiler.
+ *  They may need to put underscores in front of the symbols.
+ */
+#define EXTERN(sym) .globl SYM (sym)
+
+#endif
diff --git a/tools/schedsim/rtems/sched_cpu/rtems/score/cpu.h b/tools/schedsim/rtems/sched_cpu/rtems/score/cpu.h
new file mode 100644
index 0000000000..7e206fd883
--- /dev/null
+++ b/tools/schedsim/rtems/sched_cpu/rtems/score/cpu.h
@@ -0,0 +1,1264 @@
+/**
+ * @file rtems/score/cpu.h
+ */
+
+/*
+ *  BASED UPON SOURCE IN RTEMS, MODIFIED FOR SIMULATOR
+ *
+ *  This include file contains information pertaining to the XXX
+ *  processor.
+ *
+ *  @note This file is part of a porting template that is intended
+ *  to be used as the starting point when porting RTEMS to a new
+ *  CPU family.  The following needs to be done when using this as
+ *  the starting point for a new port:
+ *
+ *  + Anywhere there is an XXX, it should be replaced
+ *    with information about the CPU family being ported to.
+ *
+ *  + At the end of each comment section, there is a heading which
+ *    says "Port Specific Information:".  When porting to RTEMS,
+ *    add CPU family specific information in this section
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2010.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  $Id$
+ */
+
+#ifndef _RTEMS_SCORE_CPU_H
+#define _RTEMS_SCORE_CPU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rtems/score/no_cpu.h>            /* pick up machine definitions */
+#ifndef ASM
+#include <rtems/score/types.h>
+#endif
+
+/* conditional compilation parameters */
+
+/**
+ *  Should the calls to @ref _Thread_Enable_dispatch be inlined?
+ *
+ *  If TRUE, then they are inlined.
+ *  If FALSE, then a subroutine call is made.
+ *
+ *  This conditional is an example of the classic trade-off of size
+ *  versus speed.  Inlining the call (TRUE) typically increases the
+ *  size of RTEMS while speeding up the enabling of dispatching.
+ *
+ *  @note In general, the @ref _Thread_Dispatch_disable_level will
+ *  only be 0 or 1 unless you are in an interrupt handler and that
+ *  interrupt handler invokes the executive.]  When not inlined
+ *  something calls @ref _Thread_Enable_dispatch which in turns calls
+ *  @ref _Thread_Dispatch.  If the enable dispatch is inlined, then
+ *  one subroutine call is avoided entirely.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_INLINE_ENABLE_DISPATCH       TRUE
+
+/**
+ *  Should the body of the search loops in _Thread_queue_Enqueue_priority
+ *  be unrolled one time?  In unrolled each iteration of the loop examines
+ *  two "nodes" on the chain being searched.  Otherwise, only one node
+ *  is examined per iteration.
+ *
+ *  If TRUE, then the loops are unrolled.
+ *  If FALSE, then the loops are not unrolled.
+ *
+ *  The primary factor in making this decision is the cost of disabling
+ *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
+ *  body of the loop.  On some CPUs, the flash is more expensive than
+ *  one iteration of the loop body.  In this case, it might be desirable
+ *  to unroll the loop.  It is important to note that on some CPUs, this
+ *  code is the longest interrupt disable period in RTEMS.  So it is
+ *  necessary to strike a balance when setting this parameter.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
+
+/**
+ *  Does RTEMS manage a dedicated interrupt stack in software?
+ *
+ *  If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
+ *  If FALSE, nothing is done.
+ *
+ *  If the CPU supports a dedicated interrupt stack in hardware,
+ *  then it is generally the responsibility of the BSP to allocate it
+ *  and set it up.
+ *
+ *  If the CPU does not support a dedicated interrupt stack, then
+ *  the porter has two options: (1) execute interrupts on the
+ *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
+ *  interrupt stack.
+ *
+ *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
+ *
+ *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
+ *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
+ *  possible that both are FALSE for a particular CPU.  Although it
+ *  is unclear what that would imply about the interrupt processing
+ *  procedure on that CPU.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
+
+/**
+ *  Does the CPU follow the simple vectored interrupt model?
+ *
+ *  If TRUE, then RTEMS allocates the vector table it internally manages.
+ *  If FALSE, then the BSP is assumed to allocate and manage the vector
+ *  table
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
+
+/**
+ *  Does this CPU have hardware support for a dedicated interrupt stack?
+ *
+ *  If TRUE, then it must be installed during initialization.
+ *  If FALSE, then no installation is performed.
+ *
+ *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
+ *
+ *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
+ *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
+ *  possible that both are FALSE for a particular CPU.  Although it
+ *  is unclear what that would imply about the interrupt processing
+ *  procedure on that CPU.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
+
+/**
+ *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
+ *
+ *  If TRUE, then the memory is allocated during initialization.
+ *  If FALSE, then the memory is allocated during initialization.
+ *
+ *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
+
+/**
+ *  Does the RTEMS invoke the user's ISR with the vector number and
+ *  a pointer to the saved interrupt frame (1) or just the vector
+ *  number (0)?
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_ISR_PASSES_FRAME_POINTER 0
+
+/**
+ *  @def CPU_HARDWARE_FP
+ *
+ *  Does the CPU have hardware floating point?
+ *
+ *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
+ *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
+ *
+ *  If there is a FP coprocessor such as the i387 or mc68881, then
+ *  the answer is TRUE.
+ *
+ *  The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
+ *  It indicates whether or not this CPU model has FP support.  For
+ *  example, it would be possible to have an i386_nofp CPU model
+ *  which set this to false to indicate that you have an i386 without
+ *  an i387 and wish to leave floating point support out of RTEMS.
+ */
+
+/**
+ *  @def CPU_SOFTWARE_FP
+ *
+ *  Does the CPU have no hardware floating point and GCC provides a
+ *  software floating point implementation which must be context
+ *  switched?
+ *
+ *  This feature conditional is used to indicate whether or not there
+ *  is software implemented floating point that must be context
+ *  switched.  The determination of whether or not this applies
+ *  is very tool specific and the state saved/restored is also
+ *  compiler specific.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#if ( NO_CPU_HAS_FPU == 1 )
+#define CPU_HARDWARE_FP     TRUE
+#else
+#define CPU_HARDWARE_FP     FALSE
+#endif
+#define CPU_SOFTWARE_FP     FALSE
+
+/**
+ *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
+ *
+ *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
+ *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
+ *
+ *  So far, the only CPUs in which this option has been used are the
+ *  HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
+ *  gcc both implicitly used the floating point registers to perform
+ *  integer multiplies.  Similarly, the PowerPC port of gcc has been
+ *  seen to allocate floating point local variables and touch the FPU
+ *  even when the flow through a subroutine (like vfprintf()) might
+ *  not use floating point formats.
+ *
+ *  If a function which you would not think utilize the FP unit DOES,
+ *  then one can not easily predict which tasks will use the FP hardware.
+ *  In this case, this option should be TRUE.
+ *
+ *  If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_ALL_TASKS_ARE_FP     TRUE
+
+/**
+ *  Should the IDLE task have a floating point context?
+ *
+ *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
+ *  and it has a floating point context which is switched in and out.
+ *  If FALSE, then the IDLE task does not have a floating point context.
+ *
+ *  Setting this to TRUE negatively impacts the time required to preempt
+ *  the IDLE task from an interrupt because the floating point context
+ *  must be saved as part of the preemption.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_IDLE_TASK_IS_FP      FALSE
+
+/**
+ *  Should the saving of the floating point registers be deferred
+ *  until a context switch is made to another different floating point
+ *  task?
+ *
+ *  If TRUE, then the floating point context will not be stored until
+ *  necessary.  It will remain in the floating point registers and not
+ *  disturned until another floating point task is switched to.
+ *
+ *  If FALSE, then the floating point context is saved when a floating
+ *  point task is switched out and restored when the next floating point
+ *  task is restored.  The state of the floating point registers between
+ *  those two operations is not specified.
+ *
+ *  If the floating point context does NOT have to be saved as part of
+ *  interrupt dispatching, then it should be safe to set this to TRUE.
+ *
+ *  Setting this flag to TRUE results in using a different algorithm
+ *  for deciding when to save and restore the floating point context.
+ *  The deferred FP switch algorithm minimizes the number of times
+ *  the FP context is saved and restored.  The FP context is not saved
+ *  until a context switch is made to another, different FP task.
+ *  Thus in a system with only one FP task, the FP context will never
+ *  be saved or restored.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
+
+/**
+ *  Does this port provide a CPU dependent IDLE task implementation?
+ *
+ *  If TRUE, then the routine @ref _CPU_Thread_Idle_body
+ *  must be provided and is the default IDLE thread body instead of
+ *  @ref _CPU_Thread_Idle_body.
+ *
+ *  If FALSE, then use the generic IDLE thread body if the BSP does
+ *  not provide one.
+ *
+ *  This is intended to allow for supporting processors which have
+ *  a low power or idle mode.  When the IDLE thread is executed, then
+ *  the CPU can be powered down.
+ *
+ *  The order of precedence for selecting the IDLE thread body is:
+ *
+ *    -#  BSP provided
+ *    -#  CPU dependent (if provided)
+ *    -#  generic (if no BSP and no CPU dependent)
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
+
+/**
+ *  Does the stack grow up (toward higher addresses) or down
+ *  (toward lower addresses)?
+ *
+ *  If TRUE, then the grows upward.
+ *  If FALSE, then the grows toward smaller addresses.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_STACK_GROWS_UP               TRUE
+
+/**
+ *  The following is the variable attribute used to force alignment
+ *  of critical RTEMS structures.  On some processors it may make
+ *  sense to have these aligned on tighter boundaries than
+ *  the minimum requirements of the compiler in order to have as
+ *  much of the critical data area as possible in a cache line.
+ *
+ *  The placement of this macro in the declaration of the variables
+ *  is based on the syntactically requirements of the GNU C
+ *  "__attribute__" extension.  For example with GNU C, use
+ *  the following to force a structures to a 32 byte boundary.
+ *
+ *      __attribute__ ((aligned (32)))
+ *
+ *  @note Currently only the Priority Bit Map table uses this feature.
+ *        To benefit from using this, the data must be heavily
+ *        used so it will stay in the cache and used frequently enough
+ *        in the executive to justify turning this on.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_STRUCTURE_ALIGNMENT
+
+/**
+ *  @defgroup CPUEndian Processor Dependent Endianness Support
+ *
+ *  This group assists in issues related to processor endianness.
+ */
+
+/**
+ *  @ingroup CPUEndian
+ *  Define what is required to specify how the network to host conversion
+ *  routines are handled.
+ *
+ *  @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
+ *  same values.
+ *
+ *  @see CPU_LITTLE_ENDIAN
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_BIG_ENDIAN                           TRUE
+
+/**
+ *  @ingroup CPUEndian
+ *  Define what is required to specify how the network to host conversion
+ *  routines are handled.
+ *
+ *  @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
+ *  same values.
+ *
+ *  @see CPU_BIG_ENDIAN
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_LITTLE_ENDIAN                        FALSE
+
+/**
+ *  @ingroup CPUInterrupt
+ *  The following defines the number of bits actually used in the
+ *  interrupt field of the task mode.  How those bits map to the
+ *  CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_MODES_INTERRUPT_MASK   0x00000001
+
+/*
+ *  Processor defined structures required for cpukit/score.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+
+/* may need to put some structures here.  */
+
+/**
+ * @defgroup CPUContext Processor Dependent Context Management
+ *
+ *  From the highest level viewpoint, there are 2 types of context to save.
+ *
+ *     -# Interrupt registers to save
+ *     -# Task level registers to save
+ *
+ *  Since RTEMS handles integer and floating point contexts separately, this
+ *  means we have the following 3 context items:
+ *
+ *     -# task level context stuff::  Context_Control
+ *     -# floating point task stuff:: Context_Control_fp
+ *     -# special interrupt level context :: CPU_Interrupt_frame
+ *
+ *  On some processors, it is cost-effective to save only the callee
+ *  preserved registers during a task context switch.  This means
+ *  that the ISR code needs to save those registers which do not
+ *  persist across function calls.  It is not mandatory to make this
+ *  distinctions between the caller/callee saves registers for the
+ *  purpose of minimizing context saved during task switch and on interrupts.
+ *  If the cost of saving extra registers is minimal, simplicity is the
+ *  choice.  Save the same context on interrupt entry as for tasks in
+ *  this case.
+ *
+ *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
+ *  care should be used in designing the context area.
+ *
+ *  On some CPUs with hardware floating point support, the Context_Control_fp
+ *  structure will not be used or it simply consist of an array of a
+ *  fixed number of bytes.   This is done when the floating point context
+ *  is dumped by a "FP save context" type instruction and the format
+ *  is not really defined by the CPU.  In this case, there is no need
+ *  to figure out the exact format -- only the size.  Of course, although
+ *  this is enough information for RTEMS, it is probably not enough for
+ *  a debugger such as gdb.  But that is another problem.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+
+/**
+ *  @ingroup CPUContext Management
+ *  This defines the minimal set of integer and processor state registers
+ *  that must be saved during a voluntary context switch from one thread
+ *  to another.
+ */
+typedef struct {
+    /** This field is a hint that a port will have a number of integer
+     *  registers that need to be saved at a context switch.
+     */
+    uint32_t   some_integer_register;
+    /** This field is a hint that a port will have a number of system
+     *  registers that need to be saved at a context switch.
+     */
+    uint32_t   some_system_register;
+
+    /** This field is a hint that a port will have a register that
+     *  is the stack pointer.
+     */
+    uint32_t   stack_pointer;
+} Context_Control;
+
+/**
+ *  @ingroup CPUContext Management
+ *
+ *  This macro returns the stack pointer associated with @a _context.
+ *
+ *  @param[in] _context is the thread context area to access
+ *
+ *  @return This method returns the stack pointer.
+ */
+#define _CPU_Context_Get_SP( _context ) \
+  (_context)->stack_pointer
+
+/**
+ *  @ingroup CPUContext Management
+ *  This defines the complete set of floating point registers that must
+ *  be saved during any context switch from one thread to another.
+ */
+typedef struct {
+    /** FPU registers are listed here */
+    double      some_float_register;
+} Context_Control_fp;
+
+/**
+ *  @ingroup CPUContext Management
+ *  This defines the set of integer and processor state registers that must
+ *  be saved during an interrupt.  This set does not include any which are
+ *  in @ref Context_Control.
+ */
+typedef struct {
+    /** This field is a hint that a port will have a number of integer
+     *  registers that need to be saved when an interrupt occurs or
+     *  when a context switch occurs at the end of an ISR.
+     */
+    uint32_t   special_interrupt_register;
+} CPU_Interrupt_frame;
+
+/**
+ *  This variable is optional.  It is used on CPUs on which it is difficult
+ *  to generate an "uninitialized" FP context.  It is filled in by
+ *  @ref _CPU_Initialize and copied into the task's FP context area during
+ *  @ref _CPU_Context_Initialize.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
+
+/**
+ *  @defgroup CPUInterrupt Processor Dependent Interrupt Management
+ *
+ *  On some CPUs, RTEMS supports a software managed interrupt stack.
+ *  This stack is allocated by the Interrupt Manager and the switch
+ *  is performed in @ref _ISR_Handler.  These variables contain pointers
+ *  to the lowest and highest addresses in the chunk of memory allocated
+ *  for the interrupt stack.  Since it is unknown whether the stack
+ *  grows up or down (in general), this give the CPU dependent
+ *  code the option of picking the version it wants to use.
+ *
+ *  @note These two variables are required if the macro
+ *        @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+
+/**
+ *  @ingroup CPUInterrupt
+ *  This variable points to the lowest physical address of the interrupt
+ *  stack.
+ */
+SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
+
+/**
+ *  @ingroup CPUInterrupt
+ *  This variable points to the lowest physical address of the interrupt
+ *  stack.
+ */
+SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
+
+/*
+ *  Nothing prevents the porter from declaring more CPU specific variables.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+
+/* XXX: if needed, put more variables here */
+
+/**
+ *  @ingroup CPUContext
+ *  The size of the floating point context area.  On some CPUs this
+ *  will not be a "sizeof" because the format of the floating point
+ *  area is not defined -- only the size is.  This is usually on
+ *  CPUs with a "floating point save context" instruction.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
+
+/**
+ *  Amount of extra stack (above minimum stack size) required by
+ *  MPCI receive server thread.  Remember that in a multiprocessor
+ *  system this thread must exist and be able to process all directives.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
+
+/**
+ *  @ingroup CPUInterrupt
+ *  This defines the number of entries in the @ref _ISR_Vector_table managed
+ *  by RTEMS.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
+
+/**
+ *  @ingroup CPUInterrupt
+ *  This defines the highest interrupt vector number for this port.
+ */
+#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
+
+/**
+ *  @ingroup CPUInterrupt
+ *  This is defined if the port has a special way to report the ISR nesting
+ *  level.  Most ports maintain the variable @a _ISR_Nest_level.
+ */
+#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
+
+/**
+ *  @ingroup CPUContext
+ *  Should be large enough to run all RTEMS tests.  This ensures
+ *  that a "reasonable" small application should not have any problems.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_STACK_MINIMUM_SIZE          (1024*4)
+
+/**
+ *  CPU's worst alignment requirement for data types on a byte boundary.  This
+ *  alignment does not take into account the requirements for the stack.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_ALIGNMENT              8
+
+/**
+ *  This number corresponds to the byte alignment requirement for the
+ *  heap handler.  This alignment requirement may be stricter than that
+ *  for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
+ *  common for the heap to follow the same alignment requirement as
+ *  @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
+ *  the heap, then this should be set to @ref CPU_ALIGNMENT.
+ *
+ *  @note  This does not have to be a power of 2 although it should be
+ *         a multiple of 2 greater than or equal to 2.  The requirement
+ *         to be a multiple of 2 is because the heap uses the least
+ *         significant field of the front and back flags to indicate
+ *         that a block is in use or free.  So you do not want any odd
+ *         length blocks really putting length data in that bit.
+ *
+ *         On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
+ *         have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
+ *         elements allocated from the heap meet all restrictions.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
+
+/**
+ *  This number corresponds to the byte alignment requirement for memory
+ *  buffers allocated by the partition manager.  This alignment requirement
+ *  may be stricter than that for the data types alignment specified by
+ *  @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
+ *  alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
+ *  strict enough for the partition, then this should be set to
+ *  @ref CPU_ALIGNMENT.
+ *
+ *  @note  This does not have to be a power of 2.  It does have to
+ *         be greater or equal to than @ref CPU_ALIGNMENT.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
+
+/**
+ *  This number corresponds to the byte alignment requirement for the
+ *  stack.  This alignment requirement may be stricter than that for the
+ *  data types alignment specified by @ref CPU_ALIGNMENT.  If the
+ *  @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
+ *  set to 0.
+ *
+ *  @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_STACK_ALIGNMENT        0
+
+/*
+ *  ISR handler macros
+ */
+
+/**
+ *  @ingroup CPUInterrupt
+ *  Support routine to initialize the RTEMS vector table after it is allocated.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define _CPU_Initialize_vectors()
+
+/**
+ *  @ingroup CPUInterrupt
+ *  Disable all interrupts for an RTEMS critical section.  The previous
+ *  level is returned in @a _isr_cookie.
+ *
+ *  @param[out] _isr_cookie will contain the previous level cookie
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define _CPU_ISR_Disable( _isr_cookie ) \
+  { \
+    (_isr_cookie) = 0;   /* do something to prevent warnings */ \
+  }
+
+/**
+ *  @ingroup CPUInterrupt
+ *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
+ *  This indicates the end of an RTEMS critical section.  The parameter
+ *  @a _isr_cookie is not modified.
+ *
+ *  @param[in] _isr_cookie contain the previous level cookie
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define _CPU_ISR_Enable( _isr_cookie )  \
+  { \
+  }
+
+/**
+ *  @ingroup CPUInterrupt
+ *  This temporarily restores the interrupt to @a _isr_cookie before immediately
+ *  disabling them again.  This is used to divide long RTEMS critical
+ *  sections into two or more parts.  The parameter @a _isr_cookie is not
+ *  modified.
+ *
+ *  @param[in] _isr_cookie contain the previous level cookie
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define _CPU_ISR_Flash( _isr_cookie ) \
+  { \
+  }
+
+/**
+ *  @ingroup CPUInterrupt
+ *
+ *  This routine and @ref _CPU_ISR_Get_level
+ *  Map the interrupt level in task mode onto the hardware that the CPU
+ *  actually provides.  Currently, interrupt levels which do not
+ *  map onto the CPU in a generic fashion are undefined.  Someday,
+ *  it would be nice if these were "mapped" by the application
+ *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
+ *  8 - 255 would be available for bsp/application specific meaning.
+ *  This could be used to manage a programmable interrupt controller
+ *  via the rtems_task_mode directive.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define _CPU_ISR_Set_level( new_level ) \
+  { \
+  }
+
+/**
+ *  @ingroup CPUInterrupt
+ *  Return the current interrupt disable level for this task in
+ *  the format used by the interrupt level portion of the task mode.
+ *
+ *  @note This routine usually must be implemented as a subroutine.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+uint32_t   _CPU_ISR_Get_level( void );
+
+/* end of ISR handler macros */
+
+/* Context handler macros */
+
+/**
+ *  @ingroup CPUContext
+ *  Initialize the context to a state suitable for starting a
+ *  task after a context restore operation.  Generally, this
+ *  involves:
+ *
+ *     - setting a starting address
+ *     - preparing the stack
+ *     - preparing the stack and frame pointers
+ *     - setting the proper interrupt level in the context
+ *     - initializing the floating point context
+ *
+ *  This routine generally does not set any unnecessary register
+ *  in the context.  The state of the "general data" registers is
+ *  undefined at task start time.
+ *
+ *  @param[in] _the_context is the context structure to be initialized
+ *  @param[in] _stack_base is the lowest physical address of this task's stack
+ *  @param[in] _size is the size of this task's stack
+ *  @param[in] _isr is the interrupt disable level
+ *  @param[in] _entry_point is the thread's entry point.  This is
+ *         always @a _Thread_Handler
+ *  @param[in] _is_fp is TRUE if the thread is to be a floating
+ *        point thread.  This is typically only used on CPUs where the
+ *        FPU may be easily disabled by software such as on the SPARC
+ *        where the PSR contains an enable FPU bit.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
+                                 _isr, _entry_point, _is_fp ) \
+  { \
+  }
+
+/**
+ *  This routine is responsible for somehow restarting the currently
+ *  executing task.  If you are lucky, then all that is necessary
+ *  is restoring the context.  Otherwise, there will need to be
+ *  a special assembly routine which does something special in this
+ *  case.  For many ports, simply adding a label to the restore path
+ *  of @ref _CPU_Context_switch will work.  On other ports, it may be
+ *  possibly to load a few arguments and jump to the restore path. It will
+ *  not work if restarting self conflicts with the stack frame
+ *  assumptions of restoring a context.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define _CPU_Context_Restart_self( _the_context ) \
+   _CPU_Context_restore( (_the_context) );
+
+/**
+ *  @ingroup CPUContext
+ *  The purpose of this macro is to allow the initial pointer into
+ *  a floating point context area (used to save the floating point
+ *  context) to be at an arbitrary place in the floating point
+ *  context area.
+ *
+ *  This is necessary because some FP units are designed to have
+ *  their context saved as a stack which grows into lower addresses.
+ *  Other FP units can be saved by simply moving registers into offsets
+ *  from the base of the context area.  Finally some FP units provide
+ *  a "dump context" instruction which could fill in from high to low
+ *  or low to high based on the whim of the CPU designers.
+ *
+ *  @param[in] _base is the lowest physical address of the floating point
+ *         context area
+ *  @param[in] _offset is the offset into the floating point area
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define _CPU_Context_Fp_start( _base, _offset ) \
+   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
+
+/**
+ *  This routine initializes the FP context area passed to it to.
+ *  There are a few standard ways in which to initialize the
+ *  floating point context.  The code included for this macro assumes
+ *  that this is a CPU in which a "initial" FP context was saved into
+ *  @a _CPU_Null_fp_context and it simply copies it to the destination
+ *  context passed to it.
+ *
+ *  Other floating point context save/restore models include:
+ *    -# not doing anything, and
+ *    -# putting a "null FP status word" in the correct place in the FP context.
+ *
+ *  @param[in] _destination is the floating point context area
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define _CPU_Context_Initialize_fp( _destination ) \
+  { \
+   *(*(_destination)) = _CPU_Null_fp_context; \
+  }
+
+/* end of Context handler macros */
+
+/* Fatal Error manager macros */
+
+/**
+ *  This routine copies _error into a known place -- typically a stack
+ *  location or a register, optionally disables interrupts, and
+ *  halts/stops the CPU.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define _CPU_Fatal_halt( _error ) \
+  { \
+  }
+
+/* end of Fatal Error manager macros */
+
+/* Bitfield handler macros */
+
+/**
+ *  @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
+ *
+ *  This set of routines are used to implement fast searches for
+ *  the most important ready task.
+ */
+
+/**
+ *  @ingroup CPUBitfield
+ *  This definition is set to TRUE if the port uses the generic bitfield
+ *  manipulation implementation.
+ */
+#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
+
+/**
+ *  @ingroup CPUBitfield
+ *  This definition is set to TRUE if the port uses the data tables provided
+ *  by the generic bitfield manipulation implementation.
+ *  This can occur when actually using the generic bitfield manipulation
+ *  implementation or when implementing the same algorithm in assembly
+ *  language for improved performance.  It is unlikely that a port will use
+ *  the data if it has a bitfield scan instruction.
+ */
+#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
+
+/**
+ *  @ingroup CPUBitfield
+ *  This routine sets @a _output to the bit number of the first bit
+ *  set in @a _value.  @a _value is of CPU dependent type
+ *  @a Priority_Bit_map_control.  This type may be either 16 or 32 bits
+ *  wide although only the 16 least significant bits will be used.
+ *
+ *  There are a number of variables in using a "find first bit" type
+ *  instruction.
+ *
+ *    -# What happens when run on a value of zero?
+ *    -# Bits may be numbered from MSB to LSB or vice-versa.
+ *    -# The numbering may be zero or one based.
+ *    -# The "find first bit" instruction may search from MSB or LSB.
+ *
+ *  RTEMS guarantees that (1) will never happen so it is not a concern.
+ *  (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
+ *  @ref _CPU_Priority_bits_index.  These three form a set of routines
+ *  which must logically operate together.  Bits in the _value are
+ *  set and cleared based on masks built by @ref _CPU_Priority_Mask.
+ *  The basic major and minor values calculated by @ref _Priority_Major
+ *  and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
+ *  to properly range between the values returned by the "find first bit"
+ *  instruction.  This makes it possible for @ref _Priority_Get_highest to
+ *  calculate the major and directly index into the minor table.
+ *  This mapping is necessary to ensure that 0 (a high priority major/minor)
+ *  is the first bit found.
+ *
+ *  This entire "find first bit" and mapping process depends heavily
+ *  on the manner in which a priority is broken into a major and minor
+ *  components with the major being the 4 MSB of a priority and minor
+ *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
+ *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
+ *  to the lowest priority.
+ *
+ *  If your CPU does not have a "find first bit" instruction, then
+ *  there are ways to make do without it.  Here are a handful of ways
+ *  to implement this in software:
+ *
+@verbatim
+      - a series of 16 bit test instructions
+      - a "binary search using if's"
+      - _number = 0
+        if _value > 0x00ff
+          _value >>=8
+          _number = 8;
+
+        if _value > 0x0000f
+          _value >=8
+          _number += 4
+
+        _number += bit_set_table[ _value ]
+@endverbatim
+
+ *    where bit_set_table[ 16 ] has values which indicate the first
+ *      bit set
+ *
+ *  @param[in] _value is the value to be scanned
+ *  @param[in] _output is the first bit set
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+
+#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
+#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
+  { \
+    (_output) = 0;   /* do something to prevent warnings */ \
+  }
+#endif
+
+/* end of Bitfield handler macros */
+
+/**
+ *  This routine builds the mask which corresponds to the bit fields
+ *  as searched by @ref _CPU_Bitfield_Find_first_bit.  See the discussion
+ *  for that routine.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
+
+#define _CPU_Priority_Mask( _bit_number ) \
+  ( 1 << (_bit_number) )
+
+#endif
+
+/**
+ *  @ingroup CPUBitfield
+ *  This routine translates the bit numbers returned by
+ *  @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
+ *  a major or minor component of a priority.  See the discussion
+ *  for that routine.
+ *
+ *  @param[in] _priority is the major or minor number to translate
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
+
+#define _CPU_Priority_bits_index( _priority ) \
+  (_priority)
+
+#endif
+
+/* end of Priority handler macros */
+
+/* functions */
+
+/**
+ *  This routine performs CPU dependent initialization.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+void _CPU_Initialize(void);
+
+/**
+ *  @ingroup CPUInterrupt
+ *  This routine installs a "raw" interrupt handler directly into the
+ *  processor's vector table.
+ *
+ *  @param[in] vector is the vector number
+ *  @param[in] new_handler is the raw ISR handler to install
+ *  @param[in] old_handler is the previously installed ISR Handler
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+void _CPU_ISR_install_raw_handler(
+  uint32_t    vector,
+  proc_ptr    new_handler,
+  proc_ptr   *old_handler
+);
+
+/**
+ *  @ingroup CPUInterrupt
+ *  This routine installs an interrupt vector.
+ *
+ *  @param[in] vector is the vector number
+ *  @param[in] new_handler is the RTEMS ISR handler to install
+ *  @param[in] old_handler is the previously installed ISR Handler
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+void _CPU_ISR_install_vector(
+  uint32_t    vector,
+  proc_ptr    new_handler,
+  proc_ptr   *old_handler
+);
+
+/**
+ *  @ingroup CPUInterrupt
+ *  This routine installs the hardware interrupt stack pointer.
+ *
+ *  @note  It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
+ *         is TRUE.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+void _CPU_Install_interrupt_stack( void );
+
+/**
+ *  This routine is the CPU dependent IDLE thread body.
+ *
+ *  @note  It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY
+ *         is TRUE.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+void *_CPU_Thread_Idle_body( uintptr_t ignored );
+
+/**
+ *  @ingroup CPUContext
+ *  This routine switches from the run context to the heir context.
+ *
+ *  @param[in] run points to the context of the currently executing task
+ *  @param[in] heir points to the context of the heir task
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+void _CPU_Context_switch(
+  Context_Control  *run,
+  Context_Control  *heir
+);
+
+/**
+ *  @ingroup CPUContext
+ *  This routine is generally used only to restart self in an
+ *  efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
+ *
+ *  @param[in] new_context points to the context to be restored.
+ *
+ *  @note May be unnecessary to reload some registers.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+void _CPU_Context_restore(
+  Context_Control *new_context
+);
+
+/**
+ *  @ingroup CPUContext
+ *  This routine saves the floating point context passed to it.
+ *
+ *  @param[in] fp_context_ptr is a pointer to a pointer to a floating
+ *  point context area
+ *
+ *  @return on output @a *fp_context_ptr will contain the address that
+ *  should be used with @ref _CPU_Context_restore_fp to restore this context.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+void _CPU_Context_save_fp(
+  Context_Control_fp **fp_context_ptr
+);
+
+/**
+ *  @ingroup CPUContext
+ *  This routine restores the floating point context passed to it.
+ *
+ *  @param[in] fp_context_ptr is a pointer to a pointer to a floating
+ *  point context area to restore
+ *
+ *  @return on output @a *fp_context_ptr will contain the address that
+ *  should be used with @ref _CPU_Context_save_fp to save this context.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+void _CPU_Context_restore_fp(
+  Context_Control_fp **fp_context_ptr
+);
+
+/**
+ *  @ingroup CPUEndian
+ *  The following routine swaps the endian format of an unsigned int.
+ *  It must be static because it is referenced indirectly.
+ *
+ *  This version will work on any processor, but if there is a better
+ *  way for your CPU PLEASE use it.  The most common way to do this is to:
+ *
+ *     swap least significant two bytes with 16-bit rotate
+ *     swap upper and lower 16-bits
+ *     swap most significant two bytes with 16-bit rotate
+ *
+ *  Some CPUs have special instructions which swap a 32-bit quantity in
+ *  a single instruction (e.g. i486).  It is probably best to avoid
+ *  an "endian swapping control bit" in the CPU.  One good reason is
+ *  that interrupts would probably have to be disabled to ensure that
+ *  an interrupt does not try to access the same "chunk" with the wrong
+ *  endian.  Another good reason is that on some CPUs, the endian bit
+ *  endianness for ALL fetches -- both code and data -- so the code
+ *  will be fetched incorrectly.
+ *
+ *  @param[in] value is the value to be swapped
+ *  @return the value after being endian swapped
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+static inline uint32_t CPU_swap_u32(
+  uint32_t value
+)
+{
+  uint32_t byte1, byte2, byte3, byte4, swapped;
+
+  byte4 = (value >> 24) & 0xff;
+  byte3 = (value >> 16) & 0xff;
+  byte2 = (value >> 8)  & 0xff;
+  byte1 =  value        & 0xff;
+
+  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
+  return swapped;
+}
+
+/**
+ *  @ingroup CPUEndian
+ *  This routine swaps a 16 bir quantity.
+ *
+ *  @param[in] value is the value to be swapped
+ *  @return the value after being endian swapped
+ */
+#define CPU_swap_u16( value ) \
+  (((value&0xff) << 8) | ((value >> 8)&0xff))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/tools/schedsim/rtems/sched_cpu/rtems/score/cpu_asm.h b/tools/schedsim/rtems/sched_cpu/rtems/score/cpu_asm.h
new file mode 100644
index 0000000000..7c80adbfd8
--- /dev/null
+++ b/tools/schedsim/rtems/sched_cpu/rtems/score/cpu_asm.h
@@ -0,0 +1,74 @@
+/**
+ * @file rtems/score/cpu_asm.h
+ */
+
+/*
+ *  BASED UPON SOURCE IN RTEMS, MODIFIED FOR SIMULATOR
+ *
+ *  Very loose template for an include file for the cpu_asm.? file
+ *  if it is implemented as a ".S" file (preprocessed by cpp) instead
+ *  of a ".s" file (preprocessed by gm4 or gasp).
+ *
+ *  COPYRIGHT (c) 1989-2010.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  $Id$
+ *
+ */
+
+#ifndef _RTEMS_SCORE_CPU_ASM_H
+#define _RTEMS_SCORE_CPU_ASM_H
+
+/* pull in the generated offsets */
+
+#include <rtems/score/offsets.h>
+
+/*
+ * Hardware General Registers
+ */
+
+/* put something here */
+
+/*
+ * Hardware Floating Point Registers
+ */
+
+/* put something here */
+
+/*
+ * Hardware Control Registers
+ */
+
+/* put something here */
+
+/*
+ * Calling Convention
+ */
+
+/* put something here */
+
+/*
+ * Temporary registers
+ */
+
+/* put something here */
+
+/*
+ * Floating Point Registers - SW Conventions
+ */
+
+/* put something here */
+
+/*
+ * Temporary floating point registers
+ */
+
+/* put something here */
+
+#endif
+
+/* end of file */
diff --git a/tools/schedsim/rtems/sched_cpu/rtems/score/cpuopts.h b/tools/schedsim/rtems/sched_cpu/rtems/score/cpuopts.h
new file mode 100644
index 0000000000..61858b369b
--- /dev/null
+++ b/tools/schedsim/rtems/sched_cpu/rtems/score/cpuopts.h
@@ -0,0 +1,72 @@
+/**
+ * @file rtems/score/cpuopts.h
+ */
+
+/*  BASED UPON SOURCE IN RTEMS, MODIFIED FOR SIMULATOR */
+
+/* target cpu dependent options file */
+/* automatically generated -- DO NOT EDIT!! */
+#ifndef _RTEMS_SCORE_CPUOPTS_H
+#define _RTEMS_SCORE_CPUOPTS_H
+
+/* This is added by hand to indicate we are on the RTEMS Scheduler Simulator */
+#define RTEMS_SCHEDSIM
+
+/* if RTEMS_DEBUG is enabled */
+/* #undef RTEMS_DEBUG */
+
+/* if itron api is supported */
+/* #undef RTEMS_ITRON_API */
+
+/* if multiprocessing is enabled */
+/* #undef RTEMS_MULTIPROCESSING */
+
+/* if using newlib */
+#define RTEMS_NEWLIB 1
+
+/* if posix api is supported */
+/* #undef RTEMS_POSIX_API */
+
+/* if networking is enabled */
+#define RTEMS_NETWORKING 1
+
+/* if RTEMS uses tar.h */
+#define RTEMS_USES_TAR_H 1
+
+/* RTEMS version string */
+#define RTEMS_VERSION "4.9.99.0"
+
+/* disable nanosecond granularity for statistics */
+/* #undef __RTEMS_USE_TICKS_FOR_STATISTICS__ */
+
+/* disable nanosecond granularity for cpu usage statistics */
+/* #undef __RTEMS_USE_TICKS_CPU_USAGE_STATISTICS__ */
+
+/* disable nanosecond granularity for period statistics */
+/* #undef __RTEMS_USE_TICKS_RATE_MONOTONIC_STATISTICS__ */
+
+/* disable inlining _Thread_Enable_dispatch */
+/* #undef __RTEMS_DO_NOT_INLINE_THREAD_ENABLE_DISPATCH__ */
+
+/* disable inlining _Thread_Enable_dispatch */
+/* #undef __RTEMS_DO_NOT_INLINE_CORE_MUTEX_SEIZE__ */
+
+/* disable inlining _Thread_queue_Enqueue_priority */
+/* #undef __RTEMS_DO_NOT_UNROLL_THREADQ_ENQUEUE_PRIORITY__ */
+
+/* disable strict order mutex */
+/* #undef __RTEMS_STRICT_ORDER_MUTEX__ */
+
+/* Define to 1 if ada/gnat bindings are built-in */
+#define __RTEMS_ADA__ 1
+
+/* major version portion of an RTEMS release */
+#define __RTEMS_MAJOR__ 4
+
+/* minor version portion of an RTEMS release */
+#define __RTEMS_MINOR__ 9
+
+/* revision version portion of an RTEMS release */
+#define __RTEMS_REVISION__ 99
+
+#endif /* _RTEMS_SCORE_CPUOPTS_H */
diff --git a/tools/schedsim/rtems/sched_cpu/rtems/score/no_cpu.h b/tools/schedsim/rtems/sched_cpu/rtems/score/no_cpu.h
new file mode 100644
index 0000000000..bb0706fd76
--- /dev/null
+++ b/tools/schedsim/rtems/sched_cpu/rtems/score/no_cpu.h
@@ -0,0 +1,59 @@
+/*  no_cpu.h
+ *
+ *  BASED UPON SOURCE IN RTEMS, MODIFIED FOR SIMULATOR
+ *
+ *  This file sets up basic CPU dependency settings based on
+ *  compiler settings.  For example, it can determine if
+ *  floating point is available.  This particular implementation
+ *  is specified to the NO CPU port.
+ *
+ *
+ *  COPYRIGHT (c) 1989-2010.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  $Id$
+ *
+ */
+
+#ifndef _RTEMS_SCORE_NO_CPU_H
+#define _RTEMS_SCORE_NO_CPU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ *  This file contains the information required to build
+ *  RTEMS for a particular member of the NO CPU family.
+ *  It does this by setting variables to indicate which
+ *  implementation dependent features are present in a particular
+ *  member of the family.
+ *
+ *  This is a good place to list all the known CPU models
+ *  that this port supports and which RTEMS CPU model they correspond
+ *  to.
+ */
+
+/*
+ *  Figure out all CPU Model Feature Flags based upon compiler
+ *  predefines.
+ */
+
+#define CPU_MODEL_NAME  ""
+#define NOCPU_HAS_FPU   1
+
+/*
+ *  Define the name of the CPU family.
+ */
+
+#define CPU_NAME "RTEMS Sheduler Simulator"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTEMS_SCORE_NO_CPU_H */
diff --git a/tools/schedsim/rtems/sched_cpu/rtems/score/types.h b/tools/schedsim/rtems/sched_cpu/rtems/score/types.h
new file mode 100644
index 0000000000..10e4f03e70
--- /dev/null
+++ b/tools/schedsim/rtems/sched_cpu/rtems/score/types.h
@@ -0,0 +1,51 @@
+/**
+ * @file rtems/score/types.h
+ */
+
+/*
+ *  BASED UPON SOURCE IN RTEMS, MODIFIED FOR SIMULATOR
+ *
+ *  This include file contains type definitions pertaining to the Intel
+ *  no_cpu processor family.
+ *
+ *  COPYRIGHT (c) 1989-2010.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  $Id$
+ */
+
+#ifndef _RTEMS_SCORE_TYPES_H
+#define _RTEMS_SCORE_TYPES_H
+
+#include <rtems/score/basedefs.h>
+
+#ifndef ASM
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ *  This section defines the basic types for this processor.
+ */
+
+/** This defines the type for a priority bit map entry. */
+typedef uint16_t Priority_bit_map_Control;
+
+/** This defines the return type for an ISR entry point. */
+typedef void no_cpu_isr;
+
+/** This defines the prototype for an ISR entry point. */
+typedef no_cpu_isr ( *no_cpu_isr_entry )( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* !ASM */
+
+#endif
diff --git a/tools/schedsim/rtems/sched_cpu/rtems/stringto.h b/tools/schedsim/rtems/sched_cpu/rtems/stringto.h
new file mode 100644
index 0000000000..9201f5bc0d
--- /dev/null
+++ b/tools/schedsim/rtems/sched_cpu/rtems/stringto.h
@@ -0,0 +1 @@
+#include <stringto.h>
diff --git a/tools/schedsim/rtems/wkspace.c b/tools/schedsim/rtems/wkspace.c
new file mode 100644
index 0000000000..beb86184c6
--- /dev/null
+++ b/tools/schedsim/rtems/wkspace.c
@@ -0,0 +1,101 @@
+/*
+ *  BASED UPON SOURCE IN RTEMS, MODIFIED FOR SIMULATOR
+ *
+ *  Workspace Handler
+ *
+ *  COPYRIGHT (c) 1989-2010.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  $Id$
+ */
+
+#if HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <rtems/system.h>
+#include <rtems/score/wkspace.h>
+#include <rtems/score/interr.h>
+
+#include <stdlib.h>
+
+#if defined(DEBUG_WORKSPACE)
+  #include <stdio.h>
+#endif
+
+/*
+ *  _Workspace_Handler_initialization
+ */
+void _Workspace_Handler_initialization(void)
+{
+}
+
+/*
+ *  _Workspace_Allocate
+ */
+void *_Workspace_Allocate(
+  size_t   size
+)
+{
+  void *memory;
+
+  memory = calloc( 1, size );
+  #if defined(DEBUG_WORKSPACE)
+    fprintf(
+      stderr,
+      "Workspace_Allocate(%d) from %p/%p -> %p\n",
+      size,
+      __builtin_return_address( 0 ),
+      __builtin_return_address( 1 ),
+      memory
+    );
+  #endif
+  return memory;
+}
+
+/*
+ *  _Workspace_Free
+ */
+bool _Workspace_Free(
+  void *block
+)
+{
+  #if defined(DEBUG_WORKSPACE)
+    fprintf(
+      stderr,
+      block,
+      __builtin_return_address( 0 ),
+      __builtin_return_address( 1 )
+    );
+  #endif
+  free( block );
+  return true;
+}
+
+/*
+ *  _Workspace_Allocate_or_fatal_error
+ */
+void *_Workspace_Allocate_or_fatal_error(
+  size_t      size
+)
+{
+  void *memory;
+
+  memory = calloc( 1, size );
+  #if defined(DEBUG_WORKSPACE)
+    fprintf(
+      stderr,
+      "Workspace_Allocate_or_fatal_error(%d) from %p/%p -> %p\n",
+      size,
+      __builtin_return_address( 0 ),
+      __builtin_return_address( 1 ),
+      memory
+    );
+  #endif
+
+  return memory;
+}