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| author | Alex White <alex.white@oarcorp.com> | 2023-10-23 09:05:55 -0500 |
|---|---|---|
| committer | Joel Sherrill <joel@rtems.org> | 2023-10-27 09:40:58 -0500 |
| commit | f6b1840f70132d82df4b2b2b7553d1200f6fd724 (patch) | |
| tree | cbc3c06f123e63ae86a8517d6ff10991f1e80608 /testsuites/validation/tc-score-isr.c | |
| parent | bsps/xil: Adjust Xilinx support code for Cortex-R5 (diff) | |
| download | rtems-f6b1840f70132d82df4b2b2b7553d1200f6fd724.tar.bz2 | |
validation: Add wrapped bsp_interrupt_dispatch for MicroBlaze
This adds a MicroBlaze-specific bsp_interrupt_dispatch wrapper which
fixes a linker error.
Diffstat (limited to '')
| -rw-r--r-- | testsuites/validation/tc-score-isr.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/testsuites/validation/tc-score-isr.c b/testsuites/validation/tc-score-isr.c index f29abbbfe8..9891829a84 100644 --- a/testsuites/validation/tc-score-isr.c +++ b/testsuites/validation/tc-score-isr.c @@ -128,6 +128,23 @@ void __wrap_bsp_interrupt_dispatch( void ) } #endif +#if defined(__microblaze__) +void __real_bsp_interrupt_dispatch( uint32_t source ); + +void __wrap_bsp_interrupt_dispatch( uint32_t source ); + +void __wrap_bsp_interrupt_dispatch( uint32_t source ) +{ + register uintptr_t sp __asm__( "1" ); + + if ( interrupted_stack_at_multitasking_start == 0 ) { + interrupted_stack_at_multitasking_start = sp; + } + + __real_bsp_interrupt_dispatch( source ); +} +#endif + #if defined(__PPC__) || defined(__powerpc64__) void __real_bsp_interrupt_dispatch( void ); |