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authorPadmarao Begari <padmarao.begari@microchip.com>2022-09-19 18:30:26 +0530
committerJoel Sherrill <joel@rtems.org>2022-09-20 12:00:51 -0500
commit6b0d3c987349d188b65e9fc8229daeba247928c5 (patch)
tree4f6f37aaab9be619b82612eb4f000a42549488ca /spec/build/cpukit/optsmp.yml
parentspec/build/bsps: Add dtb support (diff)
downloadrtems-6b0d3c987349d188b65e9fc8229daeba247928c5.tar.bz2
bsps/riscv: Add Microchip PolarFire SoC BSP variant
The Microchip PolarFire SoC support is implemented as a riscv BSP variant to boot with any individual hart(cpu core) or SMP based on the boot HARTID configurable and support components are 4 CPU Cores (U54), Interrupt controller (PLIC), Timer (CLINT), UART.
Diffstat (limited to '')
-rw-r--r--spec/build/cpukit/optsmp.yml1
1 files changed, 1 insertions, 0 deletions
diff --git a/spec/build/cpukit/optsmp.yml b/spec/build/cpukit/optsmp.yml
index a9e62bf8b9..b218364194 100644
--- a/spec/build/cpukit/optsmp.yml
+++ b/spec/build/cpukit/optsmp.yml
@@ -31,6 +31,7 @@ enabled-by:
- riscv/griscv
- riscv/grv32imac
- riscv/grv32imafdc
+- riscv/mpfs64imafdc
- riscv/noel32imafd
- riscv/noel64imac
- riscv/noel64imafdc