build: Use enabled by for defaults

Merge the "default" and "default-by-variant" attributes.  Use an
"enabled-by" expression to select the default value based on the enabled
set.  This makes it possible to select default values depending on other
options.  For example you could choose memory settings based on whether
RTEMS_SMP is enabled or disabled.

The change was tested by comparing the output of

  ./waf bspdefaults

before and after the change.

7 files changed, 25 insertions, 18 deletions

diff --git a/spec/build/bsps/dev/irq/optarmgic-icc-bpr0.yml b/spec/build/bsps/dev/irq/optarmgic-icc-bpr0.yml
index 993fea48bf..51df0db964 100644
--- a/spec/build/bsps/dev/irq/optarmgic-icc-bpr0.yml
+++ b/spec/build/bsps/dev/irq/optarmgic-icc-bpr0.yml
@@ -5,10 +5,8 @@ actions:
 build-type: option
 copyrights:
 - Copyright (C) 2022 embedded brains GmbH (http://www.embedded-brains.de)
-default: 0x00000002
-default-by-variant:
-- value: null
-  variants:
+default:
+- enabled-by:
   - aarch64/a53_ilp32_qemu
   - aarch64/a53_lp64_qemu
   - aarch64/a72_ilp32_qemu
@@ -22,6 +20,9 @@ default-by-variant:
   - aarch64/xilinx_zynqmp_lp64_cfc400x
   - aarch64/xilinx_zynqmp_lp64_qemu
   - aarch64/xilinx_zynqmp_lp64_zu3eg
+  value: null
+- enabled-by: true
+  value: 0x00000002
 description: |
   Defines the initial value of the ICC_BPR0 register of the ARM GIC CPU
   Interface.  The value is optional.  If it is not defined, then the register
diff --git a/spec/build/bsps/dev/irq/optarmgic-icc-bpr1.yml b/spec/build/bsps/dev/irq/optarmgic-icc-bpr1.yml
index ee66a63969..003c832b4f 100644
--- a/spec/build/bsps/dev/irq/optarmgic-icc-bpr1.yml
+++ b/spec/build/bsps/dev/irq/optarmgic-icc-bpr1.yml
@@ -5,8 +5,9 @@ actions:
 build-type: option
 copyrights:
 - Copyright (C) 2022 embedded brains GmbH (http://www.embedded-brains.de)
-default: 0x00000003
-default-by-variant: []
+default:
+- enabled-by: true
+  value: 0x00000003
 description: |
   Defines the initial value of the ICC_BPR1 register of the ARM GIC CPU
   Interface.  The value is optional.  If it is not defined, then the register
diff --git a/spec/build/bsps/dev/irq/optarmgic-icc-ctrl.yml b/spec/build/bsps/dev/irq/optarmgic-icc-ctrl.yml
index 68988f2248..93f4c6aa42 100644
--- a/spec/build/bsps/dev/irq/optarmgic-icc-ctrl.yml
+++ b/spec/build/bsps/dev/irq/optarmgic-icc-ctrl.yml
@@ -5,8 +5,9 @@ actions:
 build-type: option
 copyrights:
 - Copyright (C) 2022 embedded brains GmbH (http://www.embedded-brains.de)
-default: 0x00000000
-default-by-variant: []
+default:
+- enabled-by: true
+  value: 0x00000000
 description: |
   Defines the initial value of the ICC_CTRL register of the ARM GIC CPU
   Interface.  The value is optional.  If it is not defined, then the register
diff --git a/spec/build/bsps/dev/irq/optarmgic-icc-igrpen0.yml b/spec/build/bsps/dev/irq/optarmgic-icc-igrpen0.yml
index 86bdcf64ee..ea5eaff3e7 100644
--- a/spec/build/bsps/dev/irq/optarmgic-icc-igrpen0.yml
+++ b/spec/build/bsps/dev/irq/optarmgic-icc-igrpen0.yml
@@ -5,10 +5,8 @@ actions:
 build-type: option
 copyrights:
 - Copyright (C) 2022 embedded brains GmbH (http://www.embedded-brains.de)
-default: 0x00000001
-default-by-variant:
-- value: null
-  variants:
+default:
+- enabled-by:
   - aarch64/a53_ilp32_qemu
   - aarch64/a53_lp64_qemu
   - aarch64/a72_ilp32_qemu
@@ -22,6 +20,9 @@ default-by-variant:
   - aarch64/xilinx_zynqmp_lp64_cfc400x
   - aarch64/xilinx_zynqmp_lp64_qemu
   - aarch64/xilinx_zynqmp_lp64_zu3eg
+  value: null
+- enabled-by: true
+  value: 0x00000001
 description: |
   Defines the initial value of the ICC_IGRPEN0 register of the ARM GIC CPU
   Interface.  The value is optional.  If it is not defined, then the register
diff --git a/spec/build/bsps/dev/irq/optarmgic-icc-igrpen1.yml b/spec/build/bsps/dev/irq/optarmgic-icc-igrpen1.yml
index a45a55e93c..111aa9e6cc 100644
--- a/spec/build/bsps/dev/irq/optarmgic-icc-igrpen1.yml
+++ b/spec/build/bsps/dev/irq/optarmgic-icc-igrpen1.yml
@@ -5,8 +5,9 @@ actions:
 build-type: option
 copyrights:
 - Copyright (C) 2022 embedded brains GmbH (http://www.embedded-brains.de)
-default: 0x00000001
-default-by-variant: []
+default:
+- enabled-by: true
+  value: 0x00000001
 description: |
   Defines the initial value of the ICC_IGRPEN1 register of the ARM GIC CPU
   Interface.  The value is optional.  If it is not defined, then the register
diff --git a/spec/build/bsps/dev/irq/optarmgic-icc-pmr.yml b/spec/build/bsps/dev/irq/optarmgic-icc-pmr.yml
index c9bef1be0e..ae2d2dd3e4 100644
--- a/spec/build/bsps/dev/irq/optarmgic-icc-pmr.yml
+++ b/spec/build/bsps/dev/irq/optarmgic-icc-pmr.yml
@@ -5,8 +5,9 @@ actions:
 build-type: option
 copyrights:
 - Copyright (C) 2022 embedded brains GmbH (http://www.embedded-brains.de)
-default: 0x000000ff
-default-by-variant: []
+default:
+- enabled-by: true
+  value: 0x000000ff
 description: |
   Defines the initial value of the ICC_PMR register of the ARM GIC CPU
   Interface.  The value is optional.  If it is not defined, then the register
diff --git a/spec/build/bsps/dev/irq/optarmgic-icc-sre.yml b/spec/build/bsps/dev/irq/optarmgic-icc-sre.yml
index 98985be4cd..45eea84bb1 100644
--- a/spec/build/bsps/dev/irq/optarmgic-icc-sre.yml
+++ b/spec/build/bsps/dev/irq/optarmgic-icc-sre.yml
@@ -5,8 +5,9 @@ actions:
 build-type: option
 copyrights:
 - Copyright (C) 2022 embedded brains GmbH (http://www.embedded-brains.de)
-default: 0x00000003
-default-by-variant: []
+default:
+- enabled-by: true
+  value: 0x00000003
 description: |
   Defines the initial value of the ICC_SRE register of the ARM GIC CPU
   Interface.  The value is optional.  If it is not defined, then the register