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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2020-12-22 13:00:27 +0100 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2020-12-23 09:24:49 +0100 |
| commit | 9f3a08ef2de99714d679aecf6b1ecb4e11869424 (patch) | |
| tree | 0d876016ae1dd067b1815dd79715cc7edc752f1e /spec/build/bsps/aarch64/xilinx-zynqmp/obj.yml | |
| parent | bsps/arm: Invalidate TLB in start.S (diff) | |
| download | rtems-9f3a08ef2de99714d679aecf6b1ecb4e11869424.tar.bz2 | |
bsps: Use header file for GIC architecture support
This avoids a function call overhead in the interrupt dispatching.
Update #4202.
Diffstat (limited to '')
| -rw-r--r-- | spec/build/bsps/aarch64/xilinx-zynqmp/obj.yml | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/spec/build/bsps/aarch64/xilinx-zynqmp/obj.yml b/spec/build/bsps/aarch64/xilinx-zynqmp/obj.yml index 2ca4ef093b..c1a859af85 100644 --- a/spec/build/bsps/aarch64/xilinx-zynqmp/obj.yml +++ b/spec/build/bsps/aarch64/xilinx-zynqmp/obj.yml @@ -29,7 +29,6 @@ source: - bsps/shared/start/bspreset-arm-psci.c - bsps/shared/start/sbrk.c - bsps/shared/dev/irq/arm-gicv2.c -- bsps/aarch64/shared/irq/irq-arm-gicvx-aarch64.c - bsps/shared/irq/irq-default-handler.c - bsps/shared/dev/btimer/btimer-cpucounter.c - bsps/shared/dev/clock/arm-generic-timer.c |