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| author | Kinsey Moore <kinsey.moore@oarcorp.com> | 2022-07-05 13:35:28 -0500 |
|---|---|---|
| committer | Joel Sherrill <joel@rtems.org> | 2022-07-06 10:22:08 -0500 |
| commit | 2f6ee01e9ebd2776d36e12bf93c11cefd4274a8e (patch) | |
| tree | cecbdccc485e0e55b117fc9cd345ea3f29c37820 /spec/build/bsps/aarch64/xilinx-versal | |
| parent | cpukit/aarch64: Remove _CPU_ISR_install_vector (diff) | |
| download | rtems-2f6ee01e9ebd2776d36e12bf93c11cefd4274a8e.tar.bz2 | |
bsps/aarch64: Use MMU pages appropriately
There were two bugs with MMU page use that were partially hiding each
other. The linker script page table section was 4x the size it needed to
be and the page table allocation routine was allocating pages PTRSIZE
times larger than it needed to. On ILP32, this resulted in incorrect but
functional allocation. On LP64, this resulted in allocation failures
earlier than expected.
Diffstat (limited to 'spec/build/bsps/aarch64/xilinx-versal')
| -rw-r--r-- | spec/build/bsps/aarch64/xilinx-versal/linkcmds_ilp32.yml | 6 | ||||
| -rw-r--r-- | spec/build/bsps/aarch64/xilinx-versal/linkcmds_lp64.yml | 6 |
2 files changed, 6 insertions, 6 deletions
diff --git a/spec/build/bsps/aarch64/xilinx-versal/linkcmds_ilp32.yml b/spec/build/bsps/aarch64/xilinx-versal/linkcmds_ilp32.yml index 3030fd0ae9..2d7a922495 100644 --- a/spec/build/bsps/aarch64/xilinx-versal/linkcmds_ilp32.yml +++ b/spec/build/bsps/aarch64/xilinx-versal/linkcmds_ilp32.yml @@ -29,9 +29,9 @@ content: | */ MEMORY { - RAM : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_LOAD_OFFSET}, LENGTH = ${BSP_XILINX_VERSAL_RAM_LENGTH} - ${BSP_XILINX_VERSAL_LOAD_OFFSET} - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH} - (0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) - NOCACHE : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}, LENGTH = ${BSP_XILINX_VERSAL_NOCACHE_LENGTH} - RAM_MMU : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}), LENGTH = 0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES} + RAM : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_LOAD_OFFSET}, LENGTH = ${BSP_XILINX_VERSAL_RAM_LENGTH} - ${BSP_XILINX_VERSAL_LOAD_OFFSET} - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH} - (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) + NOCACHE : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}, LENGTH = ${BSP_XILINX_VERSAL_NOCACHE_LENGTH} + RAM_MMU : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}), LENGTH = 0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES} } REGION_ALIAS ("REGION_START", RAM); diff --git a/spec/build/bsps/aarch64/xilinx-versal/linkcmds_lp64.yml b/spec/build/bsps/aarch64/xilinx-versal/linkcmds_lp64.yml index bd5d1f791b..76c0220f0e 100644 --- a/spec/build/bsps/aarch64/xilinx-versal/linkcmds_lp64.yml +++ b/spec/build/bsps/aarch64/xilinx-versal/linkcmds_lp64.yml @@ -29,9 +29,9 @@ content: | */ MEMORY { - RAM : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_LOAD_OFFSET}, LENGTH = ${BSP_XILINX_VERSAL_RAM_LENGTH} - ${BSP_XILINX_VERSAL_LOAD_OFFSET} - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH} - (0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) - NOCACHE : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}, LENGTH = ${BSP_XILINX_VERSAL_NOCACHE_LENGTH} - RAM_MMU : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}), LENGTH = 0x4000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES} + RAM : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_LOAD_OFFSET}, LENGTH = ${BSP_XILINX_VERSAL_RAM_LENGTH} - ${BSP_XILINX_VERSAL_LOAD_OFFSET} - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH} - (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) + NOCACHE : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}) - ${BSP_XILINX_VERSAL_NOCACHE_LENGTH}, LENGTH = ${BSP_XILINX_VERSAL_NOCACHE_LENGTH} + RAM_MMU : ORIGIN = ${BSP_XILINX_VERSAL_RAM_BASE} + ${BSP_XILINX_VERSAL_RAM_LENGTH} - (0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES}), LENGTH = 0x1000 * ${AARCH64_MMU_TRANSLATION_TABLE_PAGES} } REGION_ALIAS ("REGION_START", RAM); |