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authorJoel Sherrill <joel.sherrill@OARcorp.com>2002-08-06 14:06:43 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>2002-08-06 14:06:43 +0000
commitc388cdc3caea9cc11f1a6d34b0f0f6d30257ddb9 (patch)
tree6626c5962d277b6791359468202e69d8ebbd2158 /make
parent41d2d1fe9c5f76afa99b5276f843ed53bcfb9737 (diff)
downloadrtems-c388cdc3caea9cc11f1a6d34b0f0f6d30257ddb9.tar.bz2
2002-08-06 Chris Ziomkowski <chris@asics.ws>
* custom/or32sim.cfg: New file added as part of merge from OpenCores repository.
Diffstat (limited to 'make')
-rw-r--r--make/ChangeLog5
-rw-r--r--make/custom/orp.cfg22
2 files changed, 27 insertions, 0 deletions
diff --git a/make/ChangeLog b/make/ChangeLog
index 41db357488..5355d4770c 100644
--- a/make/ChangeLog
+++ b/make/ChangeLog
@@ -1,3 +1,8 @@
+2002-08-06 Chris Ziomkowski <chris@asics.ws>
+
+ * custom/or32sim.cfg: New file added as part of merge from
+ OpenCores repository.
+
2002-08-05 Joel Sherrill <joel@OARcorp.com>
* Per PR260 eliminate use of make-target-options. This impacted
diff --git a/make/custom/orp.cfg b/make/custom/orp.cfg
new file mode 100644
index 0000000000..3857ef6acf
--- /dev/null
+++ b/make/custom/orp.cfg
@@ -0,0 +1,22 @@
+#
+# Configuration file for the "bender" chip which is simulated
+# by or1ksim.
+#
+# $Id$
+#
+
+include $(RTEMS_ROOT)/make/custom/default.cfg
+
+RTEMS_CPU=or32
+RTEMS_CPU_MODEL=or1k_model
+
+# This is the actual bsp directory used during the build process.
+RTEMS_BSP_FAMILY=or32sim
+
+# Miscellaneous additions go here
+define make-exe
+ $(LINK.c) -W,l$(AM_CFLAGS) $(AM_LDFLAGS) -o $(basename $@).exe \
+ $(LINK_OBJS) $(LINK_LIBS) -W,l -e ___rst
+ $(NM) -n $(basename $@).exe > $(basename $@).num
+ $(SIZE) $(basename $@).exe
+endef