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authorJoel Sherrill <joel.sherrill@OARcorp.com>2002-07-31 00:17:12 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>2002-07-31 00:17:12 +0000
commit0b93b9785601ef8da6b7ae501c55033230d6589c (patch)
tree775300aba4f973e9b6d844c49487f13c99d0ca65 /doc/supplements/template/timeBSP.t
parent2002-07-30 Joel Sherrill <joel@OARcorp.com> (diff)
downloadrtems-0b93b9785601ef8da6b7ae501c55033230d6589c.tar.bz2
2002-07-30 Joel Sherrill <joel@OARcorp.com>
* intr_NOTIMES.t, timeBSP.t: Replaced XXX's with real info.
Diffstat (limited to '')
-rw-r--r--doc/supplements/template/timeBSP.t18
1 files changed, 11 insertions, 7 deletions
diff --git a/doc/supplements/template/timeBSP.t b/doc/supplements/template/timeBSP.t
index 153aa8ffaf..85e5ea44aa 100644
--- a/doc/supplements/template/timeBSP.t
+++ b/doc/supplements/template/timeBSP.t
@@ -27,12 +27,13 @@ times as they pertain to the XXX version of RTEMS.
All times reported except for the maximum period
interrupts are disabled by RTEMS were measured using a Motorola
-MYBSP CPU board. The MYBSP is a 20Mhz board with one wait
+MYBSP CPU board. The MYBSP is a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
+Mhz board with one wait
state dynamic memory and a XXX numeric coprocessor. The
Zilog 8036 countdown timer on this board was used to measure
elapsed time with a one-half microsecond resolution. All
sources of hardware interrupts were disabled, although the
-interrupt level of the XXX allows all interrupts.
+interrupt level of the processor allows all interrupts.
The maximum period interrupts are disabled was
measured by summing the number of CPU cycles required by each
@@ -41,9 +42,10 @@ disabled. The worst case times of the XXX microprocessor
were used for each instruction. Zero wait state memory was
assumed. The total CPU cycles executed with interrupts
disabled, including the instructions to disable and enable
-interrupts, was divided by 20 to simulate a 20Mhz XXX. It
+interrupts, was divided by 20 to simulate a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
+Mhz processor. It
should be noted that the worst case instruction times for the
-XXX assume that the internal cache is disabled and that no
+processor assume that the internal cache is disabled and that no
instructions overlap.
@section Interrupt Latency
@@ -52,20 +54,22 @@ The maximum period with interrupts disabled within
RTEMS is less than RTEMS_MAXIMUM_DISABLE_PERIOD
microseconds including the instructions
which disable and re-enable interrupts. The time required for
-the XXX to vector an interrupt and for the RTEMS entry
+the processor to vector an interrupt and for the RTEMS entry
overhead before invoking the user's interrupt handler are a
total of RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK
microseconds. These combine to yield a worst case
interrupt latency of less than
RTEMS_MAXIMUM_DISABLE_PERIOD + RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK
-microseconds at 20Mhz. [NOTE: The maximum period with interrupts
+microseconds at RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
+Mhz. [NOTE: The maximum period with interrupts
disabled was last determined for Release
RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.]
It should be noted again that the maximum period with
interrupts disabled within RTEMS is hand-timed and based upon
worst case (i.e. CPU cache disabled and no instruction overlap)
-times for a 20Mhz XXX. The interrupt vector and entry
+times for a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
+Mhz processor. The interrupt vector and entry
overhead time was generated on an MYBSP benchmark platform
using the Multiprocessing Communications registers to generate
as the interrupt source.