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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2002-07-31 00:17:12 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2002-07-31 00:17:12 +0000 |
| commit | 0b93b9785601ef8da6b7ae501c55033230d6589c (patch) | |
| tree | 775300aba4f973e9b6d844c49487f13c99d0ca65 /doc/supplements/template/intr_NOTIMES.t | |
| parent | 2002-07-30 Joel Sherrill <joel@OARcorp.com> (diff) | |
| download | rtems-0b93b9785601ef8da6b7ae501c55033230d6589c.tar.bz2 | |
2002-07-30 Joel Sherrill <joel@OARcorp.com>
* intr_NOTIMES.t, timeBSP.t: Replaced XXX's with real info.
Diffstat (limited to '')
| -rw-r--r-- | doc/supplements/template/intr_NOTIMES.t | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/doc/supplements/template/intr_NOTIMES.t b/doc/supplements/template/intr_NOTIMES.t index 04e4dff717..13e4921ea9 100644 --- a/doc/supplements/template/intr_NOTIMES.t +++ b/doc/supplements/template/intr_NOTIMES.t @@ -23,7 +23,7 @@ special control mechanisms to return to the normal processing stream. Although RTEMS hides many of the processor dependent details of interrupt processing, it is important to understand how the RTEMS interrupt manager is mapped onto the processor's -unique architecture. Discussed in this chapter are the XXX's +unique architecture. Discussed in this chapter are the processor's interrupt response and control mechanisms as they pertain to RTEMS. |