2002-07-30 Joel Sherrill <joel@OARcorp.com>

	* .cvsignore: Corrected some errors.
	* intr_NOTIMES.t, timeBSP.t: Replaced XXX's with real info.

1 files changed, 12 insertions, 8 deletions

diff --git a/doc/supplements/mips/timeBSP.t b/doc/supplements/mips/timeBSP.t
index 63877b8de3..a00259ec94 100644
--- a/doc/supplements/mips/timeBSP.t
+++ b/doc/supplements/mips/timeBSP.t
@@ -15,19 +15,20 @@
 
 @section Introduction
 
-The timing data for the XXX version of RTEMS is
+The timing data for the MIPS version of RTEMS is
 provided along with the target dependent aspects concerning the
 gathering of the timing data.  The hardware platform used to
 gather the times is described to give the reader a better
 understanding of each directive time provided.  Also, provided
 is a description of the interrupt latency and the context switch
-times as they pertain to the XXX version of RTEMS.
+times as they pertain to the MIPS version of RTEMS.
 
 @section Hardware Platform
 
 All times reported except for the maximum period
 interrupts are disabled by RTEMS were measured using a Motorola
-BSP_FOR_TIMES CPU board.  The BSP_FOR_TIMES is a 20Mhz board with one wait
+BSP_FOR_TIMES CPU board.  The BSP_FOR_TIMES is a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
+Mhz board with one wait
 state dynamic memory and a XXX numeric coprocessor.  The
 Zilog 8036 countdown timer on this board was used to measure
 elapsed time with a one-half microsecond resolution.  All
@@ -41,7 +42,8 @@ disabled.  The worst case times of the XXX microprocessor
 were used for each instruction.  Zero wait state memory was
 assumed.  The total CPU cycles executed with interrupts
 disabled, including the instructions to disable and enable
-interrupts, was divided by 20 to simulate a 20Mhz XXX.  It
+interrupts, was divided by 20 to simulate a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
+Mhz processor.  It
 should be noted that the worst case instruction times for the
 XXX assume that the internal cache is disabled and that no
 instructions overlap.
@@ -58,14 +60,16 @@ total of RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK
 microseconds.  These combine to yield a worst case
 interrupt latency of less than 
 RTEMS_MAXIMUM_DISABLE_PERIOD + RTEMS_INTR_ENTRY_RETURNS_TO_PREEMPTING_TASK 
-microseconds at 20Mhz.  [NOTE:  The maximum period with interrupts
+microseconds at RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
+Mhz.  [NOTE:  The maximum period with interrupts
 disabled was last determined for Release 
 RTEMS_RELEASE_FOR_MAXIMUM_DISABLE_PERIOD.]
 
 It should be noted again that the maximum period with
 interrupts disabled within RTEMS is hand-timed and based upon
 worst case (i.e. CPU cache disabled and no instruction overlap)
-times for a 20Mhz XXX.  The interrupt vector and entry
+times for a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
+Mhz processor.  The interrupt vector and entry
 overhead time was generated on an BSP_FOR_TIMES benchmark platform
 using the Multiprocessing Communications registers to generate
 as the interrupt source.
@@ -93,8 +97,8 @@ is dispatched, RTEMS does not need to save the current state of
 the numeric coprocessor.
 
 The exact amount of time required to save and restore
-floating point context is dependent on whether an XXX or
-XXX is being used as well as the state of the numeric
+floating point context is dependent which FPU is being
+used as well as the state of the numeric
 coprocessor.  These numeric coprocessors define three operating
 states: initialized, idle, and busy.  RTEMS places the
 coprocessor in the initialized state when a task is started or