All of the Supplemental manuals are now generated as automatically

as possible.

10 files changed, 78 insertions, 250 deletions

diff --git a/doc/supplements/m68k/Makefile b/doc/supplements/m68k/Makefile
index 2995d519b5..3fbbfa7ed6 100644
--- a/doc/supplements/m68k/Makefile
+++ b/doc/supplements/m68k/Makefile
@@ -20,12 +20,12 @@ dirs:
 
 COMMON_FILES=../../common/cpright.texi ../../common/setup.texi
 
-GENERATED_FILES= \
-  timing.texi wksheets.texi
+GENERATED_FILES=\
+  cpumodel.texi callconv.texi memmodel.texi intr.texi fatalerr.texi \
+  bsp.texi cputable.texi timing.texi wksheets.texi timeMVME136.texi
 
 FILES= $(PROJECT).texi \
-  bsp.texi callconv.texi cpumodel.texi cputable.texi fatalerr.texi \
-  intr.texi memmodel.texi preface.texi timetbl.texi timedata.texi \
+  preface.texi \
   $(GENERATED_FILES)
 
 info: dirs c_m68k
@@ -44,27 +44,61 @@ $(PROJECT).ps: $(PROJECT).dvi
 $(PROJECT).dvi: $(FILES)
 	$(TEXI2DVI) $(PROJECT).texi
 
-replace: timedata.texi
-
 #
 #  Chapters which get automatic processing
 #
 
-# CPU Model
-# Calling Conventions
-# Memory Model
+cpumodel.texi: cpumodel.t Makefile
+	$(BMENU) -p "Preface" \
+	    -u "Top" \
+	    -n "Calling Conventions" ${*}.t
+
+callconv.texi: callconv.t Makefile
+	$(BMENU) -p "CPU Model Dependent Features Extend Byte to Long Instruction" \
+	    -u "Top" \
+	    -n "Memory Model" ${*}.t
+
+memmodel.texi: memmodel.t Makefile
+	$(BMENU) -p "Calling Conventions User-Provided Routines" \
+	    -u "Top" \
+	    -n "Interrupt Processing" ${*}.t
+
+
+## Interrupt Chapter:
+##  1.  Replace Times and Sizes
+##  2.  Build Node Structure
+#
+#intr.texi: intr.t MVME136_TIMES
+#	${REPLACE} -p MVME136_TIMES intr.t
+#	mv intr.t.fixed intr.texi
 
 # Interrupt Chapter:
 #  1.  Replace Times and Sizes
 #  2.  Build Node Structure
+intr.t: intr_NOTIMES.t MVME136_TIMES
+	${REPLACE} -p MVME136_TIMES intr_NOTIMES.t
+	mv intr_NOTIMES.t.fixed intr.t
 
-intr.texi: intr.t MVME136_TIMES
-	${REPLACE} -p MVME136_TIMES intr.t
-	mv intr.t.fixed intr.texi
+intr.texi: intr.t Makefile
+	$(BMENU) -p "Memory Model Flat Memory Model" \
+	    -u "Top" \
+	    -n "Default Fatal Error Processing" ${*}.t
+
+fatalerr.texi: fatalerr.t Makefile
+	$(BMENU) -p "Interrupt Processing Interrupt Stack" \
+	    -u "Top" \
+	    -n "Board Support Packages" ${*}.t
+
+bsp.texi: bsp.t Makefile
+	$(BMENU) -p "Default Fatal Error Processing Default Fatal Error Handler Operations" \
+	    -u "Top" \
+	    -n "Processor Dependent Information Table" ${*}.t
+
+cputable.texi: cputable.t Makefile
+	$(BMENU) -p "Board Support Packages Processor Initialization" \
+	    -u "Top" \
+	    -n "Memory Requirements" ${*}.t
 
-# Fatal Error
-# BSP
-# CPU Table
 
 # Worksheets Chapter:
 #  1.  Obtain the Shared File
@@ -95,17 +129,25 @@ timing.texi: timing.t Makefile
             -u "Top" \
             -n "MVME136 Timing Data" ${*}.t
 
-timetbl.t: ../../common/timetbl.t
-	sed -e 's/TIMETABLE_NEXT_LINK/Command and Variable Index/' \
-	      <../../common/timetbl.t >timetbl.t
-
-timetbl.texi: timetbl.t MVME136_TIMES
-	${REPLACE} -p MVME136_TIMES timetbl.t
-	mv timetbl.t.fixed timetbl.texi
+# Timing Data for BSP Chapter:
+#  1.  Copy the Shared File
+#  2.  Replace Times and Sizes
+#  3.  Build Node Structure
 
-timedata.texi: timedata.t MVME136_TIMES
-	${REPLACE} -p MVME136_TIMES timedata.t
-	mv timedata.t.fixed timedata.texi
+timeMVME136_.t: ../../common/timetbl.t timeMVME136.t
+	cat timeMVME136.t ../../common/timetbl.t             >timeMVME136_.t
+	@echo                                               >>timeMVME136_.t
+	@echo "@tex"                                        >>timeMVME136_.t
+	@echo "\\global\\advance \\smallskipamount by 4pt"  >>timeMVME136_.t
+	@echo "@end tex"                                    >>timeMVME136_.t
+	${REPLACE} -p MVME136_TIMES timeMVME136_.t
+	mv timeMVME136_.t.fixed timeMVME136_.t
+
+timeMVME136.texi: timeMVME136_.t Makefile
+	$(BMENU) -p "Timing Specification Terminology" \
+	    -u "Top" \
+	    -n "Command and Variable Index" timeMVME136_.t
+	mv timeMVME136_.texi timeMVME136.texi
 
 html: dirs $(FILES)
 	-mkdir -p $(WWW_INSTALL)/c_m68k
@@ -117,6 +159,7 @@ clean:
 	rm -f *.dvi *.ps *.log *.aux *.cp *.fn *.ky *.pg *.toc *.tp *.vr $(BASE)
 	rm -f $(PROJECT) $(PROJECT)-*
 	rm -f c_m68k c_m68k-*
-	rm -f timedata.texi timetbl.texi intr.texi $(GENERATED_FILES)
-	rm -f timetbl.t wksheets.t wksheets_NOTIMES.t
+	rm -f intr.t $(GENERATED_FILES)
+	rm -f wksheets.t wksheets_NOTIMES.t
+	rm -f timeMVME136_.t timeMVME136_.texi
 	rm -f *.fixed _* timing.t
diff --git a/doc/supplements/m68k/bsp.t b/doc/supplements/m68k/bsp.t
index cc056b2c06..7782fe2e3d 100644
--- a/doc/supplements/m68k/bsp.t
+++ b/doc/supplements/m68k/bsp.t
@@ -6,21 +6,8 @@
 @c  $Id$
 @c
 
-@ifinfo
-@node Board Support Packages, Board Support Packages Introduction, Default Fatal Error Processing Default Fatal Error Handler Operations, Top
-@end ifinfo
 @chapter Board Support Packages
-@ifinfo
-@menu
-* Board Support Packages Introduction::
-* Board Support Packages System Reset::
-* Board Support Packages Processor Initialization::
-@end menu
-@end ifinfo
-
-@ifinfo
-@node Board Support Packages Introduction, Board Support Packages System Reset, Board Support Packages, Board Support Packages
-@end ifinfo
+
 @section Introduction
 
 An RTEMS Board Support Package (BSP) must be designed
@@ -30,9 +17,6 @@ issues.   For more information on developing a BSP, refer to the
 chapter titled Board Support Packages in the RTEMS
 Applications User's Guide.
 
-@ifinfo
-@node Board Support Packages System Reset, Board Support Packages Processor Initialization, Board Support Packages Introduction, Board Support Packages
-@end ifinfo
 @section System Reset
 
 An RTEMS based application is initiated or
@@ -66,9 +50,6 @@ vector 1 (bytes 4-7) of the EVT.
 the PC.
 @end itemize
 
-@ifinfo
-@node Board Support Packages Processor Initialization, Processor Dependent Information Table, Board Support Packages System Reset, Board Support Packages
-@end ifinfo
 @section Processor Initialization
 
 The address of the application's initialization code
diff --git a/doc/supplements/m68k/callconv.t b/doc/supplements/m68k/callconv.t
index 014222a9fc..1ebdf7592e 100644
--- a/doc/supplements/m68k/callconv.t
+++ b/doc/supplements/m68k/callconv.t
@@ -6,24 +6,8 @@
 @c  $Id$
 @c
 
-@ifinfo
-@node Calling Conventions, Calling Conventions Introduction, CPU Model Dependent Features Extend Byte to Long Instruction, Top
-@end ifinfo
 @chapter Calling Conventions
-@ifinfo
-@menu
-* Calling Conventions Introduction::
-* Calling Conventions Processor Background::
-* Calling Conventions Calling Mechanism::
-* Calling Conventions Register Usage::
-* Calling Conventions Parameter Passing::
-* Calling Conventions User-Provided Routines::
-@end menu
-@end ifinfo
-
-@ifinfo
-@node Calling Conventions Introduction, Calling Conventions Processor Background, Calling Conventions, Calling Conventions
-@end ifinfo
+
 @section Introduction
 
 Each high-level language compiler generates
@@ -44,9 +28,6 @@ target processor are the same, different compilers may use
 different calling conventions.  As a result, calling conventions
 are both processor and compiler dependent.
 
-@ifinfo
-@node Calling Conventions Processor Background, Calling Conventions Calling Mechanism, Calling Conventions Introduction, Calling Conventions
-@end ifinfo
 @section Processor Background
 
 The MC68xxx architecture supports a simple yet
@@ -61,18 +42,12 @@ automatically save or restore any registers.  It is the
 responsibility of the high-level language compiler to define the
 register preservation and usage convention.
 
-@ifinfo
-@node Calling Conventions Calling Mechanism, Calling Conventions Register Usage, Calling Conventions Processor Background, Calling Conventions
-@end ifinfo
 @section Calling Mechanism
 
 All RTEMS directives are invoked using either a bsr
 or jsr instruction and return to the user application via the
 rts instruction.
 
-@ifinfo
-@node Calling Conventions Register Usage, Calling Conventions Parameter Passing, Calling Conventions Calling Mechanism, Calling Conventions
-@end ifinfo
 @section Register Usage
 
 As discussed above, the bsr and jsr instructions do
@@ -82,9 +57,6 @@ not preserved by RTEMS directives therefore, the contents of
 these registers should not be assumed upon return from any RTEMS
 directive.
 
-@ifinfo
-@node Calling Conventions Parameter Passing, Calling Conventions User-Provided Routines, Calling Conventions Register Usage, Calling Conventions
-@end ifinfo
 @section Parameter Passing
 
 RTEMS assumes that arguments are placed on the
@@ -112,9 +84,6 @@ from the stack after control is returned to the caller.  This
 removal is typically accomplished by adding the size of the
 argument list in bytes to the current stack pointer.
 
-@ifinfo
-@node Calling Conventions User-Provided Routines, Memory Model, Calling Conventions Parameter Passing, Calling Conventions
-@end ifinfo
 @section User-Provided Routines
 
 All user-provided routines invoked by RTEMS, such as
diff --git a/doc/supplements/m68k/cpumodel.t b/doc/supplements/m68k/cpumodel.t
index 0c693ad8c3..d9bf601e1f 100644
--- a/doc/supplements/m68k/cpumodel.t
+++ b/doc/supplements/m68k/cpumodel.t
@@ -6,26 +6,8 @@
 @c  $Id$
 @c
 
-@ifinfo
-@node CPU Model Dependent Features, CPU Model Dependent Features Introduction, Preface, Top
-@end ifinfo
 @chapter CPU Model Dependent Features
-@ifinfo
-@menu
-* CPU Model Dependent Features Introduction::
-* CPU Model Dependent Features CPU Model Name::
-* CPU Model Dependent Features Floating Point Unit::
-* CPU Model Dependent Features BFFFO Instruction::
-* CPU Model Dependent Features Vector Base Register::
-* CPU Model Dependent Features Separate Stacks::
-* CPU Model Dependent Features Pre-Indexing Address Mode::
-* CPU Model Dependent Features Extend Byte to Long Instruction::
-@end menu
-@end ifinfo
-
-@ifinfo
-@node CPU Model Dependent Features Introduction, CPU Model Dependent Features CPU Model Name, CPU Model Dependent Features, CPU Model Dependent Features
-@end ifinfo
+
 @section Introduction
 
 Microprocessors are generally classified into
@@ -67,18 +49,12 @@ The set of CPU model feature macros are defined in the file
 c/src/exec/score/cpu/m68k/m68k.h based upon the particular CPU
 model defined on the compilation command line.
 
-@ifinfo
-@node CPU Model Dependent Features CPU Model Name, CPU Model Dependent Features Floating Point Unit, CPU Model Dependent Features Introduction, CPU Model Dependent Features
-@end ifinfo
 @section CPU Model Name
 
 The macro CPU_MODEL_NAME is a string which designates
 the name of this CPU model.  For example, for the MC68020
 processor, this macro is set to the string "mc68020".
 
-@ifinfo
-@node CPU Model Dependent Features Floating Point Unit, CPU Model Dependent Features BFFFO Instruction, CPU Model Dependent Features CPU Model Name, CPU Model Dependent Features
-@end ifinfo
 @section Floating Point Unit
 
 The macro M68K_HAS_FPU is set to 1 to indicate that
@@ -87,42 +63,27 @@ otherwise.  It does not matter whether the hardware floating
 point support is incorporated on-chip or is an external
 coprocessor.
 
-@ifinfo
-@node CPU Model Dependent Features BFFFO Instruction, CPU Model Dependent Features Vector Base Register, CPU Model Dependent Features Floating Point Unit, CPU Model Dependent Features
-@end ifinfo
 @section BFFFO Instruction
 
 The macro M68K_HAS_BFFFO is set to 1 to indicate that
 this CPU model has the bfffo instruction.
 
-@ifinfo
-@node CPU Model Dependent Features Vector Base Register, CPU Model Dependent Features Separate Stacks, CPU Model Dependent Features BFFFO Instruction, CPU Model Dependent Features
-@end ifinfo
 @section Vector Base Register
 
 The macro M68K_HAS_VBR is set to 1 to indicate that
 this CPU model has a vector base register (vbr).
 
-@ifinfo
-@node CPU Model Dependent Features Separate Stacks, CPU Model Dependent Features Pre-Indexing Address Mode, CPU Model Dependent Features Vector Base Register, CPU Model Dependent Features
-@end ifinfo
 @section Separate Stacks
 
 The macro M68K_HAS_SEPARATE_STACKS is set to 1 to
 indicate that this CPU model has separate interrupt, user, and
 supervisor mode stacks.
 
-@ifinfo
-@node CPU Model Dependent Features Pre-Indexing Address Mode, CPU Model Dependent Features Extend Byte to Long Instruction, CPU Model Dependent Features Separate Stacks, CPU Model Dependent Features
-@end ifinfo
 @section Pre-Indexing Address Mode
 
 The macro M68K_HAS_PREINDEXING is set to 1 to indicate that
 this CPU model has the pre-indexing address mode.
 
-@ifinfo
-@node CPU Model Dependent Features Extend Byte to Long Instruction, Calling Conventions, CPU Model Dependent Features Pre-Indexing Address Mode, CPU Model Dependent Features
-@end ifinfo
 @section Extend Byte to Long Instruction
  
 The macro M68K_HAS_EXTB_L is set to 1 to indicate that this CPU model 
diff --git a/doc/supplements/m68k/cputable.t b/doc/supplements/m68k/cputable.t
index b0d011e2c5..7a7273ea8e 100644
--- a/doc/supplements/m68k/cputable.t
+++ b/doc/supplements/m68k/cputable.t
@@ -6,20 +6,8 @@
 @c  $Id$
 @c
 
-@ifinfo
-@node Processor Dependent Information Table, Processor Dependent Information Table Introduction, Board Support Packages Processor Initialization, Top
-@end ifinfo
-@chapter  Processor Dependent Information Table
-@ifinfo
-@menu
-* Processor Dependent Information Table Introduction::
-* Processor Dependent Information Table CPU Dependent Information Table::
-@end menu
-@end ifinfo
-
-@ifinfo
-@node Processor Dependent Information Table Introduction, Processor Dependent Information Table CPU Dependent Information Table, Processor Dependent Information Table, Processor Dependent Information Table
-@end ifinfo
+@chapter Processor Dependent Information Table
+
 @section Introduction
 
 Any highly processor dependent information required
@@ -28,9 +16,6 @@ Dependent Information Table.  This table is not required for all
 processors supported by RTEMS.  This chapter describes the
 contents, if any, for a particular processor type.
 
-@ifinfo
-@node Processor Dependent Information Table CPU Dependent Information Table, Memory Requirements, Processor Dependent Information Table Introduction, Processor Dependent Information Table
-@end ifinfo
 @section CPU Dependent Information Table
 
 The MC68xxx version of the RTEMS CPU Dependent
diff --git a/doc/supplements/m68k/fatalerr.t b/doc/supplements/m68k/fatalerr.t
index c2390f50bd..4b4c8d0b8d 100644
--- a/doc/supplements/m68k/fatalerr.t
+++ b/doc/supplements/m68k/fatalerr.t
@@ -6,20 +6,8 @@
 @c  $Id$
 @c
 
-@ifinfo
-@node Default Fatal Error Processing, Default Fatal Error Processing Introduction, Interrupt Processing Interrupt Stack, Top
-@end ifinfo
 @chapter Default Fatal Error Processing
-@ifinfo
-@menu
-* Default Fatal Error Processing Introduction::
-* Default Fatal Error Processing Default Fatal Error Handler Operations::
-@end menu
-@end ifinfo
 
-@ifinfo
-@node Default Fatal Error Processing Introduction, Default Fatal Error Processing Default Fatal Error Handler Operations, Default Fatal Error Processing, Default Fatal Error Processing
-@end ifinfo
 @section Introduction
 
 Upon detection of a fatal error by either the
@@ -32,9 +20,6 @@ default fatal error handler is then invoked.  This chapter
 describes the precise operations of the default fatal error
 handler.
 
-@ifinfo
-@node Default Fatal Error Processing Default Fatal Error Handler Operations, Board Support Packages, Default Fatal Error Processing Introduction, Default Fatal Error Processing
-@end ifinfo
 @section Default Fatal Error Handler Operations
 
 The default fatal error handler which is invoked by
diff --git a/doc/supplements/m68k/intr_NOTIMES.t b/doc/supplements/m68k/intr_NOTIMES.t
index ea28bdbc84..89c5225625 100644
--- a/doc/supplements/m68k/intr_NOTIMES.t
+++ b/doc/supplements/m68k/intr_NOTIMES.t
@@ -8,23 +8,8 @@
 @c  $Id$
 @c
 
-@ifinfo
-@node Interrupt Processing, Interrupt Processing Introduction, Memory Model Flat Memory Model, Top
-@end ifinfo
 @chapter Interrupt Processing
-@ifinfo
-@menu
-* Interrupt Processing Introduction::
-* Interrupt Processing Vectoring of an Interrupt Handler::
-* Interrupt Processing Interrupt Levels::
-* Interrupt Processing Disabling of Interrupts by RTEMS::
-* Interrupt Processing Interrupt Stack::
-@end menu
-@end ifinfo
-
-@ifinfo
-@node Interrupt Processing Introduction, Interrupt Processing Vectoring of an Interrupt Handler, Interrupt Processing, Interrupt Processing
-@end ifinfo
+
 @section Introduction
 
 Different types of processors respond to the
@@ -42,24 +27,12 @@ unique architecture. Discussed in this chapter are the MC68xxx's
 interrupt response and control mechanisms as they pertain to
 RTEMS.
 
-@ifinfo
-@node Interrupt Processing Vectoring of an Interrupt Handler, Models Without Separate Interrupt Stacks, Interrupt Processing Introduction, Interrupt Processing
-@end ifinfo
 @section Vectoring of an Interrupt Handler
-@ifinfo
-@menu
-* Models Without Separate Interrupt Stacks::
-* Models With Separate Interrupt Stacks::
-@end menu
-@end ifinfo
 
 Depending on whether or not the particular CPU
 supports a separate interrupt stack, the MC68xxx family has two
 different interrupt handling models.
 
-@ifinfo
-@node Models Without Separate Interrupt Stacks, Models With Separate Interrupt Stacks, Interrupt Processing Vectoring of an Interrupt Handler, Interrupt Processing Vectoring of an Interrupt Handler
-@end ifinfo
 @subsection Models Without Separate Interrupt Stacks
 
 Upon receipt of an interrupt the MC68xxx family
@@ -70,9 +43,6 @@ the following actions:
 @item To Be Written
 @end itemize
 
-@ifinfo
-@node Models With Separate Interrupt Stacks, Interrupt Processing Interrupt Levels, Models Without Separate Interrupt Stacks, Interrupt Processing Vectoring of an Interrupt Handler
-@end ifinfo
 @subsection Models With Separate Interrupt Stacks
 
 Upon receipt of an interrupt the MC68xxx family
@@ -173,9 +143,6 @@ MC68xxx CPU models with separate interrupt stacks:
 @end html
 @end ifset
 
-@ifinfo
-@node Interrupt Processing Interrupt Levels, Interrupt Processing Disabling of Interrupts by RTEMS, Models With Separate Interrupt Stacks, Interrupt Processing
-@end ifinfo
 @section Interrupt Levels
 
 Eight levels (0-7) of interrupt priorities are
@@ -191,9 +158,6 @@ through 7 directly correspond to MC68xxx interrupt levels.  All
 other RTEMS interrupt levels are undefined and their behavior is
 unpredictable.
 
-@ifinfo
-@node Interrupt Processing Disabling of Interrupts by RTEMS, Interrupt Processing Interrupt Stack, Interrupt Processing Interrupt Levels, Interrupt Processing
-@end ifinfo
 @section Disabling of Interrupts by RTEMS
 
 During the execution of directive calls, critical
@@ -217,9 +181,6 @@ occur due to the inability of RTEMS to protect its critical
 sections.  However, ISRs that make no system calls may safely
 execute as non-maskable interrupts.
 
-@ifinfo
-@node Interrupt Processing Interrupt Stack, Default Fatal Error Processing, Interrupt Processing Disabling of Interrupts by RTEMS, Interrupt Processing
-@end ifinfo
 @section Interrupt Stack
 
 RTEMS allocates the interrupt stack from the
diff --git a/doc/supplements/m68k/m68k.texi b/doc/supplements/m68k/m68k.texi
index 5137005216..edd541331d 100644
--- a/doc/supplements/m68k/m68k.texi
+++ b/doc/supplements/m68k/m68k.texi
@@ -73,7 +73,7 @@ END-INFO-DIR-ENTRY
 @include cputable.texi
 @include wksheets.texi
 @include timing.texi
-@include timedata.texi
+@include timeMVME136.texi
 @ifinfo
 @node Top, Preface, (dir), (dir)
 @top c_m68k
diff --git a/doc/supplements/m68k/memmodel.t b/doc/supplements/m68k/memmodel.t
index e8c7c460dd..6054fd54a9 100644
--- a/doc/supplements/m68k/memmodel.t
+++ b/doc/supplements/m68k/memmodel.t
@@ -6,20 +6,8 @@
 @c  $Id$
 @c
 
-@ifinfo
-@node Memory Model, Memory Model Introduction, Calling Conventions User-Provided Routines, Top
-@end ifinfo
 @chapter Memory Model
-@ifinfo
-@menu
-* Memory Model Introduction::
-* Memory Model Flat Memory Model::
-@end menu
-@end ifinfo
 
-@ifinfo
-@node Memory Model Introduction, Memory Model Flat Memory Model, Memory Model, Memory Model
-@end ifinfo
 @section Introduction
 
 A processor may support any combination of memory
@@ -31,9 +19,6 @@ memory of any kind.  The appropriate memory model for RTEMS
 provided by the targeted processor and related characteristics
 of that model are described in this chapter.
 
-@ifinfo
-@node Memory Model Flat Memory Model, Interrupt Processing, Memory Model Introduction, Memory Model
-@end ifinfo
 @section Flat Memory Model
 
 The MC68xxx family supports a flat 32-bit address
diff --git a/doc/supplements/m68k/timeMVME136.t b/doc/supplements/m68k/timeMVME136.t
index 74b64bd088..7f126b4606 100644
--- a/doc/supplements/m68k/timeMVME136.t
+++ b/doc/supplements/m68k/timeMVME136.t
@@ -11,36 +11,8 @@
 \global\advance \smallskipamount by -4pt
 @end tex
 
-@ifinfo
-@node MVME136 Timing Data, MVME136 Timing Data Introduction, Timing Specification Terminology, Top
-@end ifinfo
 @chapter MVME136 Timing Data
-@ifinfo
-@menu
-* MVME136 Timing Data Introduction::
-* MVME136 Timing Data Hardware Platform::
-* MVME136 Timing Data Interrupt Latency::
-* MVME136 Timing Data Context Switch::
-* MVME136 Timing Data Directive Times::
-* MVME136 Timing Data Task Manager::
-* MVME136 Timing Data Interrupt Manager::
-* MVME136 Timing Data Clock Manager::
-* MVME136 Timing Data Timer Manager::
-* MVME136 Timing Data Semaphore Manager::
-* MVME136 Timing Data Message Manager::
-* MVME136 Timing Data Event Manager::
-* MVME136 Timing Data Signal Manager::
-* MVME136 Timing Data Partition Manager::
-* MVME136 Timing Data Region Manager::
-* MVME136 Timing Data Dual-Ported Memory Manager::
-* MVME136 Timing Data I/O Manager::
-* MVME136 Timing Data Rate Monotonic Manager::
-@end menu
-@end ifinfo
-
-@ifinfo
-@node MVME136 Timing Data Introduction, MVME136 Timing Data Hardware Platform, MVME136 Timing Data, MVME136 Timing Data
-@end ifinfo
+
 @section Introduction
 
 The timing data for the MC68020 version of RTEMS is
@@ -51,9 +23,6 @@ understanding of each directive time provided.  Also, provided
 is a description of the interrupt latency and the context switch
 times as they pertain to the MC68020 version of RTEMS.
 
-@ifinfo
-@node MVME136 Timing Data Hardware Platform, MVME136 Timing Data Interrupt Latency, MVME136 Timing Data Introduction, MVME136 Timing Data
-@end ifinfo
 @section Hardware Platform
 
 All times reported except for the maximum period
@@ -77,9 +46,6 @@ should be noted that the worst case instruction times for the
 MC68020 assume that the internal cache is disabled and that no
 instructions overlap.
 
-@ifinfo
-@node MVME136 Timing Data Interrupt Latency, MVME136 Timing Data Context Switch, MVME136 Timing Data Hardware Platform, MVME136 Timing Data
-@end ifinfo
 @section Interrupt Latency
 
 The maximum period with interrupts disabled within
@@ -104,9 +70,6 @@ overhead time was generated on an MVME135 benchmark platform
 using the Multiprocessing Communications registers to generate
 as the interrupt source.
 
-@ifinfo
-@node MVME136 Timing Data Context Switch, MVME136 Timing Data Directive Times, MVME136 Timing Data Interrupt Latency, MVME136 Timing Data
-@end ifinfo
 @section Context Switch
 
 The RTEMS processor context switch time is RTEMS_NO_FP_CONTEXTS
@@ -143,8 +106,3 @@ are executing.  The state of the coprocessor is task specific.
 The following table summarizes the context switch
 times for the MVME135 benchmark platform:
 
-@include timetbl.texi
-
-@tex
-\global\advance \smallskipamount by 4pt
-@end tex